imbis
/
AKM_Demo_Board
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'master'
${ noResults }
AKM_Demo_Board/Project/SDK/Debuggint_Info/max32660.sfd

19992 lines
721 KiB
Raw Permalink Normal View History Unescape

Init Commit
5 months ago
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @file max32660.sfd
* @brief CMSIS-SVD SFD File
* @version 1.0
* @date 03. June 2022
* @note Generated by SVDConv V3.3.39 on Friday, 03.06.2022 16:50:52
* from File 'max32660.svd',
* last modified on Thursday, 30.09.2021 05:36:38
*/
// --------------------------- Register Item Address: BBFC_BBFCR0 -------------------------------
// SVD Line: 35
unsigned int BBFC_BBFCR0 __AT (0x40005800);
// ----------------------------- Field Item: BBFC_BBFCR0_CKPDRV ---------------------------------
// SVD Line: 41
// <item> SFDITEM_FIELD__BBFC_BBFCR0_CKPDRV
// <name> CKPDRV </name>
// <rw>
// <i> [Bits 3..0] RW (@ 0x40005800) Hyperbus CK Pad Driver Control. </i>
// <edit>
// <loc> ( (unsigned char)((BBFC_BBFCR0 >> 0) & 0xF), ((BBFC_BBFCR0 = (BBFC_BBFCR0 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: BBFC_BBFCR0_CKNPDRV --------------------------------
// SVD Line: 47
// <item> SFDITEM_FIELD__BBFC_BBFCR0_CKNPDRV
// <name> CKNPDRV </name>
// <rw>
// <i> [Bits 7..4] RW (@ 0x40005800) Hyperbus CKN Pad Driver Control. </i>
// <edit>
// <loc> ( (unsigned char)((BBFC_BBFCR0 >> 4) & 0xF), ((BBFC_BBFCR0 = (BBFC_BBFCR0 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: BBFC_BBFCR0_RDSDLLEN --------------------------------
// SVD Line: 53
// <item> SFDITEM_FIELD__BBFC_BBFCR0_RDSDLLEN
// <name> RDSDLLEN </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40005800) \nHyperbus RDS DLL Power Up Control.\n0 : dis = Disabled.\n1 : en = Enabled. </i>
// <combo>
// <loc> ( (unsigned int) BBFC_BBFCR0 ) </loc>
// <o.8..8> RDSDLLEN
// <0=> 0: dis = Disabled.
// <1=> 1: en = Enabled.
// </combo>
// </item>
//
// ------------------------------- Register RTree: BBFC_BBFCR0 ----------------------------------
// SVD Line: 35
// <rtree> SFDITEM_REG__BBFC_BBFCR0
// <name> BBFCR0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40005800) Function Control Register 0. </i>
// <loc> ( (unsigned int)((BBFC_BBFCR0 >> 0) & 0xFFFFFFFF), ((BBFC_BBFCR0 = (BBFC_BBFCR0 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__BBFC_BBFCR0_CKPDRV </item>
// <item> SFDITEM_FIELD__BBFC_BBFCR0_CKNPDRV </item>
// <item> SFDITEM_FIELD__BBFC_BBFCR0_RDSDLLEN </item>
// </rtree>
//
// ---------------------------------- Peripheral View: BBFC -------------------------------------
// SVD Line: 25
// <view> BBFC
// <name> BBFC </name>
// <item> SFDITEM_REG__BBFC_BBFCR0 </item>
// </view>
//
// ---------------------------- Register Item Address: BBSIR_rsv0 -------------------------------
// SVD Line: 86
unsigned int BBSIR_rsv0 __AT (0x40005400);
// -------------------------------- Register Item: BBSIR_rsv0 -----------------------------------
// SVD Line: 86
// <item> SFDITEM_REG__BBSIR_rsv0
// <name> rsv0 </name>
// <i> [Bits 31..0] RW (@ 0x40005400) RFU </i>
// <edit>
// <loc> ( (unsigned int)((BBSIR_rsv0 >> 0) & 0xFFFFFFFF), ((BBSIR_rsv0 = (BBSIR_rsv0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register Item Address: BBSIR_BB_SIR2 ------------------------------
// SVD Line: 91
unsigned int BBSIR_BB_SIR2 __AT (0x40005408);
// ------------------------------ Register Item: BBSIR_BB_SIR2 ----------------------------------
// SVD Line: 91
// <item> SFDITEM_REG__BBSIR_BB_SIR2
// <name> BB_SIR2 </name>
// <i> [Bits 31..0] RO (@ 0x40005408) System Init. Configuration Register 2. </i>
// <edit>
// <loc> ( (unsigned int)((BBSIR_BB_SIR2 >> 0) & 0xFFFFFFFF), ((BBSIR_BB_SIR2 = (BBSIR_BB_SIR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register Item Address: BBSIR_BB_SIR3 ------------------------------
// SVD Line: 97
unsigned int BBSIR_BB_SIR3 __AT (0x4000540C);
// ------------------------------ Register Item: BBSIR_BB_SIR3 ----------------------------------
// SVD Line: 97
// <item> SFDITEM_REG__BBSIR_BB_SIR3
// <name> BB_SIR3 </name>
// <i> [Bits 31..0] RO (@ 0x4000540C) System Init. Configuration Register 3. </i>
// <edit>
// <loc> ( (unsigned int)((BBSIR_BB_SIR3 >> 0) & 0xFFFFFFFF), ((BBSIR_BB_SIR3 = (BBSIR_BB_SIR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------------------- Peripheral View: BBSIR -------------------------------------
// SVD Line: 76
// <view> BBSIR
// <name> BBSIR </name>
// <item> SFDITEM_REG__BBSIR_rsv0 </item>
// <item> SFDITEM_REG__BBSIR_BB_SIR2 </item>
// <item> SFDITEM_REG__BBSIR_BB_SIR3 </item>
// </view>
//
// ------------------------------ Register Item Address: DMA_CN ---------------------------------
// SVD Line: 181
unsigned int DMA_CN __AT (0x40028000);
// ------------------------------- Field Item: DMA_CN_CH0_IEN -----------------------------------
// SVD Line: 186
// <item> SFDITEM_FIELD__DMA_CN_CH0_IEN
// <name> CH0_IEN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40028000) \nChannel 0 Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CN ) </loc>
// <o.0..0> CH0_IEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: DMA_CN_CH1_IEN -----------------------------------
// SVD Line: 204
// <item> SFDITEM_FIELD__DMA_CN_CH1_IEN
// <name> CH1_IEN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40028000) \nChannel 1 Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CN ) </loc>
// <o.1..1> CH1_IEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: DMA_CN_CH2_IEN -----------------------------------
// SVD Line: 210
// <item> SFDITEM_FIELD__DMA_CN_CH2_IEN
// <name> CH2_IEN </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40028000) \nChannel 2 Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CN ) </loc>
// <o.2..2> CH2_IEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: DMA_CN_CH3_IEN -----------------------------------
// SVD Line: 216
// <item> SFDITEM_FIELD__DMA_CN_CH3_IEN
// <name> CH3_IEN </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40028000) \nChannel 3 Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CN ) </loc>
// <o.3..3> CH3_IEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------------- Register RTree: DMA_CN -------------------------------------
// SVD Line: 181
// <rtree> SFDITEM_REG__DMA_CN
// <name> CN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028000) DMA Control Register. </i>
// <loc> ( (unsigned int)((DMA_CN >> 0) & 0xFFFFFFFF), ((DMA_CN = (DMA_CN & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CN_CH0_IEN </item>
// <item> SFDITEM_FIELD__DMA_CN_CH1_IEN </item>
// <item> SFDITEM_FIELD__DMA_CN_CH2_IEN </item>
// <item> SFDITEM_FIELD__DMA_CN_CH3_IEN </item>
// </rtree>
//
// ----------------------------- Register Item Address: DMA_INTR --------------------------------
// SVD Line: 224
unsigned int DMA_INTR __AT (0x40028004);
// ----------------------------- Field Item: DMA_INTR_CH0_IPEND ---------------------------------
// SVD Line: 230
// <item> SFDITEM_FIELD__DMA_INTR_CH0_IPEND
// <name> CH0_IPEND </name>
// <r>
// <i> [Bit 0] RO (@ 0x40028004) \nChannel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) DMA_INTR ) </loc>
// <o.0..0> CH0_IPEND
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ----------------------------- Field Item: DMA_INTR_CH1_IPEND ---------------------------------
// SVD Line: 249
// <item> SFDITEM_FIELD__DMA_INTR_CH1_IPEND
// <name> CH1_IPEND </name>
// <r>
// <i> [Bit 1] RO (@ 0x40028004) \nChannel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) DMA_INTR ) </loc>
// <o.1..1> CH1_IPEND
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ----------------------------- Field Item: DMA_INTR_CH2_IPEND ---------------------------------
// SVD Line: 254
// <item> SFDITEM_FIELD__DMA_INTR_CH2_IPEND
// <name> CH2_IPEND </name>
// <r>
// <i> [Bit 2] RO (@ 0x40028004) \nChannel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) DMA_INTR ) </loc>
// <o.2..2> CH2_IPEND
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ----------------------------- Field Item: DMA_INTR_CH3_IPEND ---------------------------------
// SVD Line: 259
// <item> SFDITEM_FIELD__DMA_INTR_CH3_IPEND
// <name> CH3_IPEND </name>
// <r>
// <i> [Bit 3] RO (@ 0x40028004) \nChannel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) DMA_INTR ) </loc>
// <o.3..3> CH3_IPEND
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------------- Register RTree: DMA_INTR ------------------------------------
// SVD Line: 224
// <rtree> SFDITEM_REG__DMA_INTR
// <name> INTR </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40028004) DMA Interrupt Register. </i>
// <loc> ( (unsigned int)((DMA_INTR >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__DMA_INTR_CH0_IPEND </item>
// <item> SFDITEM_FIELD__DMA_INTR_CH1_IPEND </item>
// <item> SFDITEM_FIELD__DMA_INTR_CH2_IPEND </item>
// <item> SFDITEM_FIELD__DMA_INTR_CH3_IPEND </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH0_CFG ----------------------------
// SVD Line: 274
unsigned int DMA_CH_CH_CH0_CFG __AT (0x40028200);
// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_CHEN -------------------------------
// SVD Line: 279
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CHEN
// <name> CHEN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40028200) \nChannel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.0..0> CHEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_RLDEN ------------------------------
// SVD Line: 297
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_RLDEN
// <name> RLDEN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40028200) \nReload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.1..1> RLDEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: DMA_CH_CH_CH0_CFG_PRI -------------------------------
// SVD Line: 315
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_PRI
// <name> PRI </name>
// <rw>
// <i> [Bits 3..2] RW (@ 0x40028200) \nDMA Priority.\n0 : high = Highest Priority.\n1 : medHigh = Medium High Priority.\n2 : medLow = Medium Low Priority.\n3 : low = Lowest Priority. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.3..2> PRI
// <0=> 0: high = Highest Priority.
// <1=> 1: medHigh = Medium High Priority.
// <2=> 2: medLow = Medium Low Priority.
// <3=> 3: low = Lowest Priority.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_REQSEL ------------------------------
// SVD Line: 343
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_REQSEL
// <name> REQSEL </name>
// <rw>
// <i> [Bits 9..4] RW (@ 0x40028200) \nRequest Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n0 : MEMTOMEM = Memory To Memory\n1 : SPI0RX = SPI0 RX\n2 : SPI1RX = SPI1 RX\n3 : Reserved - do not use\n4 : UART0RX = UART0 RX\n5 : UART1RX = UART1 RX\n6 : Reserved - do not use\n7 : I2C0RX = I2C0 RX\n8 : I2C1RX = I2C1 RX\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : SPI0TX = SPI0 TX\n34 : SPI1TX = SPI1 TX\n35 : Reserved - do not use\n36 : UART0TX = UART0 TX\n37 : UART1TX = UART1 TX\n38 : Reserved - do not use\n39 : I2C0TX = I2C0 TX\n40 : I2C1TX = I2C1 TX\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.9..4> REQSEL
// <0=> 0: MEMTOMEM = Memory To Memory
// <1=> 1: SPI0RX = SPI0 RX
// <2=> 2: SPI1RX = SPI1 RX
// <3=> 3:
// <4=> 4: UART0RX = UART0 RX
// <5=> 5: UART1RX = UART1 RX
// <6=> 6:
// <7=> 7: I2C0RX = I2C0 RX
// <8=> 8: I2C1RX = I2C1 RX
// <9=> 9:
// <10=> 10:
// <11=> 11:
// <12=> 12:
// <13=> 13:
// <14=> 14:
// <15=> 15:
// <16=> 16:
// <17=> 17:
// <18=> 18:
// <19=> 19:
// <20=> 20:
// <21=> 21:
// <22=> 22:
// <23=> 23:
// <24=> 24:
// <25=> 25:
// <26=> 26:
// <27=> 27:
// <28=> 28:
// <29=> 29:
// <30=> 30:
// <31=> 31:
// <32=> 32:
// <33=> 33: SPI0TX = SPI0 TX
// <34=> 34: SPI1TX = SPI1 TX
// <35=> 35:
// <36=> 36: UART0TX = UART0 TX
// <37=> 37: UART1TX = UART1 TX
// <38=> 38:
// <39=> 39: I2C0TX = I2C0 TX
// <40=> 40: I2C1TX = I2C1 TX
// <41=> 41:
// <42=> 42:
// <43=> 43:
// <44=> 44:
// <45=> 45:
// <46=> 46:
// <47=> 47:
// <48=> 48:
// <49=> 49:
// <50=> 50:
// <51=> 51:
// <52=> 52:
// <53=> 53:
// <54=> 54:
// <55=> 55:
// <56=> 56:
// <57=> 57:
// <58=> 58:
// <59=> 59:
// <60=> 60:
// <61=> 61:
// <62=> 62:
// <63=> 63:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_REQWAIT -----------------------------
// SVD Line: 416
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_REQWAIT
// <name> REQWAIT </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40028200) \nRequest Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.10..10> REQWAIT
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_TOSEL ------------------------------
// SVD Line: 434
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_TOSEL
// <name> TOSEL </name>
// <rw>
// <i> [Bits 13..11] RW (@ 0x40028200) \nTime-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.\n0 : to4 = Timeout of 3 to 4 prescale clocks.\n1 : to8 = Timeout of 7 to 8 prescale clocks.\n2 : to16 = Timeout of 15 to 16 prescale clocks.\n3 : to32 = Timeout of 31 to 32 prescale clocks.\n4 : to64 = Timeout of 63 to 64 prescale clocks.\n5 : to128 = Timeout of 127 to 128 prescale clocks.\n6 : to256 = Timeout of 255 to 256 prescale clocks.\n7 : to512 = Timeout of 511 to 512 prescale clocks. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.13..11> TOSEL
// <0=> 0: to4 = Timeout of 3 to 4 prescale clocks.
// <1=> 1: to8 = Timeout of 7 to 8 prescale clocks.
// <2=> 2: to16 = Timeout of 15 to 16 prescale clocks.
// <3=> 3: to32 = Timeout of 31 to 32 prescale clocks.
// <4=> 4: to64 = Timeout of 63 to 64 prescale clocks.
// <5=> 5: to128 = Timeout of 127 to 128 prescale clocks.
// <6=> 6: to256 = Timeout of 255 to 256 prescale clocks.
// <7=> 7: to512 = Timeout of 511 to 512 prescale clocks.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_PSSEL ------------------------------
// SVD Line: 482
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_PSSEL
// <name> PSSEL </name>
// <rw>
// <i> [Bits 15..14] RW (@ 0x40028200) \nPre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n0 : dis = Disable timer.\n1 : div256 = hclk / 256.\n2 : div64k = hclk / 64k.\n3 : div16M = hclk / 16M. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.15..14> PSSEL
// <0=> 0: dis = Disable timer.
// <1=> 1: div256 = hclk / 256.
// <2=> 2: div64k = hclk / 64k.
// <3=> 3: div16M = hclk / 16M.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_SRCWD ------------------------------
// SVD Line: 510
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_SRCWD
// <name> SRCWD </name>
// <rw>
// <i> [Bits 17..16] RW (@ 0x40028200) \nSource Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.17..16> SRCWD
// <0=> 0: byte = Byte.
// <1=> 1: halfWord = Halfword.
// <2=> 2: word = Word.
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_SRCINC ------------------------------
// SVD Line: 533
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_SRCINC
// <name> SRCINC </name>
// <rw>
// <i> [Bit 18] RW (@ 0x40028200) \nSource Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.18..18> SRCINC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_DSTWD ------------------------------
// SVD Line: 551
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_DSTWD
// <name> DSTWD </name>
// <rw>
// <i> [Bits 21..20] RW (@ 0x40028200) \nDestination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.21..20> DSTWD
// <0=> 0: byte = Byte.
// <1=> 1: halfWord = Halfword.
// <2=> 2: word = Word.
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_DSTINC ------------------------------
// SVD Line: 574
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_DSTINC
// <name> DSTINC </name>
// <rw>
// <i> [Bit 22] RW (@ 0x40028200) \nDestination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.22..22> DSTINC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_BRST -------------------------------
// SVD Line: 592
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_BRST
// <name> BRST </name>
// <rw>
// <i> [Bits 28..24] RW (@ 0x40028200) Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. </i>
// <edit>
// <loc> ( (unsigned char)((DMA_CH_CH_CH0_CFG >> 24) & 0x1F), ((DMA_CH_CH_CH0_CFG = (DMA_CH_CH_CH0_CFG & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_CHDIEN ------------------------------
// SVD Line: 598
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CHDIEN
// <name> CHDIEN </name>
// <rw>
// <i> [Bit 30] RW (@ 0x40028200) \nChannel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.30..30> CHDIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_CTZIEN ------------------------------
// SVD Line: 616
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CTZIEN
// <name> CTZIEN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40028200) \nCount-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CFG ) </loc>
// <o.31..31> CTZIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH0_CFG -------------------------------
// SVD Line: 274
// <rtree> SFDITEM_REG__DMA_CH_CH_CH0_CFG
// <name> CFG </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028200) DMA Channel Configuration Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_CFG >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_CFG = (DMA_CH_CH_CH0_CFG & ~(0xDF77FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF77FFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CHEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_RLDEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_PRI </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_REQSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_REQWAIT </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_TOSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_PSSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_SRCWD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_SRCINC </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_DSTWD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_DSTINC </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_BRST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CHDIEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CTZIEN </item>
// </rtree>
//
// ------------------------- Register Item Address: DMA_CH_CH_CH0_ST ----------------------------
// SVD Line: 636
unsigned int DMA_CH_CH_CH0_ST __AT (0x40028204);
// --------------------------- Field Item: DMA_CH_CH_CH0_ST_CH_ST -------------------------------
// SVD Line: 641
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_CH_ST
// <name> CH_ST </name>
// <r>
// <i> [Bit 0] RO (@ 0x40028204) \nChannel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_ST ) </loc>
// <o.0..0> CH_ST
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_ST_IPEND -------------------------------
// SVD Line: 660
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_IPEND
// <name> IPEND </name>
// <r>
// <i> [Bit 1] RO (@ 0x40028204) \nChannel Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_ST ) </loc>
// <o.1..1> IPEND
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_ST_CTZ_ST ------------------------------
// SVD Line: 679
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_CTZ_ST
// <name> CTZ_ST </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40028204) \nCount-to-Zero (CTZ) Status\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_ST ) </loc>
// <o.2..2> CTZ_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_ST_RLD_ST ------------------------------
// SVD Line: 709
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_RLD_ST
// <name> RLD_ST </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40028204) \nReload Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_ST ) </loc>
// <o.3..3> RLD_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH0_ST_BUS_ERR ------------------------------
// SVD Line: 737
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_BUS_ERR
// <name> BUS_ERR </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40028204) \nBus Error. Indicates that an AHB abort was received and the channel has been disabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_ST ) </loc>
// <o.4..4> BUS_ERR
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH0_ST_TO_ST -------------------------------
// SVD Line: 765
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_TO_ST
// <name> TO_ST </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40028204) \nTime-Out Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_ST ) </loc>
// <o.6..6> TO_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH0_ST --------------------------------
// SVD Line: 636
// <rtree> SFDITEM_REG__DMA_CH_CH_CH0_ST
// <name> ST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028204) DMA Channel Status Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_ST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_ST = (DMA_CH_CH_CH0_ST & ~(0x5CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5C) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_CH_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_IPEND </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_CTZ_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_RLD_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_BUS_ERR </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_ST_TO_ST </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH0_SRC ----------------------------
// SVD Line: 795
unsigned int DMA_CH_CH_CH0_SRC __AT (0x40028208);
// --------------------------- Field Item: DMA_CH_CH_CH0_SRC_ADDR -------------------------------
// SVD Line: 800
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_SRC_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028208) ADDR </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_SRC = (DMA_CH_CH_CH0_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH0_SRC -------------------------------
// SVD Line: 795
// <rtree> SFDITEM_REG__DMA_CH_CH_CH0_SRC
// <name> SRC </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028208) Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_SRC = (DMA_CH_CH_CH0_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_SRC_ADDR </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH0_DST ----------------------------
// SVD Line: 807
unsigned int DMA_CH_CH_CH0_DST __AT (0x4002820C);
// --------------------------- Field Item: DMA_CH_CH_CH0_DST_ADDR -------------------------------
// SVD Line: 812
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_DST_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002820C) ADDR </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_DST = (DMA_CH_CH_CH0_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH0_DST -------------------------------
// SVD Line: 807
// <rtree> SFDITEM_REG__DMA_CH_CH_CH0_DST
// <name> DST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002820C) Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_DST = (DMA_CH_CH_CH0_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_DST_ADDR </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH0_CNT ----------------------------
// SVD Line: 819
unsigned int DMA_CH_CH_CH0_CNT __AT (0x40028210);
// ---------------------------- Field Item: DMA_CH_CH_CH0_CNT_CNT -------------------------------
// SVD Line: 824
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_CNT
// <name> CNT </name>
// <rw>
// <i> [Bits 23..0] RW (@ 0x40028210) DMA Counter. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_CNT >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH0_CNT = (DMA_CH_CH_CH0_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH0_CNT -------------------------------
// SVD Line: 819
// <rtree> SFDITEM_REG__DMA_CH_CH_CH0_CNT
// <name> CNT </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028210) DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_CNT >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_CNT = (DMA_CH_CH_CH0_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_CNT </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH0_SRC_RLD --------------------------
// SVD Line: 832
unsigned int DMA_CH_CH_CH0_SRC_RLD __AT (0x40028214);
// ------------------------ Field Item: DMA_CH_CH_CH0_SRC_RLD_SRC_RLD ---------------------------
// SVD Line: 837
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_SRC_RLD_SRC_RLD
// <name> SRC_RLD </name>
// <rw>
// <i> [Bits 30..0] RW (@ 0x40028214) Source Address Reload Value. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_SRC_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH0_SRC_RLD = (DMA_CH_CH_CH0_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH0_SRC_RLD -----------------------------
// SVD Line: 832
// <rtree> SFDITEM_REG__DMA_CH_CH_CH0_SRC_RLD
// <name> SRC_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028214) Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_SRC_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_SRC_RLD = (DMA_CH_CH_CH0_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_SRC_RLD_SRC_RLD </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH0_DST_RLD --------------------------
// SVD Line: 845
unsigned int DMA_CH_CH_CH0_DST_RLD __AT (0x40028218);
// ------------------------ Field Item: DMA_CH_CH_CH0_DST_RLD_DST_RLD ---------------------------
// SVD Line: 850
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_DST_RLD_DST_RLD
// <name> DST_RLD </name>
// <rw>
// <i> [Bits 30..0] RW (@ 0x40028218) Destination Address Reload Value. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_DST_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH0_DST_RLD = (DMA_CH_CH_CH0_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH0_DST_RLD -----------------------------
// SVD Line: 845
// <rtree> SFDITEM_REG__DMA_CH_CH_CH0_DST_RLD
// <name> DST_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028218) Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_DST_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_DST_RLD = (DMA_CH_CH_CH0_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_DST_RLD_DST_RLD </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH0_CNT_RLD --------------------------
// SVD Line: 858
unsigned int DMA_CH_CH_CH0_CNT_RLD __AT (0x4002821C);
// ------------------------ Field Item: DMA_CH_CH_CH0_CNT_RLD_CNT_RLD ---------------------------
// SVD Line: 863
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_RLD_CNT_RLD
// <name> CNT_RLD </name>
// <rw>
// <i> [Bits 23..0] RW (@ 0x4002821C) Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_CNT_RLD >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH0_CNT_RLD = (DMA_CH_CH_CH0_CNT_RLD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------- Field Item: DMA_CH_CH_CH0_CNT_RLD_RLDEN ----------------------------
// SVD Line: 869
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_RLD_RLDEN
// <name> RLDEN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x4002821C) \nReload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH0_CNT_RLD ) </loc>
// <o.31..31> RLDEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH0_CNT_RLD -----------------------------
// SVD Line: 858
// <rtree> SFDITEM_REG__DMA_CH_CH_CH0_CNT_RLD
// <name> CNT_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002821C) DMA Channel Count Reload Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH0_CNT_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_CNT_RLD = (DMA_CH_CH_CH0_CNT_RLD & ~(0x80FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80FFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_RLD_CNT_RLD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_RLD_RLDEN </item>
// </rtree>
//
// ------------------------------ Cluster ITree: DMA_CH_CH_CH0 ----------------------------------
// SVD Line: 266
// <itree> SFDITEM_CLUST__DMA_CH_CH_CH0
// <name> [0] </name>
// <i> DMA Channel registers. </i>
// <item> SFDITEM_REG__DMA_CH_CH_CH0_CFG </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH0_ST </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH0_SRC </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH0_DST </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH0_CNT </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH0_SRC_RLD </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH0_DST_RLD </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH0_CNT_RLD </item>
// </itree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH1_CFG ----------------------------
// SVD Line: 274
unsigned int DMA_CH_CH_CH1_CFG __AT (0x40028204);
// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_CHEN -------------------------------
// SVD Line: 279
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CHEN
// <name> CHEN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40028204) \nChannel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.0..0> CHEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_RLDEN ------------------------------
// SVD Line: 297
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_RLDEN
// <name> RLDEN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40028204) \nReload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.1..1> RLDEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: DMA_CH_CH_CH1_CFG_PRI -------------------------------
// SVD Line: 315
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_PRI
// <name> PRI </name>
// <rw>
// <i> [Bits 3..2] RW (@ 0x40028204) \nDMA Priority.\n0 : high = Highest Priority.\n1 : medHigh = Medium High Priority.\n2 : medLow = Medium Low Priority.\n3 : low = Lowest Priority. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.3..2> PRI
// <0=> 0: high = Highest Priority.
// <1=> 1: medHigh = Medium High Priority.
// <2=> 2: medLow = Medium Low Priority.
// <3=> 3: low = Lowest Priority.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_REQSEL ------------------------------
// SVD Line: 343
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_REQSEL
// <name> REQSEL </name>
// <rw>
// <i> [Bits 9..4] RW (@ 0x40028204) \nRequest Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n0 : MEMTOMEM = Memory To Memory\n1 : SPI0RX = SPI0 RX\n2 : SPI1RX = SPI1 RX\n3 : Reserved - do not use\n4 : UART0RX = UART0 RX\n5 : UART1RX = UART1 RX\n6 : Reserved - do not use\n7 : I2C0RX = I2C0 RX\n8 : I2C1RX = I2C1 RX\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : SPI0TX = SPI0 TX\n34 : SPI1TX = SPI1 TX\n35 : Reserved - do not use\n36 : UART0TX = UART0 TX\n37 : UART1TX = UART1 TX\n38 : Reserved - do not use\n39 : I2C0TX = I2C0 TX\n40 : I2C1TX = I2C1 TX\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.9..4> REQSEL
// <0=> 0: MEMTOMEM = Memory To Memory
// <1=> 1: SPI0RX = SPI0 RX
// <2=> 2: SPI1RX = SPI1 RX
// <3=> 3:
// <4=> 4: UART0RX = UART0 RX
// <5=> 5: UART1RX = UART1 RX
// <6=> 6:
// <7=> 7: I2C0RX = I2C0 RX
// <8=> 8: I2C1RX = I2C1 RX
// <9=> 9:
// <10=> 10:
// <11=> 11:
// <12=> 12:
// <13=> 13:
// <14=> 14:
// <15=> 15:
// <16=> 16:
// <17=> 17:
// <18=> 18:
// <19=> 19:
// <20=> 20:
// <21=> 21:
// <22=> 22:
// <23=> 23:
// <24=> 24:
// <25=> 25:
// <26=> 26:
// <27=> 27:
// <28=> 28:
// <29=> 29:
// <30=> 30:
// <31=> 31:
// <32=> 32:
// <33=> 33: SPI0TX = SPI0 TX
// <34=> 34: SPI1TX = SPI1 TX
// <35=> 35:
// <36=> 36: UART0TX = UART0 TX
// <37=> 37: UART1TX = UART1 TX
// <38=> 38:
// <39=> 39: I2C0TX = I2C0 TX
// <40=> 40: I2C1TX = I2C1 TX
// <41=> 41:
// <42=> 42:
// <43=> 43:
// <44=> 44:
// <45=> 45:
// <46=> 46:
// <47=> 47:
// <48=> 48:
// <49=> 49:
// <50=> 50:
// <51=> 51:
// <52=> 52:
// <53=> 53:
// <54=> 54:
// <55=> 55:
// <56=> 56:
// <57=> 57:
// <58=> 58:
// <59=> 59:
// <60=> 60:
// <61=> 61:
// <62=> 62:
// <63=> 63:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_REQWAIT -----------------------------
// SVD Line: 416
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_REQWAIT
// <name> REQWAIT </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40028204) \nRequest Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.10..10> REQWAIT
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_TOSEL ------------------------------
// SVD Line: 434
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_TOSEL
// <name> TOSEL </name>
// <rw>
// <i> [Bits 13..11] RW (@ 0x40028204) \nTime-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.\n0 : to4 = Timeout of 3 to 4 prescale clocks.\n1 : to8 = Timeout of 7 to 8 prescale clocks.\n2 : to16 = Timeout of 15 to 16 prescale clocks.\n3 : to32 = Timeout of 31 to 32 prescale clocks.\n4 : to64 = Timeout of 63 to 64 prescale clocks.\n5 : to128 = Timeout of 127 to 128 prescale clocks.\n6 : to256 = Timeout of 255 to 256 prescale clocks.\n7 : to512 = Timeout of 511 to 512 prescale clocks. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.13..11> TOSEL
// <0=> 0: to4 = Timeout of 3 to 4 prescale clocks.
// <1=> 1: to8 = Timeout of 7 to 8 prescale clocks.
// <2=> 2: to16 = Timeout of 15 to 16 prescale clocks.
// <3=> 3: to32 = Timeout of 31 to 32 prescale clocks.
// <4=> 4: to64 = Timeout of 63 to 64 prescale clocks.
// <5=> 5: to128 = Timeout of 127 to 128 prescale clocks.
// <6=> 6: to256 = Timeout of 255 to 256 prescale clocks.
// <7=> 7: to512 = Timeout of 511 to 512 prescale clocks.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_PSSEL ------------------------------
// SVD Line: 482
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_PSSEL
// <name> PSSEL </name>
// <rw>
// <i> [Bits 15..14] RW (@ 0x40028204) \nPre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n0 : dis = Disable timer.\n1 : div256 = hclk / 256.\n2 : div64k = hclk / 64k.\n3 : div16M = hclk / 16M. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.15..14> PSSEL
// <0=> 0: dis = Disable timer.
// <1=> 1: div256 = hclk / 256.
// <2=> 2: div64k = hclk / 64k.
// <3=> 3: div16M = hclk / 16M.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_SRCWD ------------------------------
// SVD Line: 510
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_SRCWD
// <name> SRCWD </name>
// <rw>
// <i> [Bits 17..16] RW (@ 0x40028204) \nSource Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.17..16> SRCWD
// <0=> 0: byte = Byte.
// <1=> 1: halfWord = Halfword.
// <2=> 2: word = Word.
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_SRCINC ------------------------------
// SVD Line: 533
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_SRCINC
// <name> SRCINC </name>
// <rw>
// <i> [Bit 18] RW (@ 0x40028204) \nSource Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.18..18> SRCINC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_DSTWD ------------------------------
// SVD Line: 551
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_DSTWD
// <name> DSTWD </name>
// <rw>
// <i> [Bits 21..20] RW (@ 0x40028204) \nDestination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.21..20> DSTWD
// <0=> 0: byte = Byte.
// <1=> 1: halfWord = Halfword.
// <2=> 2: word = Word.
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_DSTINC ------------------------------
// SVD Line: 574
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_DSTINC
// <name> DSTINC </name>
// <rw>
// <i> [Bit 22] RW (@ 0x40028204) \nDestination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.22..22> DSTINC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_BRST -------------------------------
// SVD Line: 592
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_BRST
// <name> BRST </name>
// <rw>
// <i> [Bits 28..24] RW (@ 0x40028204) Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. </i>
// <edit>
// <loc> ( (unsigned char)((DMA_CH_CH_CH1_CFG >> 24) & 0x1F), ((DMA_CH_CH_CH1_CFG = (DMA_CH_CH_CH1_CFG & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_CHDIEN ------------------------------
// SVD Line: 598
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CHDIEN
// <name> CHDIEN </name>
// <rw>
// <i> [Bit 30] RW (@ 0x40028204) \nChannel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.30..30> CHDIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_CTZIEN ------------------------------
// SVD Line: 616
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CTZIEN
// <name> CTZIEN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40028204) \nCount-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CFG ) </loc>
// <o.31..31> CTZIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH1_CFG -------------------------------
// SVD Line: 274
// <rtree> SFDITEM_REG__DMA_CH_CH_CH1_CFG
// <name> CFG </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028204) DMA Channel Configuration Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_CFG >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_CFG = (DMA_CH_CH_CH1_CFG & ~(0xDF77FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF77FFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CHEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_RLDEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_PRI </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_REQSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_REQWAIT </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_TOSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_PSSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_SRCWD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_SRCINC </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_DSTWD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_DSTINC </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_BRST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CHDIEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CTZIEN </item>
// </rtree>
//
// ------------------------- Register Item Address: DMA_CH_CH_CH1_ST ----------------------------
// SVD Line: 636
unsigned int DMA_CH_CH_CH1_ST __AT (0x40028208);
// --------------------------- Field Item: DMA_CH_CH_CH1_ST_CH_ST -------------------------------
// SVD Line: 641
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_CH_ST
// <name> CH_ST </name>
// <r>
// <i> [Bit 0] RO (@ 0x40028208) \nChannel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_ST ) </loc>
// <o.0..0> CH_ST
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_ST_IPEND -------------------------------
// SVD Line: 660
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_IPEND
// <name> IPEND </name>
// <r>
// <i> [Bit 1] RO (@ 0x40028208) \nChannel Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_ST ) </loc>
// <o.1..1> IPEND
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_ST_CTZ_ST ------------------------------
// SVD Line: 679
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_CTZ_ST
// <name> CTZ_ST </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40028208) \nCount-to-Zero (CTZ) Status\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_ST ) </loc>
// <o.2..2> CTZ_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_ST_RLD_ST ------------------------------
// SVD Line: 709
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_RLD_ST
// <name> RLD_ST </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40028208) \nReload Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_ST ) </loc>
// <o.3..3> RLD_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH1_ST_BUS_ERR ------------------------------
// SVD Line: 737
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_BUS_ERR
// <name> BUS_ERR </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40028208) \nBus Error. Indicates that an AHB abort was received and the channel has been disabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_ST ) </loc>
// <o.4..4> BUS_ERR
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH1_ST_TO_ST -------------------------------
// SVD Line: 765
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_TO_ST
// <name> TO_ST </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40028208) \nTime-Out Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_ST ) </loc>
// <o.6..6> TO_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH1_ST --------------------------------
// SVD Line: 636
// <rtree> SFDITEM_REG__DMA_CH_CH_CH1_ST
// <name> ST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028208) DMA Channel Status Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_ST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_ST = (DMA_CH_CH_CH1_ST & ~(0x5CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5C) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_CH_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_IPEND </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_CTZ_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_RLD_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_BUS_ERR </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_ST_TO_ST </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH1_SRC ----------------------------
// SVD Line: 795
unsigned int DMA_CH_CH_CH1_SRC __AT (0x4002820C);
// --------------------------- Field Item: DMA_CH_CH_CH1_SRC_ADDR -------------------------------
// SVD Line: 800
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_SRC_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002820C) ADDR </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_SRC = (DMA_CH_CH_CH1_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH1_SRC -------------------------------
// SVD Line: 795
// <rtree> SFDITEM_REG__DMA_CH_CH_CH1_SRC
// <name> SRC </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002820C) Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_SRC = (DMA_CH_CH_CH1_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_SRC_ADDR </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH1_DST ----------------------------
// SVD Line: 807
unsigned int DMA_CH_CH_CH1_DST __AT (0x40028210);
// --------------------------- Field Item: DMA_CH_CH_CH1_DST_ADDR -------------------------------
// SVD Line: 812
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_DST_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028210) ADDR </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_DST = (DMA_CH_CH_CH1_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH1_DST -------------------------------
// SVD Line: 807
// <rtree> SFDITEM_REG__DMA_CH_CH_CH1_DST
// <name> DST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028210) Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_DST = (DMA_CH_CH_CH1_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_DST_ADDR </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH1_CNT ----------------------------
// SVD Line: 819
unsigned int DMA_CH_CH_CH1_CNT __AT (0x40028214);
// ---------------------------- Field Item: DMA_CH_CH_CH1_CNT_CNT -------------------------------
// SVD Line: 824
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_CNT
// <name> CNT </name>
// <rw>
// <i> [Bits 23..0] RW (@ 0x40028214) DMA Counter. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_CNT >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH1_CNT = (DMA_CH_CH_CH1_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH1_CNT -------------------------------
// SVD Line: 819
// <rtree> SFDITEM_REG__DMA_CH_CH_CH1_CNT
// <name> CNT </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028214) DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_CNT >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_CNT = (DMA_CH_CH_CH1_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_CNT </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH1_SRC_RLD --------------------------
// SVD Line: 832
unsigned int DMA_CH_CH_CH1_SRC_RLD __AT (0x40028218);
// ------------------------ Field Item: DMA_CH_CH_CH1_SRC_RLD_SRC_RLD ---------------------------
// SVD Line: 837
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_SRC_RLD_SRC_RLD
// <name> SRC_RLD </name>
// <rw>
// <i> [Bits 30..0] RW (@ 0x40028218) Source Address Reload Value. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_SRC_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH1_SRC_RLD = (DMA_CH_CH_CH1_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH1_SRC_RLD -----------------------------
// SVD Line: 832
// <rtree> SFDITEM_REG__DMA_CH_CH_CH1_SRC_RLD
// <name> SRC_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028218) Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_SRC_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_SRC_RLD = (DMA_CH_CH_CH1_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_SRC_RLD_SRC_RLD </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH1_DST_RLD --------------------------
// SVD Line: 845
unsigned int DMA_CH_CH_CH1_DST_RLD __AT (0x4002821C);
// ------------------------ Field Item: DMA_CH_CH_CH1_DST_RLD_DST_RLD ---------------------------
// SVD Line: 850
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_DST_RLD_DST_RLD
// <name> DST_RLD </name>
// <rw>
// <i> [Bits 30..0] RW (@ 0x4002821C) Destination Address Reload Value. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_DST_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH1_DST_RLD = (DMA_CH_CH_CH1_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH1_DST_RLD -----------------------------
// SVD Line: 845
// <rtree> SFDITEM_REG__DMA_CH_CH_CH1_DST_RLD
// <name> DST_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002821C) Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_DST_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_DST_RLD = (DMA_CH_CH_CH1_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_DST_RLD_DST_RLD </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH1_CNT_RLD --------------------------
// SVD Line: 858
unsigned int DMA_CH_CH_CH1_CNT_RLD __AT (0x40028220);
// ------------------------ Field Item: DMA_CH_CH_CH1_CNT_RLD_CNT_RLD ---------------------------
// SVD Line: 863
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_RLD_CNT_RLD
// <name> CNT_RLD </name>
// <rw>
// <i> [Bits 23..0] RW (@ 0x40028220) Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_CNT_RLD >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH1_CNT_RLD = (DMA_CH_CH_CH1_CNT_RLD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------- Field Item: DMA_CH_CH_CH1_CNT_RLD_RLDEN ----------------------------
// SVD Line: 869
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_RLD_RLDEN
// <name> RLDEN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40028220) \nReload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH1_CNT_RLD ) </loc>
// <o.31..31> RLDEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH1_CNT_RLD -----------------------------
// SVD Line: 858
// <rtree> SFDITEM_REG__DMA_CH_CH_CH1_CNT_RLD
// <name> CNT_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028220) DMA Channel Count Reload Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH1_CNT_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_CNT_RLD = (DMA_CH_CH_CH1_CNT_RLD & ~(0x80FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80FFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_RLD_CNT_RLD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_RLD_RLDEN </item>
// </rtree>
//
// ------------------------------ Cluster ITree: DMA_CH_CH_CH1 ----------------------------------
// SVD Line: 266
// <itree> SFDITEM_CLUST__DMA_CH_CH_CH1
// <name> [1] </name>
// <i> DMA Channel registers. </i>
// <item> SFDITEM_REG__DMA_CH_CH_CH1_CFG </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH1_ST </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH1_SRC </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH1_DST </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH1_CNT </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH1_SRC_RLD </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH1_DST_RLD </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH1_CNT_RLD </item>
// </itree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH2_CFG ----------------------------
// SVD Line: 274
unsigned int DMA_CH_CH_CH2_CFG __AT (0x40028208);
// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_CHEN -------------------------------
// SVD Line: 279
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CHEN
// <name> CHEN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40028208) \nChannel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.0..0> CHEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_RLDEN ------------------------------
// SVD Line: 297
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_RLDEN
// <name> RLDEN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40028208) \nReload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.1..1> RLDEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: DMA_CH_CH_CH2_CFG_PRI -------------------------------
// SVD Line: 315
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_PRI
// <name> PRI </name>
// <rw>
// <i> [Bits 3..2] RW (@ 0x40028208) \nDMA Priority.\n0 : high = Highest Priority.\n1 : medHigh = Medium High Priority.\n2 : medLow = Medium Low Priority.\n3 : low = Lowest Priority. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.3..2> PRI
// <0=> 0: high = Highest Priority.
// <1=> 1: medHigh = Medium High Priority.
// <2=> 2: medLow = Medium Low Priority.
// <3=> 3: low = Lowest Priority.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_REQSEL ------------------------------
// SVD Line: 343
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_REQSEL
// <name> REQSEL </name>
// <rw>
// <i> [Bits 9..4] RW (@ 0x40028208) \nRequest Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n0 : MEMTOMEM = Memory To Memory\n1 : SPI0RX = SPI0 RX\n2 : SPI1RX = SPI1 RX\n3 : Reserved - do not use\n4 : UART0RX = UART0 RX\n5 : UART1RX = UART1 RX\n6 : Reserved - do not use\n7 : I2C0RX = I2C0 RX\n8 : I2C1RX = I2C1 RX\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : SPI0TX = SPI0 TX\n34 : SPI1TX = SPI1 TX\n35 : Reserved - do not use\n36 : UART0TX = UART0 TX\n37 : UART1TX = UART1 TX\n38 : Reserved - do not use\n39 : I2C0TX = I2C0 TX\n40 : I2C1TX = I2C1 TX\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.9..4> REQSEL
// <0=> 0: MEMTOMEM = Memory To Memory
// <1=> 1: SPI0RX = SPI0 RX
// <2=> 2: SPI1RX = SPI1 RX
// <3=> 3:
// <4=> 4: UART0RX = UART0 RX
// <5=> 5: UART1RX = UART1 RX
// <6=> 6:
// <7=> 7: I2C0RX = I2C0 RX
// <8=> 8: I2C1RX = I2C1 RX
// <9=> 9:
// <10=> 10:
// <11=> 11:
// <12=> 12:
// <13=> 13:
// <14=> 14:
// <15=> 15:
// <16=> 16:
// <17=> 17:
// <18=> 18:
// <19=> 19:
// <20=> 20:
// <21=> 21:
// <22=> 22:
// <23=> 23:
// <24=> 24:
// <25=> 25:
// <26=> 26:
// <27=> 27:
// <28=> 28:
// <29=> 29:
// <30=> 30:
// <31=> 31:
// <32=> 32:
// <33=> 33: SPI0TX = SPI0 TX
// <34=> 34: SPI1TX = SPI1 TX
// <35=> 35:
// <36=> 36: UART0TX = UART0 TX
// <37=> 37: UART1TX = UART1 TX
// <38=> 38:
// <39=> 39: I2C0TX = I2C0 TX
// <40=> 40: I2C1TX = I2C1 TX
// <41=> 41:
// <42=> 42:
// <43=> 43:
// <44=> 44:
// <45=> 45:
// <46=> 46:
// <47=> 47:
// <48=> 48:
// <49=> 49:
// <50=> 50:
// <51=> 51:
// <52=> 52:
// <53=> 53:
// <54=> 54:
// <55=> 55:
// <56=> 56:
// <57=> 57:
// <58=> 58:
// <59=> 59:
// <60=> 60:
// <61=> 61:
// <62=> 62:
// <63=> 63:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_REQWAIT -----------------------------
// SVD Line: 416
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_REQWAIT
// <name> REQWAIT </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40028208) \nRequest Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.10..10> REQWAIT
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_TOSEL ------------------------------
// SVD Line: 434
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_TOSEL
// <name> TOSEL </name>
// <rw>
// <i> [Bits 13..11] RW (@ 0x40028208) \nTime-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.\n0 : to4 = Timeout of 3 to 4 prescale clocks.\n1 : to8 = Timeout of 7 to 8 prescale clocks.\n2 : to16 = Timeout of 15 to 16 prescale clocks.\n3 : to32 = Timeout of 31 to 32 prescale clocks.\n4 : to64 = Timeout of 63 to 64 prescale clocks.\n5 : to128 = Timeout of 127 to 128 prescale clocks.\n6 : to256 = Timeout of 255 to 256 prescale clocks.\n7 : to512 = Timeout of 511 to 512 prescale clocks. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.13..11> TOSEL
// <0=> 0: to4 = Timeout of 3 to 4 prescale clocks.
// <1=> 1: to8 = Timeout of 7 to 8 prescale clocks.
// <2=> 2: to16 = Timeout of 15 to 16 prescale clocks.
// <3=> 3: to32 = Timeout of 31 to 32 prescale clocks.
// <4=> 4: to64 = Timeout of 63 to 64 prescale clocks.
// <5=> 5: to128 = Timeout of 127 to 128 prescale clocks.
// <6=> 6: to256 = Timeout of 255 to 256 prescale clocks.
// <7=> 7: to512 = Timeout of 511 to 512 prescale clocks.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_PSSEL ------------------------------
// SVD Line: 482
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_PSSEL
// <name> PSSEL </name>
// <rw>
// <i> [Bits 15..14] RW (@ 0x40028208) \nPre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n0 : dis = Disable timer.\n1 : div256 = hclk / 256.\n2 : div64k = hclk / 64k.\n3 : div16M = hclk / 16M. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.15..14> PSSEL
// <0=> 0: dis = Disable timer.
// <1=> 1: div256 = hclk / 256.
// <2=> 2: div64k = hclk / 64k.
// <3=> 3: div16M = hclk / 16M.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_SRCWD ------------------------------
// SVD Line: 510
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_SRCWD
// <name> SRCWD </name>
// <rw>
// <i> [Bits 17..16] RW (@ 0x40028208) \nSource Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.17..16> SRCWD
// <0=> 0: byte = Byte.
// <1=> 1: halfWord = Halfword.
// <2=> 2: word = Word.
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_SRCINC ------------------------------
// SVD Line: 533
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_SRCINC
// <name> SRCINC </name>
// <rw>
// <i> [Bit 18] RW (@ 0x40028208) \nSource Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.18..18> SRCINC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_DSTWD ------------------------------
// SVD Line: 551
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_DSTWD
// <name> DSTWD </name>
// <rw>
// <i> [Bits 21..20] RW (@ 0x40028208) \nDestination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.21..20> DSTWD
// <0=> 0: byte = Byte.
// <1=> 1: halfWord = Halfword.
// <2=> 2: word = Word.
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_DSTINC ------------------------------
// SVD Line: 574
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_DSTINC
// <name> DSTINC </name>
// <rw>
// <i> [Bit 22] RW (@ 0x40028208) \nDestination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.22..22> DSTINC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_BRST -------------------------------
// SVD Line: 592
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_BRST
// <name> BRST </name>
// <rw>
// <i> [Bits 28..24] RW (@ 0x40028208) Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. </i>
// <edit>
// <loc> ( (unsigned char)((DMA_CH_CH_CH2_CFG >> 24) & 0x1F), ((DMA_CH_CH_CH2_CFG = (DMA_CH_CH_CH2_CFG & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_CHDIEN ------------------------------
// SVD Line: 598
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CHDIEN
// <name> CHDIEN </name>
// <rw>
// <i> [Bit 30] RW (@ 0x40028208) \nChannel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.30..30> CHDIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_CTZIEN ------------------------------
// SVD Line: 616
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CTZIEN
// <name> CTZIEN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40028208) \nCount-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CFG ) </loc>
// <o.31..31> CTZIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH2_CFG -------------------------------
// SVD Line: 274
// <rtree> SFDITEM_REG__DMA_CH_CH_CH2_CFG
// <name> CFG </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028208) DMA Channel Configuration Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_CFG >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_CFG = (DMA_CH_CH_CH2_CFG & ~(0xDF77FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF77FFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CHEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_RLDEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_PRI </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_REQSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_REQWAIT </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_TOSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_PSSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_SRCWD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_SRCINC </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_DSTWD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_DSTINC </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_BRST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CHDIEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CTZIEN </item>
// </rtree>
//
// ------------------------- Register Item Address: DMA_CH_CH_CH2_ST ----------------------------
// SVD Line: 636
unsigned int DMA_CH_CH_CH2_ST __AT (0x4002820C);
// --------------------------- Field Item: DMA_CH_CH_CH2_ST_CH_ST -------------------------------
// SVD Line: 641
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_CH_ST
// <name> CH_ST </name>
// <r>
// <i> [Bit 0] RO (@ 0x4002820C) \nChannel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_ST ) </loc>
// <o.0..0> CH_ST
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_ST_IPEND -------------------------------
// SVD Line: 660
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_IPEND
// <name> IPEND </name>
// <r>
// <i> [Bit 1] RO (@ 0x4002820C) \nChannel Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_ST ) </loc>
// <o.1..1> IPEND
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_ST_CTZ_ST ------------------------------
// SVD Line: 679
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_CTZ_ST
// <name> CTZ_ST </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4002820C) \nCount-to-Zero (CTZ) Status\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_ST ) </loc>
// <o.2..2> CTZ_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_ST_RLD_ST ------------------------------
// SVD Line: 709
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_RLD_ST
// <name> RLD_ST </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4002820C) \nReload Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_ST ) </loc>
// <o.3..3> RLD_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH2_ST_BUS_ERR ------------------------------
// SVD Line: 737
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_BUS_ERR
// <name> BUS_ERR </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4002820C) \nBus Error. Indicates that an AHB abort was received and the channel has been disabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_ST ) </loc>
// <o.4..4> BUS_ERR
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH2_ST_TO_ST -------------------------------
// SVD Line: 765
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_TO_ST
// <name> TO_ST </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4002820C) \nTime-Out Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_ST ) </loc>
// <o.6..6> TO_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH2_ST --------------------------------
// SVD Line: 636
// <rtree> SFDITEM_REG__DMA_CH_CH_CH2_ST
// <name> ST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002820C) DMA Channel Status Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_ST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_ST = (DMA_CH_CH_CH2_ST & ~(0x5CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5C) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_CH_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_IPEND </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_CTZ_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_RLD_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_BUS_ERR </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_ST_TO_ST </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH2_SRC ----------------------------
// SVD Line: 795
unsigned int DMA_CH_CH_CH2_SRC __AT (0x40028210);
// --------------------------- Field Item: DMA_CH_CH_CH2_SRC_ADDR -------------------------------
// SVD Line: 800
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_SRC_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028210) ADDR </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_SRC = (DMA_CH_CH_CH2_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH2_SRC -------------------------------
// SVD Line: 795
// <rtree> SFDITEM_REG__DMA_CH_CH_CH2_SRC
// <name> SRC </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028210) Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_SRC = (DMA_CH_CH_CH2_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_SRC_ADDR </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH2_DST ----------------------------
// SVD Line: 807
unsigned int DMA_CH_CH_CH2_DST __AT (0x40028214);
// --------------------------- Field Item: DMA_CH_CH_CH2_DST_ADDR -------------------------------
// SVD Line: 812
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_DST_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028214) ADDR </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_DST = (DMA_CH_CH_CH2_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH2_DST -------------------------------
// SVD Line: 807
// <rtree> SFDITEM_REG__DMA_CH_CH_CH2_DST
// <name> DST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028214) Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_DST = (DMA_CH_CH_CH2_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_DST_ADDR </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH2_CNT ----------------------------
// SVD Line: 819
unsigned int DMA_CH_CH_CH2_CNT __AT (0x40028218);
// ---------------------------- Field Item: DMA_CH_CH_CH2_CNT_CNT -------------------------------
// SVD Line: 824
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_CNT
// <name> CNT </name>
// <rw>
// <i> [Bits 23..0] RW (@ 0x40028218) DMA Counter. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_CNT >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH2_CNT = (DMA_CH_CH_CH2_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH2_CNT -------------------------------
// SVD Line: 819
// <rtree> SFDITEM_REG__DMA_CH_CH_CH2_CNT
// <name> CNT </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028218) DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_CNT >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_CNT = (DMA_CH_CH_CH2_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_CNT </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH2_SRC_RLD --------------------------
// SVD Line: 832
unsigned int DMA_CH_CH_CH2_SRC_RLD __AT (0x4002821C);
// ------------------------ Field Item: DMA_CH_CH_CH2_SRC_RLD_SRC_RLD ---------------------------
// SVD Line: 837
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_SRC_RLD_SRC_RLD
// <name> SRC_RLD </name>
// <rw>
// <i> [Bits 30..0] RW (@ 0x4002821C) Source Address Reload Value. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_SRC_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH2_SRC_RLD = (DMA_CH_CH_CH2_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH2_SRC_RLD -----------------------------
// SVD Line: 832
// <rtree> SFDITEM_REG__DMA_CH_CH_CH2_SRC_RLD
// <name> SRC_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002821C) Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_SRC_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_SRC_RLD = (DMA_CH_CH_CH2_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_SRC_RLD_SRC_RLD </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH2_DST_RLD --------------------------
// SVD Line: 845
unsigned int DMA_CH_CH_CH2_DST_RLD __AT (0x40028220);
// ------------------------ Field Item: DMA_CH_CH_CH2_DST_RLD_DST_RLD ---------------------------
// SVD Line: 850
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_DST_RLD_DST_RLD
// <name> DST_RLD </name>
// <rw>
// <i> [Bits 30..0] RW (@ 0x40028220) Destination Address Reload Value. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_DST_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH2_DST_RLD = (DMA_CH_CH_CH2_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH2_DST_RLD -----------------------------
// SVD Line: 845
// <rtree> SFDITEM_REG__DMA_CH_CH_CH2_DST_RLD
// <name> DST_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028220) Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_DST_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_DST_RLD = (DMA_CH_CH_CH2_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_DST_RLD_DST_RLD </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH2_CNT_RLD --------------------------
// SVD Line: 858
unsigned int DMA_CH_CH_CH2_CNT_RLD __AT (0x40028224);
// ------------------------ Field Item: DMA_CH_CH_CH2_CNT_RLD_CNT_RLD ---------------------------
// SVD Line: 863
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_RLD_CNT_RLD
// <name> CNT_RLD </name>
// <rw>
// <i> [Bits 23..0] RW (@ 0x40028224) Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_CNT_RLD >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH2_CNT_RLD = (DMA_CH_CH_CH2_CNT_RLD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------- Field Item: DMA_CH_CH_CH2_CNT_RLD_RLDEN ----------------------------
// SVD Line: 869
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_RLD_RLDEN
// <name> RLDEN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40028224) \nReload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH2_CNT_RLD ) </loc>
// <o.31..31> RLDEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH2_CNT_RLD -----------------------------
// SVD Line: 858
// <rtree> SFDITEM_REG__DMA_CH_CH_CH2_CNT_RLD
// <name> CNT_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028224) DMA Channel Count Reload Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH2_CNT_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_CNT_RLD = (DMA_CH_CH_CH2_CNT_RLD & ~(0x80FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80FFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_RLD_CNT_RLD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_RLD_RLDEN </item>
// </rtree>
//
// ------------------------------ Cluster ITree: DMA_CH_CH_CH2 ----------------------------------
// SVD Line: 266
// <itree> SFDITEM_CLUST__DMA_CH_CH_CH2
// <name> [2] </name>
// <i> DMA Channel registers. </i>
// <item> SFDITEM_REG__DMA_CH_CH_CH2_CFG </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH2_ST </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH2_SRC </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH2_DST </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH2_CNT </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH2_SRC_RLD </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH2_DST_RLD </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH2_CNT_RLD </item>
// </itree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH3_CFG ----------------------------
// SVD Line: 274
unsigned int DMA_CH_CH_CH3_CFG __AT (0x4002820C);
// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_CHEN -------------------------------
// SVD Line: 279
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CHEN
// <name> CHEN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4002820C) \nChannel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.0..0> CHEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_RLDEN ------------------------------
// SVD Line: 297
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_RLDEN
// <name> RLDEN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4002820C) \nReload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.1..1> RLDEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: DMA_CH_CH_CH3_CFG_PRI -------------------------------
// SVD Line: 315
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_PRI
// <name> PRI </name>
// <rw>
// <i> [Bits 3..2] RW (@ 0x4002820C) \nDMA Priority.\n0 : high = Highest Priority.\n1 : medHigh = Medium High Priority.\n2 : medLow = Medium Low Priority.\n3 : low = Lowest Priority. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.3..2> PRI
// <0=> 0: high = Highest Priority.
// <1=> 1: medHigh = Medium High Priority.
// <2=> 2: medLow = Medium Low Priority.
// <3=> 3: low = Lowest Priority.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_REQSEL ------------------------------
// SVD Line: 343
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_REQSEL
// <name> REQSEL </name>
// <rw>
// <i> [Bits 9..4] RW (@ 0x4002820C) \nRequest Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n0 : MEMTOMEM = Memory To Memory\n1 : SPI0RX = SPI0 RX\n2 : SPI1RX = SPI1 RX\n3 : Reserved - do not use\n4 : UART0RX = UART0 RX\n5 : UART1RX = UART1 RX\n6 : Reserved - do not use\n7 : I2C0RX = I2C0 RX\n8 : I2C1RX = I2C1 RX\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : SPI0TX = SPI0 TX\n34 : SPI1TX = SPI1 TX\n35 : Reserved - do not use\n36 : UART0TX = UART0 TX\n37 : UART1TX = UART1 TX\n38 : Reserved - do not use\n39 : I2C0TX = I2C0 TX\n40 : I2C1TX = I2C1 TX\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.9..4> REQSEL
// <0=> 0: MEMTOMEM = Memory To Memory
// <1=> 1: SPI0RX = SPI0 RX
// <2=> 2: SPI1RX = SPI1 RX
// <3=> 3:
// <4=> 4: UART0RX = UART0 RX
// <5=> 5: UART1RX = UART1 RX
// <6=> 6:
// <7=> 7: I2C0RX = I2C0 RX
// <8=> 8: I2C1RX = I2C1 RX
// <9=> 9:
// <10=> 10:
// <11=> 11:
// <12=> 12:
// <13=> 13:
// <14=> 14:
// <15=> 15:
// <16=> 16:
// <17=> 17:
// <18=> 18:
// <19=> 19:
// <20=> 20:
// <21=> 21:
// <22=> 22:
// <23=> 23:
// <24=> 24:
// <25=> 25:
// <26=> 26:
// <27=> 27:
// <28=> 28:
// <29=> 29:
// <30=> 30:
// <31=> 31:
// <32=> 32:
// <33=> 33: SPI0TX = SPI0 TX
// <34=> 34: SPI1TX = SPI1 TX
// <35=> 35:
// <36=> 36: UART0TX = UART0 TX
// <37=> 37: UART1TX = UART1 TX
// <38=> 38:
// <39=> 39: I2C0TX = I2C0 TX
// <40=> 40: I2C1TX = I2C1 TX
// <41=> 41:
// <42=> 42:
// <43=> 43:
// <44=> 44:
// <45=> 45:
// <46=> 46:
// <47=> 47:
// <48=> 48:
// <49=> 49:
// <50=> 50:
// <51=> 51:
// <52=> 52:
// <53=> 53:
// <54=> 54:
// <55=> 55:
// <56=> 56:
// <57=> 57:
// <58=> 58:
// <59=> 59:
// <60=> 60:
// <61=> 61:
// <62=> 62:
// <63=> 63:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_REQWAIT -----------------------------
// SVD Line: 416
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_REQWAIT
// <name> REQWAIT </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4002820C) \nRequest Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.10..10> REQWAIT
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_TOSEL ------------------------------
// SVD Line: 434
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_TOSEL
// <name> TOSEL </name>
// <rw>
// <i> [Bits 13..11] RW (@ 0x4002820C) \nTime-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.\n0 : to4 = Timeout of 3 to 4 prescale clocks.\n1 : to8 = Timeout of 7 to 8 prescale clocks.\n2 : to16 = Timeout of 15 to 16 prescale clocks.\n3 : to32 = Timeout of 31 to 32 prescale clocks.\n4 : to64 = Timeout of 63 to 64 prescale clocks.\n5 : to128 = Timeout of 127 to 128 prescale clocks.\n6 : to256 = Timeout of 255 to 256 prescale clocks.\n7 : to512 = Timeout of 511 to 512 prescale clocks. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.13..11> TOSEL
// <0=> 0: to4 = Timeout of 3 to 4 prescale clocks.
// <1=> 1: to8 = Timeout of 7 to 8 prescale clocks.
// <2=> 2: to16 = Timeout of 15 to 16 prescale clocks.
// <3=> 3: to32 = Timeout of 31 to 32 prescale clocks.
// <4=> 4: to64 = Timeout of 63 to 64 prescale clocks.
// <5=> 5: to128 = Timeout of 127 to 128 prescale clocks.
// <6=> 6: to256 = Timeout of 255 to 256 prescale clocks.
// <7=> 7: to512 = Timeout of 511 to 512 prescale clocks.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_PSSEL ------------------------------
// SVD Line: 482
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_PSSEL
// <name> PSSEL </name>
// <rw>
// <i> [Bits 15..14] RW (@ 0x4002820C) \nPre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n0 : dis = Disable timer.\n1 : div256 = hclk / 256.\n2 : div64k = hclk / 64k.\n3 : div16M = hclk / 16M. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.15..14> PSSEL
// <0=> 0: dis = Disable timer.
// <1=> 1: div256 = hclk / 256.
// <2=> 2: div64k = hclk / 64k.
// <3=> 3: div16M = hclk / 16M.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_SRCWD ------------------------------
// SVD Line: 510
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_SRCWD
// <name> SRCWD </name>
// <rw>
// <i> [Bits 17..16] RW (@ 0x4002820C) \nSource Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.17..16> SRCWD
// <0=> 0: byte = Byte.
// <1=> 1: halfWord = Halfword.
// <2=> 2: word = Word.
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_SRCINC ------------------------------
// SVD Line: 533
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_SRCINC
// <name> SRCINC </name>
// <rw>
// <i> [Bit 18] RW (@ 0x4002820C) \nSource Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.18..18> SRCINC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_DSTWD ------------------------------
// SVD Line: 551
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_DSTWD
// <name> DSTWD </name>
// <rw>
// <i> [Bits 21..20] RW (@ 0x4002820C) \nDestination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.21..20> DSTWD
// <0=> 0: byte = Byte.
// <1=> 1: halfWord = Halfword.
// <2=> 2: word = Word.
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_DSTINC ------------------------------
// SVD Line: 574
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_DSTINC
// <name> DSTINC </name>
// <rw>
// <i> [Bit 22] RW (@ 0x4002820C) \nDestination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.22..22> DSTINC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_BRST -------------------------------
// SVD Line: 592
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_BRST
// <name> BRST </name>
// <rw>
// <i> [Bits 28..24] RW (@ 0x4002820C) Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. </i>
// <edit>
// <loc> ( (unsigned char)((DMA_CH_CH_CH3_CFG >> 24) & 0x1F), ((DMA_CH_CH_CH3_CFG = (DMA_CH_CH_CH3_CFG & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_CHDIEN ------------------------------
// SVD Line: 598
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CHDIEN
// <name> CHDIEN </name>
// <rw>
// <i> [Bit 30] RW (@ 0x4002820C) \nChannel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.30..30> CHDIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_CTZIEN ------------------------------
// SVD Line: 616
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CTZIEN
// <name> CTZIEN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x4002820C) \nCount-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CFG ) </loc>
// <o.31..31> CTZIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH3_CFG -------------------------------
// SVD Line: 274
// <rtree> SFDITEM_REG__DMA_CH_CH_CH3_CFG
// <name> CFG </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002820C) DMA Channel Configuration Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_CFG >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_CFG = (DMA_CH_CH_CH3_CFG & ~(0xDF77FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF77FFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CHEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_RLDEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_PRI </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_REQSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_REQWAIT </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_TOSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_PSSEL </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_SRCWD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_SRCINC </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_DSTWD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_DSTINC </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_BRST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CHDIEN </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CTZIEN </item>
// </rtree>
//
// ------------------------- Register Item Address: DMA_CH_CH_CH3_ST ----------------------------
// SVD Line: 636
unsigned int DMA_CH_CH_CH3_ST __AT (0x40028210);
// --------------------------- Field Item: DMA_CH_CH_CH3_ST_CH_ST -------------------------------
// SVD Line: 641
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_CH_ST
// <name> CH_ST </name>
// <r>
// <i> [Bit 0] RO (@ 0x40028210) \nChannel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_ST ) </loc>
// <o.0..0> CH_ST
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_ST_IPEND -------------------------------
// SVD Line: 660
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_IPEND
// <name> IPEND </name>
// <r>
// <i> [Bit 1] RO (@ 0x40028210) \nChannel Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_ST ) </loc>
// <o.1..1> IPEND
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_ST_CTZ_ST ------------------------------
// SVD Line: 679
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_CTZ_ST
// <name> CTZ_ST </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40028210) \nCount-to-Zero (CTZ) Status\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_ST ) </loc>
// <o.2..2> CTZ_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_ST_RLD_ST ------------------------------
// SVD Line: 709
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_RLD_ST
// <name> RLD_ST </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40028210) \nReload Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_ST ) </loc>
// <o.3..3> RLD_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// -------------------------- Field Item: DMA_CH_CH_CH3_ST_BUS_ERR ------------------------------
// SVD Line: 737
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_BUS_ERR
// <name> BUS_ERR </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40028210) \nBus Error. Indicates that an AHB abort was received and the channel has been disabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_ST ) </loc>
// <o.4..4> BUS_ERR
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// --------------------------- Field Item: DMA_CH_CH_CH3_ST_TO_ST -------------------------------
// SVD Line: 765
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_TO_ST
// <name> TO_ST </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40028210) \nTime-Out Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_ST ) </loc>
// <o.6..6> TO_ST
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH3_ST --------------------------------
// SVD Line: 636
// <rtree> SFDITEM_REG__DMA_CH_CH_CH3_ST
// <name> ST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028210) DMA Channel Status Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_ST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_ST = (DMA_CH_CH_CH3_ST & ~(0x5CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5C) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_CH_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_IPEND </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_CTZ_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_RLD_ST </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_BUS_ERR </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_ST_TO_ST </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH3_SRC ----------------------------
// SVD Line: 795
unsigned int DMA_CH_CH_CH3_SRC __AT (0x40028214);
// --------------------------- Field Item: DMA_CH_CH_CH3_SRC_ADDR -------------------------------
// SVD Line: 800
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_SRC_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028214) ADDR </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_SRC = (DMA_CH_CH_CH3_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH3_SRC -------------------------------
// SVD Line: 795
// <rtree> SFDITEM_REG__DMA_CH_CH_CH3_SRC
// <name> SRC </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028214) Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_SRC = (DMA_CH_CH_CH3_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_SRC_ADDR </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH3_DST ----------------------------
// SVD Line: 807
unsigned int DMA_CH_CH_CH3_DST __AT (0x40028218);
// --------------------------- Field Item: DMA_CH_CH_CH3_DST_ADDR -------------------------------
// SVD Line: 812
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_DST_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028218) ADDR </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_DST = (DMA_CH_CH_CH3_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH3_DST -------------------------------
// SVD Line: 807
// <rtree> SFDITEM_REG__DMA_CH_CH_CH3_DST
// <name> DST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028218) Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_DST = (DMA_CH_CH_CH3_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_DST_ADDR </item>
// </rtree>
//
// ------------------------ Register Item Address: DMA_CH_CH_CH3_CNT ----------------------------
// SVD Line: 819
unsigned int DMA_CH_CH_CH3_CNT __AT (0x4002821C);
// ---------------------------- Field Item: DMA_CH_CH_CH3_CNT_CNT -------------------------------
// SVD Line: 824
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_CNT
// <name> CNT </name>
// <rw>
// <i> [Bits 23..0] RW (@ 0x4002821C) DMA Counter. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_CNT >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH3_CNT = (DMA_CH_CH_CH3_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: DMA_CH_CH_CH3_CNT -------------------------------
// SVD Line: 819
// <rtree> SFDITEM_REG__DMA_CH_CH_CH3_CNT
// <name> CNT </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002821C) DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_CNT >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_CNT = (DMA_CH_CH_CH3_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_CNT </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH3_SRC_RLD --------------------------
// SVD Line: 832
unsigned int DMA_CH_CH_CH3_SRC_RLD __AT (0x40028220);
// ------------------------ Field Item: DMA_CH_CH_CH3_SRC_RLD_SRC_RLD ---------------------------
// SVD Line: 837
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_SRC_RLD_SRC_RLD
// <name> SRC_RLD </name>
// <rw>
// <i> [Bits 30..0] RW (@ 0x40028220) Source Address Reload Value. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_SRC_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH3_SRC_RLD = (DMA_CH_CH_CH3_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH3_SRC_RLD -----------------------------
// SVD Line: 832
// <rtree> SFDITEM_REG__DMA_CH_CH_CH3_SRC_RLD
// <name> SRC_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028220) Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_SRC_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_SRC_RLD = (DMA_CH_CH_CH3_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_SRC_RLD_SRC_RLD </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH3_DST_RLD --------------------------
// SVD Line: 845
unsigned int DMA_CH_CH_CH3_DST_RLD __AT (0x40028224);
// ------------------------ Field Item: DMA_CH_CH_CH3_DST_RLD_DST_RLD ---------------------------
// SVD Line: 850
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_DST_RLD_DST_RLD
// <name> DST_RLD </name>
// <rw>
// <i> [Bits 30..0] RW (@ 0x40028224) Destination Address Reload Value. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_DST_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH3_DST_RLD = (DMA_CH_CH_CH3_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH3_DST_RLD -----------------------------
// SVD Line: 845
// <rtree> SFDITEM_REG__DMA_CH_CH_CH3_DST_RLD
// <name> DST_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028224) Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_DST_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_DST_RLD = (DMA_CH_CH_CH3_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_DST_RLD_DST_RLD </item>
// </rtree>
//
// ---------------------- Register Item Address: DMA_CH_CH_CH3_CNT_RLD --------------------------
// SVD Line: 858
unsigned int DMA_CH_CH_CH3_CNT_RLD __AT (0x40028228);
// ------------------------ Field Item: DMA_CH_CH_CH3_CNT_RLD_CNT_RLD ---------------------------
// SVD Line: 863
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_RLD_CNT_RLD
// <name> CNT_RLD </name>
// <rw>
// <i> [Bits 23..0] RW (@ 0x40028228) Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. </i>
// <edit>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_CNT_RLD >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH3_CNT_RLD = (DMA_CH_CH_CH3_CNT_RLD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------- Field Item: DMA_CH_CH_CH3_CNT_RLD_RLDEN ----------------------------
// SVD Line: 869
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_RLD_RLDEN
// <name> RLDEN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40028228) \nReload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) DMA_CH_CH_CH3_CNT_RLD ) </loc>
// <o.31..31> RLDEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------- Register RTree: DMA_CH_CH_CH3_CNT_RLD -----------------------------
// SVD Line: 858
// <rtree> SFDITEM_REG__DMA_CH_CH_CH3_CNT_RLD
// <name> CNT_RLD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40028228) DMA Channel Count Reload Register. </i>
// <loc> ( (unsigned int)((DMA_CH_CH_CH3_CNT_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_CNT_RLD = (DMA_CH_CH_CH3_CNT_RLD & ~(0x80FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80FFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_RLD_CNT_RLD </item>
// <item> SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_RLD_RLDEN </item>
// </rtree>
//
// ------------------------------ Cluster ITree: DMA_CH_CH_CH3 ----------------------------------
// SVD Line: 266
// <itree> SFDITEM_CLUST__DMA_CH_CH_CH3
// <name> [3] </name>
// <i> DMA Channel registers. </i>
// <item> SFDITEM_REG__DMA_CH_CH_CH3_CFG </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH3_ST </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH3_SRC </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH3_DST </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH3_CNT </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH3_SRC_RLD </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH3_DST_RLD </item>
// <item> SFDITEM_REG__DMA_CH_CH_CH3_CNT_RLD </item>
// </itree>
//
// ------------------------------- Cluster Array ITree: DMA_CH ----------------------------------
// SVD Line: 266
// <itree> SFDITEM_CLUST__DMA_CH
// <name> CH </name>
// <i> DMA Channel registers. </i>
// <item> SFDITEM_CLUST__DMA_CH_CH_CH0 </item>
// <item> SFDITEM_CLUST__DMA_CH_CH_CH1 </item>
// <item> SFDITEM_CLUST__DMA_CH_CH_CH2 </item>
// <item> SFDITEM_CLUST__DMA_CH_CH_CH3 </item>
// </itree>
//
// ---------------------------------- Peripheral View: DMA --------------------------------------
// SVD Line: 106
// <view> DMA
// <name> DMA </name>
// <item> SFDITEM_REG__DMA_CN </item>
// <item> SFDITEM_REG__DMA_INTR </item>
// <item> SFDITEM_CLUST__DMA_CH </item>
// </view>
//
// ----------------------------- Register Item Address: FLC_ADDR --------------------------------
// SVD Line: 909
unsigned int FLC_ADDR __AT (0x40029000);
// -------------------------------- Field Item: FLC_ADDR_ADDR -----------------------------------
// SVD Line: 914
// <item> SFDITEM_FIELD__FLC_ADDR_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029000) Address for next operation. </i>
// <edit>
// <loc> ( (unsigned int)((FLC_ADDR >> 0) & 0xFFFFFFFF), ((FLC_ADDR = (FLC_ADDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: FLC_ADDR ------------------------------------
// SVD Line: 909
// <rtree> SFDITEM_REG__FLC_ADDR
// <name> ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029000) Flash Write Address. </i>
// <loc> ( (unsigned int)((FLC_ADDR >> 0) & 0xFFFFFFFF), ((FLC_ADDR = (FLC_ADDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_ADDR_ADDR </item>
// </rtree>
//
// ---------------------------- Register Item Address: FLC_CLKDIV -------------------------------
// SVD Line: 922
unsigned int FLC_CLKDIV __AT (0x40029004);
// ------------------------------ Field Item: FLC_CLKDIV_CLKDIV ---------------------------------
// SVD Line: 928
// <item> SFDITEM_FIELD__FLC_CLKDIV_CLKDIV
// <name> CLKDIV </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40029004) Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. </i>
// <edit>
// <loc> ( (unsigned char)((FLC_CLKDIV >> 0) & 0xFF), ((FLC_CLKDIV = (FLC_CLKDIV & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: FLC_CLKDIV -----------------------------------
// SVD Line: 922
// <rtree> SFDITEM_REG__FLC_CLKDIV
// <name> CLKDIV </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029004) Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. </i>
// <loc> ( (unsigned int)((FLC_CLKDIV >> 0) & 0xFFFFFFFF), ((FLC_CLKDIV = (FLC_CLKDIV & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_CLKDIV_CLKDIV </item>
// </rtree>
//
// ------------------------------ Register Item Address: FLC_CN ---------------------------------
// SVD Line: 936
unsigned int FLC_CN __AT (0x40029008);
// ---------------------------------- Field Item: FLC_CN_WR -------------------------------------
// SVD Line: 941
// <item> SFDITEM_FIELD__FLC_CN_WR
// <name> WR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40029008) \nWrite. This bit is automatically cleared after the operation.\n0 : complete = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) FLC_CN ) </loc>
// <o.0..0> WR
// <0=> 0: complete = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// ---------------------------------- Field Item: FLC_CN_ME -------------------------------------
// SVD Line: 959
// <item> SFDITEM_FIELD__FLC_CN_ME
// <name> ME </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40029008) \nMass Erase. This bit is automatically cleared after the operation.\n0 : complete = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) FLC_CN ) </loc>
// <o.1..1> ME
// <0=> 0: complete = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// --------------------------------- Field Item: FLC_CN_PGE -------------------------------------
// SVD Line: 965
// <item> SFDITEM_FIELD__FLC_CN_PGE
// <name> PGE </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40029008) \nPage Erase. This bit is automatically cleared after the operation.\n0 : complete = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) FLC_CN ) </loc>
// <o.2..2> PGE
// <0=> 0: complete = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// --------------------------------- Field Item: FLC_CN_WDTH ------------------------------------
// SVD Line: 971
// <item> SFDITEM_FIELD__FLC_CN_WDTH
// <name> WDTH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40029008) \nData Width. This bits selects write data width.\n0 : size128 = 128-bit.\n1 : size32 = 32-bit. </i>
// <combo>
// <loc> ( (unsigned int) FLC_CN ) </loc>
// <o.4..4> WDTH
// <0=> 0: size128 = 128-bit.
// <1=> 1: size32 = 32-bit.
// </combo>
// </item>
//
// ------------------------------ Field Item: FLC_CN_ERASE_CODE ---------------------------------
// SVD Line: 989
// <item> SFDITEM_FIELD__FLC_CN_ERASE_CODE
// <name> ERASE_CODE </name>
// <rw>
// <i> [Bits 15..8] RW (@ 0x40029008) Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. </i>
// <edit>
// <loc> ( (unsigned char)((FLC_CN >> 8) & 0xFF), ((FLC_CN = (FLC_CN & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------------------- Field Item: FLC_CN_PEND ------------------------------------
// SVD Line: 1012
// <item> SFDITEM_FIELD__FLC_CN_PEND
// <name> PEND </name>
// <r>
// <i> [Bit 24] RO (@ 0x40029008) \nFlash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.\n0 : idle = Idle.\n1 : busy = Busy. </i>
// <combo>
// <loc> ( (unsigned int) FLC_CN ) </loc>
// <o.24..24> PEND
// <0=> 0: idle = Idle.
// <1=> 1: busy = Busy.
// </combo>
// </item>
//
// --------------------------------- Field Item: FLC_CN_LVE -------------------------------------
// SVD Line: 1031
// <item> SFDITEM_FIELD__FLC_CN_LVE
// <name> LVE </name>
// <r>
// <i> [Bit 25] RO (@ 0x40029008) \nLow Voltage Read Enable\n0 : dis = Disabled\n1 : en = Enabled </i>
// <combo>
// <loc> ( (unsigned int) FLC_CN ) </loc>
// <o.25..25> LVE
// <0=> 0: dis = Disabled
// <1=> 1: en = Enabled
// </combo>
// </item>
//
// --------------------------------- Field Item: FLC_CN_BRST ------------------------------------
// SVD Line: 1052
// <item> SFDITEM_FIELD__FLC_CN_BRST
// <name> BRST </name>
// <rw>
// <i> [Bit 27] RW (@ 0x40029008) \nBurst Mode Enable.\n0 : disable = Disable\n1 : enable = Enable </i>
// <combo>
// <loc> ( (unsigned int) FLC_CN ) </loc>
// <o.27..27> BRST
// <0=> 0: disable = Disable
// <1=> 1: enable = Enable
// </combo>
// </item>
//
// -------------------------------- Field Item: FLC_CN_UNLOCK -----------------------------------
// SVD Line: 1070
// <item> SFDITEM_FIELD__FLC_CN_UNLOCK
// <name> UNLOCK </name>
// <rw>
// <i> [Bits 31..28] RW (@ 0x40029008) \nFlash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.\n0 : Reserved - do not use\n1 : Reserved - do not use\n2 : unlocked = Flash Unlocked\n3 : locked = Flash Locked\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) FLC_CN ) </loc>
// <o.31..28> UNLOCK
// <0=> 0:
// <1=> 1:
// <2=> 2: unlocked = Flash Unlocked
// <3=> 3: locked = Flash Locked
// <4=> 4:
// <5=> 5:
// <6=> 6:
// <7=> 7:
// <8=> 8:
// <9=> 9:
// <10=> 10:
// <11=> 11:
// <12=> 12:
// <13=> 13:
// <14=> 14:
// <15=> 15:
// </combo>
// </item>
//
// --------------------------------- Register RTree: FLC_CN -------------------------------------
// SVD Line: 936
// <rtree> SFDITEM_REG__FLC_CN
// <name> CN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029008) Flash Control Register. </i>
// <loc> ( (unsigned int)((FLC_CN >> 0) & 0xFFFFFFFF), ((FLC_CN = (FLC_CN & ~(0xF800FF17UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF800FF17) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_CN_WR </item>
// <item> SFDITEM_FIELD__FLC_CN_ME </item>
// <item> SFDITEM_FIELD__FLC_CN_PGE </item>
// <item> SFDITEM_FIELD__FLC_CN_WDTH </item>
// <item> SFDITEM_FIELD__FLC_CN_ERASE_CODE </item>
// <item> SFDITEM_FIELD__FLC_CN_PEND </item>
// <item> SFDITEM_FIELD__FLC_CN_LVE </item>
// <item> SFDITEM_FIELD__FLC_CN_BRST </item>
// <item> SFDITEM_FIELD__FLC_CN_UNLOCK </item>
// </rtree>
//
// ----------------------------- Register Item Address: FLC_INTR --------------------------------
// SVD Line: 1090
unsigned int FLC_INTR __AT (0x40029024);
// -------------------------------- Field Item: FLC_INTR_DONE -----------------------------------
// SVD Line: 1095
// <item> SFDITEM_FIELD__FLC_INTR_DONE
// <name> DONE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40029024) \nFlash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.\n0 : inactive = No interrupt is pending\n1 : pending = An interrupt is pending </i>
// <combo>
// <loc> ( (unsigned int) FLC_INTR ) </loc>
// <o.0..0> DONE
// <0=> 0: inactive = No interrupt is pending
// <1=> 1: pending = An interrupt is pending
// </combo>
// </item>
//
// --------------------------------- Field Item: FLC_INTR_AF ------------------------------------
// SVD Line: 1113
// <item> SFDITEM_FIELD__FLC_INTR_AF
// <name> AF </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40029024) \nFlash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.\n0 : noError = No Failure.\n1 : error = Failure occurs. </i>
// <combo>
// <loc> ( (unsigned int) FLC_INTR ) </loc>
// <o.1..1> AF
// <0=> 0: noError = No Failure.
// <1=> 1: error = Failure occurs.
// </combo>
// </item>
//
// ------------------------------- Field Item: FLC_INTR_DONEIE ----------------------------------
// SVD Line: 1131
// <item> SFDITEM_FIELD__FLC_INTR_DONEIE
// <name> DONEIE </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40029024) \nFlash Done Interrupt Enable.\n0 : disable = Disable.\n1 : enable = Enable. </i>
// <combo>
// <loc> ( (unsigned int) FLC_INTR ) </loc>
// <o.8..8> DONEIE
// <0=> 0: disable = Disable.
// <1=> 1: enable = Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: FLC_INTR_AFIE -----------------------------------
// SVD Line: 1149
// <item> SFDITEM_FIELD__FLC_INTR_AFIE
// <name> AFIE </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40029024) \nFlash Done Interrupt Enable.\n0 : disable = Disable.\n1 : enable = Enable. </i>
// <combo>
// <loc> ( (unsigned int) FLC_INTR ) </loc>
// <o.9..9> AFIE
// <0=> 0: disable = Disable.
// <1=> 1: enable = Enable.
// </combo>
// </item>
//
// -------------------------------- Register RTree: FLC_INTR ------------------------------------
// SVD Line: 1090
// <rtree> SFDITEM_REG__FLC_INTR
// <name> INTR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029024) Flash Interrupt Register. </i>
// <loc> ( (unsigned int)((FLC_INTR >> 0) & 0xFFFFFFFF), ((FLC_INTR = (FLC_INTR & ~(0x303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x303) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_INTR_DONE </item>
// <item> SFDITEM_FIELD__FLC_INTR_AF </item>
// <item> SFDITEM_FIELD__FLC_INTR_DONEIE </item>
// <item> SFDITEM_FIELD__FLC_INTR_AFIE </item>
// </rtree>
//
// -------------------- Register Array Item Address: FLC_DATA_DATA_DATA0 ------------------------
// SVD Line: 1156
unsigned int FLC_DATA_DATA_DATA0 __AT (0x40029030);
// -------------------------- Field Item: FLC_DATA_DATA_DATA0_DATA ------------------------------
// SVD Line: 1163
// <item> SFDITEM_FIELD__FLC_DATA_DATA_DATA0_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029030) Data next operation. </i>
// <edit>
// <loc> ( (unsigned int)((FLC_DATA_DATA_DATA0 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA0 = (FLC_DATA_DATA_DATA0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------ Register Array RTree: FLC_DATA_DATA_DATA0 ---------------------------
// SVD Line: 1156
// <rtree> SFDITEM_REG__FLC_DATA_DATA_DATA0
// <name> [0] </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029030) Flash Write Data. </i>
// <loc> ( (unsigned int)((FLC_DATA_DATA_DATA0 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA0 = (FLC_DATA_DATA_DATA0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_DATA_DATA_DATA0_DATA </item>
// </rtree>
//
// -------------------- Register Array Item Address: FLC_DATA_DATA_DATA1 ------------------------
// SVD Line: 1156
unsigned int FLC_DATA_DATA_DATA1 __AT (0x40029034);
// -------------------------- Field Item: FLC_DATA_DATA_DATA1_DATA ------------------------------
// SVD Line: 1163
// <item> SFDITEM_FIELD__FLC_DATA_DATA_DATA1_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029034) Data next operation. </i>
// <edit>
// <loc> ( (unsigned int)((FLC_DATA_DATA_DATA1 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA1 = (FLC_DATA_DATA_DATA1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------ Register Array RTree: FLC_DATA_DATA_DATA1 ---------------------------
// SVD Line: 1156
// <rtree> SFDITEM_REG__FLC_DATA_DATA_DATA1
// <name> [1] </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029034) Flash Write Data. </i>
// <loc> ( (unsigned int)((FLC_DATA_DATA_DATA1 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA1 = (FLC_DATA_DATA_DATA1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_DATA_DATA_DATA1_DATA </item>
// </rtree>
//
// -------------------- Register Array Item Address: FLC_DATA_DATA_DATA2 ------------------------
// SVD Line: 1156
unsigned int FLC_DATA_DATA_DATA2 __AT (0x40029038);
// -------------------------- Field Item: FLC_DATA_DATA_DATA2_DATA ------------------------------
// SVD Line: 1163
// <item> SFDITEM_FIELD__FLC_DATA_DATA_DATA2_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029038) Data next operation. </i>
// <edit>
// <loc> ( (unsigned int)((FLC_DATA_DATA_DATA2 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA2 = (FLC_DATA_DATA_DATA2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------ Register Array RTree: FLC_DATA_DATA_DATA2 ---------------------------
// SVD Line: 1156
// <rtree> SFDITEM_REG__FLC_DATA_DATA_DATA2
// <name> [2] </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40029038) Flash Write Data. </i>
// <loc> ( (unsigned int)((FLC_DATA_DATA_DATA2 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA2 = (FLC_DATA_DATA_DATA2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_DATA_DATA_DATA2_DATA </item>
// </rtree>
//
// -------------------- Register Array Item Address: FLC_DATA_DATA_DATA3 ------------------------
// SVD Line: 1156
unsigned int FLC_DATA_DATA_DATA3 __AT (0x4002903C);
// -------------------------- Field Item: FLC_DATA_DATA_DATA3_DATA ------------------------------
// SVD Line: 1163
// <item> SFDITEM_FIELD__FLC_DATA_DATA_DATA3_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002903C) Data next operation. </i>
// <edit>
// <loc> ( (unsigned int)((FLC_DATA_DATA_DATA3 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA3 = (FLC_DATA_DATA_DATA3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------ Register Array RTree: FLC_DATA_DATA_DATA3 ---------------------------
// SVD Line: 1156
// <rtree> SFDITEM_REG__FLC_DATA_DATA_DATA3
// <name> [3] </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002903C) Flash Write Data. </i>
// <loc> ( (unsigned int)((FLC_DATA_DATA_DATA3 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA3 = (FLC_DATA_DATA_DATA3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_DATA_DATA_DATA3_DATA </item>
// </rtree>
//
// ----------------------------- Register Array ITree: FLC_DATA ---------------------------------
// SVD Line: 1156
// <itree> SFDITEM_REG__FLC_DATA
// <name> DATA </name>
// <i> Flash Write Data. </i>
// <item> SFDITEM_REG__FLC_DATA_DATA_DATA0 </item>
// <item> SFDITEM_REG__FLC_DATA_DATA_DATA1 </item>
// <item> SFDITEM_REG__FLC_DATA_DATA_DATA2 </item>
// <item> SFDITEM_REG__FLC_DATA_DATA_DATA3 </item>
// </itree>
//
// ---------------------------- Register Item Address: FLC_ACNTL --------------------------------
// SVD Line: 1171
unsigned int FLC_ACNTL __AT (0x40029040);
// ------------------------------- Field Item: FLC_ACNTL_ACNTL ----------------------------------
// SVD Line: 1177
// <item> SFDITEM_FIELD__FLC_ACNTL_ACNTL
// <name> ACNTL </name>
// <w>
// <i> [Bits 31..0] WO (@ 0x40029040) Access control. </i>
// <edit>
// <loc> ( (unsigned int)((FLC_ACNTL >> 0) & 0x0), ((FLC_ACNTL = (FLC_ACNTL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: FLC_ACNTL -----------------------------------
// SVD Line: 1171
// <rtree> SFDITEM_REG__FLC_ACNTL
// <name> ACNTL </name>
// <w>
// <i> [Bits 31..0] WO (@ 0x40029040) Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. </i>
// <loc> ( (unsigned int)((FLC_ACNTL >> 0) & 0xFFFFFFFF), ((FLC_ACNTL = (FLC_ACNTL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__FLC_ACNTL_ACNTL </item>
// </rtree>
//
// ---------------------------------- Peripheral View: FLC --------------------------------------
// SVD Line: 893
// <view> FLC
// <name> FLC </name>
// <item> SFDITEM_REG__FLC_ADDR </item>
// <item> SFDITEM_REG__FLC_CLKDIV </item>
// <item> SFDITEM_REG__FLC_CN </item>
// <item> SFDITEM_REG__FLC_INTR </item>
// <item> SFDITEM_REG__FLC_DATA </item>
// <item> SFDITEM_REG__FLC_ACNTL </item>
// </view>
//
// ----------------------------- Register Item Address: GCR_SCON --------------------------------
// SVD Line: 1198
unsigned int GCR_SCON __AT (0x40000000);
// ------------------------------ Field Item: GCR_SCON_SBUSARB ----------------------------------
// SVD Line: 1204
// <item> SFDITEM_FIELD__GCR_SCON_SBUSARB
// <name> SBUSARB </name>
// <rw>
// <i> [Bits 2..1] RW (@ 0x40000000) \nSystem bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.\n0 : fix = Fixed Burst abritration.\n1 : round = Round-robin scheme.\n2 : Reserved - do not use\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) GCR_SCON ) </loc>
// <o.2..1> SBUSARB
// <0=> 0: fix = Fixed Burst abritration.
// <1=> 1: round = Round-robin scheme.
// <2=> 2:
// <3=> 3:
// </combo>
// </item>
//
// -------------------------- Field Item: GCR_SCON_FLASH_PAGE_FLIP ------------------------------
// SVD Line: 1222
// <item> SFDITEM_FIELD__GCR_SCON_FLASH_PAGE_FLIP
// <name> FLASH_PAGE_FLIP </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40000000) \nFlips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.\n0 : normal = Physical layout matches logical layout.\n1 : swapped = Bottom half mapped to logical top half and vice versa. </i>
// <combo>
// <loc> ( (unsigned int) GCR_SCON ) </loc>
// <o.4..4> FLASH_PAGE_FLIP
// <0=> 0: normal = Physical layout matches logical layout.
// <1=> 1: swapped = Bottom half mapped to logical top half and vice versa.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_SCON_FPU_DIS ----------------------------------
// SVD Line: 1240
// <item> SFDITEM_FIELD__GCR_SCON_FPU_DIS
// <name> FPU_DIS </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40000000) \nFloating Point Unit Disable\n0 : enable = enable Floating point unit\n1 : disable = disable floating point unit </i>
// <combo>
// <loc> ( (unsigned int) GCR_SCON ) </loc>
// <o.5..5> FPU_DIS
// <0=> 0: enable = enable Floating point unit
// <1=> 1: disable = disable floating point unit
// </combo>
// </item>
//
// ---------------------------- Field Item: GCR_SCON_CCACHE_FLUSH -------------------------------
// SVD Line: 1258
// <item> SFDITEM_FIELD__GCR_SCON_CCACHE_FLUSH
// <name> CCACHE_FLUSH </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40000000) \nCode Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4.\n0 : normal = Normal Code Cache Operation\n1 : flush = Code Caches and CPU instruction buffer are flushed </i>
// <combo>
// <loc> ( (unsigned int) GCR_SCON ) </loc>
// <o.6..6> CCACHE_FLUSH
// <0=> 0: normal = Normal Code Cache Operation
// <1=> 1: flush = Code Caches and CPU instruction buffer are flushed
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_SCON_SWD_DIS ----------------------------------
// SVD Line: 1276
// <item> SFDITEM_FIELD__GCR_SCON_SWD_DIS
// <name> SWD_DIS </name>
// <rw>
// <i> [Bit 14] RW (@ 0x40000000) \nSerial Wire Debug Disable\n0 : enable = Enable JTAG SWD\n1 : disable = Disable JTAG SWD </i>
// <combo>
// <loc> ( (unsigned int) GCR_SCON ) </loc>
// <o.14..14> SWD_DIS
// <0=> 0: enable = Enable JTAG SWD
// <1=> 1: disable = Disable JTAG SWD
// </combo>
// </item>
//
// -------------------------------- Register RTree: GCR_SCON ------------------------------------
// SVD Line: 1198
// <rtree> SFDITEM_REG__GCR_SCON
// <name> SCON </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000000) System Control. </i>
// <loc> ( (unsigned int)((GCR_SCON >> 0) & 0xFFFFFFFF), ((GCR_SCON = (GCR_SCON & ~(0x4076UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x4076) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_SCON_SBUSARB </item>
// <item> SFDITEM_FIELD__GCR_SCON_FLASH_PAGE_FLIP </item>
// <item> SFDITEM_FIELD__GCR_SCON_FPU_DIS </item>
// <item> SFDITEM_FIELD__GCR_SCON_CCACHE_FLUSH </item>
// <item> SFDITEM_FIELD__GCR_SCON_SWD_DIS </item>
// </rtree>
//
// ---------------------------- Register Item Address: GCR_RSTR0 --------------------------------
// SVD Line: 1296
unsigned int GCR_RSTR0 __AT (0x40000004);
// -------------------------------- Field Item: GCR_RSTR0_DMA -----------------------------------
// SVD Line: 1301
// <item> SFDITEM_FIELD__GCR_RSTR0_DMA
// <name> DMA </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40000004) \nDMA Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.0..0> DMA
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// -------------------------------- Field Item: GCR_RSTR0_WDT -----------------------------------
// SVD Line: 1335
// <item> SFDITEM_FIELD__GCR_RSTR0_WDT
// <name> WDT </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40000004) \nWatchdog Timer Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.1..1> WDT
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_RSTR0_GPIO0 ----------------------------------
// SVD Line: 1369
// <item> SFDITEM_FIELD__GCR_RSTR0_GPIO0
// <name> GPIO0 </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40000004) \nGPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.2..2> GPIO0
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_RSTR0_TIMER0 ----------------------------------
// SVD Line: 1403
// <item> SFDITEM_FIELD__GCR_RSTR0_TIMER0
// <name> TIMER0 </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40000004) \nTimer0 Reset. Setting this bit to 1 resets Timer 0 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.5..5> TIMER0
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_RSTR0_TIMER1 ----------------------------------
// SVD Line: 1437
// <item> SFDITEM_FIELD__GCR_RSTR0_TIMER1
// <name> TIMER1 </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40000004) \nTimer1 Reset. Setting this bit to 1 resets Timer 1 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.6..6> TIMER1
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_RSTR0_TIMER2 ----------------------------------
// SVD Line: 1471
// <item> SFDITEM_FIELD__GCR_RSTR0_TIMER2
// <name> TIMER2 </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40000004) \nTimer2 Reset. Setting this bit to 1 resets Timer 2 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.7..7> TIMER2
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_RSTR0_UART0 ----------------------------------
// SVD Line: 1505
// <item> SFDITEM_FIELD__GCR_RSTR0_UART0
// <name> UART0 </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40000004) \nUART0 Reset. Setting this bit to 1 resets all UART 0 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.11..11> UART0
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_RSTR0_UART1 ----------------------------------
// SVD Line: 1539
// <item> SFDITEM_FIELD__GCR_RSTR0_UART1
// <name> UART1 </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40000004) \nUART1 Reset. Setting this bit to 1 resets all UART 1 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.12..12> UART1
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_RSTR0_SPI0 -----------------------------------
// SVD Line: 1573
// <item> SFDITEM_FIELD__GCR_RSTR0_SPI0
// <name> SPI0 </name>
// <rw>
// <i> [Bit 13] RW (@ 0x40000004) \nSPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.13..13> SPI0
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_RSTR0_SPI1 -----------------------------------
// SVD Line: 1607
// <item> SFDITEM_FIELD__GCR_RSTR0_SPI1
// <name> SPI1 </name>
// <rw>
// <i> [Bit 14] RW (@ 0x40000004) \nSPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.14..14> SPI1
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_RSTR0_I2C0 -----------------------------------
// SVD Line: 1641
// <item> SFDITEM_FIELD__GCR_RSTR0_I2C0
// <name> I2C0 </name>
// <rw>
// <i> [Bit 16] RW (@ 0x40000004) \nI2C0 Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.16..16> I2C0
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// -------------------------------- Field Item: GCR_RSTR0_RTC -----------------------------------
// SVD Line: 1675
// <item> SFDITEM_FIELD__GCR_RSTR0_RTC
// <name> RTC </name>
// <rw>
// <i> [Bit 17] RW (@ 0x40000004) \nReal Time Clock Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.17..17> RTC
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_RSTR0_SRST -----------------------------------
// SVD Line: 1709
// <item> SFDITEM_FIELD__GCR_RSTR0_SRST
// <name> SRST </name>
// <rw>
// <i> [Bit 29] RW (@ 0x40000004) \nSoft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.29..29> SRST
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_RSTR0_PRST -----------------------------------
// SVD Line: 1743
// <item> SFDITEM_FIELD__GCR_RSTR0_PRST
// <name> PRST </name>
// <rw>
// <i> [Bit 30] RW (@ 0x40000004) \nPeripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.30..30> PRST
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_RSTR0_SYSTEM ----------------------------------
// SVD Line: 1777
// <item> SFDITEM_FIELD__GCR_RSTR0_SYSTEM
// <name> SYSTEM </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40000004) \nSystem Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR0 ) </loc>
// <o.31..31> SYSTEM
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// -------------------------------- Register RTree: GCR_RSTR0 -----------------------------------
// SVD Line: 1296
// <rtree> SFDITEM_REG__GCR_RSTR0
// <name> RSTR0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000004) Reset. </i>
// <loc> ( (unsigned int)((GCR_RSTR0 >> 0) & 0xFFFFFFFF), ((GCR_RSTR0 = (GCR_RSTR0 & ~(0xE00378E7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xE00378E7) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_RSTR0_DMA </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_WDT </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_GPIO0 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_TIMER0 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_TIMER1 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_TIMER2 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_UART0 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_UART1 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_SPI0 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_SPI1 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_I2C0 </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_RTC </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_SRST </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_PRST </item>
// <item> SFDITEM_FIELD__GCR_RSTR0_SYSTEM </item>
// </rtree>
//
// ---------------------------- Register Item Address: GCR_CLKCN --------------------------------
// SVD Line: 1813
unsigned int GCR_CLKCN __AT (0x40000008);
// -------------------------------- Field Item: GCR_CLKCN_PSC -----------------------------------
// SVD Line: 1819
// <item> SFDITEM_FIELD__GCR_CLKCN_PSC
// <name> PSC </name>
// <rw>
// <i> [Bits 8..6] RW (@ 0x40000008) \nPrescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.\n0 : div1 = Divide by 1.\n1 : div2 = Divide by 2.\n2 : div4 = Divide by 4.\n3 : div8 = Divide by 8.\n4 : div16 = Divide by 16.\n5 : div32 = Divide by 32.\n6 : div64 = Divide by 64.\n7 : div128 = Divide by 128. </i>
// <combo>
// <loc> ( (unsigned int) GCR_CLKCN ) </loc>
// <o.8..6> PSC
// <0=> 0: div1 = Divide by 1.
// <1=> 1: div2 = Divide by 2.
// <2=> 2: div4 = Divide by 4.
// <3=> 3: div8 = Divide by 8.
// <4=> 4: div16 = Divide by 16.
// <5=> 5: div32 = Divide by 32.
// <6=> 6: div64 = Divide by 64.
// <7=> 7: div128 = Divide by 128.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_CLKCN_CLKSEL ----------------------------------
// SVD Line: 1867
// <item> SFDITEM_FIELD__GCR_CLKCN_CLKSEL
// <name> CLKSEL </name>
// <rw>
// <i> [Bits 11..9] RW (@ 0x40000008) \nClock Source Select. This 3 bit field selects the source for the system clock.\n0 : HIRC = The internal 96 MHz oscillator is used for the system clock.\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : nanoRing = The nano-ring output is used for the system clock.\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : hfxIn = HFXIN is used for the system clock.\n7 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) GCR_CLKCN ) </loc>
// <o.11..9> CLKSEL
// <0=> 0: HIRC = The internal 96 MHz oscillator is used for the system clock.
// <1=> 1:
// <2=> 2:
// <3=> 3: nanoRing = The nano-ring output is used for the system clock.
// <4=> 4:
// <5=> 5:
// <6=> 6: hfxIn = HFXIN is used for the system clock.
// <7=> 7:
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_CLKCN_CKRDY ----------------------------------
// SVD Line: 1890
// <item> SFDITEM_FIELD__GCR_CLKCN_CKRDY
// <name> CKRDY </name>
// <r>
// <i> [Bit 13] RO (@ 0x40000008) \nClock Ready. This read only bit reflects whether the currently selected system clock source is running.\n0 : busy = Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.\n1 : ready = System clock running from CLKSEL clock source. </i>
// <combo>
// <loc> ( (unsigned int) GCR_CLKCN ) </loc>
// <o.13..13> CKRDY
// <0=> 0: busy = Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.
// <1=> 1: ready = System clock running from CLKSEL clock source.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_CLKCN_X32K_EN ---------------------------------
// SVD Line: 1909
// <item> SFDITEM_FIELD__GCR_CLKCN_X32K_EN
// <name> X32K_EN </name>
// <rw>
// <i> [Bit 17] RW (@ 0x40000008) \n32kHz Crystal Oscillator Enable.\n0 : dis = Is Disabled.\n1 : en = Is Enabled. </i>
// <combo>
// <loc> ( (unsigned int) GCR_CLKCN ) </loc>
// <o.17..17> X32K_EN
// <0=> 0: dis = Is Disabled.
// <1=> 1: en = Is Enabled.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_CLKCN_HIRC_EN ---------------------------------
// SVD Line: 1927
// <item> SFDITEM_FIELD__GCR_CLKCN_HIRC_EN
// <name> HIRC_EN </name>
// <rw>
// <i> [Bit 18] RW (@ 0x40000008) \n60MHz High Frequency Internal Reference Clock Enable.\n0 : dis = Is Disabled.\n1 : en = Is Enabled. </i>
// <combo>
// <loc> ( (unsigned int) GCR_CLKCN ) </loc>
// <o.18..18> HIRC_EN
// <0=> 0: dis = Is Disabled.
// <1=> 1: en = Is Enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_CLKCN_X32K_RDY ---------------------------------
// SVD Line: 1945
// <item> SFDITEM_FIELD__GCR_CLKCN_X32K_RDY
// <name> X32K_RDY </name>
// <r>
// <i> [Bit 25] RO (@ 0x40000008) \n32kHz Crystal Oscillator Ready\n0 : not = Not Ready\n1 : Ready = X32K Ready </i>
// <combo>
// <loc> ( (unsigned int) GCR_CLKCN ) </loc>
// <o.25..25> X32K_RDY
// <0=> 0: not = Not Ready
// <1=> 1: Ready = X32K Ready
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_CLKCN_HIRC_RDY ---------------------------------
// SVD Line: 1964
// <item> SFDITEM_FIELD__GCR_CLKCN_HIRC_RDY
// <name> HIRC_RDY </name>
// <rw>
// <i> [Bit 26] RW (@ 0x40000008) \n60MHz HIRC Ready.\n0 : not = Not Ready\n1 : ready = HIRC Ready </i>
// <combo>
// <loc> ( (unsigned int) GCR_CLKCN ) </loc>
// <o.26..26> HIRC_RDY
// <0=> 0: not = Not Ready
// <1=> 1: ready = HIRC Ready
// </combo>
// </item>
//
// ---------------------------- Field Item: GCR_CLKCN_LIRC8K_RDY --------------------------------
// SVD Line: 1982
// <item> SFDITEM_FIELD__GCR_CLKCN_LIRC8K_RDY
// <name> LIRC8K_RDY </name>
// <rw>
// <i> [Bit 29] RW (@ 0x40000008) \n8kHz Low Frequency Reference Clock Ready.\n0 : not = Not Ready\n1 : ready = Clock Ready </i>
// <combo>
// <loc> ( (unsigned int) GCR_CLKCN ) </loc>
// <o.29..29> LIRC8K_RDY
// <0=> 0: not = Not Ready
// <1=> 1: ready = Clock Ready
// </combo>
// </item>
//
// -------------------------------- Register RTree: GCR_CLKCN -----------------------------------
// SVD Line: 1813
// <rtree> SFDITEM_REG__GCR_CLKCN
// <name> CLKCN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000008) Clock Control. </i>
// <loc> ( (unsigned int)((GCR_CLKCN >> 0) & 0xFFFFFFFF), ((GCR_CLKCN = (GCR_CLKCN & ~(0x24060FC0UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x24060FC0) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_CLKCN_PSC </item>
// <item> SFDITEM_FIELD__GCR_CLKCN_CLKSEL </item>
// <item> SFDITEM_FIELD__GCR_CLKCN_CKRDY </item>
// <item> SFDITEM_FIELD__GCR_CLKCN_X32K_EN </item>
// <item> SFDITEM_FIELD__GCR_CLKCN_HIRC_EN </item>
// <item> SFDITEM_FIELD__GCR_CLKCN_X32K_RDY </item>
// <item> SFDITEM_FIELD__GCR_CLKCN_HIRC_RDY </item>
// <item> SFDITEM_FIELD__GCR_CLKCN_LIRC8K_RDY </item>
// </rtree>
//
// ------------------------------ Register Item Address: GCR_PM ---------------------------------
// SVD Line: 2002
unsigned int GCR_PM __AT (0x4000000C);
// --------------------------------- Field Item: GCR_PM_MODE ------------------------------------
// SVD Line: 2007
// <item> SFDITEM_FIELD__GCR_PM_MODE
// <name> MODE </name>
// <rw>
// <i> [Bits 2..0] RW (@ 0x4000000C) \nOperating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.\n0 : active = Active Mode.\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : shutdown = Shutdown Mode.\n4 : backup = Backup Mode.\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) GCR_PM ) </loc>
// <o.2..0> MODE
// <0=> 0: active = Active Mode.
// <1=> 1:
// <2=> 2:
// <3=> 3: shutdown = Shutdown Mode.
// <4=> 4: backup = Backup Mode.
// <5=> 5:
// <6=> 6:
// <7=> 7:
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_PM_GPIOWKEN ----------------------------------
// SVD Line: 2030
// <item> SFDITEM_FIELD__GCR_PM_GPIOWKEN
// <name> GPIOWKEN </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4000000C) \nGPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.\n0 : dis = Wake Up Disable.\n1 : en = Wake Up Enable. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PM ) </loc>
// <o.4..4> GPIOWKEN
// <0=> 0: dis = Wake Up Disable.
// <1=> 1: en = Wake Up Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: GCR_PM_RTCWKEN -----------------------------------
// SVD Line: 2048
// <item> SFDITEM_FIELD__GCR_PM_RTCWKEN
// <name> RTCWKEN </name>
// <rw>
// <i> [Bit 5] RW (@ 0x4000000C) \nRTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.\n0 : dis = Wake Up Disable.\n1 : en = Wake Up Enable. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PM ) </loc>
// <o.5..5> RTCWKEN
// <0=> 0: dis = Wake Up Disable.
// <1=> 1: en = Wake Up Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: GCR_PM_HIRCPD -----------------------------------
// SVD Line: 2066
// <item> SFDITEM_FIELD__GCR_PM_HIRCPD
// <name> HIRCPD </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4000000C) \nHIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode.\n0 : active = Mode is Active.\n1 : deepsleep = Powered down in DEEPSLEEP. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PM ) </loc>
// <o.15..15> HIRCPD
// <0=> 0: active = Mode is Active.
// <1=> 1: deepsleep = Powered down in DEEPSLEEP.
// </combo>
// </item>
//
// --------------------------------- Register RTree: GCR_PM -------------------------------------
// SVD Line: 2002
// <rtree> SFDITEM_REG__GCR_PM
// <name> PM </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000000C) Power Management. </i>
// <loc> ( (unsigned int)((GCR_PM >> 0) & 0xFFFFFFFF), ((GCR_PM = (GCR_PM & ~(0x8037UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8037) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_PM_MODE </item>
// <item> SFDITEM_FIELD__GCR_PM_GPIOWKEN </item>
// <item> SFDITEM_FIELD__GCR_PM_RTCWKEN </item>
// <item> SFDITEM_FIELD__GCR_PM_HIRCPD </item>
// </rtree>
//
// ---------------------------- Register Item Address: GCR_PCKDIV -------------------------------
// SVD Line: 2086
unsigned int GCR_PCKDIV __AT (0x40000018);
// ------------------------------ Field Item: GCR_PCKDIV_AONCD ----------------------------------
// SVD Line: 2092
// <item> SFDITEM_FIELD__GCR_PCKDIV_AONCD
// <name> AONCD </name>
// <rw>
// <i> [Bits 1..0] RW (@ 0x40000018) \nAlways-ON(AON) domain CLock Divider. These bits define the AON domain clock divider.\n0 : div_4 = PCLK divide by 4.\n1 : div_8 = PCLK divide by 8.\n2 : div_16 = PCLK divide by 16.\n3 : div_32 = PCLK divide by 32. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PCKDIV ) </loc>
// <o.1..0> AONCD
// <0=> 0: div_4 = PCLK divide by 4.
// <1=> 1: div_8 = PCLK divide by 8.
// <2=> 2: div_16 = PCLK divide by 16.
// <3=> 3: div_32 = PCLK divide by 32.
// </combo>
// </item>
//
// ------------------------------- Register RTree: GCR_PCKDIV -----------------------------------
// SVD Line: 2086
// <rtree> SFDITEM_REG__GCR_PCKDIV
// <name> PCKDIV </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000018) Peripheral Clock Divider. </i>
// <loc> ( (unsigned int)((GCR_PCKDIV >> 0) & 0xFFFFFFFF), ((GCR_PCKDIV = (GCR_PCKDIV & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_PCKDIV_AONCD </item>
// </rtree>
//
// --------------------------- Register Item Address: GCR_PERCKCN0 ------------------------------
// SVD Line: 2122
unsigned int GCR_PERCKCN0 __AT (0x40000024);
// ----------------------------- Field Item: GCR_PERCKCN0_GPIO0D --------------------------------
// SVD Line: 2127
// <item> SFDITEM_FIELD__GCR_PERCKCN0_GPIO0D
// <name> GPIO0D </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40000024) \nGPIO0 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.0..0> GPIO0D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_PERCKCN0_DMAD ---------------------------------
// SVD Line: 2146
// <item> SFDITEM_FIELD__GCR_PERCKCN0_DMAD
// <name> DMAD </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40000024) \nDMA Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.5..5> DMAD
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_PERCKCN0_SPI0D ---------------------------------
// SVD Line: 2165
// <item> SFDITEM_FIELD__GCR_PERCKCN0_SPI0D
// <name> SPI0D </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40000024) \nSPI 0 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.6..6> SPI0D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_PERCKCN0_SPI1D ---------------------------------
// SVD Line: 2184
// <item> SFDITEM_FIELD__GCR_PERCKCN0_SPI1D
// <name> SPI1D </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40000024) \nSPI 1 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.7..7> SPI1D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_PERCKCN0_UART0D --------------------------------
// SVD Line: 2203
// <item> SFDITEM_FIELD__GCR_PERCKCN0_UART0D
// <name> UART0D </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40000024) \nUART 0 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.9..9> UART0D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_PERCKCN0_UART1D --------------------------------
// SVD Line: 2222
// <item> SFDITEM_FIELD__GCR_PERCKCN0_UART1D
// <name> UART1D </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40000024) \nUART 1 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.10..10> UART1D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_PERCKCN0_I2C0D ---------------------------------
// SVD Line: 2241
// <item> SFDITEM_FIELD__GCR_PERCKCN0_I2C0D
// <name> I2C0D </name>
// <rw>
// <i> [Bit 13] RW (@ 0x40000024) \nI2C 0 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.13..13> I2C0D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_PERCKCN0_T0D ----------------------------------
// SVD Line: 2260
// <item> SFDITEM_FIELD__GCR_PERCKCN0_T0D
// <name> T0D </name>
// <rw>
// <i> [Bit 15] RW (@ 0x40000024) \nTimer 0 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.15..15> T0D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_PERCKCN0_T1D ----------------------------------
// SVD Line: 2279
// <item> SFDITEM_FIELD__GCR_PERCKCN0_T1D
// <name> T1D </name>
// <rw>
// <i> [Bit 16] RW (@ 0x40000024) \nTimer 1 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.16..16> T1D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_PERCKCN0_T2D ----------------------------------
// SVD Line: 2298
// <item> SFDITEM_FIELD__GCR_PERCKCN0_T2D
// <name> T2D </name>
// <rw>
// <i> [Bit 17] RW (@ 0x40000024) \nTimer 2 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.17..17> T2D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_PERCKCN0_I2C1D ---------------------------------
// SVD Line: 2317
// <item> SFDITEM_FIELD__GCR_PERCKCN0_I2C1D
// <name> I2C1D </name>
// <rw>
// <i> [Bit 28] RW (@ 0x40000024) \nI2C 1 Disable.\n0 : en = enable it.\n1 : dis = disable it. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN0 ) </loc>
// <o.28..28> I2C1D
// <0=> 0: en = enable it.
// <1=> 1: dis = disable it.
// </combo>
// </item>
//
// ------------------------------ Register RTree: GCR_PERCKCN0 ----------------------------------
// SVD Line: 2122
// <rtree> SFDITEM_REG__GCR_PERCKCN0
// <name> PERCKCN0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000024) Peripheral Clock Disable. </i>
// <loc> ( (unsigned int)((GCR_PERCKCN0 >> 0) & 0xFFFFFFFF), ((GCR_PERCKCN0 = (GCR_PERCKCN0 & ~(0x1003A6E1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1003A6E1) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_GPIO0D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_DMAD </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_SPI0D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_SPI1D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_UART0D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_UART1D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_I2C0D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_T0D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_T1D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_T2D </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN0_I2C1D </item>
// </rtree>
//
// --------------------------- Register Item Address: GCR_MEMCKCN -------------------------------
// SVD Line: 2338
unsigned int GCR_MEMCKCN __AT (0x40000028);
// ------------------------------- Field Item: GCR_MEMCKCN_FWS ----------------------------------
// SVD Line: 2343
// <item> SFDITEM_FIELD__GCR_MEMCKCN_FWS
// <name> FWS </name>
// <rw>
// <i> [Bits 2..0] RW (@ 0x40000028) Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. </i>
// <edit>
// <loc> ( (unsigned char)((GCR_MEMCKCN >> 0) & 0x7), ((GCR_MEMCKCN = (GCR_MEMCKCN & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: GCR_MEMCKCN_SYSRAM0LS -------------------------------
// SVD Line: 2349
// <item> SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM0LS
// <name> SYSRAM0LS </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40000028) \nSystem RAM 0 Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. </i>
// <combo>
// <loc> ( (unsigned int) GCR_MEMCKCN ) </loc>
// <o.8..8> SYSRAM0LS
// <0=> 0: active = Memory is active.
// <1=> 1: light_sleep = Memory is in Light Sleep mode.
// </combo>
// </item>
//
// ---------------------------- Field Item: GCR_MEMCKCN_SYSRAM1LS -------------------------------
// SVD Line: 2367
// <item> SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM1LS
// <name> SYSRAM1LS </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40000028) \nSystem RAM 1 Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. </i>
// <combo>
// <loc> ( (unsigned int) GCR_MEMCKCN ) </loc>
// <o.9..9> SYSRAM1LS
// <0=> 0: active = Memory is active.
// <1=> 1: light_sleep = Memory is in Light Sleep mode.
// </combo>
// </item>
//
// ---------------------------- Field Item: GCR_MEMCKCN_SYSRAM2LS -------------------------------
// SVD Line: 2385
// <item> SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM2LS
// <name> SYSRAM2LS </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40000028) \nSystem RAM 2 Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. </i>
// <combo>
// <loc> ( (unsigned int) GCR_MEMCKCN ) </loc>
// <o.10..10> SYSRAM2LS
// <0=> 0: active = Memory is active.
// <1=> 1: light_sleep = Memory is in Light Sleep mode.
// </combo>
// </item>
//
// ---------------------------- Field Item: GCR_MEMCKCN_SYSRAM3LS -------------------------------
// SVD Line: 2403
// <item> SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM3LS
// <name> SYSRAM3LS </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40000028) \nSystem RAM 3 Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. </i>
// <combo>
// <loc> ( (unsigned int) GCR_MEMCKCN ) </loc>
// <o.11..11> SYSRAM3LS
// <0=> 0: active = Memory is active.
// <1=> 1: light_sleep = Memory is in Light Sleep mode.
// </combo>
// </item>
//
// ---------------------------- Field Item: GCR_MEMCKCN_ICACHELS --------------------------------
// SVD Line: 2421
// <item> SFDITEM_FIELD__GCR_MEMCKCN_ICACHELS
// <name> ICACHELS </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40000028) \nICache RAM Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. </i>
// <combo>
// <loc> ( (unsigned int) GCR_MEMCKCN ) </loc>
// <o.12..12> ICACHELS
// <0=> 0: active = Memory is active.
// <1=> 1: light_sleep = Memory is in Light Sleep mode.
// </combo>
// </item>
//
// ------------------------------- Register RTree: GCR_MEMCKCN ----------------------------------
// SVD Line: 2338
// <rtree> SFDITEM_REG__GCR_MEMCKCN
// <name> MEMCKCN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000028) Memory Clock Control Register. </i>
// <loc> ( (unsigned int)((GCR_MEMCKCN >> 0) & 0xFFFFFFFF), ((GCR_MEMCKCN = (GCR_MEMCKCN & ~(0x1F07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F07) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_MEMCKCN_FWS </item>
// <item> SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM0LS </item>
// <item> SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM1LS </item>
// <item> SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM2LS </item>
// <item> SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM3LS </item>
// <item> SFDITEM_FIELD__GCR_MEMCKCN_ICACHELS </item>
// </rtree>
//
// ---------------------------- Register Item Address: GCR_MEMZCN -------------------------------
// SVD Line: 2441
unsigned int GCR_MEMZCN __AT (0x4000002C);
// ------------------------------ Field Item: GCR_MEMZCN_SRAM0Z ---------------------------------
// SVD Line: 2446
// <item> SFDITEM_FIELD__GCR_MEMZCN_SRAM0Z
// <name> SRAM0Z </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4000002C) \nSystem RAM Block 0.\n0 : nop = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_MEMZCN ) </loc>
// <o.0..0> SRAM0Z
// <0=> 0: nop = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// ----------------------------- Field Item: GCR_MEMZCN_ICACHEZ ---------------------------------
// SVD Line: 2464
// <item> SFDITEM_FIELD__GCR_MEMZCN_ICACHEZ
// <name> ICACHEZ </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4000002C) \nInstruction Cache.\n0 : nop = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_MEMZCN ) </loc>
// <o.1..1> ICACHEZ
// <0=> 0: nop = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// ------------------------------- Register RTree: GCR_MEMZCN -----------------------------------
// SVD Line: 2441
// <rtree> SFDITEM_REG__GCR_MEMZCN
// <name> MEMZCN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000002C) Memory Zeroize Control. </i>
// <loc> ( (unsigned int)((GCR_MEMZCN >> 0) & 0xFFFFFFFF), ((GCR_MEMZCN = (GCR_MEMZCN & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_MEMZCN_SRAM0Z </item>
// <item> SFDITEM_FIELD__GCR_MEMZCN_ICACHEZ </item>
// </rtree>
//
// ----------------------------- Register Item Address: GCR_SCCK --------------------------------
// SVD Line: 2484
unsigned int GCR_SCCK __AT (0x40000034);
// --------------------------------- Register Item: GCR_SCCK ------------------------------------
// SVD Line: 2484
// <item> SFDITEM_REG__GCR_SCCK
// <name> SCCK </name>
// <i> [Bits 31..0] RW (@ 0x40000034) Smart Card Clock Control. </i>
// <edit>
// <loc> ( (unsigned int)((GCR_SCCK >> 0) & 0xFFFFFFFF), ((GCR_SCCK = (GCR_SCCK & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register Item Address: GCR_MPRI0 --------------------------------
// SVD Line: 2490
unsigned int GCR_MPRI0 __AT (0x40000038);
// -------------------------------- Register Item: GCR_MPRI0 ------------------------------------
// SVD Line: 2490
// <item> SFDITEM_REG__GCR_MPRI0
// <name> MPRI0 </name>
// <i> [Bits 31..0] RW (@ 0x40000038) Master Priority Control Register 0. </i>
// <edit>
// <loc> ( (unsigned int)((GCR_MPRI0 >> 0) & 0xFFFFFFFF), ((GCR_MPRI0 = (GCR_MPRI0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register Item Address: GCR_MPRI1 --------------------------------
// SVD Line: 2496
unsigned int GCR_MPRI1 __AT (0x4000003C);
// -------------------------------- Register Item: GCR_MPRI1 ------------------------------------
// SVD Line: 2496
// <item> SFDITEM_REG__GCR_MPRI1
// <name> MPRI1 </name>
// <i> [Bits 31..0] RW (@ 0x4000003C) Mater Priority Control Register 1. </i>
// <edit>
// <loc> ( (unsigned int)((GCR_MPRI1 >> 0) & 0xFFFFFFFF), ((GCR_MPRI1 = (GCR_MPRI1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register Item Address: GCR_SYSST --------------------------------
// SVD Line: 2502
unsigned int GCR_SYSST __AT (0x40000040);
// ----------------------------- Field Item: GCR_SYSST_ICECLOCK ---------------------------------
// SVD Line: 2507
// <item> SFDITEM_FIELD__GCR_SYSST_ICECLOCK
// <name> ICECLOCK </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40000040) \nARM ICE Lock Status.\n0 : unlocked = ICE is unlocked.\n1 : locked = ICE is locked. </i>
// <combo>
// <loc> ( (unsigned int) GCR_SYSST ) </loc>
// <o.0..0> ICECLOCK
// <0=> 0: unlocked = ICE is unlocked.
// <1=> 1: locked = ICE is locked.
// </combo>
// </item>
//
// ---------------------------- Field Item: GCR_SYSST_CODEINTERR --------------------------------
// SVD Line: 2525
// <item> SFDITEM_FIELD__GCR_SYSST_CODEINTERR
// <name> CODEINTERR </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40000040) \nCode Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface.\n0 : norm = Normal Operating Condition.\n1 : code = Code Integrity Error. </i>
// <combo>
// <loc> ( (unsigned int) GCR_SYSST ) </loc>
// <o.1..1> CODEINTERR
// <0=> 0: norm = Normal Operating Condition.
// <1=> 1: code = Code Integrity Error.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_SYSST_SCMEMF ----------------------------------
// SVD Line: 2543
// <item> SFDITEM_FIELD__GCR_SYSST_SCMEMF
// <name> SCMEMF </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40000040) \nSystem Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.\n0 : norm = Normal Operating Condition.\n1 : memory = Memory Fault. </i>
// <combo>
// <loc> ( (unsigned int) GCR_SYSST ) </loc>
// <o.5..5> SCMEMF
// <0=> 0: norm = Normal Operating Condition.
// <1=> 1: memory = Memory Fault.
// </combo>
// </item>
//
// -------------------------------- Register RTree: GCR_SYSST -----------------------------------
// SVD Line: 2502
// <rtree> SFDITEM_REG__GCR_SYSST
// <name> SYSST </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000040) System Status Register. </i>
// <loc> ( (unsigned int)((GCR_SYSST >> 0) & 0xFFFFFFFF), ((GCR_SYSST = (GCR_SYSST & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_SYSST_ICECLOCK </item>
// <item> SFDITEM_FIELD__GCR_SYSST_CODEINTERR </item>
// <item> SFDITEM_FIELD__GCR_SYSST_SCMEMF </item>
// </rtree>
//
// ---------------------------- Register Item Address: GCR_RSTR1 --------------------------------
// SVD Line: 2563
unsigned int GCR_RSTR1 __AT (0x40000044);
// ------------------------------- Field Item: GCR_RSTR1_I2C1 -----------------------------------
// SVD Line: 2568
// <item> SFDITEM_FIELD__GCR_RSTR1_I2C1
// <name> I2C1 </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40000044) \nI2C1 Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. </i>
// <combo>
// <loc> ( (unsigned int) GCR_RSTR1 ) </loc>
// <o.0..0> I2C1
// <0=> 0: RFU = Reserved. Do not use.
// <1=> 1: reset = Starts reset operation.
// </combo>
// </item>
//
// -------------------------------- Register RTree: GCR_RSTR1 -----------------------------------
// SVD Line: 2563
// <rtree> SFDITEM_REG__GCR_RSTR1
// <name> RSTR1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000044) Reset 1. </i>
// <loc> ( (unsigned int)((GCR_RSTR1 >> 0) & 0xFFFFFFFF), ((GCR_RSTR1 = (GCR_RSTR1 & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_RSTR1_I2C1 </item>
// </rtree>
//
// --------------------------- Register Item Address: GCR_PERCKCN1 ------------------------------
// SVD Line: 2604
unsigned int GCR_PERCKCN1 __AT (0x40000048);
// ------------------------------ Field Item: GCR_PERCKCN1_FLCD ---------------------------------
// SVD Line: 2609
// <item> SFDITEM_FIELD__GCR_PERCKCN1_FLCD
// <name> FLCD </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40000048) \nSecure Flash Controller Disable.\n0 : en = Enable.\n1 : dis = Disable. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN1 ) </loc>
// <o.3..3> FLCD
// <0=> 0: en = Enable.
// <1=> 1: dis = Disable.
// </combo>
// </item>
//
// ---------------------------- Field Item: GCR_PERCKCN1_ICACHED --------------------------------
// SVD Line: 2627
// <item> SFDITEM_FIELD__GCR_PERCKCN1_ICACHED
// <name> ICACHED </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40000048) \nICache Clock Disable.\n0 : en = Enable.\n1 : dis = Disable. </i>
// <combo>
// <loc> ( (unsigned int) GCR_PERCKCN1 ) </loc>
// <o.11..11> ICACHED
// <0=> 0: en = Enable.
// <1=> 1: dis = Disable.
// </combo>
// </item>
//
// ------------------------------ Register RTree: GCR_PERCKCN1 ----------------------------------
// SVD Line: 2604
// <rtree> SFDITEM_REG__GCR_PERCKCN1
// <name> PERCKCN1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000048) Peripheral Clock Disable. </i>
// <loc> ( (unsigned int)((GCR_PERCKCN1 >> 0) & 0xFFFFFFFF), ((GCR_PERCKCN1 = (GCR_PERCKCN1 & ~(0x808UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x808) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_PERCKCN1_FLCD </item>
// <item> SFDITEM_FIELD__GCR_PERCKCN1_ICACHED </item>
// </rtree>
//
// ---------------------------- Register Item Address: GCR_EVTEN --------------------------------
// SVD Line: 2647
unsigned int GCR_EVTEN __AT (0x4000004C);
// ----------------------------- Field Item: GCR_EVTEN_DMAEVENT ---------------------------------
// SVD Line: 2652
// <item> SFDITEM_FIELD__GCR_EVTEN_DMAEVENT
// <name> DMAEVENT </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4000004C) Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. </i>
// <check>
// <loc> ( (unsigned int) GCR_EVTEN ) </loc>
// <o.0..0> DMAEVENT
// </check>
// </item>
//
// ------------------------------ Field Item: GCR_EVTEN_RXEVENT ---------------------------------
// SVD Line: 2658
// <item> SFDITEM_FIELD__GCR_EVTEN_RXEVENT
// <name> RXEVENT </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4000004C) Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </i>
// <check>
// <loc> ( (unsigned int) GCR_EVTEN ) </loc>
// <o.1..1> RXEVENT
// </check>
// </item>
//
// -------------------------------- Register RTree: GCR_EVTEN -----------------------------------
// SVD Line: 2647
// <rtree> SFDITEM_REG__GCR_EVTEN
// <name> EVTEN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000004C) Event Enable Register. </i>
// <loc> ( (unsigned int)((GCR_EVTEN >> 0) & 0xFFFFFFFF), ((GCR_EVTEN = (GCR_EVTEN & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_EVTEN_DMAEVENT </item>
// <item> SFDITEM_FIELD__GCR_EVTEN_RXEVENT </item>
// </rtree>
//
// --------------------------- Register Item Address: GCR_REVISION ------------------------------
// SVD Line: 2666
unsigned int GCR_REVISION __AT (0x40000050);
// ---------------------------- Field Item: GCR_REVISION_REVISION -------------------------------
// SVD Line: 2672
// <item> SFDITEM_FIELD__GCR_REVISION_REVISION
// <name> REVISION </name>
// <r>
// <i> [Bits 15..0] RO (@ 0x40000050) Manufacturer Chip Revision. </i>
// <edit>
// <loc> ( (unsigned short)((GCR_REVISION >> 0) & 0xFFFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GCR_REVISION ----------------------------------
// SVD Line: 2666
// <rtree> SFDITEM_REG__GCR_REVISION
// <name> REVISION </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40000050) Revision Register. </i>
// <loc> ( (unsigned int)((GCR_REVISION >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__GCR_REVISION_REVISION </item>
// </rtree>
//
// ---------------------------- Register Item Address: GCR_SYSSIE -------------------------------
// SVD Line: 2680
unsigned int GCR_SYSSIE __AT (0x40000054);
// ----------------------------- Field Item: GCR_SYSSIE_ICEULIE ---------------------------------
// SVD Line: 2685
// <item> SFDITEM_FIELD__GCR_SYSSIE_ICEULIE
// <name> ICEULIE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40000054) \nARM ICE Unlock Interrupt Enable.\n0 : dis = disabled.\n1 : en = enabled. </i>
// <combo>
// <loc> ( (unsigned int) GCR_SYSSIE ) </loc>
// <o.0..0> ICEULIE
// <0=> 0: dis = disabled.
// <1=> 1: en = enabled.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_SYSSIE_CIEIE ----------------------------------
// SVD Line: 2703
// <item> SFDITEM_FIELD__GCR_SYSSIE_CIEIE
// <name> CIEIE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40000054) \nCode Integrity Error Interrupt Enable.\n0 : dis = disabled.\n1 : en = enabled. </i>
// <combo>
// <loc> ( (unsigned int) GCR_SYSSIE ) </loc>
// <o.1..1> CIEIE
// <0=> 0: dis = disabled.
// <1=> 1: en = enabled.
// </combo>
// </item>
//
// ------------------------------ Field Item: GCR_SYSSIE_SCMFIE ---------------------------------
// SVD Line: 2721
// <item> SFDITEM_FIELD__GCR_SYSSIE_SCMFIE
// <name> SCMFIE </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40000054) \nSystem Cache Memory Fault Interrupt Enable.\n0 : dis = disabled.\n1 : en = enabled. </i>
// <combo>
// <loc> ( (unsigned int) GCR_SYSSIE ) </loc>
// <o.5..5> SCMFIE
// <0=> 0: dis = disabled.
// <1=> 1: en = enabled.
// </combo>
// </item>
//
// ------------------------------- Register RTree: GCR_SYSSIE -----------------------------------
// SVD Line: 2680
// <rtree> SFDITEM_REG__GCR_SYSSIE
// <name> SYSSIE </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40000054) System Status Interrupt Enable Register. </i>
// <loc> ( (unsigned int)((GCR_SYSSIE >> 0) & 0xFFFFFFFF), ((GCR_SYSSIE = (GCR_SYSSIE & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GCR_SYSSIE_ICEULIE </item>
// <item> SFDITEM_FIELD__GCR_SYSSIE_CIEIE </item>
// <item> SFDITEM_FIELD__GCR_SYSSIE_SCMFIE </item>
// </rtree>
//
// ---------------------------------- Peripheral View: GCR --------------------------------------
// SVD Line: 1188
// <view> GCR
// <name> GCR </name>
// <item> SFDITEM_REG__GCR_SCON </item>
// <item> SFDITEM_REG__GCR_RSTR0 </item>
// <item> SFDITEM_REG__GCR_CLKCN </item>
// <item> SFDITEM_REG__GCR_PM </item>
// <item> SFDITEM_REG__GCR_PCKDIV </item>
// <item> SFDITEM_REG__GCR_PERCKCN0 </item>
// <item> SFDITEM_REG__GCR_MEMCKCN </item>
// <item> SFDITEM_REG__GCR_MEMZCN </item>
// <item> SFDITEM_REG__GCR_SCCK </item>
// <item> SFDITEM_REG__GCR_MPRI0 </item>
// <item> SFDITEM_REG__GCR_MPRI1 </item>
// <item> SFDITEM_REG__GCR_SYSST </item>
// <item> SFDITEM_REG__GCR_RSTR1 </item>
// <item> SFDITEM_REG__GCR_PERCKCN1 </item>
// <item> SFDITEM_REG__GCR_EVTEN </item>
// <item> SFDITEM_REG__GCR_REVISION </item>
// <item> SFDITEM_REG__GCR_SYSSIE </item>
// </view>
//
// ----------------------------- Register Item Address: GPIO0_EN --------------------------------
// SVD Line: 2760
unsigned int GPIO0_EN __AT (0x40008000);
// ------------------------------ Field Item: GPIO0_EN_GPIO_EN ----------------------------------
// SVD Line: 2765
// <item> SFDITEM_FIELD__GPIO0_EN_GPIO_EN
// <name> GPIO_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008000) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN >> 0) & 0xFFFFFFFF), ((GPIO0_EN = (GPIO0_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: GPIO0_EN ------------------------------------
// SVD Line: 2760
// <rtree> SFDITEM_REG__GPIO0_EN
// <name> EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008000) GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. </i>
// <loc> ( (unsigned int)((GPIO0_EN >> 0) & 0xFFFFFFFF), ((GPIO0_EN = (GPIO0_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN_GPIO_EN </item>
// </rtree>
//
// --------------------------- Register Item Address: GPIO0_EN_SET ------------------------------
// SVD Line: 2785
unsigned int GPIO0_EN_SET __AT (0x40008004);
// ------------------------------ Field Item: GPIO0_EN_SET_ALL ----------------------------------
// SVD Line: 2790
// <item> SFDITEM_FIELD__GPIO0_EN_SET_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008004) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN_SET = (GPIO0_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_EN_SET ----------------------------------
// SVD Line: 2785
// <rtree> SFDITEM_REG__GPIO0_EN_SET
// <name> EN_SET </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008004) GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN_SET = (GPIO0_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN_SET_ALL </item>
// </rtree>
//
// --------------------------- Register Item Address: GPIO0_EN_CLR ------------------------------
// SVD Line: 2798
unsigned int GPIO0_EN_CLR __AT (0x40008008);
// ------------------------------ Field Item: GPIO0_EN_CLR_ALL ----------------------------------
// SVD Line: 2803
// <item> SFDITEM_FIELD__GPIO0_EN_CLR_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008008) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN_CLR = (GPIO0_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_EN_CLR ----------------------------------
// SVD Line: 2798
// <rtree> SFDITEM_REG__GPIO0_EN_CLR
// <name> EN_CLR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008008) GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN_CLR = (GPIO0_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN_CLR_ALL </item>
// </rtree>
//
// --------------------------- Register Item Address: GPIO0_OUT_EN ------------------------------
// SVD Line: 2811
unsigned int GPIO0_OUT_EN __AT (0x4000800C);
// -------------------------- Field Item: GPIO0_OUT_EN_GPIO_OUT_EN ------------------------------
// SVD Line: 2816
// <item> SFDITEM_FIELD__GPIO0_OUT_EN_GPIO_OUT_EN
// <name> GPIO_OUT_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000800C) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_OUT_EN >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN = (GPIO0_OUT_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_OUT_EN ----------------------------------
// SVD Line: 2811
// <rtree> SFDITEM_REG__GPIO0_OUT_EN
// <name> OUT_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000800C) GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. </i>
// <loc> ( (unsigned int)((GPIO0_OUT_EN >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN = (GPIO0_OUT_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_OUT_EN_GPIO_OUT_EN </item>
// </rtree>
//
// ------------------------- Register Item Address: GPIO0_OUT_EN_SET ----------------------------
// SVD Line: 2836
unsigned int GPIO0_OUT_EN_SET __AT (0x40008010);
// ---------------------------- Field Item: GPIO0_OUT_EN_SET_ALL --------------------------------
// SVD Line: 2841
// <item> SFDITEM_FIELD__GPIO0_OUT_EN_SET_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008010) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_OUT_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN_SET = (GPIO0_OUT_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: GPIO0_OUT_EN_SET --------------------------------
// SVD Line: 2836
// <rtree> SFDITEM_REG__GPIO0_OUT_EN_SET
// <name> OUT_EN_SET </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008010) GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_OUT_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN_SET = (GPIO0_OUT_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_OUT_EN_SET_ALL </item>
// </rtree>
//
// ------------------------- Register Item Address: GPIO0_OUT_EN_CLR ----------------------------
// SVD Line: 2849
unsigned int GPIO0_OUT_EN_CLR __AT (0x40008014);
// ---------------------------- Field Item: GPIO0_OUT_EN_CLR_ALL --------------------------------
// SVD Line: 2854
// <item> SFDITEM_FIELD__GPIO0_OUT_EN_CLR_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008014) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_OUT_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN_CLR = (GPIO0_OUT_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: GPIO0_OUT_EN_CLR --------------------------------
// SVD Line: 2849
// <rtree> SFDITEM_REG__GPIO0_OUT_EN_CLR
// <name> OUT_EN_CLR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008014) GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_OUT_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN_CLR = (GPIO0_OUT_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_OUT_EN_CLR_ALL </item>
// </rtree>
//
// ---------------------------- Register Item Address: GPIO0_OUT --------------------------------
// SVD Line: 2862
unsigned int GPIO0_OUT __AT (0x40008018);
// ----------------------------- Field Item: GPIO0_OUT_GPIO_OUT ---------------------------------
// SVD Line: 2867
// <item> SFDITEM_FIELD__GPIO0_OUT_GPIO_OUT
// <name> GPIO_OUT </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008018) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_OUT >> 0) & 0xFFFFFFFF), ((GPIO0_OUT = (GPIO0_OUT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: GPIO0_OUT -----------------------------------
// SVD Line: 2862
// <rtree> SFDITEM_REG__GPIO0_OUT
// <name> OUT </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008018) GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. </i>
// <loc> ( (unsigned int)((GPIO0_OUT >> 0) & 0xFFFFFFFF), ((GPIO0_OUT = (GPIO0_OUT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_OUT_GPIO_OUT </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_OUT_SET ------------------------------
// SVD Line: 2887
unsigned int GPIO0_OUT_SET __AT (0x4000801C);
// ------------------------- Field Item: GPIO0_OUT_SET_GPIO_OUT_SET -----------------------------
// SVD Line: 2893
// <item> SFDITEM_FIELD__GPIO0_OUT_SET_GPIO_OUT_SET
// <name> GPIO_OUT_SET </name>
// <w>
// <i> [Bits 31..0] WO (@ 0x4000801C) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_OUT_SET >> 0) & 0x0), ((GPIO0_OUT_SET = (GPIO0_OUT_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_OUT_SET ---------------------------------
// SVD Line: 2887
// <rtree> SFDITEM_REG__GPIO0_OUT_SET
// <name> OUT_SET </name>
// <w>
// <i> [Bits 31..0] WO (@ 0x4000801C) GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_OUT_SET >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_SET = (GPIO0_OUT_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_OUT_SET_GPIO_OUT_SET </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_OUT_CLR ------------------------------
// SVD Line: 2913
unsigned int GPIO0_OUT_CLR __AT (0x40008020);
// ------------------------- Field Item: GPIO0_OUT_CLR_GPIO_OUT_CLR -----------------------------
// SVD Line: 2919
// <item> SFDITEM_FIELD__GPIO0_OUT_CLR_GPIO_OUT_CLR
// <name> GPIO_OUT_CLR </name>
// <w>
// <i> [Bits 31..0] WO (@ 0x40008020) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_OUT_CLR >> 0) & 0x0), ((GPIO0_OUT_CLR = (GPIO0_OUT_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_OUT_CLR ---------------------------------
// SVD Line: 2913
// <rtree> SFDITEM_REG__GPIO0_OUT_CLR
// <name> OUT_CLR </name>
// <w>
// <i> [Bits 31..0] WO (@ 0x40008020) GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_OUT_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_CLR = (GPIO0_OUT_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_OUT_CLR_GPIO_OUT_CLR </item>
// </rtree>
//
// ----------------------------- Register Item Address: GPIO0_IN --------------------------------
// SVD Line: 2927
unsigned int GPIO0_IN __AT (0x40008024);
// ------------------------------ Field Item: GPIO0_IN_GPIO_IN ----------------------------------
// SVD Line: 2933
// <item> SFDITEM_FIELD__GPIO0_IN_GPIO_IN
// <name> GPIO_IN </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40008024) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_IN >> 0) & 0xFFFFFFFF) ) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: GPIO0_IN ------------------------------------
// SVD Line: 2927
// <rtree> SFDITEM_REG__GPIO0_IN
// <name> IN </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40008024) GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. </i>
// <loc> ( (unsigned int)((GPIO0_IN >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__GPIO0_IN_GPIO_IN </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_INT_MOD ------------------------------
// SVD Line: 2941
unsigned int GPIO0_INT_MOD __AT (0x40008028);
// ------------------------- Field Item: GPIO0_INT_MOD_GPIO_INT_MOD -----------------------------
// SVD Line: 2946
// <item> SFDITEM_FIELD__GPIO0_INT_MOD_GPIO_INT_MOD
// <name> GPIO_INT_MOD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008028) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_INT_MOD >> 0) & 0xFFFFFFFF), ((GPIO0_INT_MOD = (GPIO0_INT_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_INT_MOD ---------------------------------
// SVD Line: 2941
// <rtree> SFDITEM_REG__GPIO0_INT_MOD
// <name> INT_MOD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008028) GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. </i>
// <loc> ( (unsigned int)((GPIO0_INT_MOD >> 0) & 0xFFFFFFFF), ((GPIO0_INT_MOD = (GPIO0_INT_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_INT_MOD_GPIO_INT_MOD </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_INT_POL ------------------------------
// SVD Line: 2966
unsigned int GPIO0_INT_POL __AT (0x4000802C);
// ------------------------- Field Item: GPIO0_INT_POL_GPIO_INT_POL -----------------------------
// SVD Line: 2971
// <item> SFDITEM_FIELD__GPIO0_INT_POL_GPIO_INT_POL
// <name> GPIO_INT_POL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000802C) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_INT_POL >> 0) & 0xFFFFFFFF), ((GPIO0_INT_POL = (GPIO0_INT_POL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_INT_POL ---------------------------------
// SVD Line: 2966
// <rtree> SFDITEM_REG__GPIO0_INT_POL
// <name> INT_POL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000802C) GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. </i>
// <loc> ( (unsigned int)((GPIO0_INT_POL >> 0) & 0xFFFFFFFF), ((GPIO0_INT_POL = (GPIO0_INT_POL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_INT_POL_GPIO_INT_POL </item>
// </rtree>
//
// --------------------------- Register Item Address: GPIO0_INT_EN ------------------------------
// SVD Line: 2991
unsigned int GPIO0_INT_EN __AT (0x40008034);
// -------------------------- Field Item: GPIO0_INT_EN_GPIO_INT_EN ------------------------------
// SVD Line: 2996
// <item> SFDITEM_FIELD__GPIO0_INT_EN_GPIO_INT_EN
// <name> GPIO_INT_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008034) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_INT_EN >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN = (GPIO0_INT_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_INT_EN ----------------------------------
// SVD Line: 2991
// <rtree> SFDITEM_REG__GPIO0_INT_EN
// <name> INT_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008034) GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. </i>
// <loc> ( (unsigned int)((GPIO0_INT_EN >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN = (GPIO0_INT_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_INT_EN_GPIO_INT_EN </item>
// </rtree>
//
// ------------------------- Register Item Address: GPIO0_INT_EN_SET ----------------------------
// SVD Line: 3016
unsigned int GPIO0_INT_EN_SET __AT (0x40008038);
// ---------------------- Field Item: GPIO0_INT_EN_SET_GPIO_INT_EN_SET --------------------------
// SVD Line: 3021
// <item> SFDITEM_FIELD__GPIO0_INT_EN_SET_GPIO_INT_EN_SET
// <name> GPIO_INT_EN_SET </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008038) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_INT_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN_SET = (GPIO0_INT_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: GPIO0_INT_EN_SET --------------------------------
// SVD Line: 3016
// <rtree> SFDITEM_REG__GPIO0_INT_EN_SET
// <name> INT_EN_SET </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008038) GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_INT_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN_SET = (GPIO0_INT_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_INT_EN_SET_GPIO_INT_EN_SET </item>
// </rtree>
//
// ------------------------- Register Item Address: GPIO0_INT_EN_CLR ----------------------------
// SVD Line: 3041
unsigned int GPIO0_INT_EN_CLR __AT (0x4000803C);
// ---------------------- Field Item: GPIO0_INT_EN_CLR_GPIO_INT_EN_CLR --------------------------
// SVD Line: 3046
// <item> SFDITEM_FIELD__GPIO0_INT_EN_CLR_GPIO_INT_EN_CLR
// <name> GPIO_INT_EN_CLR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000803C) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_INT_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN_CLR = (GPIO0_INT_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: GPIO0_INT_EN_CLR --------------------------------
// SVD Line: 3041
// <rtree> SFDITEM_REG__GPIO0_INT_EN_CLR
// <name> INT_EN_CLR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000803C) GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_INT_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN_CLR = (GPIO0_INT_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_INT_EN_CLR_GPIO_INT_EN_CLR </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_INT_STAT -----------------------------
// SVD Line: 3066
unsigned int GPIO0_INT_STAT __AT (0x40008040);
// ------------------------ Field Item: GPIO0_INT_STAT_GPIO_INT_STAT ----------------------------
// SVD Line: 3072
// <item> SFDITEM_FIELD__GPIO0_INT_STAT_GPIO_INT_STAT
// <name> GPIO_INT_STAT </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40008040) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_INT_STAT >> 0) & 0xFFFFFFFF) ) </loc>
// </edit>
// </item>
//
// ----------------------------- Register RTree: GPIO0_INT_STAT ---------------------------------
// SVD Line: 3066
// <rtree> SFDITEM_REG__GPIO0_INT_STAT
// <name> INT_STAT </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40008040) GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. </i>
// <loc> ( (unsigned int)((GPIO0_INT_STAT >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__GPIO0_INT_STAT_GPIO_INT_STAT </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_INT_CLR ------------------------------
// SVD Line: 3092
unsigned int GPIO0_INT_CLR __AT (0x40008048);
// ------------------------------ Field Item: GPIO0_INT_CLR_ALL ---------------------------------
// SVD Line: 3097
// <item> SFDITEM_FIELD__GPIO0_INT_CLR_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008048) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_INT_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_INT_CLR = (GPIO0_INT_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_INT_CLR ---------------------------------
// SVD Line: 3092
// <rtree> SFDITEM_REG__GPIO0_INT_CLR
// <name> INT_CLR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008048) GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_INT_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_INT_CLR = (GPIO0_INT_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_INT_CLR_ALL </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_WAKE_EN ------------------------------
// SVD Line: 3105
unsigned int GPIO0_WAKE_EN __AT (0x4000804C);
// ------------------------- Field Item: GPIO0_WAKE_EN_GPIO_WAKE_EN -----------------------------
// SVD Line: 3110
// <item> SFDITEM_FIELD__GPIO0_WAKE_EN_GPIO_WAKE_EN
// <name> GPIO_WAKE_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000804C) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_WAKE_EN >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN = (GPIO0_WAKE_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_WAKE_EN ---------------------------------
// SVD Line: 3105
// <rtree> SFDITEM_REG__GPIO0_WAKE_EN
// <name> WAKE_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000804C) GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. </i>
// <loc> ( (unsigned int)((GPIO0_WAKE_EN >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN = (GPIO0_WAKE_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_WAKE_EN_GPIO_WAKE_EN </item>
// </rtree>
//
// ------------------------ Register Item Address: GPIO0_WAKE_EN_SET ----------------------------
// SVD Line: 3130
unsigned int GPIO0_WAKE_EN_SET __AT (0x40008050);
// ---------------------------- Field Item: GPIO0_WAKE_EN_SET_ALL -------------------------------
// SVD Line: 3135
// <item> SFDITEM_FIELD__GPIO0_WAKE_EN_SET_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008050) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_WAKE_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN_SET = (GPIO0_WAKE_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: GPIO0_WAKE_EN_SET -------------------------------
// SVD Line: 3130
// <rtree> SFDITEM_REG__GPIO0_WAKE_EN_SET
// <name> WAKE_EN_SET </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008050) GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_WAKE_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN_SET = (GPIO0_WAKE_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_WAKE_EN_SET_ALL </item>
// </rtree>
//
// ------------------------ Register Item Address: GPIO0_WAKE_EN_CLR ----------------------------
// SVD Line: 3143
unsigned int GPIO0_WAKE_EN_CLR __AT (0x40008054);
// ---------------------------- Field Item: GPIO0_WAKE_EN_CLR_ALL -------------------------------
// SVD Line: 3148
// <item> SFDITEM_FIELD__GPIO0_WAKE_EN_CLR_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008054) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_WAKE_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN_CLR = (GPIO0_WAKE_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: GPIO0_WAKE_EN_CLR -------------------------------
// SVD Line: 3143
// <rtree> SFDITEM_REG__GPIO0_WAKE_EN_CLR
// <name> WAKE_EN_CLR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008054) GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_WAKE_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN_CLR = (GPIO0_WAKE_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_WAKE_EN_CLR_ALL </item>
// </rtree>
//
// ----------------------- Register Item Address: GPIO0_INT_DUAL_EDGE ---------------------------
// SVD Line: 3156
unsigned int GPIO0_INT_DUAL_EDGE __AT (0x4000805C);
// ------------------- Field Item: GPIO0_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE -----------------------
// SVD Line: 3161
// <item> SFDITEM_FIELD__GPIO0_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE
// <name> GPIO_INT_DUAL_EDGE </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000805C) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_INT_DUAL_EDGE >> 0) & 0xFFFFFFFF), ((GPIO0_INT_DUAL_EDGE = (GPIO0_INT_DUAL_EDGE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------------- Register RTree: GPIO0_INT_DUAL_EDGE ------------------------------
// SVD Line: 3156
// <rtree> SFDITEM_REG__GPIO0_INT_DUAL_EDGE
// <name> INT_DUAL_EDGE </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000805C) GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. </i>
// <loc> ( (unsigned int)((GPIO0_INT_DUAL_EDGE >> 0) & 0xFFFFFFFF), ((GPIO0_INT_DUAL_EDGE = (GPIO0_INT_DUAL_EDGE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_PAD_CFG1 -----------------------------
// SVD Line: 3181
unsigned int GPIO0_PAD_CFG1 __AT (0x40008060);
// ------------------------ Field Item: GPIO0_PAD_CFG1_GPIO_PAD_CFG1 ----------------------------
// SVD Line: 3186
// <item> SFDITEM_FIELD__GPIO0_PAD_CFG1_GPIO_PAD_CFG1
// <name> GPIO_PAD_CFG1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008060) The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_PAD_CFG1 >> 0) & 0xFFFFFFFF), ((GPIO0_PAD_CFG1 = (GPIO0_PAD_CFG1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register RTree: GPIO0_PAD_CFG1 ---------------------------------
// SVD Line: 3181
// <rtree> SFDITEM_REG__GPIO0_PAD_CFG1
// <name> PAD_CFG1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008060) GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. </i>
// <loc> ( (unsigned int)((GPIO0_PAD_CFG1 >> 0) & 0xFFFFFFFF), ((GPIO0_PAD_CFG1 = (GPIO0_PAD_CFG1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_PAD_CFG1_GPIO_PAD_CFG1 </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_PAD_CFG2 -----------------------------
// SVD Line: 3211
unsigned int GPIO0_PAD_CFG2 __AT (0x40008064);
// ------------------------ Field Item: GPIO0_PAD_CFG2_GPIO_PAD_CFG2 ----------------------------
// SVD Line: 3216
// <item> SFDITEM_FIELD__GPIO0_PAD_CFG2_GPIO_PAD_CFG2
// <name> GPIO_PAD_CFG2 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008064) The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_PAD_CFG2 >> 0) & 0xFFFFFFFF), ((GPIO0_PAD_CFG2 = (GPIO0_PAD_CFG2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register RTree: GPIO0_PAD_CFG2 ---------------------------------
// SVD Line: 3211
// <rtree> SFDITEM_REG__GPIO0_PAD_CFG2
// <name> PAD_CFG2 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008064) GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. </i>
// <loc> ( (unsigned int)((GPIO0_PAD_CFG2 >> 0) & 0xFFFFFFFF), ((GPIO0_PAD_CFG2 = (GPIO0_PAD_CFG2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_PAD_CFG2_GPIO_PAD_CFG2 </item>
// </rtree>
//
// ---------------------------- Register Item Address: GPIO0_EN1 --------------------------------
// SVD Line: 3241
unsigned int GPIO0_EN1 __AT (0x40008068);
// ----------------------------- Field Item: GPIO0_EN1_GPIO_EN1 ---------------------------------
// SVD Line: 3246
// <item> SFDITEM_FIELD__GPIO0_EN1_GPIO_EN1
// <name> GPIO_EN1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008068) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN1 >> 0) & 0xFFFFFFFF), ((GPIO0_EN1 = (GPIO0_EN1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: GPIO0_EN1 -----------------------------------
// SVD Line: 3241
// <rtree> SFDITEM_REG__GPIO0_EN1
// <name> EN1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008068) GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. </i>
// <loc> ( (unsigned int)((GPIO0_EN1 >> 0) & 0xFFFFFFFF), ((GPIO0_EN1 = (GPIO0_EN1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN1_GPIO_EN1 </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_EN1_SET ------------------------------
// SVD Line: 3266
unsigned int GPIO0_EN1_SET __AT (0x4000806C);
// ------------------------------ Field Item: GPIO0_EN1_SET_ALL ---------------------------------
// SVD Line: 3271
// <item> SFDITEM_FIELD__GPIO0_EN1_SET_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000806C) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN1_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN1_SET = (GPIO0_EN1_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_EN1_SET ---------------------------------
// SVD Line: 3266
// <rtree> SFDITEM_REG__GPIO0_EN1_SET
// <name> EN1_SET </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000806C) GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_EN1_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN1_SET = (GPIO0_EN1_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN1_SET_ALL </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_EN1_CLR ------------------------------
// SVD Line: 3279
unsigned int GPIO0_EN1_CLR __AT (0x40008070);
// ------------------------------ Field Item: GPIO0_EN1_CLR_ALL ---------------------------------
// SVD Line: 3284
// <item> SFDITEM_FIELD__GPIO0_EN1_CLR_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008070) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN1_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN1_CLR = (GPIO0_EN1_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_EN1_CLR ---------------------------------
// SVD Line: 3279
// <rtree> SFDITEM_REG__GPIO0_EN1_CLR
// <name> EN1_CLR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008070) GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_EN1_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN1_CLR = (GPIO0_EN1_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN1_CLR_ALL </item>
// </rtree>
//
// ---------------------------- Register Item Address: GPIO0_EN2 --------------------------------
// SVD Line: 3292
unsigned int GPIO0_EN2 __AT (0x40008074);
// ----------------------------- Field Item: GPIO0_EN2_GPIO_EN2 ---------------------------------
// SVD Line: 3297
// <item> SFDITEM_FIELD__GPIO0_EN2_GPIO_EN2
// <name> GPIO_EN2 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008074) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN2 >> 0) & 0xFFFFFFFF), ((GPIO0_EN2 = (GPIO0_EN2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: GPIO0_EN2 -----------------------------------
// SVD Line: 3292
// <rtree> SFDITEM_REG__GPIO0_EN2
// <name> EN2 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008074) GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. </i>
// <loc> ( (unsigned int)((GPIO0_EN2 >> 0) & 0xFFFFFFFF), ((GPIO0_EN2 = (GPIO0_EN2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN2_GPIO_EN2 </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_EN2_SET ------------------------------
// SVD Line: 3317
unsigned int GPIO0_EN2_SET __AT (0x40008078);
// ------------------------------ Field Item: GPIO0_EN2_SET_ALL ---------------------------------
// SVD Line: 3322
// <item> SFDITEM_FIELD__GPIO0_EN2_SET_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008078) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN2_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN2_SET = (GPIO0_EN2_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_EN2_SET ---------------------------------
// SVD Line: 3317
// <rtree> SFDITEM_REG__GPIO0_EN2_SET
// <name> EN2_SET </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40008078) GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_EN2_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN2_SET = (GPIO0_EN2_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN2_SET_ALL </item>
// </rtree>
//
// -------------------------- Register Item Address: GPIO0_EN2_CLR ------------------------------
// SVD Line: 3330
unsigned int GPIO0_EN2_CLR __AT (0x4000807C);
// ------------------------------ Field Item: GPIO0_EN2_CLR_ALL ---------------------------------
// SVD Line: 3335
// <item> SFDITEM_FIELD__GPIO0_EN2_CLR_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000807C) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_EN2_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN2_CLR = (GPIO0_EN2_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: GPIO0_EN2_CLR ---------------------------------
// SVD Line: 3330
// <rtree> SFDITEM_REG__GPIO0_EN2_CLR
// <name> EN2_CLR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000807C) GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. </i>
// <loc> ( (unsigned int)((GPIO0_EN2_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN2_CLR = (GPIO0_EN2_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_EN2_CLR_ALL </item>
// </rtree>
//
// ----------------------------- Register Item Address: GPIO0_IS --------------------------------
// SVD Line: 3343
unsigned int GPIO0_IS __AT (0x400080A8);
// --------------------------------- Register Item: GPIO0_IS ------------------------------------
// SVD Line: 3343
// <item> SFDITEM_REG__GPIO0_IS
// <name> IS </name>
// <i> [Bits 31..0] RW (@ 0x400080A8) Input Hysteresis Enable Register </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_IS >> 0) & 0xFFFFFFFF), ((GPIO0_IS = (GPIO0_IS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: GPIO0_SR --------------------------------
// SVD Line: 3348
unsigned int GPIO0_SR __AT (0x400080AC);
// --------------------------------- Register Item: GPIO0_SR ------------------------------------
// SVD Line: 3348
// <item> SFDITEM_REG__GPIO0_SR
// <name> SR </name>
// <i> [Bits 31..0] RW (@ 0x400080AC) Slew Rate Select Register. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_SR >> 0) & 0xFFFFFFFF), ((GPIO0_SR = (GPIO0_SR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: GPIO0_DS --------------------------------
// SVD Line: 3353
unsigned int GPIO0_DS __AT (0x400080B0);
// --------------------------------- Field Item: GPIO0_DS_DS ------------------------------------
// SVD Line: 3358
// <item> SFDITEM_FIELD__GPIO0_DS_DS
// <name> DS </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x400080B0) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_DS >> 0) & 0xFFFFFFFF), ((GPIO0_DS = (GPIO0_DS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: GPIO0_DS ------------------------------------
// SVD Line: 3353
// <rtree> SFDITEM_REG__GPIO0_DS
// <name> DS </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x400080B0) GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. </i>
// <loc> ( (unsigned int)((GPIO0_DS >> 0) & 0xFFFFFFFF), ((GPIO0_DS = (GPIO0_DS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_DS_DS </item>
// </rtree>
//
// ---------------------------- Register Item Address: GPIO0_DS1 --------------------------------
// SVD Line: 3378
unsigned int GPIO0_DS1 __AT (0x400080B4);
// -------------------------------- Field Item: GPIO0_DS1_ALL -----------------------------------
// SVD Line: 3383
// <item> SFDITEM_FIELD__GPIO0_DS1_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x400080B4) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_DS1 >> 0) & 0xFFFFFFFF), ((GPIO0_DS1 = (GPIO0_DS1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: GPIO0_DS1 -----------------------------------
// SVD Line: 3378
// <rtree> SFDITEM_REG__GPIO0_DS1
// <name> DS1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x400080B4) GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. </i>
// <loc> ( (unsigned int)((GPIO0_DS1 >> 0) & 0xFFFFFFFF), ((GPIO0_DS1 = (GPIO0_DS1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_DS1_ALL </item>
// </rtree>
//
// ----------------------------- Register Item Address: GPIO0_PS --------------------------------
// SVD Line: 3391
unsigned int GPIO0_PS __AT (0x400080B8);
// -------------------------------- Field Item: GPIO0_PS_ALL ------------------------------------
// SVD Line: 3396
// <item> SFDITEM_FIELD__GPIO0_PS_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x400080B8) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_PS >> 0) & 0xFFFFFFFF), ((GPIO0_PS = (GPIO0_PS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: GPIO0_PS ------------------------------------
// SVD Line: 3391
// <rtree> SFDITEM_REG__GPIO0_PS
// <name> PS </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x400080B8) GPIO Pull Select Mode. </i>
// <loc> ( (unsigned int)((GPIO0_PS >> 0) & 0xFFFFFFFF), ((GPIO0_PS = (GPIO0_PS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_PS_ALL </item>
// </rtree>
//
// --------------------------- Register Item Address: GPIO0_VSSEL -------------------------------
// SVD Line: 3404
unsigned int GPIO0_VSSEL __AT (0x400080C0);
// ------------------------------- Field Item: GPIO0_VSSEL_ALL ----------------------------------
// SVD Line: 3409
// <item> SFDITEM_FIELD__GPIO0_VSSEL_ALL
// <name> ALL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x400080C0) Mask of all of the pins on the port. </i>
// <edit>
// <loc> ( (unsigned int)((GPIO0_VSSEL >> 0) & 0xFFFFFFFF), ((GPIO0_VSSEL = (GPIO0_VSSEL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: GPIO0_VSSEL ----------------------------------
// SVD Line: 3404
// <rtree> SFDITEM_REG__GPIO0_VSSEL
// <name> VSSEL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x400080C0) GPIO Voltage Select. </i>
// <loc> ( (unsigned int)((GPIO0_VSSEL >> 0) & 0xFFFFFFFF), ((GPIO0_VSSEL = (GPIO0_VSSEL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__GPIO0_VSSEL_ALL </item>
// </rtree>
//
// --------------------------------- Peripheral View: GPIO0 -------------------------------------
// SVD Line: 2744
// <view> GPIO0
// <name> GPIO0 </name>
// <item> SFDITEM_REG__GPIO0_EN </item>
// <item> SFDITEM_REG__GPIO0_EN_SET </item>
// <item> SFDITEM_REG__GPIO0_EN_CLR </item>
// <item> SFDITEM_REG__GPIO0_OUT_EN </item>
// <item> SFDITEM_REG__GPIO0_OUT_EN_SET </item>
// <item> SFDITEM_REG__GPIO0_OUT_EN_CLR </item>
// <item> SFDITEM_REG__GPIO0_OUT </item>
// <item> SFDITEM_REG__GPIO0_OUT_SET </item>
// <item> SFDITEM_REG__GPIO0_OUT_CLR </item>
// <item> SFDITEM_REG__GPIO0_IN </item>
// <item> SFDITEM_REG__GPIO0_INT_MOD </item>
// <item> SFDITEM_REG__GPIO0_INT_POL </item>
// <item> SFDITEM_REG__GPIO0_INT_EN </item>
// <item> SFDITEM_REG__GPIO0_INT_EN_SET </item>
// <item> SFDITEM_REG__GPIO0_INT_EN_CLR </item>
// <item> SFDITEM_REG__GPIO0_INT_STAT </item>
// <item> SFDITEM_REG__GPIO0_INT_CLR </item>
// <item> SFDITEM_REG__GPIO0_WAKE_EN </item>
// <item> SFDITEM_REG__GPIO0_WAKE_EN_SET </item>
// <item> SFDITEM_REG__GPIO0_WAKE_EN_CLR </item>
// <item> SFDITEM_REG__GPIO0_INT_DUAL_EDGE </item>
// <item> SFDITEM_REG__GPIO0_PAD_CFG1 </item>
// <item> SFDITEM_REG__GPIO0_PAD_CFG2 </item>
// <item> SFDITEM_REG__GPIO0_EN1 </item>
// <item> SFDITEM_REG__GPIO0_EN1_SET </item>
// <item> SFDITEM_REG__GPIO0_EN1_CLR </item>
// <item> SFDITEM_REG__GPIO0_EN2 </item>
// <item> SFDITEM_REG__GPIO0_EN2_SET </item>
// <item> SFDITEM_REG__GPIO0_EN2_CLR </item>
// <item> SFDITEM_REG__GPIO0_IS </item>
// <item> SFDITEM_REG__GPIO0_SR </item>
// <item> SFDITEM_REG__GPIO0_DS </item>
// <item> SFDITEM_REG__GPIO0_DS1 </item>
// <item> SFDITEM_REG__GPIO0_PS </item>
// <item> SFDITEM_REG__GPIO0_VSSEL </item>
// </view>
//
// ---------------------------- Register Item Address: I2C0_CTRL --------------------------------
// SVD Line: 3437
unsigned int I2C0_CTRL __AT (0x4001D000);
// ------------------------------ Field Item: I2C0_CTRL_I2C_EN ----------------------------------
// SVD Line: 3442
// <item> SFDITEM_FIELD__I2C0_CTRL_I2C_EN
// <name> I2C_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D000) \nI2C Enable.\n0 : dis = Disable I2C.\n1 : en = enable I2C. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.0..0> I2C_EN
// <0=> 0: dis = Disable I2C.
// <1=> 1: en = enable I2C.
// </combo>
// </item>
//
// -------------------------------- Field Item: I2C0_CTRL_MST -----------------------------------
// SVD Line: 3460
// <item> SFDITEM_FIELD__I2C0_CTRL_MST
// <name> MST </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D000) \nMaster Mode Enable.\n0 : slave_mode = Slave Mode.\n1 : master_mode = Master Mode. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.1..1> MST
// <0=> 0: slave_mode = Slave Mode.
// <1=> 1: master_mode = Master Mode.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_CTRL_GEN_CALL_ADDR ------------------------------
// SVD Line: 3478
// <item> SFDITEM_FIELD__I2C0_CTRL_GEN_CALL_ADDR
// <name> GEN_CALL_ADDR </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001D000) \nGeneral Call Address Enable.\n0 : dis = Ignore Gneral Call Address.\n1 : en = Acknowledge general call address. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.2..2> GEN_CALL_ADDR
// <0=> 0: dis = Ignore Gneral Call Address.
// <1=> 1: en = Acknowledge general call address.
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C0_CTRL_RX_MODE ---------------------------------
// SVD Line: 3496
// <item> SFDITEM_FIELD__I2C0_CTRL_RX_MODE
// <name> RX_MODE </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001D000) \nInteractive Receive Mode.\n0 : dis = Disable Interactive Receive Mode.\n1 : en = Enable Interactive Receive Mode. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.3..3> RX_MODE
// <0=> 0: dis = Disable Interactive Receive Mode.
// <1=> 1: en = Enable Interactive Receive Mode.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_CTRL_RX_MODE_ACK -------------------------------
// SVD Line: 3514
// <item> SFDITEM_FIELD__I2C0_CTRL_RX_MODE_ACK
// <name> RX_MODE_ACK </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001D000) \nData Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.\n0 : ack = return ACK (pulling SDA LOW).\n1 : nack = return NACK (leaving SDA HIGH). </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.4..4> RX_MODE_ACK
// <0=> 0: ack = return ACK (pulling SDA LOW).
// <1=> 1: nack = return NACK (leaving SDA HIGH).
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C0_CTRL_SCL_OUT ---------------------------------
// SVD Line: 3532
// <item> SFDITEM_FIELD__I2C0_CTRL_SCL_OUT
// <name> SCL_OUT </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4001D000) \nSCL Output. This bits control SCL output when SWOE =1.\n0 : drive_scl_low = Drive SCL low.\n1 : release_scl = Release SCL. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.6..6> SCL_OUT
// <0=> 0: drive_scl_low = Drive SCL low.
// <1=> 1: release_scl = Release SCL.
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C0_CTRL_SDA_OUT ---------------------------------
// SVD Line: 3550
// <item> SFDITEM_FIELD__I2C0_CTRL_SDA_OUT
// <name> SDA_OUT </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001D000) \nSDA Output. This bits control SDA output when SWOE = 1.\n0 : drive_sda_low = Drive SDA low.\n1 : release_sda = Release SDA. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.7..7> SDA_OUT
// <0=> 0: drive_sda_low = Drive SDA low.
// <1=> 1: release_sda = Release SDA.
// </combo>
// </item>
//
// -------------------------------- Field Item: I2C0_CTRL_SCL -----------------------------------
// SVD Line: 3568
// <item> SFDITEM_FIELD__I2C0_CTRL_SCL
// <name> SCL </name>
// <r>
// <i> [Bit 8] RO (@ 0x4001D000) SCL status. This bit reflects the logic gate of SCL signal. </i>
// <check>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.8..8> SCL
// </check>
// </item>
//
// -------------------------------- Field Item: I2C0_CTRL_SDA -----------------------------------
// SVD Line: 3574
// <item> SFDITEM_FIELD__I2C0_CTRL_SDA
// <name> SDA </name>
// <r>
// <i> [Bit 9] RO (@ 0x4001D000) SDA status. THis bit reflects the logic gate of SDA signal. </i>
// <check>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.9..9> SDA
// </check>
// </item>
//
// ----------------------------- Field Item: I2C0_CTRL_SW_OUT_EN --------------------------------
// SVD Line: 3580
// <item> SFDITEM_FIELD__I2C0_CTRL_SW_OUT_EN
// <name> SW_OUT_EN </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001D000) \nSoftware Output Enable.\n0 : outputs_disable = I2C Outputs SCLO and SDAO disabled.\n1 : outputs_enable = I2C Outputs SCLO and SDAO enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.10..10> SW_OUT_EN
// <0=> 0: outputs_disable = I2C Outputs SCLO and SDAO disabled.
// <1=> 1: outputs_enable = I2C Outputs SCLO and SDAO enabled.
// </combo>
// </item>
//
// ------------------------------- Field Item: I2C0_CTRL_READ -----------------------------------
// SVD Line: 3598
// <item> SFDITEM_FIELD__I2C0_CTRL_READ
// <name> READ </name>
// <r>
// <i> [Bit 11] RO (@ 0x4001D000) \nRead. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.\n0 : write = Write.\n1 : read = Read. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.11..11> READ
// <0=> 0: write = Write.
// <1=> 1: read = Read.
// </combo>
// </item>
//
// ------------------------ Field Item: I2C0_CTRL_SCL_CLK_STRECH_DIS ----------------------------
// SVD Line: 3616
// <item> SFDITEM_FIELD__I2C0_CTRL_SCL_CLK_STRECH_DIS
// <name> SCL_CLK_STRECH_DIS </name>
// <rw>
// <i> [Bit 12] RW (@ 0x4001D000) \nThis bit will disable slave clock stretching when set.\n0 : en = Slave clock stretching enabled.\n1 : dis = Slave clock stretching disabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.12..12> SCL_CLK_STRECH_DIS
// <0=> 0: en = Slave clock stretching enabled.
// <1=> 1: dis = Slave clock stretching disabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_CTRL_SCL_PP_MODE -------------------------------
// SVD Line: 3634
// <item> SFDITEM_FIELD__I2C0_CTRL_SCL_PP_MODE
// <name> SCL_PP_MODE </name>
// <rw>
// <i> [Bit 13] RW (@ 0x4001D000) \nSCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.\n0 : dis = Standard open-drain operation: drive low for 0, Hi-Z for 1\n1 : en = Non-standard push-pull operation: drive low for 0, drive high for 1 </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.13..13> SCL_PP_MODE
// <0=> 0: dis = Standard open-drain operation: drive low for 0, Hi-Z for 1
// <1=> 1: en = Non-standard push-pull operation: drive low for 0, drive high for 1
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C0_CTRL_HS_MODE ---------------------------------
// SVD Line: 3652
// <item> SFDITEM_FIELD__I2C0_CTRL_HS_MODE
// <name> HS_MODE </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4001D000) \nHs-mode Enable.\n0 : dis = Hs-mode disabled.\n1 : en = Hs-mode enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_CTRL ) </loc>
// <o.15..15> HS_MODE
// <0=> 0: dis = Hs-mode disabled.
// <1=> 1: en = Hs-mode enabled.
// </combo>
// </item>
//
// -------------------------------- Register RTree: I2C0_CTRL -----------------------------------
// SVD Line: 3437
// <rtree> SFDITEM_REG__I2C0_CTRL
// <name> CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D000) Control Register0. </i>
// <loc> ( (unsigned int)((I2C0_CTRL >> 0) & 0xFFFFFFFF), ((I2C0_CTRL = (I2C0_CTRL & ~(0xB4DFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB4DF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_CTRL_I2C_EN </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_MST </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_GEN_CALL_ADDR </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_RX_MODE </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_RX_MODE_ACK </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_SCL_OUT </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_SDA_OUT </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_SCL </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_SDA </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_SW_OUT_EN </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_READ </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_SCL_CLK_STRECH_DIS </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_SCL_PP_MODE </item>
// <item> SFDITEM_FIELD__I2C0_CTRL_HS_MODE </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_STATUS -------------------------------
// SVD Line: 3672
unsigned int I2C0_STATUS __AT (0x4001D004);
// ------------------------------- Field Item: I2C0_STATUS_BUS ----------------------------------
// SVD Line: 3677
// <item> SFDITEM_FIELD__I2C0_STATUS_BUS
// <name> BUS </name>
// <r>
// <i> [Bit 0] RO (@ 0x4001D004) \nBus Status.\n0 : idle = I2C Bus Idle.\n1 : busy = I2C Bus Busy. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_STATUS ) </loc>
// <o.0..0> BUS
// <0=> 0: idle = I2C Bus Idle.
// <1=> 1: busy = I2C Bus Busy.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_STATUS_RX_EMPTY --------------------------------
// SVD Line: 3695
// <item> SFDITEM_FIELD__I2C0_STATUS_RX_EMPTY
// <name> RX_EMPTY </name>
// <r>
// <i> [Bit 1] RO (@ 0x4001D004) \nRX empty.\n0 : not_empty = Not Empty.\n1 : empty = Empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_STATUS ) </loc>
// <o.1..1> RX_EMPTY
// <0=> 0: not_empty = Not Empty.
// <1=> 1: empty = Empty.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C0_STATUS_RX_FULL --------------------------------
// SVD Line: 3713
// <item> SFDITEM_FIELD__I2C0_STATUS_RX_FULL
// <name> RX_FULL </name>
// <r>
// <i> [Bit 2] RO (@ 0x4001D004) \nRX Full.\n0 : not_full = Not Full.\n1 : full = Full. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_STATUS ) </loc>
// <o.2..2> RX_FULL
// <0=> 0: not_full = Not Full.
// <1=> 1: full = Full.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_STATUS_TX_EMPTY --------------------------------
// SVD Line: 3731
// <item> SFDITEM_FIELD__I2C0_STATUS_TX_EMPTY
// <name> TX_EMPTY </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001D004) \nTX Empty.\n0 : not_empty = Not Empty.\n1 : empty = Empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_STATUS ) </loc>
// <o.3..3> TX_EMPTY
// <0=> 0: not_empty = Not Empty.
// <1=> 1: empty = Empty.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C0_STATUS_TX_FULL --------------------------------
// SVD Line: 3748
// <item> SFDITEM_FIELD__I2C0_STATUS_TX_FULL
// <name> TX_FULL </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001D004) \nTX Full.\n0 : not_empty = Not Empty.\n1 : empty = Empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_STATUS ) </loc>
// <o.4..4> TX_FULL
// <0=> 0: not_empty = Not Empty.
// <1=> 1: empty = Empty.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_STATUS_CLK_MODE --------------------------------
// SVD Line: 3765
// <item> SFDITEM_FIELD__I2C0_STATUS_CLK_MODE
// <name> CLK_MODE </name>
// <r>
// <i> [Bit 5] RO (@ 0x4001D004) \nClock Mode.\n0 : not_actively_driving_scl_clock = Device not actively driving SCL clock cycles.\n1 : actively_driving_scl_clock = Device operating as master and actively driving SCL clock cycles. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_STATUS ) </loc>
// <o.5..5> CLK_MODE
// <0=> 0: not_actively_driving_scl_clock = Device not actively driving SCL clock cycles.
// <1=> 1: actively_driving_scl_clock = Device operating as master and actively driving SCL clock cycles.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C0_STATUS_STATUS ---------------------------------
// SVD Line: 3783
// <item> SFDITEM_FIELD__I2C0_STATUS_STATUS
// <name> STATUS </name>
// <rw>
// <i> [Bits 11..8] RW (@ 0x4001D004) \nController Status.\n0 : idle = Controller Idle.\n1 : mtx_addr = master Transmit address.\n2 : mrx_addr_ack = Master Receive address ACK.\n3 : mtx_ex_addr = Master Transmit extended address.\n4 : mrx_ex_addr = Master Receive extended address ACK.\n5 : srx_addr = Slave Receive address.\n6 : stx_addr_ack = Slave Transmit address ACK.\n7 : srx_ex_addr = Slave Receive extended address.\n8 : stx_ex_addr_ack = Slave Transmit extended address ACK.\n9 : tx = Transmit data (master or slave).\n10 : rx_ack = Receive data ACK (master or slave).\n11 : rx = Receive data (master or slave).\n12 : tx_ack = Transmit data ACK (master or slave).\n13 : nack = NACK stage (master or slave).\n14 : Reserved - do not use\n15 : by_st = Bystander state (ongoing transaction but not participant- another master addressing another slave). </i>
// <combo>
// <loc> ( (unsigned int) I2C0_STATUS ) </loc>
// <o.11..8> STATUS
// <0=> 0: idle = Controller Idle.
// <1=> 1: mtx_addr = master Transmit address.
// <2=> 2: mrx_addr_ack = Master Receive address ACK.
// <3=> 3: mtx_ex_addr = Master Transmit extended address.
// <4=> 4: mrx_ex_addr = Master Receive extended address ACK.
// <5=> 5: srx_addr = Slave Receive address.
// <6=> 6: stx_addr_ack = Slave Transmit address ACK.
// <7=> 7: srx_ex_addr = Slave Receive extended address.
// <8=> 8: stx_ex_addr_ack = Slave Transmit extended address ACK.
// <9=> 9: tx = Transmit data (master or slave).
// <10=> 10: rx_ack = Receive data ACK (master or slave).
// <11=> 11: rx = Receive data (master or slave).
// <12=> 12: tx_ack = Transmit data ACK (master or slave).
// <13=> 13: nack = NACK stage (master or slave).
// <14=> 14:
// <15=> 15: by_st = Bystander state (ongoing transaction but not participant- another master addressing another slave).
// </combo>
// </item>
//
// ------------------------------- Register RTree: I2C0_STATUS ----------------------------------
// SVD Line: 3672
// <rtree> SFDITEM_REG__I2C0_STATUS
// <name> STATUS </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D004) Status Register. </i>
// <loc> ( (unsigned int)((I2C0_STATUS >> 0) & 0xFFFFFFFF), ((I2C0_STATUS = (I2C0_STATUS & ~(0xF18UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF18) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_STATUS_BUS </item>
// <item> SFDITEM_FIELD__I2C0_STATUS_RX_EMPTY </item>
// <item> SFDITEM_FIELD__I2C0_STATUS_RX_FULL </item>
// <item> SFDITEM_FIELD__I2C0_STATUS_TX_EMPTY </item>
// <item> SFDITEM_FIELD__I2C0_STATUS_TX_FULL </item>
// <item> SFDITEM_FIELD__I2C0_STATUS_CLK_MODE </item>
// <item> SFDITEM_FIELD__I2C0_STATUS_STATUS </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_INT_FL0 ------------------------------
// SVD Line: 3867
unsigned int I2C0_INT_FL0 __AT (0x4001D008);
// ------------------------------ Field Item: I2C0_INT_FL0_DONE ---------------------------------
// SVD Line: 3872
// <item> SFDITEM_FIELD__I2C0_INT_FL0_DONE
// <name> DONE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D008) \nTransfer Done Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.0..0> DONE
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_FL0_RX_MODE --------------------------------
// SVD Line: 3890
// <item> SFDITEM_FIELD__I2C0_INT_FL0_RX_MODE
// <name> RX_MODE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D008) \nInteractive Receive Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.1..1> RX_MODE
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------- Field Item: I2C0_INT_FL0_GEN_CALL_ADDR -----------------------------
// SVD Line: 3907
// <item> SFDITEM_FIELD__I2C0_INT_FL0_GEN_CALL_ADDR
// <name> GEN_CALL_ADDR </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001D008) \nSlave General Call Address Match Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.2..2> GEN_CALL_ADDR
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_INT_FL0_ADDR_MATCH ------------------------------
// SVD Line: 3924
// <item> SFDITEM_FIELD__I2C0_INT_FL0_ADDR_MATCH
// <name> ADDR_MATCH </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001D008) \nSlave Address Match Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.3..3> ADDR_MATCH
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_INT_FL0_RX_THRESH -------------------------------
// SVD Line: 3941
// <item> SFDITEM_FIELD__I2C0_INT_FL0_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001D008) \nReceive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. RX_FIFO equal or more bytes than the threshold. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.4..4> RX_THRESH
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending. RX_FIFO equal or more bytes than the threshold.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_INT_FL0_TX_THRESH -------------------------------
// SVD Line: 3958
// <item> SFDITEM_FIELD__I2C0_INT_FL0_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bit 5] RW (@ 0x4001D008) \nTransmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.5..5> TX_THRESH
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C0_INT_FL0_STOP ---------------------------------
// SVD Line: 3975
// <item> SFDITEM_FIELD__I2C0_INT_FL0_STOP
// <name> STOP </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4001D008) \nSTOP Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.6..6> STOP
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_FL0_ADDR_ACK -------------------------------
// SVD Line: 3992
// <item> SFDITEM_FIELD__I2C0_INT_FL0_ADDR_ACK
// <name> ADDR_ACK </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001D008) \nAddress Acknowledge Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.7..7> ADDR_ACK
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C0_INT_FL0_ARB_ER --------------------------------
// SVD Line: 4009
// <item> SFDITEM_FIELD__I2C0_INT_FL0_ARB_ER
// <name> ARB_ER </name>
// <rw>
// <i> [Bit 8] RW (@ 0x4001D008) \nArbritation error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.8..8> ARB_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C0_INT_FL0_TO_ER ---------------------------------
// SVD Line: 4026
// <item> SFDITEM_FIELD__I2C0_INT_FL0_TO_ER
// <name> TO_ER </name>
// <rw>
// <i> [Bit 9] RW (@ 0x4001D008) \ntimeout Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.9..9> TO_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C0_INT_FL0_ADDR_NACK_ER -----------------------------
// SVD Line: 4043
// <item> SFDITEM_FIELD__I2C0_INT_FL0_ADDR_NACK_ER
// <name> ADDR_NACK_ER </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001D008) \nAddress NACK Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.10..10> ADDR_NACK_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_FL0_DATA_ER --------------------------------
// SVD Line: 4060
// <item> SFDITEM_FIELD__I2C0_INT_FL0_DATA_ER
// <name> DATA_ER </name>
// <rw>
// <i> [Bit 11] RW (@ 0x4001D008) \nData NACK Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.11..11> DATA_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------- Field Item: I2C0_INT_FL0_DO_NOT_RESP_ER ----------------------------
// SVD Line: 4077
// <item> SFDITEM_FIELD__I2C0_INT_FL0_DO_NOT_RESP_ER
// <name> DO_NOT_RESP_ER </name>
// <rw>
// <i> [Bit 12] RW (@ 0x4001D008) \nDo Not Respond Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.12..12> DO_NOT_RESP_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_FL0_START_ER -------------------------------
// SVD Line: 4094
// <item> SFDITEM_FIELD__I2C0_INT_FL0_START_ER
// <name> START_ER </name>
// <rw>
// <i> [Bit 13] RW (@ 0x4001D008) \nStart Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.13..13> START_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_FL0_STOP_ER --------------------------------
// SVD Line: 4111
// <item> SFDITEM_FIELD__I2C0_INT_FL0_STOP_ER
// <name> STOP_ER </name>
// <rw>
// <i> [Bit 14] RW (@ 0x4001D008) \nStop Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.14..14> STOP_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C0_INT_FL0_TX_LOCK_OUT ------------------------------
// SVD Line: 4128
// <item> SFDITEM_FIELD__I2C0_INT_FL0_TX_LOCK_OUT
// <name> TX_LOCK_OUT </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4001D008) Transmit Lock Out Interrupt. </i>
// <check>
// <loc> ( (unsigned int) I2C0_INT_FL0 ) </loc>
// <o.15..15> TX_LOCK_OUT
// </check>
// </item>
//
// ------------------------------ Register RTree: I2C0_INT_FL0 ----------------------------------
// SVD Line: 3867
// <rtree> SFDITEM_REG__I2C0_INT_FL0
// <name> INT_FL0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D008) Interrupt Status Register. </i>
// <loc> ( (unsigned int)((I2C0_INT_FL0 >> 0) & 0xFFFFFFFF), ((I2C0_INT_FL0 = (I2C0_INT_FL0 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_DONE </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_RX_MODE </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_GEN_CALL_ADDR </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_ADDR_MATCH </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_RX_THRESH </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_TX_THRESH </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_STOP </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_ADDR_ACK </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_ARB_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_TO_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_ADDR_NACK_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_DATA_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_DO_NOT_RESP_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_START_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_STOP_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL0_TX_LOCK_OUT </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_INT_EN0 ------------------------------
// SVD Line: 4135
unsigned int I2C0_INT_EN0 __AT (0x4001D00C);
// ------------------------------ Field Item: I2C0_INT_EN0_DONE ---------------------------------
// SVD Line: 4141
// <item> SFDITEM_FIELD__I2C0_INT_EN0_DONE
// <name> DONE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D00C) \nTransfer Done Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when DONE = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.0..0> DONE
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when DONE = 1.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_EN0_RX_MODE --------------------------------
// SVD Line: 4159
// <item> SFDITEM_FIELD__I2C0_INT_EN0_RX_MODE
// <name> RX_MODE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D00C) \nDescription not available.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when RX_MODE = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.1..1> RX_MODE
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when RX_MODE = 1.
// </combo>
// </item>
//
// ------------------------- Field Item: I2C0_INT_EN0_GEN_CTRL_ADDR -----------------------------
// SVD Line: 4177
// <item> SFDITEM_FIELD__I2C0_INT_EN0_GEN_CTRL_ADDR
// <name> GEN_CTRL_ADDR </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001D00C) \nSlave mode general call address match received input enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when GEN_CTRL_ADDR = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.2..2> GEN_CTRL_ADDR
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when GEN_CTRL_ADDR = 1.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_INT_EN0_ADDR_MATCH ------------------------------
// SVD Line: 4195
// <item> SFDITEM_FIELD__I2C0_INT_EN0_ADDR_MATCH
// <name> ADDR_MATCH </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001D00C) \nSlave mode incoming address match interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when ADDR_MATCH = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.3..3> ADDR_MATCH
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when ADDR_MATCH = 1.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_INT_EN0_RX_THRESH -------------------------------
// SVD Line: 4213
// <item> SFDITEM_FIELD__I2C0_INT_EN0_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001D00C) \nRX FIFO Above Treshold Level Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.4..4> RX_THRESH
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_INT_EN0_TX_THRESH -------------------------------
// SVD Line: 4231
// <item> SFDITEM_FIELD__I2C0_INT_EN0_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bit 5] RW (@ 0x4001D00C) \nTX FIFO Below Treshold Level Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.5..5> TX_THRESH
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C0_INT_EN0_STOP ---------------------------------
// SVD Line: 4248
// <item> SFDITEM_FIELD__I2C0_INT_EN0_STOP
// <name> STOP </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4001D00C) \nStop Interrupt Enable\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when STOP = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.6..6> STOP
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when STOP = 1.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_EN0_ADDR_ACK -------------------------------
// SVD Line: 4266
// <item> SFDITEM_FIELD__I2C0_INT_EN0_ADDR_ACK
// <name> ADDR_ACK </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001D00C) \nReceived Address ACK from Slave Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.7..7> ADDR_ACK
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C0_INT_EN0_ARB_ER --------------------------------
// SVD Line: 4283
// <item> SFDITEM_FIELD__I2C0_INT_EN0_ARB_ER
// <name> ARB_ER </name>
// <rw>
// <i> [Bit 8] RW (@ 0x4001D00C) \nMaster Mode Arbitration Lost Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.8..8> ARB_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C0_INT_EN0_TO_ER ---------------------------------
// SVD Line: 4300
// <item> SFDITEM_FIELD__I2C0_INT_EN0_TO_ER
// <name> TO_ER </name>
// <rw>
// <i> [Bit 9] RW (@ 0x4001D00C) \nTimeout Error Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.9..9> TO_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_EN0_ADDR_ER --------------------------------
// SVD Line: 4317
// <item> SFDITEM_FIELD__I2C0_INT_EN0_ADDR_ER
// <name> ADDR_ER </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001D00C) \nMaster Mode Address NACK Received Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.10..10> ADDR_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_EN0_DATA_ER --------------------------------
// SVD Line: 4334
// <item> SFDITEM_FIELD__I2C0_INT_EN0_DATA_ER
// <name> DATA_ER </name>
// <rw>
// <i> [Bit 11] RW (@ 0x4001D00C) \nMaster Mode Data NACK Received Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.11..11> DATA_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ------------------------- Field Item: I2C0_INT_EN0_DO_NOT_RESP_ER ----------------------------
// SVD Line: 4351
// <item> SFDITEM_FIELD__I2C0_INT_EN0_DO_NOT_RESP_ER
// <name> DO_NOT_RESP_ER </name>
// <rw>
// <i> [Bit 12] RW (@ 0x4001D00C) \nSlave Mode Do Not Respond Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.12..12> DO_NOT_RESP_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_EN0_START_ER -------------------------------
// SVD Line: 4368
// <item> SFDITEM_FIELD__I2C0_INT_EN0_START_ER
// <name> START_ER </name>
// <rw>
// <i> [Bit 13] RW (@ 0x4001D00C) \nOut of Sequence START condition detected interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.13..13> START_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_INT_EN0_STOP_ER --------------------------------
// SVD Line: 4385
// <item> SFDITEM_FIELD__I2C0_INT_EN0_STOP_ER
// <name> STOP_ER </name>
// <rw>
// <i> [Bit 14] RW (@ 0x4001D00C) \nOut of Sequence STOP condition detected interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.14..14> STOP_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C0_INT_EN0_TX_LOCK_OUT ------------------------------
// SVD Line: 4402
// <item> SFDITEM_FIELD__I2C0_INT_EN0_TX_LOCK_OUT
// <name> TX_LOCK_OUT </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4001D00C) \nTX FIFO Locked Out Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when TXLOIE = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN0 ) </loc>
// <o.15..15> TX_LOCK_OUT
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when TXLOIE = 1.
// </combo>
// </item>
//
// ------------------------------ Register RTree: I2C0_INT_EN0 ----------------------------------
// SVD Line: 4135
// <rtree> SFDITEM_REG__I2C0_INT_EN0
// <name> INT_EN0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D00C) Interrupt Enable Register. </i>
// <loc> ( (unsigned int)((I2C0_INT_EN0 >> 0) & 0xFFFFFFFF), ((I2C0_INT_EN0 = (I2C0_INT_EN0 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_DONE </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_RX_MODE </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_GEN_CTRL_ADDR </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_ADDR_MATCH </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_RX_THRESH </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_TX_THRESH </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_STOP </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_ADDR_ACK </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_ARB_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_TO_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_ADDR_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_DATA_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_DO_NOT_RESP_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_START_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_STOP_ER </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN0_TX_LOCK_OUT </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_INT_FL1 ------------------------------
// SVD Line: 4421
unsigned int I2C0_INT_FL1 __AT (0x4001D010);
// -------------------------- Field Item: I2C0_INT_FL1_RX_OVERFLOW ------------------------------
// SVD Line: 4426
// <item> SFDITEM_FIELD__I2C0_INT_FL1_RX_OVERFLOW
// <name> RX_OVERFLOW </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D010) \nReceiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL1 ) </loc>
// <o.0..0> RX_OVERFLOW
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C0_INT_FL1_TX_UNDERFLOW -----------------------------
// SVD Line: 4443
// <item> SFDITEM_FIELD__I2C0_INT_FL1_TX_UNDERFLOW
// <name> TX_UNDERFLOW </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D010) \nTransmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_FL1 ) </loc>
// <o.1..1> TX_UNDERFLOW
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------------ Register RTree: I2C0_INT_FL1 ----------------------------------
// SVD Line: 4421
// <rtree> SFDITEM_REG__I2C0_INT_FL1
// <name> INT_FL1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D010) Interrupt Status Register 1. </i>
// <loc> ( (unsigned int)((I2C0_INT_FL1 >> 0) & 0xFFFFFFFF), ((I2C0_INT_FL1 = (I2C0_INT_FL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_INT_FL1_RX_OVERFLOW </item>
// <item> SFDITEM_FIELD__I2C0_INT_FL1_TX_UNDERFLOW </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_INT_EN1 ------------------------------
// SVD Line: 4462
unsigned int I2C0_INT_EN1 __AT (0x4001D014);
// -------------------------- Field Item: I2C0_INT_EN1_RX_OVERFLOW ------------------------------
// SVD Line: 4468
// <item> SFDITEM_FIELD__I2C0_INT_EN1_RX_OVERFLOW
// <name> RX_OVERFLOW </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D014) \nReceiver Overflow Interrupt Enable.\n0 : dis = No Interrupt is Pending.\n1 : en = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN1 ) </loc>
// <o.0..0> RX_OVERFLOW
// <0=> 0: dis = No Interrupt is Pending.
// <1=> 1: en = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C0_INT_EN1_TX_UNDERFLOW -----------------------------
// SVD Line: 4485
// <item> SFDITEM_FIELD__I2C0_INT_EN1_TX_UNDERFLOW
// <name> TX_UNDERFLOW </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D014) \nTransmit Underflow Interrupt Enable.\n0 : dis = No Interrupt is Pending.\n1 : en = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_INT_EN1 ) </loc>
// <o.1..1> TX_UNDERFLOW
// <0=> 0: dis = No Interrupt is Pending.
// <1=> 1: en = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------------ Register RTree: I2C0_INT_EN1 ----------------------------------
// SVD Line: 4462
// <rtree> SFDITEM_REG__I2C0_INT_EN1
// <name> INT_EN1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D014) Interrupt Staus Register 1. </i>
// <loc> ( (unsigned int)((I2C0_INT_EN1 >> 0) & 0xFFFFFFFF), ((I2C0_INT_EN1 = (I2C0_INT_EN1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_INT_EN1_RX_OVERFLOW </item>
// <item> SFDITEM_FIELD__I2C0_INT_EN1_TX_UNDERFLOW </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C0_FIFO_LEN ------------------------------
// SVD Line: 4504
unsigned int I2C0_FIFO_LEN __AT (0x4001D018);
// ---------------------------- Field Item: I2C0_FIFO_LEN_RX_LEN --------------------------------
// SVD Line: 4509
// <item> SFDITEM_FIELD__I2C0_FIFO_LEN_RX_LEN
// <name> RX_LEN </name>
// <r>
// <i> [Bits 7..0] RO (@ 0x4001D018) Receive FIFO Length. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_FIFO_LEN >> 0) & 0xFF) ) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: I2C0_FIFO_LEN_TX_LEN --------------------------------
// SVD Line: 4515
// <item> SFDITEM_FIELD__I2C0_FIFO_LEN_TX_LEN
// <name> TX_LEN </name>
// <r>
// <i> [Bits 15..8] RO (@ 0x4001D018) Transmit FIFO Length. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_FIFO_LEN >> 8) & 0xFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C0_FIFO_LEN ---------------------------------
// SVD Line: 4504
// <rtree> SFDITEM_REG__I2C0_FIFO_LEN
// <name> FIFO_LEN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D018) FIFO Configuration Register. </i>
// <loc> ( (unsigned int)((I2C0_FIFO_LEN >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__I2C0_FIFO_LEN_RX_LEN </item>
// <item> SFDITEM_FIELD__I2C0_FIFO_LEN_TX_LEN </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C0_RX_CTRL0 ------------------------------
// SVD Line: 4523
unsigned int I2C0_RX_CTRL0 __AT (0x4001D01C);
// ------------------------------ Field Item: I2C0_RX_CTRL0_DNR ---------------------------------
// SVD Line: 4528
// <item> SFDITEM_FIELD__I2C0_RX_CTRL0_DNR
// <name> DNR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D01C) \nDo Not Respond.\n0 : respond = Always respond to address match.\n1 : not_respond_rx_fifo_empty = Do not respond to address match when RX_FIFO is not empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_RX_CTRL0 ) </loc>
// <o.0..0> DNR
// <0=> 0: respond = Always respond to address match.
// <1=> 1: not_respond_rx_fifo_empty = Do not respond to address match when RX_FIFO is not empty.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_RX_CTRL0_RX_FLUSH -------------------------------
// SVD Line: 4545
// <item> SFDITEM_FIELD__I2C0_RX_CTRL0_RX_FLUSH
// <name> RX_FLUSH </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001D01C) \nReceive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.\n0 : not_flushed = FIFO not flushed.\n1 : flush = Flush RX_FIFO. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_RX_CTRL0 ) </loc>
// <o.7..7> RX_FLUSH
// <0=> 0: not_flushed = FIFO not flushed.
// <1=> 1: flush = Flush RX_FIFO.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_RX_CTRL0_RX_THRESH ------------------------------
// SVD Line: 4562
// <item> SFDITEM_FIELD__I2C0_RX_CTRL0_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bits 11..8] RW (@ 0x4001D01C) Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_RX_CTRL0 >> 8) & 0xF), ((I2C0_RX_CTRL0 = (I2C0_RX_CTRL0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C0_RX_CTRL0 ---------------------------------
// SVD Line: 4523
// <rtree> SFDITEM_REG__I2C0_RX_CTRL0
// <name> RX_CTRL0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D01C) Receive Control Register 0. </i>
// <loc> ( (unsigned int)((I2C0_RX_CTRL0 >> 0) & 0xFFFFFFFF), ((I2C0_RX_CTRL0 = (I2C0_RX_CTRL0 & ~(0xF81UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF81) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_RX_CTRL0_DNR </item>
// <item> SFDITEM_FIELD__I2C0_RX_CTRL0_RX_FLUSH </item>
// <item> SFDITEM_FIELD__I2C0_RX_CTRL0_RX_THRESH </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C0_RX_CTRL1 ------------------------------
// SVD Line: 4569
unsigned int I2C0_RX_CTRL1 __AT (0x4001D020);
// ---------------------------- Field Item: I2C0_RX_CTRL1_RX_CNT --------------------------------
// SVD Line: 4574
// <item> SFDITEM_FIELD__I2C0_RX_CTRL1_RX_CNT
// <name> RX_CNT </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x4001D020) Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_RX_CTRL1 >> 0) & 0xFF), ((I2C0_RX_CTRL1 = (I2C0_RX_CTRL1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: I2C0_RX_CTRL1_RX_FIFO -------------------------------
// SVD Line: 4579
// <item> SFDITEM_FIELD__I2C0_RX_CTRL1_RX_FIFO
// <name> RX_FIFO </name>
// <r>
// <i> [Bits 11..8] RO (@ 0x4001D020) Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_RX_CTRL1 >> 8) & 0xF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C0_RX_CTRL1 ---------------------------------
// SVD Line: 4569
// <rtree> SFDITEM_REG__I2C0_RX_CTRL1
// <name> RX_CTRL1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D020) Receive Control Register 1. </i>
// <loc> ( (unsigned int)((I2C0_RX_CTRL1 >> 0) & 0xFFFFFFFF), ((I2C0_RX_CTRL1 = (I2C0_RX_CTRL1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_RX_CTRL1_RX_CNT </item>
// <item> SFDITEM_FIELD__I2C0_RX_CTRL1_RX_FIFO </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C0_TX_CTRL0 ------------------------------
// SVD Line: 4587
unsigned int I2C0_TX_CTRL0 __AT (0x4001D024);
// -------------------------- Field Item: I2C0_TX_CTRL0_TX_PRELOAD ------------------------------
// SVD Line: 4592
// <item> SFDITEM_FIELD__I2C0_TX_CTRL0_TX_PRELOAD
// <name> TX_PRELOAD </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D024) Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. </i>
// <check>
// <loc> ( (unsigned int) I2C0_TX_CTRL0 ) </loc>
// <o.0..0> TX_PRELOAD
// </check>
// </item>
//
// ------------------------- Field Item: I2C0_TX_CTRL0_TX_READY_MODE ----------------------------
// SVD Line: 4597
// <item> SFDITEM_FIELD__I2C0_TX_CTRL0_TX_READY_MODE
// <name> TX_READY_MODE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D024) \nTransmit FIFO Ready Manual Mode.\n0 : en = HW control of I2CTXRDY enabled.\n1 : dis = HW control of I2CTXRDY disabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_TX_CTRL0 ) </loc>
// <o.1..1> TX_READY_MODE
// <0=> 0: en = HW control of I2CTXRDY enabled.
// <1=> 1: dis = HW control of I2CTXRDY disabled.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_TX_CTRL0_TX_FLUSH -------------------------------
// SVD Line: 4614
// <item> SFDITEM_FIELD__I2C0_TX_CTRL0_TX_FLUSH
// <name> TX_FLUSH </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001D024) \nTransmit FIFO Flush. This bit is automatically cleared to 0 after the operation.\n0 : not_flushed = FIFO not flushed.\n1 : flush = Flush TX_FIFO. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_TX_CTRL0 ) </loc>
// <o.7..7> TX_FLUSH
// <0=> 0: not_flushed = FIFO not flushed.
// <1=> 1: flush = Flush TX_FIFO.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C0_TX_CTRL0_TX_THRESH ------------------------------
// SVD Line: 4631
// <item> SFDITEM_FIELD__I2C0_TX_CTRL0_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bits 11..8] RW (@ 0x4001D024) Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_TX_CTRL0 >> 8) & 0xF), ((I2C0_TX_CTRL0 = (I2C0_TX_CTRL0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C0_TX_CTRL0 ---------------------------------
// SVD Line: 4587
// <rtree> SFDITEM_REG__I2C0_TX_CTRL0
// <name> TX_CTRL0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D024) Transmit Control Register 0. </i>
// <loc> ( (unsigned int)((I2C0_TX_CTRL0 >> 0) & 0xFFFFFFFF), ((I2C0_TX_CTRL0 = (I2C0_TX_CTRL0 & ~(0xF83UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF83) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_TX_CTRL0_TX_PRELOAD </item>
// <item> SFDITEM_FIELD__I2C0_TX_CTRL0_TX_READY_MODE </item>
// <item> SFDITEM_FIELD__I2C0_TX_CTRL0_TX_FLUSH </item>
// <item> SFDITEM_FIELD__I2C0_TX_CTRL0_TX_THRESH </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C0_TX_CTRL1 ------------------------------
// SVD Line: 4638
unsigned int I2C0_TX_CTRL1 __AT (0x4001D028);
// --------------------------- Field Item: I2C0_TX_CTRL1_TX_READY -------------------------------
// SVD Line: 4643
// <item> SFDITEM_FIELD__I2C0_TX_CTRL1_TX_READY
// <name> TX_READY </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D028) Transmit FIFO Preload Ready. </i>
// <check>
// <loc> ( (unsigned int) I2C0_TX_CTRL1 ) </loc>
// <o.0..0> TX_READY
// </check>
// </item>
//
// ---------------------------- Field Item: I2C0_TX_CTRL1_TX_LAST -------------------------------
// SVD Line: 4648
// <item> SFDITEM_FIELD__I2C0_TX_CTRL1_TX_LAST
// <name> TX_LAST </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D028) \nTransmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).\n0 : hold_scl_low = Hold SCL low on TX_FIFO empty.\n1 : end_transaction = End transaction on TX_FIFO empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_TX_CTRL1 ) </loc>
// <o.1..1> TX_LAST
// <0=> 0: hold_scl_low = Hold SCL low on TX_FIFO empty.
// <1=> 1: end_transaction = End transaction on TX_FIFO empty.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C0_TX_CTRL1_TX_FIFO -------------------------------
// SVD Line: 4665
// <item> SFDITEM_FIELD__I2C0_TX_CTRL1_TX_FIFO
// <name> TX_FIFO </name>
// <r>
// <i> [Bits 11..8] RO (@ 0x4001D028) Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_TX_CTRL1 >> 8) & 0xF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C0_TX_CTRL1 ---------------------------------
// SVD Line: 4638
// <rtree> SFDITEM_REG__I2C0_TX_CTRL1
// <name> TX_CTRL1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D028) Transmit Control Register 1. </i>
// <loc> ( (unsigned int)((I2C0_TX_CTRL1 >> 0) & 0xFFFFFFFF), ((I2C0_TX_CTRL1 = (I2C0_TX_CTRL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_TX_CTRL1_TX_READY </item>
// <item> SFDITEM_FIELD__I2C0_TX_CTRL1_TX_LAST </item>
// <item> SFDITEM_FIELD__I2C0_TX_CTRL1_TX_FIFO </item>
// </rtree>
//
// ---------------------------- Register Item Address: I2C0_FIFO --------------------------------
// SVD Line: 4673
unsigned int I2C0_FIFO __AT (0x4001D02C);
// ------------------------------- Field Item: I2C0_FIFO_DATA -----------------------------------
// SVD Line: 4678
// <item> SFDITEM_FIELD__I2C0_FIFO_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x4001D02C) Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_FIFO >> 0) & 0xFF), ((I2C0_FIFO = (I2C0_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: I2C0_FIFO -----------------------------------
// SVD Line: 4673
// <rtree> SFDITEM_REG__I2C0_FIFO
// <name> FIFO </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D02C) Data Register. </i>
// <loc> ( (unsigned int)((I2C0_FIFO >> 0) & 0xFFFFFFFF), ((I2C0_FIFO = (I2C0_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_FIFO_DATA </item>
// </rtree>
//
// ------------------------- Register Item Address: I2C0_MASTER_CTRL ----------------------------
// SVD Line: 4686
unsigned int I2C0_MASTER_CTRL __AT (0x4001D030);
// --------------------------- Field Item: I2C0_MASTER_CTRL_START -------------------------------
// SVD Line: 4691
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_START
// <name> START </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D030) Setting this bit to 1 will start a master transfer. </i>
// <check>
// <loc> ( (unsigned int) I2C0_MASTER_CTRL ) </loc>
// <o.0..0> START
// </check>
// </item>
//
// -------------------------- Field Item: I2C0_MASTER_CTRL_RESTART ------------------------------
// SVD Line: 4696
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_RESTART
// <name> RESTART </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D030) Setting this bit to 1 will generate a repeated START. </i>
// <check>
// <loc> ( (unsigned int) I2C0_MASTER_CTRL ) </loc>
// <o.1..1> RESTART
// </check>
// </item>
//
// ---------------------------- Field Item: I2C0_MASTER_CTRL_STOP -------------------------------
// SVD Line: 4701
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_STOP
// <name> STOP </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001D030) Setting this bit to 1 will generate a STOP condition. </i>
// <check>
// <loc> ( (unsigned int) I2C0_MASTER_CTRL ) </loc>
// <o.2..2> STOP
// </check>
// </item>
//
// ------------------------- Field Item: I2C0_MASTER_CTRL_SL_EX_ADDR ----------------------------
// SVD Line: 4706
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_SL_EX_ADDR
// <name> SL_EX_ADDR </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001D030) \nSlave Extend Address Select.\n0 : 7_bits_address = 7-bit address.\n1 : 10_bits_address = 10-bit address. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_MASTER_CTRL ) </loc>
// <o.7..7> SL_EX_ADDR
// <0=> 0: 7_bits_address = 7-bit address.
// <1=> 1: 10_bits_address = 10-bit address.
// </combo>
// </item>
//
// ------------------------ Field Item: I2C0_MASTER_CTRL_MASTER_CODE ----------------------------
// SVD Line: 4723
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_MASTER_CODE
// <name> MASTER_CODE </name>
// <rw>
// <i> [Bits 10..8] RW (@ 0x4001D030) Master Code. These bits set the Master Code used in Hs-mode operation. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_MASTER_CTRL >> 8) & 0x7), ((I2C0_MASTER_CTRL = (I2C0_MASTER_CTRL & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------ Field Item: I2C0_MASTER_CTRL_SCL_SPEED_UP ---------------------------
// SVD Line: 4728
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_SCL_SPEED_UP
// <name> SCL_SPEED_UP </name>
// <rw>
// <i> [Bit 11] RW (@ 0x4001D030) \nSerial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves.\n0 : en = Master monitors SCL state.\n1 : dis = SCL state monitoring disabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_MASTER_CTRL ) </loc>
// <o.11..11> SCL_SPEED_UP
// <0=> 0: en = Master monitors SCL state.
// <1=> 1: dis = SCL state monitoring disabled.
// </combo>
// </item>
//
// ---------------------------- Register RTree: I2C0_MASTER_CTRL --------------------------------
// SVD Line: 4686
// <rtree> SFDITEM_REG__I2C0_MASTER_CTRL
// <name> MASTER_CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D030) Master Control Register. </i>
// <loc> ( (unsigned int)((I2C0_MASTER_CTRL >> 0) & 0xFFFFFFFF), ((I2C0_MASTER_CTRL = (I2C0_MASTER_CTRL & ~(0xF87UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF87) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_START </item>
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_RESTART </item>
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_STOP </item>
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_SL_EX_ADDR </item>
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_MASTER_CODE </item>
// <item> SFDITEM_FIELD__I2C0_MASTER_CTRL_SCL_SPEED_UP </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_CLK_LO -------------------------------
// SVD Line: 4747
unsigned int I2C0_CLK_LO __AT (0x4001D034);
// ----------------------------- Field Item: I2C0_CLK_LO_CLK_LO ---------------------------------
// SVD Line: 4752
// <item> SFDITEM_FIELD__I2C0_CLK_LO_CLK_LO
// <name> CLK_LO </name>
// <rw>
// <i> [Bits 8..0] RW (@ 0x4001D034) Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. </i>
// <edit>
// <loc> ( (unsigned short)((I2C0_CLK_LO >> 0) & 0x1FF), ((I2C0_CLK_LO = (I2C0_CLK_LO & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: I2C0_CLK_LO ----------------------------------
// SVD Line: 4747
// <rtree> SFDITEM_REG__I2C0_CLK_LO
// <name> CLK_LO </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D034) Clock Low Register. </i>
// <loc> ( (unsigned int)((I2C0_CLK_LO >> 0) & 0xFFFFFFFF), ((I2C0_CLK_LO = (I2C0_CLK_LO & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_CLK_LO_CLK_LO </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_CLK_HI -------------------------------
// SVD Line: 4759
unsigned int I2C0_CLK_HI __AT (0x4001D038);
// ------------------------------- Field Item: I2C0_CLK_HI_CKH ----------------------------------
// SVD Line: 4764
// <item> SFDITEM_FIELD__I2C0_CLK_HI_CKH
// <name> CKH </name>
// <rw>
// <i> [Bits 8..0] RW (@ 0x4001D038) Clock High. In master mode, these bits define the SCL high period. </i>
// <edit>
// <loc> ( (unsigned short)((I2C0_CLK_HI >> 0) & 0x1FF), ((I2C0_CLK_HI = (I2C0_CLK_HI & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: I2C0_CLK_HI ----------------------------------
// SVD Line: 4759
// <rtree> SFDITEM_REG__I2C0_CLK_HI
// <name> CLK_HI </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D038) Clock high Register. </i>
// <loc> ( (unsigned int)((I2C0_CLK_HI >> 0) & 0xFFFFFFFF), ((I2C0_CLK_HI = (I2C0_CLK_HI & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_CLK_HI_CKH </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_HS_CLK -------------------------------
// SVD Line: 4771
unsigned int I2C0_HS_CLK __AT (0x4001D03C);
// ---------------------------- Field Item: I2C0_HS_CLK_HS_CLK_LO -------------------------------
// SVD Line: 4776
// <item> SFDITEM_FIELD__I2C0_HS_CLK_HS_CLK_LO
// <name> HS_CLK_LO </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x4001D03C) Slave Address. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_HS_CLK >> 0) & 0xFF), ((I2C0_HS_CLK = (I2C0_HS_CLK & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: I2C0_HS_CLK_HS_CLK_HI -------------------------------
// SVD Line: 4781
// <item> SFDITEM_FIELD__I2C0_HS_CLK_HS_CLK_HI
// <name> HS_CLK_HI </name>
// <rw>
// <i> [Bits 15..8] RW (@ 0x4001D03C) Slave Address. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_HS_CLK >> 8) & 0xFF), ((I2C0_HS_CLK = (I2C0_HS_CLK & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: I2C0_HS_CLK ----------------------------------
// SVD Line: 4771
// <rtree> SFDITEM_REG__I2C0_HS_CLK
// <name> HS_CLK </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D03C) HS-Mode Clock Control Register </i>
// <loc> ( (unsigned int)((I2C0_HS_CLK >> 0) & 0xFFFFFFFF), ((I2C0_HS_CLK = (I2C0_HS_CLK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_HS_CLK_HS_CLK_LO </item>
// <item> SFDITEM_FIELD__I2C0_HS_CLK_HS_CLK_HI </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C0_TIMEOUT ------------------------------
// SVD Line: 4788
unsigned int I2C0_TIMEOUT __AT (0x4001D040);
// ------------------------------- Field Item: I2C0_TIMEOUT_TO ----------------------------------
// SVD Line: 4793
// <item> SFDITEM_FIELD__I2C0_TIMEOUT_TO
// <name> TO </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x4001D040) Timeout </i>
// <edit>
// <loc> ( (unsigned short)((I2C0_TIMEOUT >> 0) & 0xFFFF), ((I2C0_TIMEOUT = (I2C0_TIMEOUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C0_TIMEOUT ----------------------------------
// SVD Line: 4788
// <rtree> SFDITEM_REG__I2C0_TIMEOUT
// <name> TIMEOUT </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D040) Timeout Register </i>
// <loc> ( (unsigned int)((I2C0_TIMEOUT >> 0) & 0xFFFFFFFF), ((I2C0_TIMEOUT = (I2C0_TIMEOUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_TIMEOUT_TO </item>
// </rtree>
//
// ------------------------- Register Item Address: I2C0_SLAVE_ADDR -----------------------------
// SVD Line: 4800
unsigned int I2C0_SLAVE_ADDR __AT (0x4001D044);
// ------------------------- Field Item: I2C0_SLAVE_ADDR_SLAVE_ADDR -----------------------------
// SVD Line: 4805
// <item> SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR
// <name> SLAVE_ADDR </name>
// <rw>
// <i> [Bits 9..0] RW (@ 0x4001D044) Slave Address. </i>
// <edit>
// <loc> ( (unsigned short)((I2C0_SLAVE_ADDR >> 0) & 0x3FF), ((I2C0_SLAVE_ADDR = (I2C0_SLAVE_ADDR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------- Field Item: I2C0_SLAVE_ADDR_SLAVE_ADDR_DIS ---------------------------
// SVD Line: 4810
// <item> SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR_DIS
// <name> SLAVE_ADDR_DIS </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001D044) Slave Address DIS. </i>
// <check>
// <loc> ( (unsigned int) I2C0_SLAVE_ADDR ) </loc>
// <o.10..10> SLAVE_ADDR_DIS
// </check>
// </item>
//
// ----------------------- Field Item: I2C0_SLAVE_ADDR_SLAVE_ADDR_IDX ---------------------------
// SVD Line: 4815
// <item> SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR_IDX
// <name> SLAVE_ADDR_IDX </name>
// <rw>
// <i> [Bits 14..11] RW (@ 0x4001D044) Slave Address Index. </i>
// <edit>
// <loc> ( (unsigned char)((I2C0_SLAVE_ADDR >> 11) & 0xF), ((I2C0_SLAVE_ADDR = (I2C0_SLAVE_ADDR & ~(0xFUL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 11 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------------- Field Item: I2C0_SLAVE_ADDR_EX_ADDR ------------------------------
// SVD Line: 4820
// <item> SFDITEM_FIELD__I2C0_SLAVE_ADDR_EX_ADDR
// <name> EX_ADDR </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4001D044) \nExtended Address Select.\n0 : 7_bits_address = 7-bit address.\n1 : 10_bits_address = 10-bit address. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_SLAVE_ADDR ) </loc>
// <o.15..15> EX_ADDR
// <0=> 0: 7_bits_address = 7-bit address.
// <1=> 1: 10_bits_address = 10-bit address.
// </combo>
// </item>
//
// ----------------------------- Register RTree: I2C0_SLAVE_ADDR --------------------------------
// SVD Line: 4800
// <rtree> SFDITEM_REG__I2C0_SLAVE_ADDR
// <name> SLAVE_ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D044) Slave Address Register. </i>
// <loc> ( (unsigned int)((I2C0_SLAVE_ADDR >> 0) & 0xFFFFFFFF), ((I2C0_SLAVE_ADDR = (I2C0_SLAVE_ADDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR </item>
// <item> SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR_DIS </item>
// <item> SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR_IDX </item>
// <item> SFDITEM_FIELD__I2C0_SLAVE_ADDR_EX_ADDR </item>
// </rtree>
//
// ----------------------------- Register Item Address: I2C0_DMA --------------------------------
// SVD Line: 4839
unsigned int I2C0_DMA __AT (0x4001D048);
// ------------------------------- Field Item: I2C0_DMA_TX_EN -----------------------------------
// SVD Line: 4844
// <item> SFDITEM_FIELD__I2C0_DMA_TX_EN
// <name> TX_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001D048) \nTX channel enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_DMA ) </loc>
// <o.0..0> TX_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: I2C0_DMA_RX_EN -----------------------------------
// SVD Line: 4861
// <item> SFDITEM_FIELD__I2C0_DMA_RX_EN
// <name> RX_EN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001D048) \nRX channel enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) I2C0_DMA ) </loc>
// <o.1..1> RX_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Register RTree: I2C0_DMA ------------------------------------
// SVD Line: 4839
// <rtree> SFDITEM_REG__I2C0_DMA
// <name> DMA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001D048) DMA Register. </i>
// <loc> ( (unsigned int)((I2C0_DMA >> 0) & 0xFFFFFFFF), ((I2C0_DMA = (I2C0_DMA & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C0_DMA_TX_EN </item>
// <item> SFDITEM_FIELD__I2C0_DMA_RX_EN </item>
// </rtree>
//
// ---------------------------------- Peripheral View: I2C0 -------------------------------------
// SVD Line: 3420
// <view> I2C0
// <name> I2C0 </name>
// <item> SFDITEM_REG__I2C0_CTRL </item>
// <item> SFDITEM_REG__I2C0_STATUS </item>
// <item> SFDITEM_REG__I2C0_INT_FL0 </item>
// <item> SFDITEM_REG__I2C0_INT_EN0 </item>
// <item> SFDITEM_REG__I2C0_INT_FL1 </item>
// <item> SFDITEM_REG__I2C0_INT_EN1 </item>
// <item> SFDITEM_REG__I2C0_FIFO_LEN </item>
// <item> SFDITEM_REG__I2C0_RX_CTRL0 </item>
// <item> SFDITEM_REG__I2C0_RX_CTRL1 </item>
// <item> SFDITEM_REG__I2C0_TX_CTRL0 </item>
// <item> SFDITEM_REG__I2C0_TX_CTRL1 </item>
// <item> SFDITEM_REG__I2C0_FIFO </item>
// <item> SFDITEM_REG__I2C0_MASTER_CTRL </item>
// <item> SFDITEM_REG__I2C0_CLK_LO </item>
// <item> SFDITEM_REG__I2C0_CLK_HI </item>
// <item> SFDITEM_REG__I2C0_HS_CLK </item>
// <item> SFDITEM_REG__I2C0_TIMEOUT </item>
// <item> SFDITEM_REG__I2C0_SLAVE_ADDR </item>
// <item> SFDITEM_REG__I2C0_DMA </item>
// </view>
//
// ---------------------------- Register Item Address: I2C1_CTRL --------------------------------
// SVD Line: 3437
unsigned int I2C1_CTRL __AT (0x4001E000);
// ------------------------------ Field Item: I2C1_CTRL_I2C_EN ----------------------------------
// SVD Line: 3442
// <item> SFDITEM_FIELD__I2C1_CTRL_I2C_EN
// <name> I2C_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E000) \nI2C Enable.\n0 : dis = Disable I2C.\n1 : en = enable I2C. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.0..0> I2C_EN
// <0=> 0: dis = Disable I2C.
// <1=> 1: en = enable I2C.
// </combo>
// </item>
//
// -------------------------------- Field Item: I2C1_CTRL_MST -----------------------------------
// SVD Line: 3460
// <item> SFDITEM_FIELD__I2C1_CTRL_MST
// <name> MST </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E000) \nMaster Mode Enable.\n0 : slave_mode = Slave Mode.\n1 : master_mode = Master Mode. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.1..1> MST
// <0=> 0: slave_mode = Slave Mode.
// <1=> 1: master_mode = Master Mode.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_CTRL_GEN_CALL_ADDR ------------------------------
// SVD Line: 3478
// <item> SFDITEM_FIELD__I2C1_CTRL_GEN_CALL_ADDR
// <name> GEN_CALL_ADDR </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001E000) \nGeneral Call Address Enable.\n0 : dis = Ignore Gneral Call Address.\n1 : en = Acknowledge general call address. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.2..2> GEN_CALL_ADDR
// <0=> 0: dis = Ignore Gneral Call Address.
// <1=> 1: en = Acknowledge general call address.
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C1_CTRL_RX_MODE ---------------------------------
// SVD Line: 3496
// <item> SFDITEM_FIELD__I2C1_CTRL_RX_MODE
// <name> RX_MODE </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001E000) \nInteractive Receive Mode.\n0 : dis = Disable Interactive Receive Mode.\n1 : en = Enable Interactive Receive Mode. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.3..3> RX_MODE
// <0=> 0: dis = Disable Interactive Receive Mode.
// <1=> 1: en = Enable Interactive Receive Mode.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_CTRL_RX_MODE_ACK -------------------------------
// SVD Line: 3514
// <item> SFDITEM_FIELD__I2C1_CTRL_RX_MODE_ACK
// <name> RX_MODE_ACK </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001E000) \nData Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.\n0 : ack = return ACK (pulling SDA LOW).\n1 : nack = return NACK (leaving SDA HIGH). </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.4..4> RX_MODE_ACK
// <0=> 0: ack = return ACK (pulling SDA LOW).
// <1=> 1: nack = return NACK (leaving SDA HIGH).
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C1_CTRL_SCL_OUT ---------------------------------
// SVD Line: 3532
// <item> SFDITEM_FIELD__I2C1_CTRL_SCL_OUT
// <name> SCL_OUT </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4001E000) \nSCL Output. This bits control SCL output when SWOE =1.\n0 : drive_scl_low = Drive SCL low.\n1 : release_scl = Release SCL. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.6..6> SCL_OUT
// <0=> 0: drive_scl_low = Drive SCL low.
// <1=> 1: release_scl = Release SCL.
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C1_CTRL_SDA_OUT ---------------------------------
// SVD Line: 3550
// <item> SFDITEM_FIELD__I2C1_CTRL_SDA_OUT
// <name> SDA_OUT </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001E000) \nSDA Output. This bits control SDA output when SWOE = 1.\n0 : drive_sda_low = Drive SDA low.\n1 : release_sda = Release SDA. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.7..7> SDA_OUT
// <0=> 0: drive_sda_low = Drive SDA low.
// <1=> 1: release_sda = Release SDA.
// </combo>
// </item>
//
// -------------------------------- Field Item: I2C1_CTRL_SCL -----------------------------------
// SVD Line: 3568
// <item> SFDITEM_FIELD__I2C1_CTRL_SCL
// <name> SCL </name>
// <r>
// <i> [Bit 8] RO (@ 0x4001E000) SCL status. This bit reflects the logic gate of SCL signal. </i>
// <check>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.8..8> SCL
// </check>
// </item>
//
// -------------------------------- Field Item: I2C1_CTRL_SDA -----------------------------------
// SVD Line: 3574
// <item> SFDITEM_FIELD__I2C1_CTRL_SDA
// <name> SDA </name>
// <r>
// <i> [Bit 9] RO (@ 0x4001E000) SDA status. THis bit reflects the logic gate of SDA signal. </i>
// <check>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.9..9> SDA
// </check>
// </item>
//
// ----------------------------- Field Item: I2C1_CTRL_SW_OUT_EN --------------------------------
// SVD Line: 3580
// <item> SFDITEM_FIELD__I2C1_CTRL_SW_OUT_EN
// <name> SW_OUT_EN </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001E000) \nSoftware Output Enable.\n0 : outputs_disable = I2C Outputs SCLO and SDAO disabled.\n1 : outputs_enable = I2C Outputs SCLO and SDAO enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.10..10> SW_OUT_EN
// <0=> 0: outputs_disable = I2C Outputs SCLO and SDAO disabled.
// <1=> 1: outputs_enable = I2C Outputs SCLO and SDAO enabled.
// </combo>
// </item>
//
// ------------------------------- Field Item: I2C1_CTRL_READ -----------------------------------
// SVD Line: 3598
// <item> SFDITEM_FIELD__I2C1_CTRL_READ
// <name> READ </name>
// <r>
// <i> [Bit 11] RO (@ 0x4001E000) \nRead. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.\n0 : write = Write.\n1 : read = Read. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.11..11> READ
// <0=> 0: write = Write.
// <1=> 1: read = Read.
// </combo>
// </item>
//
// ------------------------ Field Item: I2C1_CTRL_SCL_CLK_STRECH_DIS ----------------------------
// SVD Line: 3616
// <item> SFDITEM_FIELD__I2C1_CTRL_SCL_CLK_STRECH_DIS
// <name> SCL_CLK_STRECH_DIS </name>
// <rw>
// <i> [Bit 12] RW (@ 0x4001E000) \nThis bit will disable slave clock stretching when set.\n0 : en = Slave clock stretching enabled.\n1 : dis = Slave clock stretching disabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.12..12> SCL_CLK_STRECH_DIS
// <0=> 0: en = Slave clock stretching enabled.
// <1=> 1: dis = Slave clock stretching disabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_CTRL_SCL_PP_MODE -------------------------------
// SVD Line: 3634
// <item> SFDITEM_FIELD__I2C1_CTRL_SCL_PP_MODE
// <name> SCL_PP_MODE </name>
// <rw>
// <i> [Bit 13] RW (@ 0x4001E000) \nSCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.\n0 : dis = Standard open-drain operation: drive low for 0, Hi-Z for 1\n1 : en = Non-standard push-pull operation: drive low for 0, drive high for 1 </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.13..13> SCL_PP_MODE
// <0=> 0: dis = Standard open-drain operation: drive low for 0, Hi-Z for 1
// <1=> 1: en = Non-standard push-pull operation: drive low for 0, drive high for 1
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C1_CTRL_HS_MODE ---------------------------------
// SVD Line: 3652
// <item> SFDITEM_FIELD__I2C1_CTRL_HS_MODE
// <name> HS_MODE </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4001E000) \nHs-mode Enable.\n0 : dis = Hs-mode disabled.\n1 : en = Hs-mode enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_CTRL ) </loc>
// <o.15..15> HS_MODE
// <0=> 0: dis = Hs-mode disabled.
// <1=> 1: en = Hs-mode enabled.
// </combo>
// </item>
//
// -------------------------------- Register RTree: I2C1_CTRL -----------------------------------
// SVD Line: 3437
// <rtree> SFDITEM_REG__I2C1_CTRL
// <name> CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E000) Control Register0. </i>
// <loc> ( (unsigned int)((I2C1_CTRL >> 0) & 0xFFFFFFFF), ((I2C1_CTRL = (I2C1_CTRL & ~(0xB4DFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB4DF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_CTRL_I2C_EN </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_MST </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_GEN_CALL_ADDR </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_RX_MODE </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_RX_MODE_ACK </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_SCL_OUT </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_SDA_OUT </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_SCL </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_SDA </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_SW_OUT_EN </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_READ </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_SCL_CLK_STRECH_DIS </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_SCL_PP_MODE </item>
// <item> SFDITEM_FIELD__I2C1_CTRL_HS_MODE </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_STATUS -------------------------------
// SVD Line: 3672
unsigned int I2C1_STATUS __AT (0x4001E004);
// ------------------------------- Field Item: I2C1_STATUS_BUS ----------------------------------
// SVD Line: 3677
// <item> SFDITEM_FIELD__I2C1_STATUS_BUS
// <name> BUS </name>
// <r>
// <i> [Bit 0] RO (@ 0x4001E004) \nBus Status.\n0 : idle = I2C Bus Idle.\n1 : busy = I2C Bus Busy. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_STATUS ) </loc>
// <o.0..0> BUS
// <0=> 0: idle = I2C Bus Idle.
// <1=> 1: busy = I2C Bus Busy.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_STATUS_RX_EMPTY --------------------------------
// SVD Line: 3695
// <item> SFDITEM_FIELD__I2C1_STATUS_RX_EMPTY
// <name> RX_EMPTY </name>
// <r>
// <i> [Bit 1] RO (@ 0x4001E004) \nRX empty.\n0 : not_empty = Not Empty.\n1 : empty = Empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_STATUS ) </loc>
// <o.1..1> RX_EMPTY
// <0=> 0: not_empty = Not Empty.
// <1=> 1: empty = Empty.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C1_STATUS_RX_FULL --------------------------------
// SVD Line: 3713
// <item> SFDITEM_FIELD__I2C1_STATUS_RX_FULL
// <name> RX_FULL </name>
// <r>
// <i> [Bit 2] RO (@ 0x4001E004) \nRX Full.\n0 : not_full = Not Full.\n1 : full = Full. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_STATUS ) </loc>
// <o.2..2> RX_FULL
// <0=> 0: not_full = Not Full.
// <1=> 1: full = Full.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_STATUS_TX_EMPTY --------------------------------
// SVD Line: 3731
// <item> SFDITEM_FIELD__I2C1_STATUS_TX_EMPTY
// <name> TX_EMPTY </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001E004) \nTX Empty.\n0 : not_empty = Not Empty.\n1 : empty = Empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_STATUS ) </loc>
// <o.3..3> TX_EMPTY
// <0=> 0: not_empty = Not Empty.
// <1=> 1: empty = Empty.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C1_STATUS_TX_FULL --------------------------------
// SVD Line: 3748
// <item> SFDITEM_FIELD__I2C1_STATUS_TX_FULL
// <name> TX_FULL </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001E004) \nTX Full.\n0 : not_empty = Not Empty.\n1 : empty = Empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_STATUS ) </loc>
// <o.4..4> TX_FULL
// <0=> 0: not_empty = Not Empty.
// <1=> 1: empty = Empty.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_STATUS_CLK_MODE --------------------------------
// SVD Line: 3765
// <item> SFDITEM_FIELD__I2C1_STATUS_CLK_MODE
// <name> CLK_MODE </name>
// <r>
// <i> [Bit 5] RO (@ 0x4001E004) \nClock Mode.\n0 : not_actively_driving_scl_clock = Device not actively driving SCL clock cycles.\n1 : actively_driving_scl_clock = Device operating as master and actively driving SCL clock cycles. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_STATUS ) </loc>
// <o.5..5> CLK_MODE
// <0=> 0: not_actively_driving_scl_clock = Device not actively driving SCL clock cycles.
// <1=> 1: actively_driving_scl_clock = Device operating as master and actively driving SCL clock cycles.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C1_STATUS_STATUS ---------------------------------
// SVD Line: 3783
// <item> SFDITEM_FIELD__I2C1_STATUS_STATUS
// <name> STATUS </name>
// <rw>
// <i> [Bits 11..8] RW (@ 0x4001E004) \nController Status.\n0 : idle = Controller Idle.\n1 : mtx_addr = master Transmit address.\n2 : mrx_addr_ack = Master Receive address ACK.\n3 : mtx_ex_addr = Master Transmit extended address.\n4 : mrx_ex_addr = Master Receive extended address ACK.\n5 : srx_addr = Slave Receive address.\n6 : stx_addr_ack = Slave Transmit address ACK.\n7 : srx_ex_addr = Slave Receive extended address.\n8 : stx_ex_addr_ack = Slave Transmit extended address ACK.\n9 : tx = Transmit data (master or slave).\n10 : rx_ack = Receive data ACK (master or slave).\n11 : rx = Receive data (master or slave).\n12 : tx_ack = Transmit data ACK (master or slave).\n13 : nack = NACK stage (master or slave).\n14 : Reserved - do not use\n15 : by_st = Bystander state (ongoing transaction but not participant- another master addressing another slave). </i>
// <combo>
// <loc> ( (unsigned int) I2C1_STATUS ) </loc>
// <o.11..8> STATUS
// <0=> 0: idle = Controller Idle.
// <1=> 1: mtx_addr = master Transmit address.
// <2=> 2: mrx_addr_ack = Master Receive address ACK.
// <3=> 3: mtx_ex_addr = Master Transmit extended address.
// <4=> 4: mrx_ex_addr = Master Receive extended address ACK.
// <5=> 5: srx_addr = Slave Receive address.
// <6=> 6: stx_addr_ack = Slave Transmit address ACK.
// <7=> 7: srx_ex_addr = Slave Receive extended address.
// <8=> 8: stx_ex_addr_ack = Slave Transmit extended address ACK.
// <9=> 9: tx = Transmit data (master or slave).
// <10=> 10: rx_ack = Receive data ACK (master or slave).
// <11=> 11: rx = Receive data (master or slave).
// <12=> 12: tx_ack = Transmit data ACK (master or slave).
// <13=> 13: nack = NACK stage (master or slave).
// <14=> 14:
// <15=> 15: by_st = Bystander state (ongoing transaction but not participant- another master addressing another slave).
// </combo>
// </item>
//
// ------------------------------- Register RTree: I2C1_STATUS ----------------------------------
// SVD Line: 3672
// <rtree> SFDITEM_REG__I2C1_STATUS
// <name> STATUS </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E004) Status Register. </i>
// <loc> ( (unsigned int)((I2C1_STATUS >> 0) & 0xFFFFFFFF), ((I2C1_STATUS = (I2C1_STATUS & ~(0xF18UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF18) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_STATUS_BUS </item>
// <item> SFDITEM_FIELD__I2C1_STATUS_RX_EMPTY </item>
// <item> SFDITEM_FIELD__I2C1_STATUS_RX_FULL </item>
// <item> SFDITEM_FIELD__I2C1_STATUS_TX_EMPTY </item>
// <item> SFDITEM_FIELD__I2C1_STATUS_TX_FULL </item>
// <item> SFDITEM_FIELD__I2C1_STATUS_CLK_MODE </item>
// <item> SFDITEM_FIELD__I2C1_STATUS_STATUS </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_INT_FL0 ------------------------------
// SVD Line: 3867
unsigned int I2C1_INT_FL0 __AT (0x4001E008);
// ------------------------------ Field Item: I2C1_INT_FL0_DONE ---------------------------------
// SVD Line: 3872
// <item> SFDITEM_FIELD__I2C1_INT_FL0_DONE
// <name> DONE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E008) \nTransfer Done Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.0..0> DONE
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_FL0_RX_MODE --------------------------------
// SVD Line: 3890
// <item> SFDITEM_FIELD__I2C1_INT_FL0_RX_MODE
// <name> RX_MODE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E008) \nInteractive Receive Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.1..1> RX_MODE
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------- Field Item: I2C1_INT_FL0_GEN_CALL_ADDR -----------------------------
// SVD Line: 3907
// <item> SFDITEM_FIELD__I2C1_INT_FL0_GEN_CALL_ADDR
// <name> GEN_CALL_ADDR </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001E008) \nSlave General Call Address Match Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.2..2> GEN_CALL_ADDR
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_INT_FL0_ADDR_MATCH ------------------------------
// SVD Line: 3924
// <item> SFDITEM_FIELD__I2C1_INT_FL0_ADDR_MATCH
// <name> ADDR_MATCH </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001E008) \nSlave Address Match Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.3..3> ADDR_MATCH
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_INT_FL0_RX_THRESH -------------------------------
// SVD Line: 3941
// <item> SFDITEM_FIELD__I2C1_INT_FL0_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001E008) \nReceive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. RX_FIFO equal or more bytes than the threshold. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.4..4> RX_THRESH
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending. RX_FIFO equal or more bytes than the threshold.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_INT_FL0_TX_THRESH -------------------------------
// SVD Line: 3958
// <item> SFDITEM_FIELD__I2C1_INT_FL0_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bit 5] RW (@ 0x4001E008) \nTransmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.5..5> TX_THRESH
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C1_INT_FL0_STOP ---------------------------------
// SVD Line: 3975
// <item> SFDITEM_FIELD__I2C1_INT_FL0_STOP
// <name> STOP </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4001E008) \nSTOP Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.6..6> STOP
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_FL0_ADDR_ACK -------------------------------
// SVD Line: 3992
// <item> SFDITEM_FIELD__I2C1_INT_FL0_ADDR_ACK
// <name> ADDR_ACK </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001E008) \nAddress Acknowledge Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.7..7> ADDR_ACK
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C1_INT_FL0_ARB_ER --------------------------------
// SVD Line: 4009
// <item> SFDITEM_FIELD__I2C1_INT_FL0_ARB_ER
// <name> ARB_ER </name>
// <rw>
// <i> [Bit 8] RW (@ 0x4001E008) \nArbritation error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.8..8> ARB_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C1_INT_FL0_TO_ER ---------------------------------
// SVD Line: 4026
// <item> SFDITEM_FIELD__I2C1_INT_FL0_TO_ER
// <name> TO_ER </name>
// <rw>
// <i> [Bit 9] RW (@ 0x4001E008) \ntimeout Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.9..9> TO_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C1_INT_FL0_ADDR_NACK_ER -----------------------------
// SVD Line: 4043
// <item> SFDITEM_FIELD__I2C1_INT_FL0_ADDR_NACK_ER
// <name> ADDR_NACK_ER </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001E008) \nAddress NACK Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.10..10> ADDR_NACK_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_FL0_DATA_ER --------------------------------
// SVD Line: 4060
// <item> SFDITEM_FIELD__I2C1_INT_FL0_DATA_ER
// <name> DATA_ER </name>
// <rw>
// <i> [Bit 11] RW (@ 0x4001E008) \nData NACK Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.11..11> DATA_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------- Field Item: I2C1_INT_FL0_DO_NOT_RESP_ER ----------------------------
// SVD Line: 4077
// <item> SFDITEM_FIELD__I2C1_INT_FL0_DO_NOT_RESP_ER
// <name> DO_NOT_RESP_ER </name>
// <rw>
// <i> [Bit 12] RW (@ 0x4001E008) \nDo Not Respond Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.12..12> DO_NOT_RESP_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_FL0_START_ER -------------------------------
// SVD Line: 4094
// <item> SFDITEM_FIELD__I2C1_INT_FL0_START_ER
// <name> START_ER </name>
// <rw>
// <i> [Bit 13] RW (@ 0x4001E008) \nStart Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.13..13> START_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_FL0_STOP_ER --------------------------------
// SVD Line: 4111
// <item> SFDITEM_FIELD__I2C1_INT_FL0_STOP_ER
// <name> STOP_ER </name>
// <rw>
// <i> [Bit 14] RW (@ 0x4001E008) \nStop Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.14..14> STOP_ER
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C1_INT_FL0_TX_LOCK_OUT ------------------------------
// SVD Line: 4128
// <item> SFDITEM_FIELD__I2C1_INT_FL0_TX_LOCK_OUT
// <name> TX_LOCK_OUT </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4001E008) Transmit Lock Out Interrupt. </i>
// <check>
// <loc> ( (unsigned int) I2C1_INT_FL0 ) </loc>
// <o.15..15> TX_LOCK_OUT
// </check>
// </item>
//
// ------------------------------ Register RTree: I2C1_INT_FL0 ----------------------------------
// SVD Line: 3867
// <rtree> SFDITEM_REG__I2C1_INT_FL0
// <name> INT_FL0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E008) Interrupt Status Register. </i>
// <loc> ( (unsigned int)((I2C1_INT_FL0 >> 0) & 0xFFFFFFFF), ((I2C1_INT_FL0 = (I2C1_INT_FL0 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_DONE </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_RX_MODE </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_GEN_CALL_ADDR </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_ADDR_MATCH </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_RX_THRESH </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_TX_THRESH </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_STOP </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_ADDR_ACK </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_ARB_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_TO_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_ADDR_NACK_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_DATA_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_DO_NOT_RESP_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_START_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_STOP_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL0_TX_LOCK_OUT </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_INT_EN0 ------------------------------
// SVD Line: 4135
unsigned int I2C1_INT_EN0 __AT (0x4001E00C);
// ------------------------------ Field Item: I2C1_INT_EN0_DONE ---------------------------------
// SVD Line: 4141
// <item> SFDITEM_FIELD__I2C1_INT_EN0_DONE
// <name> DONE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E00C) \nTransfer Done Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when DONE = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.0..0> DONE
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when DONE = 1.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_EN0_RX_MODE --------------------------------
// SVD Line: 4159
// <item> SFDITEM_FIELD__I2C1_INT_EN0_RX_MODE
// <name> RX_MODE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E00C) \nDescription not available.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when RX_MODE = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.1..1> RX_MODE
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when RX_MODE = 1.
// </combo>
// </item>
//
// ------------------------- Field Item: I2C1_INT_EN0_GEN_CTRL_ADDR -----------------------------
// SVD Line: 4177
// <item> SFDITEM_FIELD__I2C1_INT_EN0_GEN_CTRL_ADDR
// <name> GEN_CTRL_ADDR </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001E00C) \nSlave mode general call address match received input enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when GEN_CTRL_ADDR = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.2..2> GEN_CTRL_ADDR
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when GEN_CTRL_ADDR = 1.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_INT_EN0_ADDR_MATCH ------------------------------
// SVD Line: 4195
// <item> SFDITEM_FIELD__I2C1_INT_EN0_ADDR_MATCH
// <name> ADDR_MATCH </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001E00C) \nSlave mode incoming address match interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when ADDR_MATCH = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.3..3> ADDR_MATCH
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when ADDR_MATCH = 1.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_INT_EN0_RX_THRESH -------------------------------
// SVD Line: 4213
// <item> SFDITEM_FIELD__I2C1_INT_EN0_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001E00C) \nRX FIFO Above Treshold Level Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.4..4> RX_THRESH
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_INT_EN0_TX_THRESH -------------------------------
// SVD Line: 4231
// <item> SFDITEM_FIELD__I2C1_INT_EN0_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bit 5] RW (@ 0x4001E00C) \nTX FIFO Below Treshold Level Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.5..5> TX_THRESH
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ------------------------------ Field Item: I2C1_INT_EN0_STOP ---------------------------------
// SVD Line: 4248
// <item> SFDITEM_FIELD__I2C1_INT_EN0_STOP
// <name> STOP </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4001E00C) \nStop Interrupt Enable\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when STOP = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.6..6> STOP
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when STOP = 1.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_EN0_ADDR_ACK -------------------------------
// SVD Line: 4266
// <item> SFDITEM_FIELD__I2C1_INT_EN0_ADDR_ACK
// <name> ADDR_ACK </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001E00C) \nReceived Address ACK from Slave Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.7..7> ADDR_ACK
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C1_INT_EN0_ARB_ER --------------------------------
// SVD Line: 4283
// <item> SFDITEM_FIELD__I2C1_INT_EN0_ARB_ER
// <name> ARB_ER </name>
// <rw>
// <i> [Bit 8] RW (@ 0x4001E00C) \nMaster Mode Arbitration Lost Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.8..8> ARB_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: I2C1_INT_EN0_TO_ER ---------------------------------
// SVD Line: 4300
// <item> SFDITEM_FIELD__I2C1_INT_EN0_TO_ER
// <name> TO_ER </name>
// <rw>
// <i> [Bit 9] RW (@ 0x4001E00C) \nTimeout Error Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.9..9> TO_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_EN0_ADDR_ER --------------------------------
// SVD Line: 4317
// <item> SFDITEM_FIELD__I2C1_INT_EN0_ADDR_ER
// <name> ADDR_ER </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001E00C) \nMaster Mode Address NACK Received Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.10..10> ADDR_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_EN0_DATA_ER --------------------------------
// SVD Line: 4334
// <item> SFDITEM_FIELD__I2C1_INT_EN0_DATA_ER
// <name> DATA_ER </name>
// <rw>
// <i> [Bit 11] RW (@ 0x4001E00C) \nMaster Mode Data NACK Received Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.11..11> DATA_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ------------------------- Field Item: I2C1_INT_EN0_DO_NOT_RESP_ER ----------------------------
// SVD Line: 4351
// <item> SFDITEM_FIELD__I2C1_INT_EN0_DO_NOT_RESP_ER
// <name> DO_NOT_RESP_ER </name>
// <rw>
// <i> [Bit 12] RW (@ 0x4001E00C) \nSlave Mode Do Not Respond Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.12..12> DO_NOT_RESP_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_EN0_START_ER -------------------------------
// SVD Line: 4368
// <item> SFDITEM_FIELD__I2C1_INT_EN0_START_ER
// <name> START_ER </name>
// <rw>
// <i> [Bit 13] RW (@ 0x4001E00C) \nOut of Sequence START condition detected interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.13..13> START_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_INT_EN0_STOP_ER --------------------------------
// SVD Line: 4385
// <item> SFDITEM_FIELD__I2C1_INT_EN0_STOP_ER
// <name> STOP_ER </name>
// <rw>
// <i> [Bit 14] RW (@ 0x4001E00C) \nOut of Sequence STOP condition detected interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.14..14> STOP_ER
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C1_INT_EN0_TX_LOCK_OUT ------------------------------
// SVD Line: 4402
// <item> SFDITEM_FIELD__I2C1_INT_EN0_TX_LOCK_OUT
// <name> TX_LOCK_OUT </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4001E00C) \nTX FIFO Locked Out Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when TXLOIE = 1. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN0 ) </loc>
// <o.15..15> TX_LOCK_OUT
// <0=> 0: dis = Interrupt disabled.
// <1=> 1: en = Interrupt enabled when TXLOIE = 1.
// </combo>
// </item>
//
// ------------------------------ Register RTree: I2C1_INT_EN0 ----------------------------------
// SVD Line: 4135
// <rtree> SFDITEM_REG__I2C1_INT_EN0
// <name> INT_EN0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E00C) Interrupt Enable Register. </i>
// <loc> ( (unsigned int)((I2C1_INT_EN0 >> 0) & 0xFFFFFFFF), ((I2C1_INT_EN0 = (I2C1_INT_EN0 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_DONE </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_RX_MODE </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_GEN_CTRL_ADDR </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_ADDR_MATCH </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_RX_THRESH </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_TX_THRESH </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_STOP </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_ADDR_ACK </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_ARB_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_TO_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_ADDR_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_DATA_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_DO_NOT_RESP_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_START_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_STOP_ER </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN0_TX_LOCK_OUT </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_INT_FL1 ------------------------------
// SVD Line: 4421
unsigned int I2C1_INT_FL1 __AT (0x4001E010);
// -------------------------- Field Item: I2C1_INT_FL1_RX_OVERFLOW ------------------------------
// SVD Line: 4426
// <item> SFDITEM_FIELD__I2C1_INT_FL1_RX_OVERFLOW
// <name> RX_OVERFLOW </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E010) \nReceiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL1 ) </loc>
// <o.0..0> RX_OVERFLOW
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C1_INT_FL1_TX_UNDERFLOW -----------------------------
// SVD Line: 4443
// <item> SFDITEM_FIELD__I2C1_INT_FL1_TX_UNDERFLOW
// <name> TX_UNDERFLOW </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E010) \nTransmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_FL1 ) </loc>
// <o.1..1> TX_UNDERFLOW
// <0=> 0: inactive = No Interrupt is Pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------------ Register RTree: I2C1_INT_FL1 ----------------------------------
// SVD Line: 4421
// <rtree> SFDITEM_REG__I2C1_INT_FL1
// <name> INT_FL1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E010) Interrupt Status Register 1. </i>
// <loc> ( (unsigned int)((I2C1_INT_FL1 >> 0) & 0xFFFFFFFF), ((I2C1_INT_FL1 = (I2C1_INT_FL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_INT_FL1_RX_OVERFLOW </item>
// <item> SFDITEM_FIELD__I2C1_INT_FL1_TX_UNDERFLOW </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_INT_EN1 ------------------------------
// SVD Line: 4462
unsigned int I2C1_INT_EN1 __AT (0x4001E014);
// -------------------------- Field Item: I2C1_INT_EN1_RX_OVERFLOW ------------------------------
// SVD Line: 4468
// <item> SFDITEM_FIELD__I2C1_INT_EN1_RX_OVERFLOW
// <name> RX_OVERFLOW </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E014) \nReceiver Overflow Interrupt Enable.\n0 : dis = No Interrupt is Pending.\n1 : en = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN1 ) </loc>
// <o.0..0> RX_OVERFLOW
// <0=> 0: dis = No Interrupt is Pending.
// <1=> 1: en = An interrupt is pending.
// </combo>
// </item>
//
// -------------------------- Field Item: I2C1_INT_EN1_TX_UNDERFLOW -----------------------------
// SVD Line: 4485
// <item> SFDITEM_FIELD__I2C1_INT_EN1_TX_UNDERFLOW
// <name> TX_UNDERFLOW </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E014) \nTransmit Underflow Interrupt Enable.\n0 : dis = No Interrupt is Pending.\n1 : en = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_INT_EN1 ) </loc>
// <o.1..1> TX_UNDERFLOW
// <0=> 0: dis = No Interrupt is Pending.
// <1=> 1: en = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------------ Register RTree: I2C1_INT_EN1 ----------------------------------
// SVD Line: 4462
// <rtree> SFDITEM_REG__I2C1_INT_EN1
// <name> INT_EN1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E014) Interrupt Staus Register 1. </i>
// <loc> ( (unsigned int)((I2C1_INT_EN1 >> 0) & 0xFFFFFFFF), ((I2C1_INT_EN1 = (I2C1_INT_EN1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_INT_EN1_RX_OVERFLOW </item>
// <item> SFDITEM_FIELD__I2C1_INT_EN1_TX_UNDERFLOW </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C1_FIFO_LEN ------------------------------
// SVD Line: 4504
unsigned int I2C1_FIFO_LEN __AT (0x4001E018);
// ---------------------------- Field Item: I2C1_FIFO_LEN_RX_LEN --------------------------------
// SVD Line: 4509
// <item> SFDITEM_FIELD__I2C1_FIFO_LEN_RX_LEN
// <name> RX_LEN </name>
// <r>
// <i> [Bits 7..0] RO (@ 0x4001E018) Receive FIFO Length. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_FIFO_LEN >> 0) & 0xFF) ) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: I2C1_FIFO_LEN_TX_LEN --------------------------------
// SVD Line: 4515
// <item> SFDITEM_FIELD__I2C1_FIFO_LEN_TX_LEN
// <name> TX_LEN </name>
// <r>
// <i> [Bits 15..8] RO (@ 0x4001E018) Transmit FIFO Length. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_FIFO_LEN >> 8) & 0xFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C1_FIFO_LEN ---------------------------------
// SVD Line: 4504
// <rtree> SFDITEM_REG__I2C1_FIFO_LEN
// <name> FIFO_LEN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E018) FIFO Configuration Register. </i>
// <loc> ( (unsigned int)((I2C1_FIFO_LEN >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__I2C1_FIFO_LEN_RX_LEN </item>
// <item> SFDITEM_FIELD__I2C1_FIFO_LEN_TX_LEN </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C1_RX_CTRL0 ------------------------------
// SVD Line: 4523
unsigned int I2C1_RX_CTRL0 __AT (0x4001E01C);
// ------------------------------ Field Item: I2C1_RX_CTRL0_DNR ---------------------------------
// SVD Line: 4528
// <item> SFDITEM_FIELD__I2C1_RX_CTRL0_DNR
// <name> DNR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E01C) \nDo Not Respond.\n0 : respond = Always respond to address match.\n1 : not_respond_rx_fifo_empty = Do not respond to address match when RX_FIFO is not empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_RX_CTRL0 ) </loc>
// <o.0..0> DNR
// <0=> 0: respond = Always respond to address match.
// <1=> 1: not_respond_rx_fifo_empty = Do not respond to address match when RX_FIFO is not empty.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_RX_CTRL0_RX_FLUSH -------------------------------
// SVD Line: 4545
// <item> SFDITEM_FIELD__I2C1_RX_CTRL0_RX_FLUSH
// <name> RX_FLUSH </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001E01C) \nReceive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.\n0 : not_flushed = FIFO not flushed.\n1 : flush = Flush RX_FIFO. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_RX_CTRL0 ) </loc>
// <o.7..7> RX_FLUSH
// <0=> 0: not_flushed = FIFO not flushed.
// <1=> 1: flush = Flush RX_FIFO.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_RX_CTRL0_RX_THRESH ------------------------------
// SVD Line: 4562
// <item> SFDITEM_FIELD__I2C1_RX_CTRL0_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bits 11..8] RW (@ 0x4001E01C) Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_RX_CTRL0 >> 8) & 0xF), ((I2C1_RX_CTRL0 = (I2C1_RX_CTRL0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C1_RX_CTRL0 ---------------------------------
// SVD Line: 4523
// <rtree> SFDITEM_REG__I2C1_RX_CTRL0
// <name> RX_CTRL0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E01C) Receive Control Register 0. </i>
// <loc> ( (unsigned int)((I2C1_RX_CTRL0 >> 0) & 0xFFFFFFFF), ((I2C1_RX_CTRL0 = (I2C1_RX_CTRL0 & ~(0xF81UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF81) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_RX_CTRL0_DNR </item>
// <item> SFDITEM_FIELD__I2C1_RX_CTRL0_RX_FLUSH </item>
// <item> SFDITEM_FIELD__I2C1_RX_CTRL0_RX_THRESH </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C1_RX_CTRL1 ------------------------------
// SVD Line: 4569
unsigned int I2C1_RX_CTRL1 __AT (0x4001E020);
// ---------------------------- Field Item: I2C1_RX_CTRL1_RX_CNT --------------------------------
// SVD Line: 4574
// <item> SFDITEM_FIELD__I2C1_RX_CTRL1_RX_CNT
// <name> RX_CNT </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x4001E020) Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_RX_CTRL1 >> 0) & 0xFF), ((I2C1_RX_CTRL1 = (I2C1_RX_CTRL1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: I2C1_RX_CTRL1_RX_FIFO -------------------------------
// SVD Line: 4579
// <item> SFDITEM_FIELD__I2C1_RX_CTRL1_RX_FIFO
// <name> RX_FIFO </name>
// <r>
// <i> [Bits 11..8] RO (@ 0x4001E020) Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_RX_CTRL1 >> 8) & 0xF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C1_RX_CTRL1 ---------------------------------
// SVD Line: 4569
// <rtree> SFDITEM_REG__I2C1_RX_CTRL1
// <name> RX_CTRL1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E020) Receive Control Register 1. </i>
// <loc> ( (unsigned int)((I2C1_RX_CTRL1 >> 0) & 0xFFFFFFFF), ((I2C1_RX_CTRL1 = (I2C1_RX_CTRL1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_RX_CTRL1_RX_CNT </item>
// <item> SFDITEM_FIELD__I2C1_RX_CTRL1_RX_FIFO </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C1_TX_CTRL0 ------------------------------
// SVD Line: 4587
unsigned int I2C1_TX_CTRL0 __AT (0x4001E024);
// -------------------------- Field Item: I2C1_TX_CTRL0_TX_PRELOAD ------------------------------
// SVD Line: 4592
// <item> SFDITEM_FIELD__I2C1_TX_CTRL0_TX_PRELOAD
// <name> TX_PRELOAD </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E024) Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. </i>
// <check>
// <loc> ( (unsigned int) I2C1_TX_CTRL0 ) </loc>
// <o.0..0> TX_PRELOAD
// </check>
// </item>
//
// ------------------------- Field Item: I2C1_TX_CTRL0_TX_READY_MODE ----------------------------
// SVD Line: 4597
// <item> SFDITEM_FIELD__I2C1_TX_CTRL0_TX_READY_MODE
// <name> TX_READY_MODE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E024) \nTransmit FIFO Ready Manual Mode.\n0 : en = HW control of I2CTXRDY enabled.\n1 : dis = HW control of I2CTXRDY disabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_TX_CTRL0 ) </loc>
// <o.1..1> TX_READY_MODE
// <0=> 0: en = HW control of I2CTXRDY enabled.
// <1=> 1: dis = HW control of I2CTXRDY disabled.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_TX_CTRL0_TX_FLUSH -------------------------------
// SVD Line: 4614
// <item> SFDITEM_FIELD__I2C1_TX_CTRL0_TX_FLUSH
// <name> TX_FLUSH </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001E024) \nTransmit FIFO Flush. This bit is automatically cleared to 0 after the operation.\n0 : not_flushed = FIFO not flushed.\n1 : flush = Flush TX_FIFO. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_TX_CTRL0 ) </loc>
// <o.7..7> TX_FLUSH
// <0=> 0: not_flushed = FIFO not flushed.
// <1=> 1: flush = Flush TX_FIFO.
// </combo>
// </item>
//
// --------------------------- Field Item: I2C1_TX_CTRL0_TX_THRESH ------------------------------
// SVD Line: 4631
// <item> SFDITEM_FIELD__I2C1_TX_CTRL0_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bits 11..8] RW (@ 0x4001E024) Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_TX_CTRL0 >> 8) & 0xF), ((I2C1_TX_CTRL0 = (I2C1_TX_CTRL0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C1_TX_CTRL0 ---------------------------------
// SVD Line: 4587
// <rtree> SFDITEM_REG__I2C1_TX_CTRL0
// <name> TX_CTRL0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E024) Transmit Control Register 0. </i>
// <loc> ( (unsigned int)((I2C1_TX_CTRL0 >> 0) & 0xFFFFFFFF), ((I2C1_TX_CTRL0 = (I2C1_TX_CTRL0 & ~(0xF83UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF83) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_TX_CTRL0_TX_PRELOAD </item>
// <item> SFDITEM_FIELD__I2C1_TX_CTRL0_TX_READY_MODE </item>
// <item> SFDITEM_FIELD__I2C1_TX_CTRL0_TX_FLUSH </item>
// <item> SFDITEM_FIELD__I2C1_TX_CTRL0_TX_THRESH </item>
// </rtree>
//
// -------------------------- Register Item Address: I2C1_TX_CTRL1 ------------------------------
// SVD Line: 4638
unsigned int I2C1_TX_CTRL1 __AT (0x4001E028);
// --------------------------- Field Item: I2C1_TX_CTRL1_TX_READY -------------------------------
// SVD Line: 4643
// <item> SFDITEM_FIELD__I2C1_TX_CTRL1_TX_READY
// <name> TX_READY </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E028) Transmit FIFO Preload Ready. </i>
// <check>
// <loc> ( (unsigned int) I2C1_TX_CTRL1 ) </loc>
// <o.0..0> TX_READY
// </check>
// </item>
//
// ---------------------------- Field Item: I2C1_TX_CTRL1_TX_LAST -------------------------------
// SVD Line: 4648
// <item> SFDITEM_FIELD__I2C1_TX_CTRL1_TX_LAST
// <name> TX_LAST </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E028) \nTransmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).\n0 : hold_scl_low = Hold SCL low on TX_FIFO empty.\n1 : end_transaction = End transaction on TX_FIFO empty. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_TX_CTRL1 ) </loc>
// <o.1..1> TX_LAST
// <0=> 0: hold_scl_low = Hold SCL low on TX_FIFO empty.
// <1=> 1: end_transaction = End transaction on TX_FIFO empty.
// </combo>
// </item>
//
// ---------------------------- Field Item: I2C1_TX_CTRL1_TX_FIFO -------------------------------
// SVD Line: 4665
// <item> SFDITEM_FIELD__I2C1_TX_CTRL1_TX_FIFO
// <name> TX_FIFO </name>
// <r>
// <i> [Bits 11..8] RO (@ 0x4001E028) Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_TX_CTRL1 >> 8) & 0xF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C1_TX_CTRL1 ---------------------------------
// SVD Line: 4638
// <rtree> SFDITEM_REG__I2C1_TX_CTRL1
// <name> TX_CTRL1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E028) Transmit Control Register 1. </i>
// <loc> ( (unsigned int)((I2C1_TX_CTRL1 >> 0) & 0xFFFFFFFF), ((I2C1_TX_CTRL1 = (I2C1_TX_CTRL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_TX_CTRL1_TX_READY </item>
// <item> SFDITEM_FIELD__I2C1_TX_CTRL1_TX_LAST </item>
// <item> SFDITEM_FIELD__I2C1_TX_CTRL1_TX_FIFO </item>
// </rtree>
//
// ---------------------------- Register Item Address: I2C1_FIFO --------------------------------
// SVD Line: 4673
unsigned int I2C1_FIFO __AT (0x4001E02C);
// ------------------------------- Field Item: I2C1_FIFO_DATA -----------------------------------
// SVD Line: 4678
// <item> SFDITEM_FIELD__I2C1_FIFO_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x4001E02C) Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_FIFO >> 0) & 0xFF), ((I2C1_FIFO = (I2C1_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: I2C1_FIFO -----------------------------------
// SVD Line: 4673
// <rtree> SFDITEM_REG__I2C1_FIFO
// <name> FIFO </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E02C) Data Register. </i>
// <loc> ( (unsigned int)((I2C1_FIFO >> 0) & 0xFFFFFFFF), ((I2C1_FIFO = (I2C1_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_FIFO_DATA </item>
// </rtree>
//
// ------------------------- Register Item Address: I2C1_MASTER_CTRL ----------------------------
// SVD Line: 4686
unsigned int I2C1_MASTER_CTRL __AT (0x4001E030);
// --------------------------- Field Item: I2C1_MASTER_CTRL_START -------------------------------
// SVD Line: 4691
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_START
// <name> START </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E030) Setting this bit to 1 will start a master transfer. </i>
// <check>
// <loc> ( (unsigned int) I2C1_MASTER_CTRL ) </loc>
// <o.0..0> START
// </check>
// </item>
//
// -------------------------- Field Item: I2C1_MASTER_CTRL_RESTART ------------------------------
// SVD Line: 4696
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_RESTART
// <name> RESTART </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E030) Setting this bit to 1 will generate a repeated START. </i>
// <check>
// <loc> ( (unsigned int) I2C1_MASTER_CTRL ) </loc>
// <o.1..1> RESTART
// </check>
// </item>
//
// ---------------------------- Field Item: I2C1_MASTER_CTRL_STOP -------------------------------
// SVD Line: 4701
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_STOP
// <name> STOP </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001E030) Setting this bit to 1 will generate a STOP condition. </i>
// <check>
// <loc> ( (unsigned int) I2C1_MASTER_CTRL ) </loc>
// <o.2..2> STOP
// </check>
// </item>
//
// ------------------------- Field Item: I2C1_MASTER_CTRL_SL_EX_ADDR ----------------------------
// SVD Line: 4706
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_SL_EX_ADDR
// <name> SL_EX_ADDR </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001E030) \nSlave Extend Address Select.\n0 : 7_bits_address = 7-bit address.\n1 : 10_bits_address = 10-bit address. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_MASTER_CTRL ) </loc>
// <o.7..7> SL_EX_ADDR
// <0=> 0: 7_bits_address = 7-bit address.
// <1=> 1: 10_bits_address = 10-bit address.
// </combo>
// </item>
//
// ------------------------ Field Item: I2C1_MASTER_CTRL_MASTER_CODE ----------------------------
// SVD Line: 4723
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_MASTER_CODE
// <name> MASTER_CODE </name>
// <rw>
// <i> [Bits 10..8] RW (@ 0x4001E030) Master Code. These bits set the Master Code used in Hs-mode operation. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_MASTER_CTRL >> 8) & 0x7), ((I2C1_MASTER_CTRL = (I2C1_MASTER_CTRL & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------ Field Item: I2C1_MASTER_CTRL_SCL_SPEED_UP ---------------------------
// SVD Line: 4728
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_SCL_SPEED_UP
// <name> SCL_SPEED_UP </name>
// <rw>
// <i> [Bit 11] RW (@ 0x4001E030) \nSerial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves.\n0 : en = Master monitors SCL state.\n1 : dis = SCL state monitoring disabled. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_MASTER_CTRL ) </loc>
// <o.11..11> SCL_SPEED_UP
// <0=> 0: en = Master monitors SCL state.
// <1=> 1: dis = SCL state monitoring disabled.
// </combo>
// </item>
//
// ---------------------------- Register RTree: I2C1_MASTER_CTRL --------------------------------
// SVD Line: 4686
// <rtree> SFDITEM_REG__I2C1_MASTER_CTRL
// <name> MASTER_CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E030) Master Control Register. </i>
// <loc> ( (unsigned int)((I2C1_MASTER_CTRL >> 0) & 0xFFFFFFFF), ((I2C1_MASTER_CTRL = (I2C1_MASTER_CTRL & ~(0xF87UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF87) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_START </item>
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_RESTART </item>
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_STOP </item>
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_SL_EX_ADDR </item>
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_MASTER_CODE </item>
// <item> SFDITEM_FIELD__I2C1_MASTER_CTRL_SCL_SPEED_UP </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_CLK_LO -------------------------------
// SVD Line: 4747
unsigned int I2C1_CLK_LO __AT (0x4001E034);
// ----------------------------- Field Item: I2C1_CLK_LO_CLK_LO ---------------------------------
// SVD Line: 4752
// <item> SFDITEM_FIELD__I2C1_CLK_LO_CLK_LO
// <name> CLK_LO </name>
// <rw>
// <i> [Bits 8..0] RW (@ 0x4001E034) Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. </i>
// <edit>
// <loc> ( (unsigned short)((I2C1_CLK_LO >> 0) & 0x1FF), ((I2C1_CLK_LO = (I2C1_CLK_LO & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: I2C1_CLK_LO ----------------------------------
// SVD Line: 4747
// <rtree> SFDITEM_REG__I2C1_CLK_LO
// <name> CLK_LO </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E034) Clock Low Register. </i>
// <loc> ( (unsigned int)((I2C1_CLK_LO >> 0) & 0xFFFFFFFF), ((I2C1_CLK_LO = (I2C1_CLK_LO & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_CLK_LO_CLK_LO </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_CLK_HI -------------------------------
// SVD Line: 4759
unsigned int I2C1_CLK_HI __AT (0x4001E038);
// ------------------------------- Field Item: I2C1_CLK_HI_CKH ----------------------------------
// SVD Line: 4764
// <item> SFDITEM_FIELD__I2C1_CLK_HI_CKH
// <name> CKH </name>
// <rw>
// <i> [Bits 8..0] RW (@ 0x4001E038) Clock High. In master mode, these bits define the SCL high period. </i>
// <edit>
// <loc> ( (unsigned short)((I2C1_CLK_HI >> 0) & 0x1FF), ((I2C1_CLK_HI = (I2C1_CLK_HI & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: I2C1_CLK_HI ----------------------------------
// SVD Line: 4759
// <rtree> SFDITEM_REG__I2C1_CLK_HI
// <name> CLK_HI </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E038) Clock high Register. </i>
// <loc> ( (unsigned int)((I2C1_CLK_HI >> 0) & 0xFFFFFFFF), ((I2C1_CLK_HI = (I2C1_CLK_HI & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_CLK_HI_CKH </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_HS_CLK -------------------------------
// SVD Line: 4771
unsigned int I2C1_HS_CLK __AT (0x4001E03C);
// ---------------------------- Field Item: I2C1_HS_CLK_HS_CLK_LO -------------------------------
// SVD Line: 4776
// <item> SFDITEM_FIELD__I2C1_HS_CLK_HS_CLK_LO
// <name> HS_CLK_LO </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x4001E03C) Slave Address. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_HS_CLK >> 0) & 0xFF), ((I2C1_HS_CLK = (I2C1_HS_CLK & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: I2C1_HS_CLK_HS_CLK_HI -------------------------------
// SVD Line: 4781
// <item> SFDITEM_FIELD__I2C1_HS_CLK_HS_CLK_HI
// <name> HS_CLK_HI </name>
// <rw>
// <i> [Bits 15..8] RW (@ 0x4001E03C) Slave Address. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_HS_CLK >> 8) & 0xFF), ((I2C1_HS_CLK = (I2C1_HS_CLK & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: I2C1_HS_CLK ----------------------------------
// SVD Line: 4771
// <rtree> SFDITEM_REG__I2C1_HS_CLK
// <name> HS_CLK </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E03C) HS-Mode Clock Control Register </i>
// <loc> ( (unsigned int)((I2C1_HS_CLK >> 0) & 0xFFFFFFFF), ((I2C1_HS_CLK = (I2C1_HS_CLK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_HS_CLK_HS_CLK_LO </item>
// <item> SFDITEM_FIELD__I2C1_HS_CLK_HS_CLK_HI </item>
// </rtree>
//
// --------------------------- Register Item Address: I2C1_TIMEOUT ------------------------------
// SVD Line: 4788
unsigned int I2C1_TIMEOUT __AT (0x4001E040);
// ------------------------------- Field Item: I2C1_TIMEOUT_TO ----------------------------------
// SVD Line: 4793
// <item> SFDITEM_FIELD__I2C1_TIMEOUT_TO
// <name> TO </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x4001E040) Timeout </i>
// <edit>
// <loc> ( (unsigned short)((I2C1_TIMEOUT >> 0) & 0xFFFF), ((I2C1_TIMEOUT = (I2C1_TIMEOUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: I2C1_TIMEOUT ----------------------------------
// SVD Line: 4788
// <rtree> SFDITEM_REG__I2C1_TIMEOUT
// <name> TIMEOUT </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E040) Timeout Register </i>
// <loc> ( (unsigned int)((I2C1_TIMEOUT >> 0) & 0xFFFFFFFF), ((I2C1_TIMEOUT = (I2C1_TIMEOUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_TIMEOUT_TO </item>
// </rtree>
//
// ------------------------- Register Item Address: I2C1_SLAVE_ADDR -----------------------------
// SVD Line: 4800
unsigned int I2C1_SLAVE_ADDR __AT (0x4001E044);
// ------------------------- Field Item: I2C1_SLAVE_ADDR_SLAVE_ADDR -----------------------------
// SVD Line: 4805
// <item> SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR
// <name> SLAVE_ADDR </name>
// <rw>
// <i> [Bits 9..0] RW (@ 0x4001E044) Slave Address. </i>
// <edit>
// <loc> ( (unsigned short)((I2C1_SLAVE_ADDR >> 0) & 0x3FF), ((I2C1_SLAVE_ADDR = (I2C1_SLAVE_ADDR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------- Field Item: I2C1_SLAVE_ADDR_SLAVE_ADDR_DIS ---------------------------
// SVD Line: 4810
// <item> SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR_DIS
// <name> SLAVE_ADDR_DIS </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001E044) Slave Address DIS. </i>
// <check>
// <loc> ( (unsigned int) I2C1_SLAVE_ADDR ) </loc>
// <o.10..10> SLAVE_ADDR_DIS
// </check>
// </item>
//
// ----------------------- Field Item: I2C1_SLAVE_ADDR_SLAVE_ADDR_IDX ---------------------------
// SVD Line: 4815
// <item> SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR_IDX
// <name> SLAVE_ADDR_IDX </name>
// <rw>
// <i> [Bits 14..11] RW (@ 0x4001E044) Slave Address Index. </i>
// <edit>
// <loc> ( (unsigned char)((I2C1_SLAVE_ADDR >> 11) & 0xF), ((I2C1_SLAVE_ADDR = (I2C1_SLAVE_ADDR & ~(0xFUL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 11 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------------- Field Item: I2C1_SLAVE_ADDR_EX_ADDR ------------------------------
// SVD Line: 4820
// <item> SFDITEM_FIELD__I2C1_SLAVE_ADDR_EX_ADDR
// <name> EX_ADDR </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4001E044) \nExtended Address Select.\n0 : 7_bits_address = 7-bit address.\n1 : 10_bits_address = 10-bit address. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_SLAVE_ADDR ) </loc>
// <o.15..15> EX_ADDR
// <0=> 0: 7_bits_address = 7-bit address.
// <1=> 1: 10_bits_address = 10-bit address.
// </combo>
// </item>
//
// ----------------------------- Register RTree: I2C1_SLAVE_ADDR --------------------------------
// SVD Line: 4800
// <rtree> SFDITEM_REG__I2C1_SLAVE_ADDR
// <name> SLAVE_ADDR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E044) Slave Address Register. </i>
// <loc> ( (unsigned int)((I2C1_SLAVE_ADDR >> 0) & 0xFFFFFFFF), ((I2C1_SLAVE_ADDR = (I2C1_SLAVE_ADDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR </item>
// <item> SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR_DIS </item>
// <item> SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR_IDX </item>
// <item> SFDITEM_FIELD__I2C1_SLAVE_ADDR_EX_ADDR </item>
// </rtree>
//
// ----------------------------- Register Item Address: I2C1_DMA --------------------------------
// SVD Line: 4839
unsigned int I2C1_DMA __AT (0x4001E048);
// ------------------------------- Field Item: I2C1_DMA_TX_EN -----------------------------------
// SVD Line: 4844
// <item> SFDITEM_FIELD__I2C1_DMA_TX_EN
// <name> TX_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001E048) \nTX channel enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_DMA ) </loc>
// <o.0..0> TX_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: I2C1_DMA_RX_EN -----------------------------------
// SVD Line: 4861
// <item> SFDITEM_FIELD__I2C1_DMA_RX_EN
// <name> RX_EN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001E048) \nRX channel enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) I2C1_DMA ) </loc>
// <o.1..1> RX_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Register RTree: I2C1_DMA ------------------------------------
// SVD Line: 4839
// <rtree> SFDITEM_REG__I2C1_DMA
// <name> DMA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001E048) DMA Register. </i>
// <loc> ( (unsigned int)((I2C1_DMA >> 0) & 0xFFFFFFFF), ((I2C1_DMA = (I2C1_DMA & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__I2C1_DMA_TX_EN </item>
// <item> SFDITEM_FIELD__I2C1_DMA_RX_EN </item>
// </rtree>
//
// ---------------------------------- Peripheral View: I2C1 -------------------------------------
// SVD Line: 4883
// <view> I2C1
// <name> I2C1 </name>
// <item> SFDITEM_REG__I2C1_CTRL </item>
// <item> SFDITEM_REG__I2C1_STATUS </item>
// <item> SFDITEM_REG__I2C1_INT_FL0 </item>
// <item> SFDITEM_REG__I2C1_INT_EN0 </item>
// <item> SFDITEM_REG__I2C1_INT_FL1 </item>
// <item> SFDITEM_REG__I2C1_INT_EN1 </item>
// <item> SFDITEM_REG__I2C1_FIFO_LEN </item>
// <item> SFDITEM_REG__I2C1_RX_CTRL0 </item>
// <item> SFDITEM_REG__I2C1_RX_CTRL1 </item>
// <item> SFDITEM_REG__I2C1_TX_CTRL0 </item>
// <item> SFDITEM_REG__I2C1_TX_CTRL1 </item>
// <item> SFDITEM_REG__I2C1_FIFO </item>
// <item> SFDITEM_REG__I2C1_MASTER_CTRL </item>
// <item> SFDITEM_REG__I2C1_CLK_LO </item>
// <item> SFDITEM_REG__I2C1_CLK_HI </item>
// <item> SFDITEM_REG__I2C1_HS_CLK </item>
// <item> SFDITEM_REG__I2C1_TIMEOUT </item>
// <item> SFDITEM_REG__I2C1_SLAVE_ADDR </item>
// <item> SFDITEM_REG__I2C1_DMA </item>
// </view>
//
// -------------------------- Register Item Address: ICC0_CACHE_ID ------------------------------
// SVD Line: 4904
unsigned int ICC0_CACHE_ID __AT (0x4002A000);
// ---------------------------- Field Item: ICC0_CACHE_ID_RELNUM --------------------------------
// SVD Line: 4910
// <item> SFDITEM_FIELD__ICC0_CACHE_ID_RELNUM
// <name> RELNUM </name>
// <r>
// <i> [Bits 5..0] RO (@ 0x4002A000) Release Number. Identifies the RTL release version. </i>
// <edit>
// <loc> ( (unsigned char)((ICC0_CACHE_ID >> 0) & 0x3F) ) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: ICC0_CACHE_ID_PARTNUM -------------------------------
// SVD Line: 4916
// <item> SFDITEM_FIELD__ICC0_CACHE_ID_PARTNUM
// <name> PARTNUM </name>
// <r>
// <i> [Bits 9..6] RO (@ 0x4002A000) Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. </i>
// <edit>
// <loc> ( (unsigned char)((ICC0_CACHE_ID >> 6) & 0xF) ) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: ICC0_CACHE_ID_CCHID --------------------------------
// SVD Line: 4922
// <item> SFDITEM_FIELD__ICC0_CACHE_ID_CCHID
// <name> CCHID </name>
// <r>
// <i> [Bits 15..10] RO (@ 0x4002A000) Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. </i>
// <edit>
// <loc> ( (unsigned char)((ICC0_CACHE_ID >> 10) & 0x3F) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: ICC0_CACHE_ID ---------------------------------
// SVD Line: 4904
// <rtree> SFDITEM_REG__ICC0_CACHE_ID
// <name> CACHE_ID </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x4002A000) Cache ID Register. </i>
// <loc> ( (unsigned int)((ICC0_CACHE_ID >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__ICC0_CACHE_ID_RELNUM </item>
// <item> SFDITEM_FIELD__ICC0_CACHE_ID_PARTNUM </item>
// <item> SFDITEM_FIELD__ICC0_CACHE_ID_CCHID </item>
// </rtree>
//
// --------------------------- Register Item Address: ICC0_MEMCFG -------------------------------
// SVD Line: 4930
unsigned int ICC0_MEMCFG __AT (0x4002A004);
// ------------------------------ Field Item: ICC0_MEMCFG_CCHSZ ---------------------------------
// SVD Line: 4937
// <item> SFDITEM_FIELD__ICC0_MEMCFG_CCHSZ
// <name> CCHSZ </name>
// <r>
// <i> [Bits 15..0] RO (@ 0x4002A004) Cache Size. Indicates total size in Kbytes of cache. </i>
// <edit>
// <loc> ( (unsigned short)((ICC0_MEMCFG >> 0) & 0xFFFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Field Item: ICC0_MEMCFG_MEMSZ ---------------------------------
// SVD Line: 4943
// <item> SFDITEM_FIELD__ICC0_MEMCFG_MEMSZ
// <name> MEMSZ </name>
// <r>
// <i> [Bits 31..16] RO (@ 0x4002A004) Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. </i>
// <edit>
// <loc> ( (unsigned short)((ICC0_MEMCFG >> 16) & 0xFFFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: ICC0_MEMCFG ----------------------------------
// SVD Line: 4930
// <rtree> SFDITEM_REG__ICC0_MEMCFG
// <name> MEMCFG </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x4002A004) Memory Configuration Register. </i>
// <loc> ( (unsigned int)((ICC0_MEMCFG >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__ICC0_MEMCFG_CCHSZ </item>
// <item> SFDITEM_FIELD__ICC0_MEMCFG_MEMSZ </item>
// </rtree>
//
// ------------------------- Register Item Address: ICC0_CACHE_CTRL -----------------------------
// SVD Line: 4951
unsigned int ICC0_CACHE_CTRL __AT (0x4002A100);
// -------------------------- Field Item: ICC0_CACHE_CTRL_CACHE_EN ------------------------------
// SVD Line: 4956
// <item> SFDITEM_FIELD__ICC0_CACHE_CTRL_CACHE_EN
// <name> CACHE_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4002A100) \nCache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.\n0 : dis = Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.\n1 : en = Cache Enabled. </i>
// <combo>
// <loc> ( (unsigned int) ICC0_CACHE_CTRL ) </loc>
// <o.0..0> CACHE_EN
// <0=> 0: dis = Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.
// <1=> 1: en = Cache Enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: ICC0_CACHE_CTRL_CACHE_RDY -----------------------------
// SVD Line: 4974
// <item> SFDITEM_FIELD__ICC0_CACHE_CTRL_CACHE_RDY
// <name> CACHE_RDY </name>
// <r>
// <i> [Bit 16] RO (@ 0x4002A100) \nCache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.\n0 : notReady = Not Ready.\n1 : ready = Ready. </i>
// <combo>
// <loc> ( (unsigned int) ICC0_CACHE_CTRL ) </loc>
// <o.16..16> CACHE_RDY
// <0=> 0: notReady = Not Ready.
// <1=> 1: ready = Ready.
// </combo>
// </item>
//
// ----------------------------- Register RTree: ICC0_CACHE_CTRL --------------------------------
// SVD Line: 4951
// <rtree> SFDITEM_REG__ICC0_CACHE_CTRL
// <name> CACHE_CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002A100) Cache Control and Status Register. </i>
// <loc> ( (unsigned int)((ICC0_CACHE_CTRL >> 0) & 0xFFFFFFFF), ((ICC0_CACHE_CTRL = (ICC0_CACHE_CTRL & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__ICC0_CACHE_CTRL_CACHE_EN </item>
// <item> SFDITEM_FIELD__ICC0_CACHE_CTRL_CACHE_RDY </item>
// </rtree>
//
// ------------------------- Register Item Address: ICC0_INVALIDATE -----------------------------
// SVD Line: 4995
unsigned int ICC0_INVALIDATE __AT (0x4002A700);
// ----------------------------- Register Item: ICC0_INVALIDATE ---------------------------------
// SVD Line: 4995
// <item> SFDITEM_REG__ICC0_INVALIDATE
// <name> INVALIDATE </name>
// <i> [Bits 31..0] RW (@ 0x4002A700) Invalidate All Registers. </i>
// <edit>
// <loc> ( (unsigned int)((ICC0_INVALIDATE >> 0) & 0xFFFFFFFF), ((ICC0_INVALIDATE = (ICC0_INVALIDATE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------------- Peripheral View: ICC0 -------------------------------------
// SVD Line: 4894
// <view> ICC0
// <name> ICC0 </name>
// <item> SFDITEM_REG__ICC0_CACHE_ID </item>
// <item> SFDITEM_REG__ICC0_MEMCFG </item>
// <item> SFDITEM_REG__ICC0_CACHE_CTRL </item>
// <item> SFDITEM_REG__ICC0_INVALIDATE </item>
// </view>
//
// -------------------------- Register Item Address: ICC1_CACHE_ID ------------------------------
// SVD Line: 4904
unsigned int ICC1_CACHE_ID __AT (0x4002F000);
// ---------------------------- Field Item: ICC1_CACHE_ID_RELNUM --------------------------------
// SVD Line: 4910
// <item> SFDITEM_FIELD__ICC1_CACHE_ID_RELNUM
// <name> RELNUM </name>
// <r>
// <i> [Bits 5..0] RO (@ 0x4002F000) Release Number. Identifies the RTL release version. </i>
// <edit>
// <loc> ( (unsigned char)((ICC1_CACHE_ID >> 0) & 0x3F) ) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: ICC1_CACHE_ID_PARTNUM -------------------------------
// SVD Line: 4916
// <item> SFDITEM_FIELD__ICC1_CACHE_ID_PARTNUM
// <name> PARTNUM </name>
// <r>
// <i> [Bits 9..6] RO (@ 0x4002F000) Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. </i>
// <edit>
// <loc> ( (unsigned char)((ICC1_CACHE_ID >> 6) & 0xF) ) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: ICC1_CACHE_ID_CCHID --------------------------------
// SVD Line: 4922
// <item> SFDITEM_FIELD__ICC1_CACHE_ID_CCHID
// <name> CCHID </name>
// <r>
// <i> [Bits 15..10] RO (@ 0x4002F000) Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. </i>
// <edit>
// <loc> ( (unsigned char)((ICC1_CACHE_ID >> 10) & 0x3F) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: ICC1_CACHE_ID ---------------------------------
// SVD Line: 4904
// <rtree> SFDITEM_REG__ICC1_CACHE_ID
// <name> CACHE_ID </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x4002F000) Cache ID Register. </i>
// <loc> ( (unsigned int)((ICC1_CACHE_ID >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__ICC1_CACHE_ID_RELNUM </item>
// <item> SFDITEM_FIELD__ICC1_CACHE_ID_PARTNUM </item>
// <item> SFDITEM_FIELD__ICC1_CACHE_ID_CCHID </item>
// </rtree>
//
// --------------------------- Register Item Address: ICC1_MEMCFG -------------------------------
// SVD Line: 4930
unsigned int ICC1_MEMCFG __AT (0x4002F004);
// ------------------------------ Field Item: ICC1_MEMCFG_CCHSZ ---------------------------------
// SVD Line: 4937
// <item> SFDITEM_FIELD__ICC1_MEMCFG_CCHSZ
// <name> CCHSZ </name>
// <r>
// <i> [Bits 15..0] RO (@ 0x4002F004) Cache Size. Indicates total size in Kbytes of cache. </i>
// <edit>
// <loc> ( (unsigned short)((ICC1_MEMCFG >> 0) & 0xFFFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------ Field Item: ICC1_MEMCFG_MEMSZ ---------------------------------
// SVD Line: 4943
// <item> SFDITEM_FIELD__ICC1_MEMCFG_MEMSZ
// <name> MEMSZ </name>
// <r>
// <i> [Bits 31..16] RO (@ 0x4002F004) Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. </i>
// <edit>
// <loc> ( (unsigned short)((ICC1_MEMCFG >> 16) & 0xFFFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: ICC1_MEMCFG ----------------------------------
// SVD Line: 4930
// <rtree> SFDITEM_REG__ICC1_MEMCFG
// <name> MEMCFG </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x4002F004) Memory Configuration Register. </i>
// <loc> ( (unsigned int)((ICC1_MEMCFG >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__ICC1_MEMCFG_CCHSZ </item>
// <item> SFDITEM_FIELD__ICC1_MEMCFG_MEMSZ </item>
// </rtree>
//
// ------------------------- Register Item Address: ICC1_CACHE_CTRL -----------------------------
// SVD Line: 4951
unsigned int ICC1_CACHE_CTRL __AT (0x4002F100);
// -------------------------- Field Item: ICC1_CACHE_CTRL_CACHE_EN ------------------------------
// SVD Line: 4956
// <item> SFDITEM_FIELD__ICC1_CACHE_CTRL_CACHE_EN
// <name> CACHE_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4002F100) \nCache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.\n0 : dis = Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.\n1 : en = Cache Enabled. </i>
// <combo>
// <loc> ( (unsigned int) ICC1_CACHE_CTRL ) </loc>
// <o.0..0> CACHE_EN
// <0=> 0: dis = Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.
// <1=> 1: en = Cache Enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: ICC1_CACHE_CTRL_CACHE_RDY -----------------------------
// SVD Line: 4974
// <item> SFDITEM_FIELD__ICC1_CACHE_CTRL_CACHE_RDY
// <name> CACHE_RDY </name>
// <r>
// <i> [Bit 16] RO (@ 0x4002F100) \nCache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.\n0 : notReady = Not Ready.\n1 : ready = Ready. </i>
// <combo>
// <loc> ( (unsigned int) ICC1_CACHE_CTRL ) </loc>
// <o.16..16> CACHE_RDY
// <0=> 0: notReady = Not Ready.
// <1=> 1: ready = Ready.
// </combo>
// </item>
//
// ----------------------------- Register RTree: ICC1_CACHE_CTRL --------------------------------
// SVD Line: 4951
// <rtree> SFDITEM_REG__ICC1_CACHE_CTRL
// <name> CACHE_CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4002F100) Cache Control and Status Register. </i>
// <loc> ( (unsigned int)((ICC1_CACHE_CTRL >> 0) & 0xFFFFFFFF), ((ICC1_CACHE_CTRL = (ICC1_CACHE_CTRL & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__ICC1_CACHE_CTRL_CACHE_EN </item>
// <item> SFDITEM_FIELD__ICC1_CACHE_CTRL_CACHE_RDY </item>
// </rtree>
//
// ------------------------- Register Item Address: ICC1_INVALIDATE -----------------------------
// SVD Line: 4995
unsigned int ICC1_INVALIDATE __AT (0x4002F700);
// ----------------------------- Register Item: ICC1_INVALIDATE ---------------------------------
// SVD Line: 4995
// <item> SFDITEM_REG__ICC1_INVALIDATE
// <name> INVALIDATE </name>
// <i> [Bits 31..0] RW (@ 0x4002F700) Invalidate All Registers. </i>
// <edit>
// <loc> ( (unsigned int)((ICC1_INVALIDATE >> 0) & 0xFFFFFFFF), ((ICC1_INVALIDATE = (ICC1_INVALIDATE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------------- Peripheral View: ICC1 -------------------------------------
// SVD Line: 5004
// <view> ICC1
// <name> ICC1 </name>
// <item> SFDITEM_REG__ICC1_CACHE_ID </item>
// <item> SFDITEM_REG__ICC1_MEMCFG </item>
// <item> SFDITEM_REG__ICC1_CACHE_CTRL </item>
// <item> SFDITEM_REG__ICC1_INVALIDATE </item>
// </view>
//
// -------------------------- Register Item Address: PWRSEQ_LP_CTRL -----------------------------
// SVD Line: 5020
unsigned int PWRSEQ_LP_CTRL __AT (0x40006800);
// ------------------------- Field Item: PWRSEQ_LP_CTRL_RAMRET_SEL0 -----------------------------
// SVD Line: 5025
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL0
// <name> RAMRET_SEL0 </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40006800) \nSystem RAM 0 Data retention in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.0..0> RAMRET_SEL0
// <0=> 0: dis = Disabled.
// <1=> 1: en = Enabled.
// </combo>
// </item>
//
// ------------------------- Field Item: PWRSEQ_LP_CTRL_RAMRET_SEL1 -----------------------------
// SVD Line: 5043
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL1
// <name> RAMRET_SEL1 </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40006800) \nSystem RAM 1 Data retention in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.1..1> RAMRET_SEL1
// <0=> 0: dis = Disabled.
// <1=> 1: en = Enabled.
// </combo>
// </item>
//
// ------------------------- Field Item: PWRSEQ_LP_CTRL_RAMRET_SEL2 -----------------------------
// SVD Line: 5061
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL2
// <name> RAMRET_SEL2 </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40006800) \nSystem RAM 2 Data retention in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.2..2> RAMRET_SEL2
// <0=> 0: dis = Disabled.
// <1=> 1: en = Enabled.
// </combo>
// </item>
//
// ------------------------- Field Item: PWRSEQ_LP_CTRL_RAMRET_SEL3 -----------------------------
// SVD Line: 5079
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL3
// <name> RAMRET_SEL3 </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40006800) \nSystem RAM 3 Data retention in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.3..3> RAMRET_SEL3
// <0=> 0: dis = Disabled.
// <1=> 1: en = Enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: PWRSEQ_LP_CTRL_OVR ---------------------------------
// SVD Line: 5097
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_OVR
// <name> OVR </name>
// <rw>
// <i> [Bits 5..4] RW (@ 0x40006800) \nOperating Voltage Range\n0 : 0_9V = 0.9V 24MHz\n1 : 1_0V = 1.0V 48MHz\n2 : 1_1V = 1.1V 96MHz\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.5..4> OVR
// <0=> 0: 0_9V = 0.9V 24MHz
// <1=> 1: 1_0V = 1.0V 48MHz
// <2=> 2: 1_1V = 1.1V 96MHz
// <3=> 3:
// </combo>
// </item>
//
// ----------------------- Field Item: PWRSEQ_LP_CTRL_VCORE_DET_BYPASS --------------------------
// SVD Line: 5120
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_DET_BYPASS
// <name> VCORE_DET_BYPASS </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40006800) \nBypass V CORE External Supply Detection\n0 : enabled = enable\n1 : Disable = disable </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.6..6> VCORE_DET_BYPASS
// <0=> 0: enabled = enable
// <1=> 1: Disable = disable
// </combo>
// </item>
//
// -------------------------- Field Item: PWRSEQ_LP_CTRL_RETREG_EN ------------------------------
// SVD Line: 5138
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RETREG_EN
// <name> RETREG_EN </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40006800) \nRetention Regulator Enable. This bit controls the retention regulator in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.8..8> RETREG_EN
// <0=> 0: dis = Disabled.
// <1=> 1: en = Enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: PWRSEQ_LP_CTRL_FAST_WK_EN -----------------------------
// SVD Line: 5156
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_FAST_WK_EN
// <name> FAST_WK_EN </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40006800) \nFast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode.\n0 : dis = Disabled.\n1 : en = Enabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.10..10> FAST_WK_EN
// <0=> 0: dis = Disabled.
// <1=> 1: en = Enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: PWRSEQ_LP_CTRL_BG_OFF -------------------------------
// SVD Line: 5174
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_BG_OFF
// <name> BG_OFF </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40006800) \nBand Gap Disable for DEEPSLEEP and BACKUP Mode\n0 : on = Bandgap is always ON.\n1 : off = Bandgap is OFF in DeepSleep mode(default). </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.11..11> BG_OFF
// <0=> 0: on = Bandgap is always ON.
// <1=> 1: off = Bandgap is OFF in DeepSleep mode(default).
// </combo>
// </item>
//
// ------------------------ Field Item: PWRSEQ_LP_CTRL_VCORE_POR_DIS ----------------------------
// SVD Line: 5192
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_POR_DIS
// <name> VCORE_POR_DIS </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40006800) \nV CORE POR Disable for DEEPSLEEP and BACKUP Mode\n0 : dis = Disabled.\n1 : en = Enabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.12..12> VCORE_POR_DIS
// <0=> 0: dis = Disabled.
// <1=> 1: en = Enabled.
// </combo>
// </item>
//
// --------------------------- Field Item: PWRSEQ_LP_CTRL_LDO_DIS -------------------------------
// SVD Line: 5210
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_LDO_DIS
// <name> LDO_DIS </name>
// <rw>
// <i> [Bit 16] RW (@ 0x40006800) \nLDO Disable\n0 : en = Enable if Bandgap is ON(default)\n1 : dis = Disabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.16..16> LDO_DIS
// <0=> 0: en = Enable if Bandgap is ON(default)
// <1=> 1: dis = Disabled.
// </combo>
// </item>
//
// ------------------------ Field Item: PWRSEQ_LP_CTRL_VCORE_SVM_DIS ----------------------------
// SVD Line: 5228
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_SVM_DIS
// <name> VCORE_SVM_DIS </name>
// <rw>
// <i> [Bit 20] RW (@ 0x40006800) \nV CORE Supply Voltage Monitor Disable\n0 : en = Enable if Bandgap is ON(default)\n1 : dis = Disabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.20..20> VCORE_SVM_DIS
// <0=> 0: en = Enable if Bandgap is ON(default)
// <1=> 1: dis = Disabled.
// </combo>
// </item>
//
// ------------------------ Field Item: PWRSEQ_LP_CTRL_VDDIO_POR_DIS ----------------------------
// SVD Line: 5246
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_VDDIO_POR_DIS
// <name> VDDIO_POR_DIS </name>
// <rw>
// <i> [Bit 25] RW (@ 0x40006800) \nVDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.\n0 : en = Enabled.\n1 : dis = Disabled. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LP_CTRL ) </loc>
// <o.25..25> VDDIO_POR_DIS
// <0=> 0: en = Enabled.
// <1=> 1: dis = Disabled.
// </combo>
// </item>
//
// ----------------------------- Register RTree: PWRSEQ_LP_CTRL ---------------------------------
// SVD Line: 5020
// <rtree> SFDITEM_REG__PWRSEQ_LP_CTRL
// <name> LP_CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006800) Low Power Control Register. </i>
// <loc> ( (unsigned int)((PWRSEQ_LP_CTRL >> 0) & 0xFFFFFFFF), ((PWRSEQ_LP_CTRL = (PWRSEQ_LP_CTRL & ~(0x2111D7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2111D7F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL0 </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL1 </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL2 </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL3 </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_OVR </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_DET_BYPASS </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_RETREG_EN </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_FAST_WK_EN </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_BG_OFF </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_POR_DIS </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_LDO_DIS </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_SVM_DIS </item>
// <item> SFDITEM_FIELD__PWRSEQ_LP_CTRL_VDDIO_POR_DIS </item>
// </rtree>
//
// ------------------------- Register Item Address: PWRSEQ_LP_WAKEFL ----------------------------
// SVD Line: 5266
unsigned int PWRSEQ_LP_WAKEFL __AT (0x40006804);
// --------------------------- Field Item: PWRSEQ_LP_WAKEFL_WAKEST ------------------------------
// SVD Line: 5271
// <item> SFDITEM_FIELD__PWRSEQ_LP_WAKEFL_WAKEST
// <name> WAKEST </name>
// <rw>
// <i> [Bits 13..0] RW (@ 0x40006804) Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. </i>
// <edit>
// <loc> ( (unsigned short)((PWRSEQ_LP_WAKEFL >> 0) & 0x3FFF), ((PWRSEQ_LP_WAKEFL = (PWRSEQ_LP_WAKEFL & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: PWRSEQ_LP_WAKEFL --------------------------------
// SVD Line: 5266
// <rtree> SFDITEM_REG__PWRSEQ_LP_WAKEFL
// <name> LP_WAKEFL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006804) Low Power Mode Wakeup Flags for GPIO0 </i>
// <loc> ( (unsigned int)((PWRSEQ_LP_WAKEFL >> 0) & 0xFFFFFFFF), ((PWRSEQ_LP_WAKEFL = (PWRSEQ_LP_WAKEFL & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__PWRSEQ_LP_WAKEFL_WAKEST </item>
// </rtree>
//
// -------------------------- Register Item Address: PWRSEQ_LPWK_EN -----------------------------
// SVD Line: 5279
unsigned int PWRSEQ_LPWK_EN __AT (0x40006808);
// ---------------------------- Field Item: PWRSEQ_LPWK_EN_WAKEEN -------------------------------
// SVD Line: 5284
// <item> SFDITEM_FIELD__PWRSEQ_LPWK_EN_WAKEEN
// <name> WAKEEN </name>
// <rw>
// <i> [Bits 13..0] RW (@ 0x40006808) Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. </i>
// <edit>
// <loc> ( (unsigned short)((PWRSEQ_LPWK_EN >> 0) & 0x3FFF), ((PWRSEQ_LPWK_EN = (PWRSEQ_LPWK_EN & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register RTree: PWRSEQ_LPWK_EN ---------------------------------
// SVD Line: 5279
// <rtree> SFDITEM_REG__PWRSEQ_LPWK_EN
// <name> LPWK_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006808) Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. </i>
// <loc> ( (unsigned int)((PWRSEQ_LPWK_EN >> 0) & 0xFFFFFFFF), ((PWRSEQ_LPWK_EN = (PWRSEQ_LPWK_EN & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__PWRSEQ_LPWK_EN_WAKEEN </item>
// </rtree>
//
// -------------------------- Register Item Address: PWRSEQ_LPMEMSD -----------------------------
// SVD Line: 5292
unsigned int PWRSEQ_LPMEMSD __AT (0x40006840);
// -------------------------- Field Item: PWRSEQ_LPMEMSD_SRAM0_OFF ------------------------------
// SVD Line: 5297
// <item> SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM0_OFF
// <name> SRAM0_OFF </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40006840) \nSystem RAM block 0 Shut Down.\n0 : normal = Normal Operating Mode.\n1 : shutdown = Shutdown Mode. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LPMEMSD ) </loc>
// <o.0..0> SRAM0_OFF
// <0=> 0: normal = Normal Operating Mode.
// <1=> 1: shutdown = Shutdown Mode.
// </combo>
// </item>
//
// -------------------------- Field Item: PWRSEQ_LPMEMSD_SRAM1_OFF ------------------------------
// SVD Line: 5315
// <item> SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM1_OFF
// <name> SRAM1_OFF </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40006840) \nSystem RAM block 1 Shut Down.\n0 : normal = Normal Operating Mode.\n1 : shutdown = Shutdown Mode. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LPMEMSD ) </loc>
// <o.1..1> SRAM1_OFF
// <0=> 0: normal = Normal Operating Mode.
// <1=> 1: shutdown = Shutdown Mode.
// </combo>
// </item>
//
// -------------------------- Field Item: PWRSEQ_LPMEMSD_SRAM2_OFF ------------------------------
// SVD Line: 5333
// <item> SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM2_OFF
// <name> SRAM2_OFF </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40006840) \nSystem RAM block 2 Shut Down.\n0 : normal = Normal Operating Mode.\n1 : shutdown = Shutdown Mode. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LPMEMSD ) </loc>
// <o.2..2> SRAM2_OFF
// <0=> 0: normal = Normal Operating Mode.
// <1=> 1: shutdown = Shutdown Mode.
// </combo>
// </item>
//
// -------------------------- Field Item: PWRSEQ_LPMEMSD_SRAM3_OFF ------------------------------
// SVD Line: 5351
// <item> SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM3_OFF
// <name> SRAM3_OFF </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40006840) \nSystem RAM block 3 Shut Down.\n0 : normal = Normal Operating Mode.\n1 : shutdown = Shutdown Mode. </i>
// <combo>
// <loc> ( (unsigned int) PWRSEQ_LPMEMSD ) </loc>
// <o.3..3> SRAM3_OFF
// <0=> 0: normal = Normal Operating Mode.
// <1=> 1: shutdown = Shutdown Mode.
// </combo>
// </item>
//
// ----------------------------- Register RTree: PWRSEQ_LPMEMSD ---------------------------------
// SVD Line: 5292
// <rtree> SFDITEM_REG__PWRSEQ_LPMEMSD
// <name> LPMEMSD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006840) Low Power Memory Shutdown Control. </i>
// <loc> ( (unsigned int)((PWRSEQ_LPMEMSD >> 0) & 0xFFFFFFFF), ((PWRSEQ_LPMEMSD = (PWRSEQ_LPMEMSD & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM0_OFF </item>
// <item> SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM1_OFF </item>
// <item> SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM2_OFF </item>
// <item> SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM3_OFF </item>
// </rtree>
//
// --------------------------------- Peripheral View: PWRSEQ ------------------------------------
// SVD Line: 5010
// <view> PWRSEQ
// <name> PWRSEQ </name>
// <item> SFDITEM_REG__PWRSEQ_LP_CTRL </item>
// <item> SFDITEM_REG__PWRSEQ_LP_WAKEFL </item>
// <item> SFDITEM_REG__PWRSEQ_LPWK_EN </item>
// <item> SFDITEM_REG__PWRSEQ_LPMEMSD </item>
// </view>
//
// ----------------------------- Register Item Address: RTC_SEC ---------------------------------
// SVD Line: 5389
unsigned int RTC_SEC __AT (0x40006000);
// --------------------------------- Register Item: RTC_SEC -------------------------------------
// SVD Line: 5389
// <item> SFDITEM_REG__RTC_SEC
// <name> SEC </name>
// <i> [Bits 31..0] RW (@ 0x40006000) RTC Second Counter. This register contains the 32-bit second counter. </i>
// <edit>
// <loc> ( (unsigned int)((RTC_SEC >> 0) & 0xFFFFFFFF), ((RTC_SEC = (RTC_SEC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: RTC_SSEC --------------------------------
// SVD Line: 5395
unsigned int RTC_SSEC __AT (0x40006004);
// -------------------------------- Field Item: RTC_SSEC_RTSS -----------------------------------
// SVD Line: 5401
// <item> SFDITEM_FIELD__RTC_SSEC_RTSS
// <name> RTSS </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40006004) RTC Sub-second Counter. </i>
// <edit>
// <loc> ( (unsigned char)((RTC_SSEC >> 0) & 0xFF), ((RTC_SSEC = (RTC_SSEC & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: RTC_SSEC ------------------------------------
// SVD Line: 5395
// <rtree> SFDITEM_REG__RTC_SSEC
// <name> SSEC </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006004) RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. </i>
// <loc> ( (unsigned int)((RTC_SSEC >> 0) & 0xFFFFFFFF), ((RTC_SSEC = (RTC_SSEC & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__RTC_SSEC_RTSS </item>
// </rtree>
//
// ----------------------------- Register Item Address: RTC_RAS ---------------------------------
// SVD Line: 5409
unsigned int RTC_RAS __AT (0x40006008);
// --------------------------------- Field Item: RTC_RAS_RAS ------------------------------------
// SVD Line: 5415
// <item> SFDITEM_FIELD__RTC_RAS_RAS
// <name> RAS </name>
// <rw>
// <i> [Bits 19..0] RW (@ 0x40006008) Time-of-day Alarm. </i>
// <edit>
// <loc> ( (unsigned int)((RTC_RAS >> 0) & 0xFFFFF), ((RTC_RAS = (RTC_RAS & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------------------- Register RTree: RTC_RAS ------------------------------------
// SVD Line: 5409
// <rtree> SFDITEM_REG__RTC_RAS
// <name> RAS </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006008) Time-of-day Alarm. </i>
// <loc> ( (unsigned int)((RTC_RAS >> 0) & 0xFFFFFFFF), ((RTC_RAS = (RTC_RAS & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__RTC_RAS_RAS </item>
// </rtree>
//
// ----------------------------- Register Item Address: RTC_RSSA --------------------------------
// SVD Line: 5423
unsigned int RTC_RSSA __AT (0x4000600C);
// -------------------------------- Field Item: RTC_RSSA_RSSA -----------------------------------
// SVD Line: 5429
// <item> SFDITEM_FIELD__RTC_RSSA_RSSA
// <name> RSSA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000600C) This register contains the reload value for the sub-second alarm. </i>
// <edit>
// <loc> ( (unsigned int)((RTC_RSSA >> 0) & 0xFFFFFFFF), ((RTC_RSSA = (RTC_RSSA & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: RTC_RSSA ------------------------------------
// SVD Line: 5423
// <rtree> SFDITEM_REG__RTC_RSSA
// <name> RSSA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4000600C) RTC sub-second alarm. This register contains the reload value for the sub-second alarm. </i>
// <loc> ( (unsigned int)((RTC_RSSA >> 0) & 0xFFFFFFFF), ((RTC_RSSA = (RTC_RSSA & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__RTC_RSSA_RSSA </item>
// </rtree>
//
// ----------------------------- Register Item Address: RTC_CTRL --------------------------------
// SVD Line: 5437
unsigned int RTC_CTRL __AT (0x40006010);
// -------------------------------- Field Item: RTC_CTRL_RTCE -----------------------------------
// SVD Line: 5444
// <item> SFDITEM_FIELD__RTC_CTRL_RTCE
// <name> RTCE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40006010) \nReal Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.0..0> RTCE
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: RTC_CTRL_ADE ------------------------------------
// SVD Line: 5462
// <item> SFDITEM_FIELD__RTC_CTRL_ADE
// <name> ADE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40006010) \nAlarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.1..1> ADE
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: RTC_CTRL_ASE ------------------------------------
// SVD Line: 5480
// <item> SFDITEM_FIELD__RTC_CTRL_ASE
// <name> ASE </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40006010) \nAlarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.2..2> ASE
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: RTC_CTRL_BUSY -----------------------------------
// SVD Line: 5498
// <item> SFDITEM_FIELD__RTC_CTRL_BUSY
// <name> BUSY </name>
// <r>
// <i> [Bit 3] RO (@ 0x40006010) \nRTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.\n0 : idle = Idle.\n1 : busy = Busy. </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.3..3> BUSY
// <0=> 0: idle = Idle.
// <1=> 1: busy = Busy.
// </combo>
// </item>
//
// -------------------------------- Field Item: RTC_CTRL_RDY ------------------------------------
// SVD Line: 5517
// <item> SFDITEM_FIELD__RTC_CTRL_RDY
// <name> RDY </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40006010) \nRTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.\n0 : busy = Register has not updated.\n1 : ready = Ready. </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.4..4> RDY
// <0=> 0: busy = Register has not updated.
// <1=> 1: ready = Ready.
// </combo>
// </item>
//
// -------------------------------- Field Item: RTC_CTRL_RDYE -----------------------------------
// SVD Line: 5535
// <item> SFDITEM_FIELD__RTC_CTRL_RDYE
// <name> RDYE </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40006010) \nRTC Ready Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.5..5> RDYE
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: RTC_CTRL_ALDF -----------------------------------
// SVD Line: 5553
// <item> SFDITEM_FIELD__RTC_CTRL_ALDF
// <name> ALDF </name>
// <r>
// <i> [Bit 6] RO (@ 0x40006010) \nTime-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.\n0 : inactive = Not active\n1 : Pending = Active </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.6..6> ALDF
// <0=> 0: inactive = Not active
// <1=> 1: Pending = Active
// </combo>
// </item>
//
// -------------------------------- Field Item: RTC_CTRL_ALSF -----------------------------------
// SVD Line: 5572
// <item> SFDITEM_FIELD__RTC_CTRL_ALSF
// <name> ALSF </name>
// <r>
// <i> [Bit 7] RO (@ 0x40006010) \nSub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.\n0 : inactive = Not active\n1 : Pending = Active </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.7..7> ALSF
// <0=> 0: inactive = Not active
// <1=> 1: Pending = Active
// </combo>
// </item>
//
// -------------------------------- Field Item: RTC_CTRL_SQE ------------------------------------
// SVD Line: 5591
// <item> SFDITEM_FIELD__RTC_CTRL_SQE
// <name> SQE </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40006010) \nSquare Wave Output Enable.\n0 : inactive = Not active\n1 : Pending = Active </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.8..8> SQE
// <0=> 0: inactive = Not active
// <1=> 1: Pending = Active
// </combo>
// </item>
//
// --------------------------------- Field Item: RTC_CTRL_FT ------------------------------------
// SVD Line: 5609
// <item> SFDITEM_FIELD__RTC_CTRL_FT
// <name> FT </name>
// <rw>
// <i> [Bits 10..9] RW (@ 0x40006010) \nFrequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.\n0 : freq1Hz = 1 Hz (Compensated).\n1 : freq512Hz = 512 Hz (Compensated).\n2 : freq4KHz = 4 KHz.\n3 : clkDiv8 = RTC Input Clock / 8. </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.10..9> FT
// <0=> 0: freq1Hz = 1 Hz (Compensated).
// <1=> 1: freq512Hz = 512 Hz (Compensated).
// <2=> 2: freq4KHz = 4 KHz.
// <3=> 3: clkDiv8 = RTC Input Clock / 8.
// </combo>
// </item>
//
// ------------------------------- Field Item: RTC_CTRL_X32KMD ----------------------------------
// SVD Line: 5637
// <item> SFDITEM_FIELD__RTC_CTRL_X32KMD
// <name> X32KMD </name>
// <rw>
// <i> [Bits 12..11] RW (@ 0x40006010) \n32KHz Oscillator Mode.\n0 : noiseImmuneMode = Always operate in Noise Immune Mode. Oscillator warm-up required.\n1 : quietMode = Always operate in Quiet Mode. No oscillator warm-up required.\n2 : quietInStopWithWarmup = Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.\n3 : quietInStopNoWarmup = Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit. </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.12..11> X32KMD
// <0=> 0: noiseImmuneMode = Always operate in Noise Immune Mode. Oscillator warm-up required.
// <1=> 1: quietMode = Always operate in Quiet Mode. No oscillator warm-up required.
// <2=> 2: quietInStopWithWarmup = Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.
// <3=> 3: quietInStopNoWarmup = Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit.
// </combo>
// </item>
//
// --------------------------------- Field Item: RTC_CTRL_WE ------------------------------------
// SVD Line: 5665
// <item> SFDITEM_FIELD__RTC_CTRL_WE
// <name> WE </name>
// <rw>
// <i> [Bit 15] RW (@ 0x40006010) \nWrite Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.\n0 : inactive = Not active\n1 : Pending = Active </i>
// <combo>
// <loc> ( (unsigned int) RTC_CTRL ) </loc>
// <o.15..15> WE
// <0=> 0: inactive = Not active
// <1=> 1: Pending = Active
// </combo>
// </item>
//
// -------------------------------- Register RTree: RTC_CTRL ------------------------------------
// SVD Line: 5437
// <rtree> SFDITEM_REG__RTC_CTRL
// <name> CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006010) RTC Control Register. </i>
// <loc> ( (unsigned int)((RTC_CTRL >> 0) & 0xFFFFFFFF), ((RTC_CTRL = (RTC_CTRL & ~(0x9F37UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x9F37) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__RTC_CTRL_RTCE </item>
// <item> SFDITEM_FIELD__RTC_CTRL_ADE </item>
// <item> SFDITEM_FIELD__RTC_CTRL_ASE </item>
// <item> SFDITEM_FIELD__RTC_CTRL_BUSY </item>
// <item> SFDITEM_FIELD__RTC_CTRL_RDY </item>
// <item> SFDITEM_FIELD__RTC_CTRL_RDYE </item>
// <item> SFDITEM_FIELD__RTC_CTRL_ALDF </item>
// <item> SFDITEM_FIELD__RTC_CTRL_ALSF </item>
// <item> SFDITEM_FIELD__RTC_CTRL_SQE </item>
// <item> SFDITEM_FIELD__RTC_CTRL_FT </item>
// <item> SFDITEM_FIELD__RTC_CTRL_X32KMD </item>
// <item> SFDITEM_FIELD__RTC_CTRL_WE </item>
// </rtree>
//
// ----------------------------- Register Item Address: RTC_TRIM --------------------------------
// SVD Line: 5685
unsigned int RTC_TRIM __AT (0x40006014);
// -------------------------------- Field Item: RTC_TRIM_TRIM -----------------------------------
// SVD Line: 5691
// <item> SFDITEM_FIELD__RTC_TRIM_TRIM
// <name> TRIM </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40006014) RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. </i>
// <edit>
// <loc> ( (unsigned char)((RTC_TRIM >> 0) & 0xFF), ((RTC_TRIM = (RTC_TRIM & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Field Item: RTC_TRIM_VBATTMR ----------------------------------
// SVD Line: 5697
// <item> SFDITEM_FIELD__RTC_TRIM_VBATTMR
// <name> VBATTMR </name>
// <rw>
// <i> [Bits 31..8] RW (@ 0x40006014) VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. </i>
// <edit>
// <loc> ( (unsigned int)((RTC_TRIM >> 8) & 0xFFFFFF), ((RTC_TRIM = (RTC_TRIM & ~(0xFFFFFFUL << 8 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: RTC_TRIM ------------------------------------
// SVD Line: 5685
// <rtree> SFDITEM_REG__RTC_TRIM
// <name> TRIM </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006014) RTC Trim Register. </i>
// <loc> ( (unsigned int)((RTC_TRIM >> 0) & 0xFFFFFFFF), ((RTC_TRIM = (RTC_TRIM & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__RTC_TRIM_TRIM </item>
// <item> SFDITEM_FIELD__RTC_TRIM_VBATTMR </item>
// </rtree>
//
// --------------------------- Register Item Address: RTC_OSCCTRL -------------------------------
// SVD Line: 5705
unsigned int RTC_OSCCTRL __AT (0x40006018);
// ---------------------------- Field Item: RTC_OSCCTRL_FLITER_EN -------------------------------
// SVD Line: 5711
// <item> SFDITEM_FIELD__RTC_OSCCTRL_FLITER_EN
// <name> FLITER_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40006018) RTC Oscillator Filter Enable </i>
// <check>
// <loc> ( (unsigned int) RTC_OSCCTRL ) </loc>
// <o.0..0> FLITER_EN
// </check>
// </item>
//
// ---------------------------- Field Item: RTC_OSCCTRL_IBIAS_SEL -------------------------------
// SVD Line: 5717
// <item> SFDITEM_FIELD__RTC_OSCCTRL_IBIAS_SEL
// <name> IBIAS_SEL </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40006018) \nRTC Oscillator 4X Bias Current Select\n0 : 2X = Selects 2X bias current for RTC oscillator\n1 : 4X = Selects 4X bias current for RTC oscillator </i>
// <combo>
// <loc> ( (unsigned int) RTC_OSCCTRL ) </loc>
// <o.1..1> IBIAS_SEL
// <0=> 0: 2X = Selects 2X bias current for RTC oscillator
// <1=> 1: 4X = Selects 4X bias current for RTC oscillator
// </combo>
// </item>
//
// ----------------------------- Field Item: RTC_OSCCTRL_HYST_EN --------------------------------
// SVD Line: 5735
// <item> SFDITEM_FIELD__RTC_OSCCTRL_HYST_EN
// <name> HYST_EN </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40006018) RTC Oscillator Hysteresis Buffer Enable </i>
// <check>
// <loc> ( (unsigned int) RTC_OSCCTRL ) </loc>
// <o.2..2> HYST_EN
// </check>
// </item>
//
// ---------------------------- Field Item: RTC_OSCCTRL_IBIAS_EN --------------------------------
// SVD Line: 5741
// <item> SFDITEM_FIELD__RTC_OSCCTRL_IBIAS_EN
// <name> IBIAS_EN </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40006018) RTC Oscillator Bias Current Enable </i>
// <check>
// <loc> ( (unsigned int) RTC_OSCCTRL ) </loc>
// <o.3..3> IBIAS_EN
// </check>
// </item>
//
// ----------------------------- Field Item: RTC_OSCCTRL_BYPASS ---------------------------------
// SVD Line: 5747
// <item> SFDITEM_FIELD__RTC_OSCCTRL_BYPASS
// <name> BYPASS </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40006018) RTC Crystal Bypass </i>
// <check>
// <loc> ( (unsigned int) RTC_OSCCTRL ) </loc>
// <o.4..4> BYPASS
// </check>
// </item>
//
// ----------------------------- Field Item: RTC_OSCCTRL_OUT32K ---------------------------------
// SVD Line: 5753
// <item> SFDITEM_FIELD__RTC_OSCCTRL_OUT32K
// <name> OUT32K </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40006018) RTC 32kHz Square Wave Output </i>
// <check>
// <loc> ( (unsigned int) RTC_OSCCTRL ) </loc>
// <o.5..5> OUT32K
// </check>
// </item>
//
// ------------------------------- Register RTree: RTC_OSCCTRL ----------------------------------
// SVD Line: 5705
// <rtree> SFDITEM_REG__RTC_OSCCTRL
// <name> OSCCTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40006018) RTC Oscillator Control Register. </i>
// <loc> ( (unsigned int)((RTC_OSCCTRL >> 0) & 0xFFFFFFFF), ((RTC_OSCCTRL = (RTC_OSCCTRL & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__RTC_OSCCTRL_FLITER_EN </item>
// <item> SFDITEM_FIELD__RTC_OSCCTRL_IBIAS_SEL </item>
// <item> SFDITEM_FIELD__RTC_OSCCTRL_HYST_EN </item>
// <item> SFDITEM_FIELD__RTC_OSCCTRL_IBIAS_EN </item>
// <item> SFDITEM_FIELD__RTC_OSCCTRL_BYPASS </item>
// <item> SFDITEM_FIELD__RTC_OSCCTRL_OUT32K </item>
// </rtree>
//
// ---------------------------------- Peripheral View: RTC --------------------------------------
// SVD Line: 5374
// <view> RTC
// <name> RTC </name>
// <item> SFDITEM_REG__RTC_SEC </item>
// <item> SFDITEM_REG__RTC_SSEC </item>
// <item> SFDITEM_REG__RTC_RAS </item>
// <item> SFDITEM_REG__RTC_RSSA </item>
// <item> SFDITEM_REG__RTC_CTRL </item>
// <item> SFDITEM_REG__RTC_TRIM </item>
// <item> SFDITEM_REG__RTC_OSCCTRL </item>
// </view>
//
// ---------------------------- Register Item Address: SIR_SISTAT -------------------------------
// SVD Line: 5775
unsigned int SIR_SISTAT __AT (0x40000400);
// ------------------------------ Field Item: SIR_SISTAT_MAGIC ----------------------------------
// SVD Line: 5781
// <item> SFDITEM_FIELD__SIR_SISTAT_MAGIC
// <name> MAGIC </name>
// <r>
// <i> [Bit 0] RO (@ 0x40000400) \nMagic Word Validation. This bit is set by the system initialization block following power-up.\n0 : magicNotSet = Magic word was not set (OTP has not been initialized properly).\n1 : magicSet = Magic word was set (OTP contains valid settings). </i>
// <combo>
// <loc> ( (unsigned int) SIR_SISTAT ) </loc>
// <o.0..0> MAGIC
// <0=> 0: magicNotSet = Magic word was not set (OTP has not been initialized properly).
// <1=> 1: magicSet = Magic word was set (OTP contains valid settings).
// </combo>
// </item>
//
// ------------------------------ Field Item: SIR_SISTAT_CRCERR ---------------------------------
// SVD Line: 5801
// <item> SFDITEM_FIELD__SIR_SISTAT_CRCERR
// <name> CRCERR </name>
// <r>
// <i> [Bit 1] RO (@ 0x40000400) \nCRC Error Status. This bit is set by the system initialization block following power-up.\n0 : noError = No CRC errors occurred during the read of the OTP memory block.\n1 : error = A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. </i>
// <combo>
// <loc> ( (unsigned int) SIR_SISTAT ) </loc>
// <o.1..1> CRCERR
// <0=> 0: noError = No CRC errors occurred during the read of the OTP memory block.
// <1=> 1: error = A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.
// </combo>
// </item>
//
// ------------------------------- Register RTree: SIR_SISTAT -----------------------------------
// SVD Line: 5775
// <rtree> SFDITEM_REG__SIR_SISTAT
// <name> SISTAT </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40000400) System Initialization Status Register. </i>
// <loc> ( (unsigned int)((SIR_SISTAT >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__SIR_SISTAT_MAGIC </item>
// <item> SFDITEM_FIELD__SIR_SISTAT_CRCERR </item>
// </rtree>
//
// --------------------------- Register Item Address: SIR_ERRADDR -------------------------------
// SVD Line: 5823
unsigned int SIR_ERRADDR __AT (0x40000404);
// ----------------------------- Field Item: SIR_ERRADDR_ERRADDR --------------------------------
// SVD Line: 5829
// <item> SFDITEM_FIELD__SIR_ERRADDR_ERRADDR
// <name> ERRADDR </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40000404) ERRADDR </i>
// <edit>
// <loc> ( (unsigned int)((SIR_ERRADDR >> 0) & 0xFFFFFFFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: SIR_ERRADDR ----------------------------------
// SVD Line: 5823
// <rtree> SFDITEM_REG__SIR_ERRADDR
// <name> ERRADDR </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40000404) Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). </i>
// <loc> ( (unsigned int)((SIR_ERRADDR >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__SIR_ERRADDR_ERRADDR </item>
// </rtree>
//
// ---------------------------- Register Item Address: SIR_FSTAT --------------------------------
// SVD Line: 5836
unsigned int SIR_FSTAT __AT (0x40000500);
// -------------------------------- Field Item: SIR_FSTAT_FPU -----------------------------------
// SVD Line: 5842
// <item> SFDITEM_FIELD__SIR_FSTAT_FPU
// <name> FPU </name>
// <r>
// <i> [Bit 0] RO (@ 0x40000500) \nFPU Function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.0..0> FPU
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// -------------------------------- Field Item: SIR_FSTAT_USB -----------------------------------
// SVD Line: 5858
// <item> SFDITEM_FIELD__SIR_FSTAT_USB
// <name> USB </name>
// <r>
// <i> [Bit 1] RO (@ 0x40000500) \nUSB Device.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.1..1> USB
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// -------------------------------- Field Item: SIR_FSTAT_ADC -----------------------------------
// SVD Line: 5874
// <item> SFDITEM_FIELD__SIR_FSTAT_ADC
// <name> ADC </name>
// <r>
// <i> [Bit 2] RO (@ 0x40000500) \n10-bit Sigma Delta ADC.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.2..2> ADC
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// -------------------------------- Field Item: SIR_FSTAT_XIP -----------------------------------
// SVD Line: 5890
// <item> SFDITEM_FIELD__SIR_FSTAT_XIP
// <name> XIP </name>
// <r>
// <i> [Bit 3] RO (@ 0x40000500) \nXiP function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.3..3> XIP
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// -------------------------------- Field Item: SIR_FSTAT_PBM -----------------------------------
// SVD Line: 5906
// <item> SFDITEM_FIELD__SIR_FSTAT_PBM
// <name> PBM </name>
// <r>
// <i> [Bit 4] RO (@ 0x40000500) \nPBM function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.4..4> PBM
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// -------------------------------- Field Item: SIR_FSTAT_HBC -----------------------------------
// SVD Line: 5922
// <item> SFDITEM_FIELD__SIR_FSTAT_HBC
// <name> HBC </name>
// <r>
// <i> [Bit 5] RO (@ 0x40000500) \nHBC function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.5..5> HBC
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// ------------------------------- Field Item: SIR_FSTAT_SDHC -----------------------------------
// SVD Line: 5938
// <item> SFDITEM_FIELD__SIR_FSTAT_SDHC
// <name> SDHC </name>
// <r>
// <i> [Bit 6] RO (@ 0x40000500) \nSDHC function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.6..6> SDHC
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// ------------------------------- Field Item: SIR_FSTAT_SMPHR ----------------------------------
// SVD Line: 5954
// <item> SFDITEM_FIELD__SIR_FSTAT_SMPHR
// <name> SMPHR </name>
// <r>
// <i> [Bit 7] RO (@ 0x40000500) \nSMPHR function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.7..7> SMPHR
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// ------------------------------ Field Item: SIR_FSTAT_SCACHE ----------------------------------
// SVD Line: 5970
// <item> SFDITEM_FIELD__SIR_FSTAT_SCACHE
// <name> SCACHE </name>
// <r>
// <i> [Bit 8] RO (@ 0x40000500) \nSystem Cache function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_FSTAT ) </loc>
// <o.8..8> SCACHE
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// -------------------------------- Register RTree: SIR_FSTAT -----------------------------------
// SVD Line: 5836
// <rtree> SFDITEM_REG__SIR_FSTAT
// <name> FSTAT </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40000500) funcstat register. </i>
// <loc> ( (unsigned int)((SIR_FSTAT >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__SIR_FSTAT_FPU </item>
// <item> SFDITEM_FIELD__SIR_FSTAT_USB </item>
// <item> SFDITEM_FIELD__SIR_FSTAT_ADC </item>
// <item> SFDITEM_FIELD__SIR_FSTAT_XIP </item>
// <item> SFDITEM_FIELD__SIR_FSTAT_PBM </item>
// <item> SFDITEM_FIELD__SIR_FSTAT_HBC </item>
// <item> SFDITEM_FIELD__SIR_FSTAT_SDHC </item>
// <item> SFDITEM_FIELD__SIR_FSTAT_SMPHR </item>
// <item> SFDITEM_FIELD__SIR_FSTAT_SCACHE </item>
// </rtree>
//
// ---------------------------- Register Item Address: SIR_SFSTAT -------------------------------
// SVD Line: 5988
unsigned int SIR_SFSTAT __AT (0x40000504);
// ------------------------------- Field Item: SIR_SFSTAT_TRNG ----------------------------------
// SVD Line: 5994
// <item> SFDITEM_FIELD__SIR_SFSTAT_TRNG
// <name> TRNG </name>
// <r>
// <i> [Bit 2] RO (@ 0x40000504) \nTRNG function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_SFSTAT ) </loc>
// <o.2..2> TRNG
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// ------------------------------- Field Item: SIR_SFSTAT_AES -----------------------------------
// SVD Line: 6010
// <item> SFDITEM_FIELD__SIR_SFSTAT_AES
// <name> AES </name>
// <r>
// <i> [Bit 3] RO (@ 0x40000504) \nAES function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_SFSTAT ) </loc>
// <o.3..3> AES
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// ------------------------------- Field Item: SIR_SFSTAT_SHA -----------------------------------
// SVD Line: 6026
// <item> SFDITEM_FIELD__SIR_SFSTAT_SHA
// <name> SHA </name>
// <r>
// <i> [Bit 4] RO (@ 0x40000504) \nSHA function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_SFSTAT ) </loc>
// <o.4..4> SHA
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// ------------------------------- Field Item: SIR_SFSTAT_MAA -----------------------------------
// SVD Line: 6042
// <item> SFDITEM_FIELD__SIR_SFSTAT_MAA
// <name> MAA </name>
// <r>
// <i> [Bit 5] RO (@ 0x40000504) \nMAA function.\n0 : no = no\n1 : yes = yes </i>
// <combo>
// <loc> ( (unsigned int) SIR_SFSTAT ) </loc>
// <o.5..5> MAA
// <0=> 0: no = no
// <1=> 1: yes = yes
// </combo>
// </item>
//
// ------------------------------- Register RTree: SIR_SFSTAT -----------------------------------
// SVD Line: 5988
// <rtree> SFDITEM_REG__SIR_SFSTAT
// <name> SFSTAT </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40000504) secfuncstat register. </i>
// <loc> ( (unsigned int)((SIR_SFSTAT >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__SIR_SFSTAT_TRNG </item>
// <item> SFDITEM_FIELD__SIR_SFSTAT_AES </item>
// <item> SFDITEM_FIELD__SIR_SFSTAT_SHA </item>
// <item> SFDITEM_FIELD__SIR_SFSTAT_MAA </item>
// </rtree>
//
// ---------------------------------- Peripheral View: SIR --------------------------------------
// SVD Line: 5764
// <view> SIR
// <name> SIR </name>
// <item> SFDITEM_REG__SIR_SISTAT </item>
// <item> SFDITEM_REG__SIR_ERRADDR </item>
// <item> SFDITEM_REG__SIR_FSTAT </item>
// <item> SFDITEM_REG__SIR_SFSTAT </item>
// </view>
//
// --------------------------- Register Item Address: SMON_EXTSCN -------------------------------
// SVD Line: 6073
unsigned int SMON_EXTSCN __AT (0x40004000);
// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN0 --------------------------------
// SVD Line: 6079
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN0
// <name> EXTS_EN0 </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 0.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.0..0> EXTS_EN0
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN1 --------------------------------
// SVD Line: 6097
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN1
// <name> EXTS_EN1 </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 1.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.1..1> EXTS_EN1
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN2 --------------------------------
// SVD Line: 6115
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN2
// <name> EXTS_EN2 </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 2.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.2..2> EXTS_EN2
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN3 --------------------------------
// SVD Line: 6133
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN3
// <name> EXTS_EN3 </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 3.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.3..3> EXTS_EN3
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN4 --------------------------------
// SVD Line: 6151
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN4
// <name> EXTS_EN4 </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 4.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.4..4> EXTS_EN4
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN5 --------------------------------
// SVD Line: 6169
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN5
// <name> EXTS_EN5 </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 5.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.5..5> EXTS_EN5
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_EXTSCN_EXTCNT ---------------------------------
// SVD Line: 6187
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTCNT
// <name> EXTCNT </name>
// <rw>
// <i> [Bits 20..16] RW (@ 0x40004000) External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered. </i>
// <edit>
// <loc> ( (unsigned char)((SMON_EXTSCN >> 16) & 0x1F), ((SMON_EXTSCN = (SMON_EXTSCN & ~(0x1FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: SMON_EXTSCN_EXTFRQ ---------------------------------
// SVD Line: 6193
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTFRQ
// <name> EXTFRQ </name>
// <rw>
// <i> [Bits 23..21] RW (@ 0x40004000) \nExternal Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.\n0 : freq2000Hz = Div 4 (2000Hz).\n1 : freq1000Hz = Div 8 (1000Hz).\n2 : freq500Hz = Div 16 (500Hz).\n3 : freq250Hz = Div 32 (250Hz).\n4 : freq125Hz = Div 64 (125Hz).\n5 : freq63Hz = Div 128 (63Hz).\n6 : freq31Hz = Div 256 (31Hz).\n7 : RFU = Reserved. Do not use. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.23..21> EXTFRQ
// <0=> 0: freq2000Hz = Div 4 (2000Hz).
// <1=> 1: freq1000Hz = Div 8 (1000Hz).
// <2=> 2: freq500Hz = Div 16 (500Hz).
// <3=> 3: freq250Hz = Div 32 (250Hz).
// <4=> 4: freq125Hz = Div 64 (125Hz).
// <5=> 5: freq63Hz = Div 128 (63Hz).
// <6=> 6: freq31Hz = Div 256 (31Hz).
// <7=> 7: RFU = Reserved. Do not use.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_EXTSCN_DIVCLK ---------------------------------
// SVD Line: 6241
// <item> SFDITEM_FIELD__SMON_EXTSCN_DIVCLK
// <name> DIVCLK </name>
// <rw>
// <i> [Bits 26..24] RW (@ 0x40004000) \nClock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.\n0 : div1 = Divide by 1 (8000 Hz).\n1 : div2 = Divide by 2 (4000 Hz).\n2 : div4 = Divide by 4 (2000 Hz).\n3 : div8 = Divide by 8 (1000 Hz).\n4 : div16 = Divide by 16 (500 Hz).\n5 : div32 = Divide by 32 (250 Hz).\n6 : div64 = Divide by 64 (125 Hz).\n7 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.26..24> DIVCLK
// <0=> 0: div1 = Divide by 1 (8000 Hz).
// <1=> 1: div2 = Divide by 2 (4000 Hz).
// <2=> 2: div4 = Divide by 4 (2000 Hz).
// <3=> 3: div8 = Divide by 8 (1000 Hz).
// <4=> 4: div16 = Divide by 16 (500 Hz).
// <5=> 5: div32 = Divide by 32 (250 Hz).
// <6=> 6: div64 = Divide by 64 (125 Hz).
// <7=> 7:
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_EXTSCN_BUSY ----------------------------------
// SVD Line: 6284
// <item> SFDITEM_FIELD__SMON_EXTSCN_BUSY
// <name> BUSY </name>
// <r>
// <i> [Bit 30] RO (@ 0x40004000) \nBusy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.\n0 : idle = Idle.\n1 : busy = Update in Progress. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.30..30> BUSY
// <0=> 0: idle = Idle.
// <1=> 1: busy = Update in Progress.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_EXTSCN_LOCK ----------------------------------
// SVD Line: 6303
// <item> SFDITEM_FIELD__SMON_EXTSCN_LOCK
// <name> LOCK </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40004000) \nLock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.\n0 : unlocked = Unlocked.\n1 : locked = Locked. </i>
// <combo>
// <loc> ( (unsigned int) SMON_EXTSCN ) </loc>
// <o.31..31> LOCK
// <0=> 0: unlocked = Unlocked.
// <1=> 1: locked = Locked.
// </combo>
// </item>
//
// ------------------------------- Register RTree: SMON_EXTSCN ----------------------------------
// SVD Line: 6073
// <rtree> SFDITEM_REG__SMON_EXTSCN
// <name> EXTSCN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40004000) External Sensor Control Register. </i>
// <loc> ( (unsigned int)((SMON_EXTSCN >> 0) & 0xFFFFFFFF), ((SMON_EXTSCN = (SMON_EXTSCN & ~(0x87FF003FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x87FF003F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN0 </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN1 </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN2 </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN3 </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN4 </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN5 </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTCNT </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_EXTFRQ </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_DIVCLK </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_BUSY </item>
// <item> SFDITEM_FIELD__SMON_EXTSCN_LOCK </item>
// </rtree>
//
// --------------------------- Register Item Address: SMON_INTSCN -------------------------------
// SVD Line: 6323
unsigned int SMON_INTSCN __AT (0x40004004);
// ---------------------------- Field Item: SMON_INTSCN_SHIELD_EN -------------------------------
// SVD Line: 6329
// <item> SFDITEM_FIELD__SMON_INTSCN_SHIELD_EN
// <name> SHIELD_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40004004) \nDie Shield Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.0..0> SHIELD_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_INTSCN_TEMP_EN --------------------------------
// SVD Line: 6347
// <item> SFDITEM_FIELD__SMON_INTSCN_TEMP_EN
// <name> TEMP_EN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40004004) \nTemperature Sensor Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.1..1> TEMP_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_INTSCN_VBAT_EN --------------------------------
// SVD Line: 6365
// <item> SFDITEM_FIELD__SMON_INTSCN_VBAT_EN
// <name> VBAT_EN </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40004004) \nBattery Monitor Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.2..2> VBAT_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// --------------------------- Field Item: SMON_INTSCN_LOTEMP_SEL -------------------------------
// SVD Line: 6383
// <item> SFDITEM_FIELD__SMON_INTSCN_LOTEMP_SEL
// <name> LOTEMP_SEL </name>
// <rw>
// <i> [Bit 16] RW (@ 0x40004004) \nLow Temperature Detection Select.\n0 : neg50C = -50 degrees C.\n1 : neg30C = -30 degrees C. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.16..16> LOTEMP_SEL
// <0=> 0: neg50C = -50 degrees C.
// <1=> 1: neg30C = -30 degrees C.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_INTSCN_VCORELOEN -------------------------------
// SVD Line: 6401
// <item> SFDITEM_FIELD__SMON_INTSCN_VCORELOEN
// <name> VCORELOEN </name>
// <rw>
// <i> [Bit 18] RW (@ 0x40004004) \nVCORE Undervoltage Detect Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.18..18> VCORELOEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_INTSCN_VCOREHIEN -------------------------------
// SVD Line: 6419
// <item> SFDITEM_FIELD__SMON_INTSCN_VCOREHIEN
// <name> VCOREHIEN </name>
// <rw>
// <i> [Bit 19] RW (@ 0x40004004) \nVCORE Overvoltage Detect Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.19..19> VCOREHIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_INTSCN_VDDLOEN --------------------------------
// SVD Line: 6437
// <item> SFDITEM_FIELD__SMON_INTSCN_VDDLOEN
// <name> VDDLOEN </name>
// <rw>
// <i> [Bit 20] RW (@ 0x40004004) \nVDD Undervoltage Detect Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.20..20> VDDLOEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_INTSCN_VDDHIEN --------------------------------
// SVD Line: 6455
// <item> SFDITEM_FIELD__SMON_INTSCN_VDDHIEN
// <name> VDDHIEN </name>
// <rw>
// <i> [Bit 21] RW (@ 0x40004004) \nVDD Overvoltage Detect Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.21..21> VDDHIEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_INTSCN_VGLEN ---------------------------------
// SVD Line: 6473
// <item> SFDITEM_FIELD__SMON_INTSCN_VGLEN
// <name> VGLEN </name>
// <rw>
// <i> [Bit 22] RW (@ 0x40004004) \nVoltage Glitch Detection Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.22..22> VGLEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_INTSCN_LOCK ----------------------------------
// SVD Line: 6491
// <item> SFDITEM_FIELD__SMON_INTSCN_LOCK
// <name> LOCK </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40004004) \nLock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.\n0 : unlocked = Unlocked.\n1 : locked = Locked. </i>
// <combo>
// <loc> ( (unsigned int) SMON_INTSCN ) </loc>
// <o.31..31> LOCK
// <0=> 0: unlocked = Unlocked.
// <1=> 1: locked = Locked.
// </combo>
// </item>
//
// ------------------------------- Register RTree: SMON_INTSCN ----------------------------------
// SVD Line: 6323
// <rtree> SFDITEM_REG__SMON_INTSCN
// <name> INTSCN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40004004) Internal Sensor Control Register. </i>
// <loc> ( (unsigned int)((SMON_INTSCN >> 0) & 0xFFFFFFFF), ((SMON_INTSCN = (SMON_INTSCN & ~(0x807D0007UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x807D0007) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SMON_INTSCN_SHIELD_EN </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_TEMP_EN </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_VBAT_EN </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_LOTEMP_SEL </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_VCORELOEN </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_VCOREHIEN </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_VDDLOEN </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_VDDHIEN </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_VGLEN </item>
// <item> SFDITEM_FIELD__SMON_INTSCN_LOCK </item>
// </rtree>
//
// --------------------------- Register Item Address: SMON_SECALM -------------------------------
// SVD Line: 6511
unsigned int SMON_SECALM __AT (0x40004008);
// ------------------------------- Field Item: SMON_SECALM_DRS ----------------------------------
// SVD Line: 6518
// <item> SFDITEM_FIELD__SMON_SECALM_DRS
// <name> DRS </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40004008) \nDestructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.\n0 : complete = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.0..0> DRS
// <0=> 0: complete = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECALM_KEYWIPE --------------------------------
// SVD Line: 6536
// <item> SFDITEM_FIELD__SMON_SECALM_KEYWIPE
// <name> KEYWIPE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40004008) \nKey Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.\n0 : complete = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.1..1> KEYWIPE
// <0=> 0: complete = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECALM_SHIELDF --------------------------------
// SVD Line: 6554
// <item> SFDITEM_FIELD__SMON_SECALM_SHIELDF
// <name> SHIELDF </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40004008) \nDie Shield Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.2..2> SHIELDF
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECALM_LOTEMP ---------------------------------
// SVD Line: 6572
// <item> SFDITEM_FIELD__SMON_SECALM_LOTEMP
// <name> LOTEMP </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40004008) \nLow Temperature Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.3..3> LOTEMP
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECALM_HITEMP ---------------------------------
// SVD Line: 6590
// <item> SFDITEM_FIELD__SMON_SECALM_HITEMP
// <name> HITEMP </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40004008) \nHigh Temperature Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.4..4> HITEMP
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_SECALM_BATLO ---------------------------------
// SVD Line: 6608
// <item> SFDITEM_FIELD__SMON_SECALM_BATLO
// <name> BATLO </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40004008) \nBattery Undervoltage Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.5..5> BATLO
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_SECALM_BATHI ---------------------------------
// SVD Line: 6626
// <item> SFDITEM_FIELD__SMON_SECALM_BATHI
// <name> BATHI </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40004008) \nBattery Overvoltage Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.6..6> BATHI
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_SECALM_EXTF ----------------------------------
// SVD Line: 6644
// <item> SFDITEM_FIELD__SMON_SECALM_EXTF
// <name> EXTF </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40004008) \nExternal Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.7..7> EXTF
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_SECALM_VDDLO ---------------------------------
// SVD Line: 6662
// <item> SFDITEM_FIELD__SMON_SECALM_VDDLO
// <name> VDDLO </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40004008) \nVDD Undervoltage Detect Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.8..8> VDDLO
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECALM_VCORELO --------------------------------
// SVD Line: 6680
// <item> SFDITEM_FIELD__SMON_SECALM_VCORELO
// <name> VCORELO </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40004008) \nVCORE Undervoltage Detect Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.9..9> VCORELO
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECALM_VCOREHI --------------------------------
// SVD Line: 6698
// <item> SFDITEM_FIELD__SMON_SECALM_VCOREHI
// <name> VCOREHI </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40004008) \nVCORE Overvoltage Detect Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.10..10> VCOREHI
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_SECALM_VDDHI ---------------------------------
// SVD Line: 6716
// <item> SFDITEM_FIELD__SMON_SECALM_VDDHI
// <name> VDDHI </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40004008) \nVDD Overvoltage Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.11..11> VDDHI
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------- Field Item: SMON_SECALM_VGL ----------------------------------
// SVD Line: 6734
// <item> SFDITEM_FIELD__SMON_SECALM_VGL
// <name> VGL </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40004008) \nVoltage Glitch Detection Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.12..12> VGL
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSTAT0 --------------------------------
// SVD Line: 6752
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT0
// <name> EXTSTAT0 </name>
// <rw>
// <i> [Bit 16] RW (@ 0x40004008) \nExternal Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.16..16> EXTSTAT0
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSTAT1 --------------------------------
// SVD Line: 6770
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT1
// <name> EXTSTAT1 </name>
// <rw>
// <i> [Bit 17] RW (@ 0x40004008) \nExternal Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.17..17> EXTSTAT1
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSTAT2 --------------------------------
// SVD Line: 6788
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT2
// <name> EXTSTAT2 </name>
// <rw>
// <i> [Bit 18] RW (@ 0x40004008) \nExternal Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.18..18> EXTSTAT2
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSTAT3 --------------------------------
// SVD Line: 6806
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT3
// <name> EXTSTAT3 </name>
// <rw>
// <i> [Bit 19] RW (@ 0x40004008) \nExternal Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.19..19> EXTSTAT3
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSTAT4 --------------------------------
// SVD Line: 6824
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT4
// <name> EXTSTAT4 </name>
// <rw>
// <i> [Bit 20] RW (@ 0x40004008) \nExternal Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.20..20> EXTSTAT4
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSTAT5 --------------------------------
// SVD Line: 6842
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT5
// <name> EXTSTAT5 </name>
// <rw>
// <i> [Bit 21] RW (@ 0x40004008) \nExternal Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.21..21> EXTSTAT5
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSWARN0 -------------------------------
// SVD Line: 6860
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN0
// <name> EXTSWARN0 </name>
// <rw>
// <i> [Bit 24] RW (@ 0x40004008) \nExternal Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.24..24> EXTSWARN0
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSWARN1 -------------------------------
// SVD Line: 6878
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN1
// <name> EXTSWARN1 </name>
// <rw>
// <i> [Bit 25] RW (@ 0x40004008) \nExternal Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.25..25> EXTSWARN1
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSWARN2 -------------------------------
// SVD Line: 6896
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN2
// <name> EXTSWARN2 </name>
// <rw>
// <i> [Bit 26] RW (@ 0x40004008) \nExternal Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.26..26> EXTSWARN2
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSWARN3 -------------------------------
// SVD Line: 6914
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN3
// <name> EXTSWARN3 </name>
// <rw>
// <i> [Bit 27] RW (@ 0x40004008) \nExternal Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.27..27> EXTSWARN3
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSWARN4 -------------------------------
// SVD Line: 6932
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN4
// <name> EXTSWARN4 </name>
// <rw>
// <i> [Bit 28] RW (@ 0x40004008) \nExternal Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.28..28> EXTSWARN4
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECALM_EXTSWARN5 -------------------------------
// SVD Line: 6950
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN5
// <name> EXTSWARN5 </name>
// <rw>
// <i> [Bit 29] RW (@ 0x40004008) \nExternal Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECALM ) </loc>
// <o.29..29> EXTSWARN5
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------- Register RTree: SMON_SECALM ----------------------------------
// SVD Line: 6511
// <rtree> SFDITEM_REG__SMON_SECALM
// <name> SECALM </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40004008) Security Alarm Register. </i>
// <loc> ( (unsigned int)((SMON_SECALM >> 0) & 0xFFFFFFFF), ((SMON_SECALM = (SMON_SECALM & ~(0x3F3F1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F1FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SMON_SECALM_DRS </item>
// <item> SFDITEM_FIELD__SMON_SECALM_KEYWIPE </item>
// <item> SFDITEM_FIELD__SMON_SECALM_SHIELDF </item>
// <item> SFDITEM_FIELD__SMON_SECALM_LOTEMP </item>
// <item> SFDITEM_FIELD__SMON_SECALM_HITEMP </item>
// <item> SFDITEM_FIELD__SMON_SECALM_BATLO </item>
// <item> SFDITEM_FIELD__SMON_SECALM_BATHI </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTF </item>
// <item> SFDITEM_FIELD__SMON_SECALM_VDDLO </item>
// <item> SFDITEM_FIELD__SMON_SECALM_VCORELO </item>
// <item> SFDITEM_FIELD__SMON_SECALM_VCOREHI </item>
// <item> SFDITEM_FIELD__SMON_SECALM_VDDHI </item>
// <item> SFDITEM_FIELD__SMON_SECALM_VGL </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT0 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT1 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT2 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT3 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT4 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSTAT5 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN0 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN1 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN2 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN3 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN4 </item>
// <item> SFDITEM_FIELD__SMON_SECALM_EXTSWARN5 </item>
// </rtree>
//
// --------------------------- Register Item Address: SMON_SECDIAG ------------------------------
// SVD Line: 6970
unsigned int SMON_SECDIAG __AT (0x4000400C);
// ------------------------------ Field Item: SMON_SECDIAG_BORF ---------------------------------
// SVD Line: 6978
// <item> SFDITEM_FIELD__SMON_SECDIAG_BORF
// <name> BORF </name>
// <r>
// <i> [Bit 0] RO (@ 0x4000400C) \nBattery-On-Reset Flag. This bit is set once the back up battery is conneted.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.0..0> BORF
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECDIAG_SHIELDF --------------------------------
// SVD Line: 6996
// <item> SFDITEM_FIELD__SMON_SECDIAG_SHIELDF
// <name> SHIELDF </name>
// <r>
// <i> [Bit 2] RO (@ 0x4000400C) \nDie Shield Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.2..2> SHIELDF
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECDIAG_LOTEMP --------------------------------
// SVD Line: 7014
// <item> SFDITEM_FIELD__SMON_SECDIAG_LOTEMP
// <name> LOTEMP </name>
// <r>
// <i> [Bit 3] RO (@ 0x4000400C) \nLow Temperature Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.3..3> LOTEMP
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECDIAG_HITEMP --------------------------------
// SVD Line: 7032
// <item> SFDITEM_FIELD__SMON_SECDIAG_HITEMP
// <name> HITEMP </name>
// <r>
// <i> [Bit 4] RO (@ 0x4000400C) \nHigh Temperature Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.4..4> HITEMP
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECDIAG_BATLO ---------------------------------
// SVD Line: 7050
// <item> SFDITEM_FIELD__SMON_SECDIAG_BATLO
// <name> BATLO </name>
// <r>
// <i> [Bit 5] RO (@ 0x4000400C) \nBattery Undervoltage Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.5..5> BATLO
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECDIAG_BATHI ---------------------------------
// SVD Line: 7068
// <item> SFDITEM_FIELD__SMON_SECDIAG_BATHI
// <name> BATHI </name>
// <r>
// <i> [Bit 6] RO (@ 0x4000400C) \nBattery Overvoltage Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.6..6> BATHI
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_SECDIAG_DYNF ---------------------------------
// SVD Line: 7086
// <item> SFDITEM_FIELD__SMON_SECDIAG_DYNF
// <name> DYNF </name>
// <r>
// <i> [Bit 7] RO (@ 0x4000400C) \nDynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.7..7> DYNF
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECDIAG_AESKT ---------------------------------
// SVD Line: 7104
// <item> SFDITEM_FIELD__SMON_SECDIAG_AESKT
// <name> AESKT </name>
// <r>
// <i> [Bit 8] RO (@ 0x4000400C) \nAES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.\n0 : incomplete = Key has not been transferred.\n1 : complete = Key has been transferred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.8..8> AESKT
// <0=> 0: incomplete = Key has not been transferred.
// <1=> 1: complete = Key has been transferred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT0 -------------------------------
// SVD Line: 7122
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT0
// <name> EXTSTAT0 </name>
// <r>
// <i> [Bit 16] RO (@ 0x4000400C) \nExternal Sensor 0 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.16..16> EXTSTAT0
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT1 -------------------------------
// SVD Line: 7140
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT1
// <name> EXTSTAT1 </name>
// <r>
// <i> [Bit 17] RO (@ 0x4000400C) \nExternal Sensor 1 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.17..17> EXTSTAT1
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT2 -------------------------------
// SVD Line: 7158
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT2
// <name> EXTSTAT2 </name>
// <r>
// <i> [Bit 18] RO (@ 0x4000400C) \nExternal Sensor 2 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.18..18> EXTSTAT2
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT3 -------------------------------
// SVD Line: 7176
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT3
// <name> EXTSTAT3 </name>
// <r>
// <i> [Bit 19] RO (@ 0x4000400C) \nExternal Sensor 3 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.19..19> EXTSTAT3
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT4 -------------------------------
// SVD Line: 7194
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT4
// <name> EXTSTAT4 </name>
// <r>
// <i> [Bit 20] RO (@ 0x4000400C) \nExternal Sensor 4 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.20..20> EXTSTAT4
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT5 -------------------------------
// SVD Line: 7212
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT5
// <name> EXTSTAT5 </name>
// <r>
// <i> [Bit 21] RO (@ 0x4000400C) \nExternal Sensor 5 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECDIAG ) </loc>
// <o.21..21> EXTSTAT5
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Register RTree: SMON_SECDIAG ----------------------------------
// SVD Line: 6970
// <rtree> SFDITEM_REG__SMON_SECDIAG
// <name> SECDIAG </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x4000400C) Security Diagnostic Register. </i>
// <loc> ( (unsigned int)((SMON_SECDIAG >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__SMON_SECDIAG_BORF </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_SHIELDF </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_LOTEMP </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_HITEMP </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_BATLO </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_BATHI </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_DYNF </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_AESKT </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT0 </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT1 </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT2 </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT3 </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT4 </item>
// <item> SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT5 </item>
// </rtree>
//
// ---------------------------- Register Item Address: SMON_DLRTC -------------------------------
// SVD Line: 7232
unsigned int SMON_DLRTC __AT (0x40004010);
// ------------------------------ Field Item: SMON_DLRTC_DLRTC ----------------------------------
// SVD Line: 7239
// <item> SFDITEM_FIELD__SMON_DLRTC_DLRTC
// <name> DLRTC </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40004010) DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured. </i>
// <edit>
// <loc> ( (unsigned int)((SMON_DLRTC >> 0) & 0xFFFFFFFF) ) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: SMON_DLRTC -----------------------------------
// SVD Line: 7232
// <rtree> SFDITEM_REG__SMON_DLRTC
// <name> DLRTC </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40004010) DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred. </i>
// <loc> ( (unsigned int)((SMON_DLRTC >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__SMON_DLRTC_DLRTC </item>
// </rtree>
//
// ---------------------------- Register Item Address: SMON_SECST -------------------------------
// SVD Line: 7247
unsigned int SMON_SECST __AT (0x40004034);
// ------------------------------ Field Item: SMON_SECST_EXTSRS ---------------------------------
// SVD Line: 7253
// <item> SFDITEM_FIELD__SMON_SECST_EXTSRS
// <name> EXTSRS </name>
// <r>
// <i> [Bit 0] RO (@ 0x40004034) \nExternal Sensor Control Register Status.\n0 : allowed = Access authorized.\n1 : notAllowed = Access not authorized. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECST ) </loc>
// <o.0..0> EXTSRS
// <0=> 0: allowed = Access authorized.
// <1=> 1: notAllowed = Access not authorized.
// </combo>
// </item>
//
// ------------------------------ Field Item: SMON_SECST_INTSRS ---------------------------------
// SVD Line: 7271
// <item> SFDITEM_FIELD__SMON_SECST_INTSRS
// <name> INTSRS </name>
// <r>
// <i> [Bit 1] RO (@ 0x40004034) \nInternal Sensor Control Register Status.\n0 : allowed = Access authorized.\n1 : notAllowed = Access not authorized. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECST ) </loc>
// <o.1..1> INTSRS
// <0=> 0: allowed = Access authorized.
// <1=> 1: notAllowed = Access not authorized.
// </combo>
// </item>
//
// ----------------------------- Field Item: SMON_SECST_SECALRS ---------------------------------
// SVD Line: 7289
// <item> SFDITEM_FIELD__SMON_SECST_SECALRS
// <name> SECALRS </name>
// <r>
// <i> [Bit 2] RO (@ 0x40004034) \nSecurity Alarm Register Status.\n0 : allowed = Access authorized.\n1 : notAllowed = Access not authorized. </i>
// <combo>
// <loc> ( (unsigned int) SMON_SECST ) </loc>
// <o.2..2> SECALRS
// <0=> 0: allowed = Access authorized.
// <1=> 1: notAllowed = Access not authorized.
// </combo>
// </item>
//
// ------------------------------- Register RTree: SMON_SECST -----------------------------------
// SVD Line: 7247
// <rtree> SFDITEM_REG__SMON_SECST
// <name> SECST </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40004034) Security Monitor Status Register. </i>
// <loc> ( (unsigned int)((SMON_SECST >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__SMON_SECST_EXTSRS </item>
// <item> SFDITEM_FIELD__SMON_SECST_INTSRS </item>
// <item> SFDITEM_FIELD__SMON_SECST_SECALRS </item>
// </rtree>
//
// ---------------------------------- Peripheral View: SMON -------------------------------------
// SVD Line: 6063
// <view> SMON
// <name> SMON </name>
// <item> SFDITEM_REG__SMON_EXTSCN </item>
// <item> SFDITEM_REG__SMON_INTSCN </item>
// <item> SFDITEM_REG__SMON_SECALM </item>
// <item> SFDITEM_REG__SMON_SECDIAG </item>
// <item> SFDITEM_REG__SMON_DLRTC </item>
// <item> SFDITEM_REG__SMON_SECST </item>
// </view>
//
// -------------------------- Register Item Address: SPI17Y_DATA32 ------------------------------
// SVD Line: 7326
unsigned int SPI17Y_DATA32 __AT (0x40046000);
// ----------------------------- Field Item: SPI17Y_DATA32_DATA ---------------------------------
// SVD Line: 7333
// <item> SFDITEM_FIELD__SPI17Y_DATA32_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046000) Read to pull from RX FIFO, write to put into TX FIFO. </i>
// <edit>
// <loc> ( (unsigned int)((SPI17Y_DATA32 >> 0) & 0xFFFFFFFF), ((SPI17Y_DATA32 = (SPI17Y_DATA32 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: SPI17Y_DATA32 ---------------------------------
// SVD Line: 7326
// <rtree> SFDITEM_REG__SPI17Y_DATA32
// <name> DATA32 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046000) Register for reading and writing the FIFO. </i>
// <loc> ( (unsigned int)((SPI17Y_DATA32 >> 0) & 0xFFFFFFFF), ((SPI17Y_DATA32 = (SPI17Y_DATA32 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_DATA32_DATA </item>
// </rtree>
//
// ---------------- Register Array Item Address: SPI17Y_DATA16_DATA16_DATA160 -------------------
// SVD Line: 7341
unsigned short SPI17Y_DATA16_DATA16_DATA160 __AT (0x40046000);
// ---------------------- Field Item: SPI17Y_DATA16_DATA16_DATA160_DATA -------------------------
// SVD Line: 7351
// <item> SFDITEM_FIELD__SPI17Y_DATA16_DATA16_DATA160_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x40046000) Read to pull from RX FIFO, write to put into TX FIFO. </i>
// <edit>
// <loc> ( (unsigned short)((SPI17Y_DATA16_DATA16_DATA160 >> 0) & 0xFFFF), ((SPI17Y_DATA16_DATA16_DATA160 = (SPI17Y_DATA16_DATA16_DATA160 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------- Register Array RTree: SPI17Y_DATA16_DATA16_DATA160 -----------------------
// SVD Line: 7341
// <rtree> SFDITEM_REG__SPI17Y_DATA16_DATA16_DATA160
// <name> [0] </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x40046000) Register for reading and writing the FIFO. </i>
// <loc> ( (unsigned short)((SPI17Y_DATA16_DATA16_DATA160 >> 0) & 0xFFFF), ((SPI17Y_DATA16_DATA16_DATA160 = (SPI17Y_DATA16_DATA16_DATA160 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_DATA16_DATA16_DATA160_DATA </item>
// </rtree>
//
// ---------------- Register Array Item Address: SPI17Y_DATA16_DATA16_DATA161 -------------------
// SVD Line: 7341
unsigned short SPI17Y_DATA16_DATA16_DATA161 __AT (0x40046002);
// ---------------------- Field Item: SPI17Y_DATA16_DATA16_DATA161_DATA -------------------------
// SVD Line: 7351
// <item> SFDITEM_FIELD__SPI17Y_DATA16_DATA16_DATA161_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x40046002) Read to pull from RX FIFO, write to put into TX FIFO. </i>
// <edit>
// <loc> ( (unsigned short)((SPI17Y_DATA16_DATA16_DATA161 >> 0) & 0xFFFF), ((SPI17Y_DATA16_DATA16_DATA161 = (SPI17Y_DATA16_DATA16_DATA161 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------- Register Array RTree: SPI17Y_DATA16_DATA16_DATA161 -----------------------
// SVD Line: 7341
// <rtree> SFDITEM_REG__SPI17Y_DATA16_DATA16_DATA161
// <name> [1] </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x40046002) Register for reading and writing the FIFO. </i>
// <loc> ( (unsigned short)((SPI17Y_DATA16_DATA16_DATA161 >> 0) & 0xFFFF), ((SPI17Y_DATA16_DATA16_DATA161 = (SPI17Y_DATA16_DATA16_DATA161 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_DATA16_DATA16_DATA161_DATA </item>
// </rtree>
//
// --------------------------- Register Array ITree: SPI17Y_DATA16 ------------------------------
// SVD Line: 7341
// <itree> SFDITEM_REG__SPI17Y_DATA16
// <name> DATA16 </name>
// <i> Register for reading and writing the FIFO. </i>
// <item> SFDITEM_REG__SPI17Y_DATA16_DATA16_DATA160 </item>
// <item> SFDITEM_REG__SPI17Y_DATA16_DATA16_DATA161 </item>
// </itree>
//
// ----------------- Register Array Item Address: SPI17Y_DATA8_DATA8_DATA80 ---------------------
// SVD Line: 7359
unsigned char SPI17Y_DATA8_DATA8_DATA80 __AT (0x40046000);
// ----------------------- Field Item: SPI17Y_DATA8_DATA8_DATA80_DATA ---------------------------
// SVD Line: 7369
// <item> SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA80_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046000) Read to pull from RX FIFO, write to put into TX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA80 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA80 = (SPI17Y_DATA8_DATA8_DATA80 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------- Register Array RTree: SPI17Y_DATA8_DATA8_DATA80 ------------------------
// SVD Line: 7359
// <rtree> SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA80
// <name> [0] </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046000) Register for reading and writing the FIFO. </i>
// <loc> ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA80 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA80 = (SPI17Y_DATA8_DATA8_DATA80 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA80_DATA </item>
// </rtree>
//
// ----------------- Register Array Item Address: SPI17Y_DATA8_DATA8_DATA81 ---------------------
// SVD Line: 7359
unsigned char SPI17Y_DATA8_DATA8_DATA81 __AT (0x40046001);
// ----------------------- Field Item: SPI17Y_DATA8_DATA8_DATA81_DATA ---------------------------
// SVD Line: 7369
// <item> SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA81_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046001) Read to pull from RX FIFO, write to put into TX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA81 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA81 = (SPI17Y_DATA8_DATA8_DATA81 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------- Register Array RTree: SPI17Y_DATA8_DATA8_DATA81 ------------------------
// SVD Line: 7359
// <rtree> SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA81
// <name> [1] </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046001) Register for reading and writing the FIFO. </i>
// <loc> ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA81 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA81 = (SPI17Y_DATA8_DATA8_DATA81 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA81_DATA </item>
// </rtree>
//
// ----------------- Register Array Item Address: SPI17Y_DATA8_DATA8_DATA82 ---------------------
// SVD Line: 7359
unsigned char SPI17Y_DATA8_DATA8_DATA82 __AT (0x40046002);
// ----------------------- Field Item: SPI17Y_DATA8_DATA8_DATA82_DATA ---------------------------
// SVD Line: 7369
// <item> SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA82_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046002) Read to pull from RX FIFO, write to put into TX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA82 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA82 = (SPI17Y_DATA8_DATA8_DATA82 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------- Register Array RTree: SPI17Y_DATA8_DATA8_DATA82 ------------------------
// SVD Line: 7359
// <rtree> SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA82
// <name> [2] </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046002) Register for reading and writing the FIFO. </i>
// <loc> ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA82 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA82 = (SPI17Y_DATA8_DATA8_DATA82 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA82_DATA </item>
// </rtree>
//
// ----------------- Register Array Item Address: SPI17Y_DATA8_DATA8_DATA83 ---------------------
// SVD Line: 7359
unsigned char SPI17Y_DATA8_DATA8_DATA83 __AT (0x40046003);
// ----------------------- Field Item: SPI17Y_DATA8_DATA8_DATA83_DATA ---------------------------
// SVD Line: 7369
// <item> SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA83_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046003) Read to pull from RX FIFO, write to put into TX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA83 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA83 = (SPI17Y_DATA8_DATA8_DATA83 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------- Register Array RTree: SPI17Y_DATA8_DATA8_DATA83 ------------------------
// SVD Line: 7359
// <rtree> SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA83
// <name> [3] </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046003) Register for reading and writing the FIFO. </i>
// <loc> ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA83 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA83 = (SPI17Y_DATA8_DATA8_DATA83 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA83_DATA </item>
// </rtree>
//
// --------------------------- Register Array ITree: SPI17Y_DATA8 -------------------------------
// SVD Line: 7359
// <itree> SFDITEM_REG__SPI17Y_DATA8
// <name> DATA8 </name>
// <i> Register for reading and writing the FIFO. </i>
// <item> SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA80 </item>
// <item> SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA81 </item>
// <item> SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA82 </item>
// <item> SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA83 </item>
// </itree>
//
// --------------------------- Register Item Address: SPI17Y_CTRL0 ------------------------------
// SVD Line: 7377
unsigned int SPI17Y_CTRL0 __AT (0x40046004);
// ------------------------------- Field Item: SPI17Y_CTRL0_EN ----------------------------------
// SVD Line: 7383
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_EN
// <name> EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40046004) \nSPI Enable.\n0 : dis = SPI is disabled.\n1 : en = SPI is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL0 ) </loc>
// <o.0..0> EN
// <0=> 0: dis = SPI is disabled.
// <1=> 1: en = SPI is enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPI17Y_CTRL0_MASTER --------------------------------
// SVD Line: 7401
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_MASTER
// <name> MASTER </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40046004) \nMaster Mode Enable.\n0 : dis = SPI is Slave mode.\n1 : en = SPI is Master mode. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL0 ) </loc>
// <o.1..1> MASTER
// <0=> 0: dis = SPI is Slave mode.
// <1=> 1: en = SPI is Master mode.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPI17Y_CTRL0_SS_IO ---------------------------------
// SVD Line: 7419
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_SS_IO
// <name> SS_IO </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40046004) \nSlave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.\n0 : output = Slave select 0 is output.\n1 : input = Slave Select 0 is input, only valid if MMEN=1. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL0 ) </loc>
// <o.4..4> SS_IO
// <0=> 0: output = Slave select 0 is output.
// <1=> 1: input = Slave Select 0 is input, only valid if MMEN=1.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPI17Y_CTRL0_START ---------------------------------
// SVD Line: 7437
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_START
// <name> START </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40046004) \nStart Transmit.\n0 : Reserved - do not use\n1 : start = Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL0 ) </loc>
// <o.5..5> START
// <0=> 0:
// <1=> 1: start = Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_CTRL0_SS_CTRL --------------------------------
// SVD Line: 7450
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_SS_CTRL
// <name> SS_CTRL </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40046004) \nStart Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.\n0 : DEASSERT = SPI De-asserts Slave Select at the end of a transaction.\n1 : ASSERT = SPI leaves Slave Select asserted at the end of a transaction. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL0 ) </loc>
// <o.8..8> SS_CTRL
// <0=> 0: DEASSERT = SPI De-asserts Slave Select at the end of a transaction.
// <1=> 1: ASSERT = SPI leaves Slave Select asserted at the end of a transaction.
// </combo>
// </item>
//
// ------------------------------- Field Item: SPI17Y_CTRL0_SS ----------------------------------
// SVD Line: 7468
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_SS
// <name> SS </name>
// <rw>
// <i> [Bits 19..16] RW (@ 0x40046004) \nSlave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.\n0 : Reserved - do not use\n1 : SS0 = SS0 is selected.\n2 : SS1 = SS1 is selected.\n3 : Reserved - do not use\n4 : SS2 = SS2 is selected.\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : SS3 = SS3 is selected.\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL0 ) </loc>
// <o.19..16> SS
// <0=> 0:
// <1=> 1: SS0 = SS0 is selected.
// <2=> 2: SS1 = SS1 is selected.
// <3=> 3:
// <4=> 4: SS2 = SS2 is selected.
// <5=> 5:
// <6=> 6:
// <7=> 7:
// <8=> 8: SS3 = SS3 is selected.
// <9=> 9:
// <10=> 10:
// <11=> 11:
// <12=> 12:
// <13=> 13:
// <14=> 14:
// <15=> 15:
// </combo>
// </item>
//
// ------------------------------ Register RTree: SPI17Y_CTRL0 ----------------------------------
// SVD Line: 7377
// <rtree> SFDITEM_REG__SPI17Y_CTRL0
// <name> CTRL0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046004) Register for controlling SPI peripheral. </i>
// <loc> ( (unsigned int)((SPI17Y_CTRL0 >> 0) & 0xFFFFFFFF), ((SPI17Y_CTRL0 = (SPI17Y_CTRL0 & ~(0xF0133UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0133) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_EN </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_MASTER </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_SS_IO </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_START </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_SS_CTRL </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL0_SS </item>
// </rtree>
//
// --------------------------- Register Item Address: SPI17Y_CTRL1 ------------------------------
// SVD Line: 7498
unsigned int SPI17Y_CTRL1 __AT (0x40046008);
// -------------------------- Field Item: SPI17Y_CTRL1_TX_NUM_CHAR ------------------------------
// SVD Line: 7504
// <item> SFDITEM_FIELD__SPI17Y_CTRL1_TX_NUM_CHAR
// <name> TX_NUM_CHAR </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x40046008) Nubmer of Characters to transmit. </i>
// <edit>
// <loc> ( (unsigned short)((SPI17Y_CTRL1 >> 0) & 0xFFFF), ((SPI17Y_CTRL1 = (SPI17Y_CTRL1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------- Field Item: SPI17Y_CTRL1_RX_NUM_CHAR ------------------------------
// SVD Line: 7510
// <item> SFDITEM_FIELD__SPI17Y_CTRL1_RX_NUM_CHAR
// <name> RX_NUM_CHAR </name>
// <rw>
// <i> [Bits 31..16] RW (@ 0x40046008) Nubmer of Characters to receive. </i>
// <edit>
// <loc> ( (unsigned short)((SPI17Y_CTRL1 >> 16) & 0xFFFF), ((SPI17Y_CTRL1 = (SPI17Y_CTRL1 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: SPI17Y_CTRL1 ----------------------------------
// SVD Line: 7498
// <rtree> SFDITEM_REG__SPI17Y_CTRL1
// <name> CTRL1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046008) Register for controlling SPI peripheral. </i>
// <loc> ( (unsigned int)((SPI17Y_CTRL1 >> 0) & 0xFFFFFFFF), ((SPI17Y_CTRL1 = (SPI17Y_CTRL1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_CTRL1_TX_NUM_CHAR </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL1_RX_NUM_CHAR </item>
// </rtree>
//
// --------------------------- Register Item Address: SPI17Y_CTRL2 ------------------------------
// SVD Line: 7518
unsigned int SPI17Y_CTRL2 __AT (0x4004600C);
// ------------------------------ Field Item: SPI17Y_CTRL2_CPHA ---------------------------------
// SVD Line: 7524
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_CPHA
// <name> CPHA </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4004600C) \nClock Phase.\n0 : Rising_Edge = Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2\n1 : Falling_Edge = Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL2 ) </loc>
// <o.0..0> CPHA
// <0=> 0: Rising_Edge = Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2
// <1=> 1: Falling_Edge = Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3
// </combo>
// </item>
//
// ------------------------------ Field Item: SPI17Y_CTRL2_CPOL ---------------------------------
// SVD Line: 7542
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_CPOL
// <name> CPOL </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4004600C) \nClock Polarity.\n0 : Normal = Normal Clock. Use when in SPI Mode 0 and Mode 1\n1 : Inverted = Inverted Clock. Use when in SPI Mode 2 and Mode 3 </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL2 ) </loc>
// <o.1..1> CPOL
// <0=> 0: Normal = Normal Clock. Use when in SPI Mode 0 and Mode 1
// <1=> 1: Inverted = Inverted Clock. Use when in SPI Mode 2 and Mode 3
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_CTRL2_SCLK_INV -------------------------------
// SVD Line: 7560
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_SCLK_INV
// <name> SCLK_INV </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4004600C) Reserved - Must Always Be Cleared to 0. </i>
// <check>
// <loc> ( (unsigned int) SPI17Y_CTRL2 ) </loc>
// <o.4..4> SCLK_INV
// </check>
// </item>
//
// ---------------------------- Field Item: SPI17Y_CTRL2_NUMBITS --------------------------------
// SVD Line: 7566
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_NUMBITS
// <name> NUMBITS </name>
// <rw>
// <i> [Bits 11..8] RW (@ 0x4004600C) \nNumber of Bits per character.\n0 : 0 = 16 bits per character.\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : Reserved - do not use\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL2 ) </loc>
// <o.11..8> NUMBITS
// <0=> 0: 0 = 16 bits per character.
// <1=> 1:
// <2=> 2:
// <3=> 3:
// <4=> 4:
// <5=> 5:
// <6=> 6:
// <7=> 7:
// <8=> 8:
// <9=> 9:
// <10=> 10:
// <11=> 11:
// <12=> 12:
// <13=> 13:
// <14=> 14:
// <15=> 15:
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_CTRL2_DATA_WIDTH ------------------------------
// SVD Line: 7579
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_DATA_WIDTH
// <name> DATA_WIDTH </name>
// <rw>
// <i> [Bits 13..12] RW (@ 0x4004600C) \nSPI Data width.\n0 : Mono = 1 data pin.\n1 : Dual = 2 data pins.\n2 : Quad = 4 data pins.\n3 : Reserved - do not use </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL2 ) </loc>
// <o.13..12> DATA_WIDTH
// <0=> 0: Mono = 1 data pin.
// <1=> 1: Dual = 2 data pins.
// <2=> 2: Quad = 4 data pins.
// <3=> 3:
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_CTRL2_THREE_WIRE ------------------------------
// SVD Line: 7602
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_THREE_WIRE
// <name> THREE_WIRE </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4004600C) \nThree Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.\n0 : dis = Use four wire mode (Mono only).\n1 : en = Use three wire mode. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_CTRL2 ) </loc>
// <o.15..15> THREE_WIRE
// <0=> 0: dis = Use four wire mode (Mono only).
// <1=> 1: en = Use three wire mode.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPI17Y_CTRL2_SS_POL --------------------------------
// SVD Line: 7620
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_SS_POL
// <name> SS_POL </name>
// <rw>
// <i> [Bits 23..16] RW (@ 0x4004600C) Slave Select Polarity, each Slave Select can have unique polarity. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_CTRL2 >> 16) & 0xFF), ((SPI17Y_CTRL2 = (SPI17Y_CTRL2 & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: SPI17Y_CTRL2_SRPOL ---------------------------------
// SVD Line: 7648
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_SRPOL
// <name> SRPOL </name>
// <rw>
// <i> [Bits 31..24] RW (@ 0x4004600C) Slave Ready Polarity, each Slave Ready can have unique polarity. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_CTRL2 >> 24) & 0xFF), ((SPI17Y_CTRL2 = (SPI17Y_CTRL2 & ~(0xFFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 24 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: SPI17Y_CTRL2 ----------------------------------
// SVD Line: 7518
// <rtree> SFDITEM_REG__SPI17Y_CTRL2
// <name> CTRL2 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4004600C) Register for controlling SPI peripheral. </i>
// <loc> ( (unsigned int)((SPI17Y_CTRL2 >> 0) & 0xFFFFFFFF), ((SPI17Y_CTRL2 = (SPI17Y_CTRL2 & ~(0xFFFFBF13UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFBF13) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_CPHA </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_CPOL </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_SCLK_INV </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_NUMBITS </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_DATA_WIDTH </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_THREE_WIRE </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_SS_POL </item>
// <item> SFDITEM_FIELD__SPI17Y_CTRL2_SRPOL </item>
// </rtree>
//
// -------------------------- Register Item Address: SPI17Y_SS_TIME -----------------------------
// SVD Line: 7698
unsigned int SPI17Y_SS_TIME __AT (0x40046010);
// ----------------------------- Field Item: SPI17Y_SS_TIME_PRE ---------------------------------
// SVD Line: 7704
// <item> SFDITEM_FIELD__SPI17Y_SS_TIME_PRE
// <name> PRE </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046010) Slave Select Pre delay 1. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_SS_TIME >> 0) & 0xFF), ((SPI17Y_SS_TIME = (SPI17Y_SS_TIME & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: SPI17Y_SS_TIME_POST --------------------------------
// SVD Line: 7717
// <item> SFDITEM_FIELD__SPI17Y_SS_TIME_POST
// <name> POST </name>
// <rw>
// <i> [Bits 15..8] RW (@ 0x40046010) Slave Select Post delay 2. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_SS_TIME >> 8) & 0xFF), ((SPI17Y_SS_TIME = (SPI17Y_SS_TIME & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: SPI17Y_SS_TIME_INACT --------------------------------
// SVD Line: 7730
// <item> SFDITEM_FIELD__SPI17Y_SS_TIME_INACT
// <name> INACT </name>
// <rw>
// <i> [Bits 23..16] RW (@ 0x40046010) Slave Select Inactive delay. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_SS_TIME >> 16) & 0xFF), ((SPI17Y_SS_TIME = (SPI17Y_SS_TIME & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register RTree: SPI17Y_SS_TIME ---------------------------------
// SVD Line: 7698
// <rtree> SFDITEM_REG__SPI17Y_SS_TIME
// <name> SS_TIME </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046010) Register for controlling SPI peripheral/Slave Select Timing. </i>
// <loc> ( (unsigned int)((SPI17Y_SS_TIME >> 0) & 0xFFFFFFFF), ((SPI17Y_SS_TIME = (SPI17Y_SS_TIME & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_SS_TIME_PRE </item>
// <item> SFDITEM_FIELD__SPI17Y_SS_TIME_POST </item>
// <item> SFDITEM_FIELD__SPI17Y_SS_TIME_INACT </item>
// </rtree>
//
// -------------------------- Register Item Address: SPI17Y_CLK_CFG -----------------------------
// SVD Line: 7745
unsigned int SPI17Y_CLK_CFG __AT (0x40046014);
// ------------------------------ Field Item: SPI17Y_CLK_CFG_LO ---------------------------------
// SVD Line: 7751
// <item> SFDITEM_FIELD__SPI17Y_CLK_CFG_LO
// <name> LO </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40046014) Low duty cycle control. In timer mode, reload[7:0]. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_CLK_CFG >> 0) & 0xFF), ((SPI17Y_CLK_CFG = (SPI17Y_CLK_CFG & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Field Item: SPI17Y_CLK_CFG_HI ---------------------------------
// SVD Line: 7764
// <item> SFDITEM_FIELD__SPI17Y_CLK_CFG_HI
// <name> HI </name>
// <rw>
// <i> [Bits 15..8] RW (@ 0x40046014) High duty cycle control. In timer mode, reload[15:8]. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_CLK_CFG >> 8) & 0xFF), ((SPI17Y_CLK_CFG = (SPI17Y_CLK_CFG & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: SPI17Y_CLK_CFG_SCALE --------------------------------
// SVD Line: 7777
// <item> SFDITEM_FIELD__SPI17Y_CLK_CFG_SCALE
// <name> SCALE </name>
// <rw>
// <i> [Bits 19..16] RW (@ 0x40046014) System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_CLK_CFG >> 16) & 0xF), ((SPI17Y_CLK_CFG = (SPI17Y_CLK_CFG & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register RTree: SPI17Y_CLK_CFG ---------------------------------
// SVD Line: 7745
// <rtree> SFDITEM_REG__SPI17Y_CLK_CFG
// <name> CLK_CFG </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046014) Register for controlling SPI clock rate. </i>
// <loc> ( (unsigned int)((SPI17Y_CLK_CFG >> 0) & 0xFFFFFFFF), ((SPI17Y_CLK_CFG = (SPI17Y_CLK_CFG & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_CLK_CFG_LO </item>
// <item> SFDITEM_FIELD__SPI17Y_CLK_CFG_HI </item>
// <item> SFDITEM_FIELD__SPI17Y_CLK_CFG_SCALE </item>
// </rtree>
//
// ---------------------------- Register Item Address: SPI17Y_DMA -------------------------------
// SVD Line: 7785
unsigned int SPI17Y_DMA __AT (0x4004601C);
// -------------------------- Field Item: SPI17Y_DMA_TX_FIFO_LEVEL ------------------------------
// SVD Line: 7791
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_LEVEL
// <name> TX_FIFO_LEVEL </name>
// <rw>
// <i> [Bits 4..0] RW (@ 0x4004601C) Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_DMA >> 0) & 0x1F), ((SPI17Y_DMA = (SPI17Y_DMA & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: SPI17Y_DMA_TX_FIFO_EN -------------------------------
// SVD Line: 7797
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_EN
// <name> TX_FIFO_EN </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4004601C) \nTransmit FIFO enabled for SPI transactions.\n0 : dis = Transmit FIFO is not enabled.\n1 : en = Transmit FIFO is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_DMA ) </loc>
// <o.6..6> TX_FIFO_EN
// <0=> 0: dis = Transmit FIFO is not enabled.
// <1=> 1: en = Transmit FIFO is enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: SPI17Y_DMA_TX_FIFO_CLEAR ------------------------------
// SVD Line: 7815
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_CLEAR
// <name> TX_FIFO_CLEAR </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4004601C) \nClear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. .\n0 : Reserved - do not use\n1 : CLEAR = Clear the Transmit FIFO, clears any pending TX FIFO status. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_DMA ) </loc>
// <o.7..7> TX_FIFO_CLEAR
// <0=> 0:
// <1=> 1: CLEAR = Clear the Transmit FIFO, clears any pending TX FIFO status.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_DMA_TX_FIFO_CNT -------------------------------
// SVD Line: 7830
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_CNT
// <name> TX_FIFO_CNT </name>
// <r>
// <i> [Bits 13..8] RO (@ 0x4004601C) Count of entries in TX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_DMA >> 8) & 0x3F) ) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: SPI17Y_DMA_TX_DMA_EN --------------------------------
// SVD Line: 7837
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_DMA_EN
// <name> TX_DMA_EN </name>
// <rw>
// <i> [Bit 15] RW (@ 0x4004601C) \nTX DMA Enable.\n0 : DIS = TX DMA requests are disabled, andy pending DMA requests are cleared.\n1 : en = TX DMA requests are enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_DMA ) </loc>
// <o.15..15> TX_DMA_EN
// <0=> 0: DIS = TX DMA requests are disabled, andy pending DMA requests are cleared.
// <1=> 1: en = TX DMA requests are enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: SPI17Y_DMA_RX_FIFO_LEVEL ------------------------------
// SVD Line: 7855
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_LEVEL
// <name> RX_FIFO_LEVEL </name>
// <rw>
// <i> [Bits 20..16] RW (@ 0x4004601C) Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_DMA >> 16) & 0x1F), ((SPI17Y_DMA = (SPI17Y_DMA & ~(0x1FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: SPI17Y_DMA_RX_FIFO_EN -------------------------------
// SVD Line: 7861
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_EN
// <name> RX_FIFO_EN </name>
// <rw>
// <i> [Bit 22] RW (@ 0x4004601C) \nReceive FIFO enabled for SPI transactions.\n0 : DIS = Receive FIFO is not enabled.\n1 : en = Receive FIFO is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_DMA ) </loc>
// <o.22..22> RX_FIFO_EN
// <0=> 0: DIS = Receive FIFO is not enabled.
// <1=> 1: en = Receive FIFO is enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: SPI17Y_DMA_RX_FIFO_CLEAR ------------------------------
// SVD Line: 7879
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_CLEAR
// <name> RX_FIFO_CLEAR </name>
// <rw>
// <i> [Bit 23] RW (@ 0x4004601C) \nClear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.\n0 : Reserved - do not use\n1 : CLEAR = Clear the Receive FIFO, clears any pending RX FIFO status. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_DMA ) </loc>
// <o.23..23> RX_FIFO_CLEAR
// <0=> 0:
// <1=> 1: CLEAR = Clear the Receive FIFO, clears any pending RX FIFO status.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_DMA_RX_FIFO_CNT -------------------------------
// SVD Line: 7892
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_CNT
// <name> RX_FIFO_CNT </name>
// <r>
// <i> [Bits 29..24] RO (@ 0x4004601C) Count of entries in RX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((SPI17Y_DMA >> 24) & 0x3F) ) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: SPI17Y_DMA_RX_DMA_EN --------------------------------
// SVD Line: 7899
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_DMA_EN
// <name> RX_DMA_EN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x4004601C) \nRX DMA Enable.\n0 : dis = RX DMA requests are disabled, any pending DMA requests are cleared.\n1 : en = RX DMA requests are enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_DMA ) </loc>
// <o.31..31> RX_DMA_EN
// <0=> 0: dis = RX DMA requests are disabled, any pending DMA requests are cleared.
// <1=> 1: en = RX DMA requests are enabled.
// </combo>
// </item>
//
// ------------------------------- Register RTree: SPI17Y_DMA -----------------------------------
// SVD Line: 7785
// <rtree> SFDITEM_REG__SPI17Y_DMA
// <name> DMA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4004601C) Register for controlling DMA. </i>
// <loc> ( (unsigned int)((SPI17Y_DMA >> 0) & 0xFFFFFFFF), ((SPI17Y_DMA = (SPI17Y_DMA & ~(0x80DF80DFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80DF80DF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_LEVEL </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_EN </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_CLEAR </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_CNT </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_TX_DMA_EN </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_LEVEL </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_EN </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_CLEAR </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_CNT </item>
// <item> SFDITEM_FIELD__SPI17Y_DMA_RX_DMA_EN </item>
// </rtree>
//
// -------------------------- Register Item Address: SPI17Y_INT_FL ------------------------------
// SVD Line: 7919
unsigned int SPI17Y_INT_FL __AT (0x40046020);
// --------------------------- Field Item: SPI17Y_INT_FL_TX_THRESH ------------------------------
// SVD Line: 7925
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40046020) \nTX FIFO Threshold Crossed.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.0..0> TX_THRESH
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_INT_FL_TX_EMPTY -------------------------------
// SVD Line: 7938
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_TX_EMPTY
// <name> TX_EMPTY </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40046020) \nTX FIFO Empty.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.1..1> TX_EMPTY
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_INT_FL_RX_THRESH ------------------------------
// SVD Line: 7951
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40046020) \nRX FIFO Threshold Crossed.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.2..2> RX_THRESH
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_FL_RX_FULL -------------------------------
// SVD Line: 7964
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_RX_FULL
// <name> RX_FULL </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40046020) \nRX FIFO FULL.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.3..3> RX_FULL
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPI17Y_INT_FL_SSA ---------------------------------
// SVD Line: 7977
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_SSA
// <name> SSA </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40046020) \nSlave Select Asserted.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.4..4> SSA
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPI17Y_INT_FL_SSD ---------------------------------
// SVD Line: 7990
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_SSD
// <name> SSD </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40046020) \nSlave Select Deasserted.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.5..5> SSD
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPI17Y_INT_FL_FAULT --------------------------------
// SVD Line: 8003
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_FAULT
// <name> FAULT </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40046020) \nMulti-Master Mode Fault.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.8..8> FAULT
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPI17Y_INT_FL_ABORT --------------------------------
// SVD Line: 8016
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_ABORT
// <name> ABORT </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40046020) \nSlave Abort Detected.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.9..9> ABORT
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_FL_M_DONE --------------------------------
// SVD Line: 8029
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_M_DONE
// <name> M_DONE </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40046020) \nMaster Done, set when SPI Master has completed any transactions.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.11..11> M_DONE
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_FL_TX_OVR --------------------------------
// SVD Line: 8042
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_TX_OVR
// <name> TX_OVR </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40046020) \nTransmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.12..12> TX_OVR
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_FL_TX_UND --------------------------------
// SVD Line: 8055
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_TX_UND
// <name> TX_UND </name>
// <rw>
// <i> [Bit 13] RW (@ 0x40046020) \nTransmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.13..13> TX_UND
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_FL_RX_OVR --------------------------------
// SVD Line: 8068
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_RX_OVR
// <name> RX_OVR </name>
// <rw>
// <i> [Bit 14] RW (@ 0x40046020) \nReceive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.14..14> RX_OVR
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_FL_RX_UND --------------------------------
// SVD Line: 8081
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_RX_UND
// <name> RX_UND </name>
// <rw>
// <i> [Bit 15] RW (@ 0x40046020) \nReceive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_FL ) </loc>
// <o.15..15> RX_UND
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ------------------------------ Register RTree: SPI17Y_INT_FL ---------------------------------
// SVD Line: 7919
// <rtree> SFDITEM_REG__SPI17Y_INT_FL
// <name> INT_FL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046020) Register for reading and clearing interrupt flags. All bits are write 1 to clear. </i>
// <loc> ( (unsigned int)((SPI17Y_INT_FL >> 0) & 0xFFFFFFFF), ((SPI17Y_INT_FL = (SPI17Y_INT_FL & ~(0xFB3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB3F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_TX_THRESH </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_TX_EMPTY </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_RX_THRESH </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_RX_FULL </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_SSA </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_SSD </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_FAULT </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_ABORT </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_M_DONE </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_TX_OVR </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_TX_UND </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_RX_OVR </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_FL_RX_UND </item>
// </rtree>
//
// -------------------------- Register Item Address: SPI17Y_INT_EN ------------------------------
// SVD Line: 8096
unsigned int SPI17Y_INT_EN __AT (0x40046024);
// --------------------------- Field Item: SPI17Y_INT_EN_TX_THRESH ------------------------------
// SVD Line: 8102
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40046024) \nTX FIFO Threshold interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.0..0> TX_THRESH
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_INT_EN_TX_EMPTY -------------------------------
// SVD Line: 8120
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_TX_EMPTY
// <name> TX_EMPTY </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40046024) \nTX FIFO Empty interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.1..1> TX_EMPTY
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_INT_EN_RX_THRESH ------------------------------
// SVD Line: 8138
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40046024) \nRX FIFO Threshold Crossed interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.2..2> RX_THRESH
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_EN_RX_FULL -------------------------------
// SVD Line: 8156
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_RX_FULL
// <name> RX_FULL </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40046024) \nRX FIFO FULL interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.3..3> RX_FULL
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPI17Y_INT_EN_SSA ---------------------------------
// SVD Line: 8174
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_SSA
// <name> SSA </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40046024) \nSlave Select Asserted interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.4..4> SSA
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPI17Y_INT_EN_SSD ---------------------------------
// SVD Line: 8192
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_SSD
// <name> SSD </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40046024) \nSlave Select Deasserted interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.5..5> SSD
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPI17Y_INT_EN_FAULT --------------------------------
// SVD Line: 8210
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_FAULT
// <name> FAULT </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40046024) \nMulti-Master Mode Fault interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.8..8> FAULT
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPI17Y_INT_EN_ABORT --------------------------------
// SVD Line: 8228
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_ABORT
// <name> ABORT </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40046024) \nSlave Abort Detected interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.9..9> ABORT
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_EN_M_DONE --------------------------------
// SVD Line: 8246
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_M_DONE
// <name> M_DONE </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40046024) \nMaster Done interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.11..11> M_DONE
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_EN_TX_OVR --------------------------------
// SVD Line: 8264
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_TX_OVR
// <name> TX_OVR </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40046024) \nTransmit FIFO Overrun interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.12..12> TX_OVR
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_EN_TX_UND --------------------------------
// SVD Line: 8282
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_TX_UND
// <name> TX_UND </name>
// <rw>
// <i> [Bit 13] RW (@ 0x40046024) \nTransmit FIFO Underrun interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.13..13> TX_UND
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_EN_RX_OVR --------------------------------
// SVD Line: 8300
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_RX_OVR
// <name> RX_OVR </name>
// <rw>
// <i> [Bit 14] RW (@ 0x40046024) \nReceive FIFO Overrun interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.14..14> RX_OVR
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: SPI17Y_INT_EN_RX_UND --------------------------------
// SVD Line: 8318
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_RX_UND
// <name> RX_UND </name>
// <rw>
// <i> [Bit 15] RW (@ 0x40046024) \nReceive FIFO Underrun interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_INT_EN ) </loc>
// <o.15..15> RX_UND
// <0=> 0: dis = Interrupt is disabled.
// <1=> 1: en = Interrupt is enabled.
// </combo>
// </item>
//
// ------------------------------ Register RTree: SPI17Y_INT_EN ---------------------------------
// SVD Line: 8096
// <rtree> SFDITEM_REG__SPI17Y_INT_EN
// <name> INT_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046024) Register for enabling interrupts. </i>
// <loc> ( (unsigned int)((SPI17Y_INT_EN >> 0) & 0xFFFFFFFF), ((SPI17Y_INT_EN = (SPI17Y_INT_EN & ~(0xFB3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB3F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_TX_THRESH </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_TX_EMPTY </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_RX_THRESH </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_RX_FULL </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_SSA </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_SSD </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_FAULT </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_ABORT </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_M_DONE </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_TX_OVR </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_TX_UND </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_RX_OVR </item>
// <item> SFDITEM_FIELD__SPI17Y_INT_EN_RX_UND </item>
// </rtree>
//
// -------------------------- Register Item Address: SPI17Y_WAKE_FL -----------------------------
// SVD Line: 8338
unsigned int SPI17Y_WAKE_FL __AT (0x40046028);
// -------------------------- Field Item: SPI17Y_WAKE_FL_TX_THRESH ------------------------------
// SVD Line: 8344
// <item> SFDITEM_FIELD__SPI17Y_WAKE_FL_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40046028) \nWake on TX FIFO Threshold Crossed.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_WAKE_FL ) </loc>
// <o.0..0> TX_THRESH
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_WAKE_FL_TX_EMPTY ------------------------------
// SVD Line: 8357
// <item> SFDITEM_FIELD__SPI17Y_WAKE_FL_TX_EMPTY
// <name> TX_EMPTY </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40046028) \nWake on TX FIFO Empty.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_WAKE_FL ) </loc>
// <o.1..1> TX_EMPTY
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// -------------------------- Field Item: SPI17Y_WAKE_FL_RX_THRESH ------------------------------
// SVD Line: 8370
// <item> SFDITEM_FIELD__SPI17Y_WAKE_FL_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40046028) \nWake on RX FIFO Threshold Crossed.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_WAKE_FL ) </loc>
// <o.2..2> RX_THRESH
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_WAKE_FL_RX_FULL -------------------------------
// SVD Line: 8383
// <item> SFDITEM_FIELD__SPI17Y_WAKE_FL_RX_FULL
// <name> RX_FULL </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40046028) \nWake on RX FIFO Full.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_WAKE_FL ) </loc>
// <o.3..3> RX_FULL
// <0=> 0:
// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag.
// </combo>
// </item>
//
// ----------------------------- Register RTree: SPI17Y_WAKE_FL ---------------------------------
// SVD Line: 8338
// <rtree> SFDITEM_REG__SPI17Y_WAKE_FL
// <name> WAKE_FL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40046028) Register for wake up flags. All bits in this register are write 1 to clear. </i>
// <loc> ( (unsigned int)((SPI17Y_WAKE_FL >> 0) & 0xFFFFFFFF), ((SPI17Y_WAKE_FL = (SPI17Y_WAKE_FL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_WAKE_FL_TX_THRESH </item>
// <item> SFDITEM_FIELD__SPI17Y_WAKE_FL_TX_EMPTY </item>
// <item> SFDITEM_FIELD__SPI17Y_WAKE_FL_RX_THRESH </item>
// <item> SFDITEM_FIELD__SPI17Y_WAKE_FL_RX_FULL </item>
// </rtree>
//
// -------------------------- Register Item Address: SPI17Y_WAKE_EN -----------------------------
// SVD Line: 8398
unsigned int SPI17Y_WAKE_EN __AT (0x4004602C);
// -------------------------- Field Item: SPI17Y_WAKE_EN_TX_THRESH ------------------------------
// SVD Line: 8404
// <item> SFDITEM_FIELD__SPI17Y_WAKE_EN_TX_THRESH
// <name> TX_THRESH </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4004602C) \nWake on TX FIFO Threshold Crossed Enable.\n0 : dis = Wakeup source disabled.\n1 : en = Wakeup source enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_WAKE_EN ) </loc>
// <o.0..0> TX_THRESH
// <0=> 0: dis = Wakeup source disabled.
// <1=> 1: en = Wakeup source enabled.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_WAKE_EN_TX_EMPTY ------------------------------
// SVD Line: 8422
// <item> SFDITEM_FIELD__SPI17Y_WAKE_EN_TX_EMPTY
// <name> TX_EMPTY </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4004602C) \nWake on TX FIFO Empty Enable.\n0 : dis = Wakeup source disabled.\n1 : en = Wakeup source enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_WAKE_EN ) </loc>
// <o.1..1> TX_EMPTY
// <0=> 0: dis = Wakeup source disabled.
// <1=> 1: en = Wakeup source enabled.
// </combo>
// </item>
//
// -------------------------- Field Item: SPI17Y_WAKE_EN_RX_THRESH ------------------------------
// SVD Line: 8440
// <item> SFDITEM_FIELD__SPI17Y_WAKE_EN_RX_THRESH
// <name> RX_THRESH </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4004602C) \nWake on RX FIFO Threshold Crossed Enable.\n0 : dis = Wakeup source disabled.\n1 : en = Wakeup source enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_WAKE_EN ) </loc>
// <o.2..2> RX_THRESH
// <0=> 0: dis = Wakeup source disabled.
// <1=> 1: en = Wakeup source enabled.
// </combo>
// </item>
//
// --------------------------- Field Item: SPI17Y_WAKE_EN_RX_FULL -------------------------------
// SVD Line: 8458
// <item> SFDITEM_FIELD__SPI17Y_WAKE_EN_RX_FULL
// <name> RX_FULL </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4004602C) \nWake on RX FIFO Full Enable.\n0 : dis = Wakeup source disabled.\n1 : en = Wakeup source enabled. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_WAKE_EN ) </loc>
// <o.3..3> RX_FULL
// <0=> 0: dis = Wakeup source disabled.
// <1=> 1: en = Wakeup source enabled.
// </combo>
// </item>
//
// ----------------------------- Register RTree: SPI17Y_WAKE_EN ---------------------------------
// SVD Line: 8398
// <rtree> SFDITEM_REG__SPI17Y_WAKE_EN
// <name> WAKE_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4004602C) Register for wake up enable. </i>
// <loc> ( (unsigned int)((SPI17Y_WAKE_EN >> 0) & 0xFFFFFFFF), ((SPI17Y_WAKE_EN = (SPI17Y_WAKE_EN & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPI17Y_WAKE_EN_TX_THRESH </item>
// <item> SFDITEM_FIELD__SPI17Y_WAKE_EN_TX_EMPTY </item>
// <item> SFDITEM_FIELD__SPI17Y_WAKE_EN_RX_THRESH </item>
// <item> SFDITEM_FIELD__SPI17Y_WAKE_EN_RX_FULL </item>
// </rtree>
//
// --------------------------- Register Item Address: SPI17Y_STAT -------------------------------
// SVD Line: 8478
unsigned int SPI17Y_STAT __AT (0x40046030);
// ------------------------------ Field Item: SPI17Y_STAT_BUSY ----------------------------------
// SVD Line: 8484
// <item> SFDITEM_FIELD__SPI17Y_STAT_BUSY
// <name> BUSY </name>
// <r>
// <i> [Bit 0] RO (@ 0x40046030) \nSPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.\n0 : not = SPI not active.\n1 : active = SPI active. </i>
// <combo>
// <loc> ( (unsigned int) SPI17Y_STAT ) </loc>
// <o.0..0> BUSY
// <0=> 0: not = SPI not active.
// <1=> 1: active = SPI active.
// </combo>
// </item>
//
// ------------------------------- Register RTree: SPI17Y_STAT ----------------------------------
// SVD Line: 8478
// <rtree> SFDITEM_REG__SPI17Y_STAT
// <name> STAT </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40046030) SPI Status register. </i>
// <loc> ( (unsigned int)((SPI17Y_STAT >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__SPI17Y_STAT_BUSY </item>
// </rtree>
//
// --------------------------------- Peripheral View: SPI17Y ------------------------------------
// SVD Line: 7312
// <view> SPI17Y
// <name> SPI17Y </name>
// <item> SFDITEM_REG__SPI17Y_DATA32 </item>
// <item> SFDITEM_REG__SPI17Y_DATA16 </item>
// <item> SFDITEM_REG__SPI17Y_DATA8 </item>
// <item> SFDITEM_REG__SPI17Y_CTRL0 </item>
// <item> SFDITEM_REG__SPI17Y_CTRL1 </item>
// <item> SFDITEM_REG__SPI17Y_CTRL2 </item>
// <item> SFDITEM_REG__SPI17Y_SS_TIME </item>
// <item> SFDITEM_REG__SPI17Y_CLK_CFG </item>
// <item> SFDITEM_REG__SPI17Y_DMA </item>
// <item> SFDITEM_REG__SPI17Y_INT_FL </item>
// <item> SFDITEM_REG__SPI17Y_INT_EN </item>
// <item> SFDITEM_REG__SPI17Y_WAKE_FL </item>
// <item> SFDITEM_REG__SPI17Y_WAKE_EN </item>
// <item> SFDITEM_REG__SPI17Y_STAT </item>
// </view>
//
// -------------------------- Register Item Address: SPIMSS_DATA16 ------------------------------
// SVD Line: 8518
unsigned short SPIMSS_DATA16 __AT (0x40018000);
// ----------------------------- Field Item: SPIMSS_DATA16_DATA ---------------------------------
// SVD Line: 8525
// <item> SFDITEM_FIELD__SPIMSS_DATA16_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x40018000) SPI data. </i>
// <edit>
// <loc> ( (unsigned short)((SPIMSS_DATA16 >> 0) & 0xFFFF), ((SPIMSS_DATA16 = (SPIMSS_DATA16 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: SPIMSS_DATA16 ---------------------------------
// SVD Line: 8518
// <rtree> SFDITEM_REG__SPIMSS_DATA16
// <name> DATA16 </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x40018000) SPI 16-bit Data Access </i>
// <loc> ( (unsigned short)((SPIMSS_DATA16 >> 0) & 0xFFFF), ((SPIMSS_DATA16 = (SPIMSS_DATA16 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_DATA16_DATA </item>
// </rtree>
//
// ----------------- Register Array Item Address: SPIMSS_DATA8_DATA8_DATA80 ---------------------
// SVD Line: 8533
unsigned char SPIMSS_DATA8_DATA8_DATA80 __AT (0x40018000);
// ----------------------- Field Item: SPIMSS_DATA8_DATA8_DATA80_DATA ---------------------------
// SVD Line: 8543
// <item> SFDITEM_FIELD__SPIMSS_DATA8_DATA8_DATA80_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40018000) SPI data. </i>
// <edit>
// <loc> ( (unsigned char)((SPIMSS_DATA8_DATA8_DATA80 >> 0) & 0xFF), ((SPIMSS_DATA8_DATA8_DATA80 = (SPIMSS_DATA8_DATA8_DATA80 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------- Register Array RTree: SPIMSS_DATA8_DATA8_DATA80 ------------------------
// SVD Line: 8533
// <rtree> SFDITEM_REG__SPIMSS_DATA8_DATA8_DATA80
// <name> [0] </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40018000) SPI Data 8-bit access </i>
// <loc> ( (unsigned char)((SPIMSS_DATA8_DATA8_DATA80 >> 0) & 0xFF), ((SPIMSS_DATA8_DATA8_DATA80 = (SPIMSS_DATA8_DATA8_DATA80 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_DATA8_DATA8_DATA80_DATA </item>
// </rtree>
//
// ----------------- Register Array Item Address: SPIMSS_DATA8_DATA8_DATA81 ---------------------
// SVD Line: 8533
unsigned char SPIMSS_DATA8_DATA8_DATA81 __AT (0x40018001);
// ----------------------- Field Item: SPIMSS_DATA8_DATA8_DATA81_DATA ---------------------------
// SVD Line: 8543
// <item> SFDITEM_FIELD__SPIMSS_DATA8_DATA8_DATA81_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40018001) SPI data. </i>
// <edit>
// <loc> ( (unsigned char)((SPIMSS_DATA8_DATA8_DATA81 >> 0) & 0xFF), ((SPIMSS_DATA8_DATA8_DATA81 = (SPIMSS_DATA8_DATA8_DATA81 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// --------------------- Register Array RTree: SPIMSS_DATA8_DATA8_DATA81 ------------------------
// SVD Line: 8533
// <rtree> SFDITEM_REG__SPIMSS_DATA8_DATA8_DATA81
// <name> [1] </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40018001) SPI Data 8-bit access </i>
// <loc> ( (unsigned char)((SPIMSS_DATA8_DATA8_DATA81 >> 0) & 0xFF), ((SPIMSS_DATA8_DATA8_DATA81 = (SPIMSS_DATA8_DATA8_DATA81 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_DATA8_DATA8_DATA81_DATA </item>
// </rtree>
//
// --------------------------- Register Array ITree: SPIMSS_DATA8 -------------------------------
// SVD Line: 8533
// <itree> SFDITEM_REG__SPIMSS_DATA8
// <name> DATA8 </name>
// <i> SPI Data 8-bit access </i>
// <item> SFDITEM_REG__SPIMSS_DATA8_DATA8_DATA80 </item>
// <item> SFDITEM_REG__SPIMSS_DATA8_DATA8_DATA81 </item>
// </itree>
//
// --------------------------- Register Item Address: SPIMSS_CTRL -------------------------------
// SVD Line: 8551
unsigned int SPIMSS_CTRL __AT (0x40018004);
// ------------------------------ Field Item: SPIMSS_CTRL_SPIEN ---------------------------------
// SVD Line: 8556
// <item> SFDITEM_FIELD__SPIMSS_CTRL_SPIEN
// <name> SPIEN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40018004) \nSPI Enable.\n0 : disable = disable\n1 : enable = enable </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_CTRL ) </loc>
// <o.0..0> SPIEN
// <0=> 0: disable = disable
// <1=> 1: enable = enable
// </combo>
// </item>
//
// ------------------------------ Field Item: SPIMSS_CTRL_MMEN ----------------------------------
// SVD Line: 8573
// <item> SFDITEM_FIELD__SPIMSS_CTRL_MMEN
// <name> MMEN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40018004) \nSPI Master Mode Enable.\n0 : slave = slave\n1 : master = master </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_CTRL ) </loc>
// <o.1..1> MMEN
// <0=> 0: slave = slave
// <1=> 1: master = master
// </combo>
// </item>
//
// ------------------------------- Field Item: SPIMSS_CTRL_WOR ----------------------------------
// SVD Line: 8590
// <item> SFDITEM_FIELD__SPIMSS_CTRL_WOR
// <name> WOR </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40018004) \nWired OR (open drain) Enable.\n0 : disable = disable\n1 : enable = enable </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_CTRL ) </loc>
// <o.2..2> WOR
// <0=> 0: disable = disable
// <1=> 1: enable = enable
// </combo>
// </item>
//
// ----------------------------- Field Item: SPIMSS_CTRL_CLKPOL ---------------------------------
// SVD Line: 8607
// <item> SFDITEM_FIELD__SPIMSS_CTRL_CLKPOL
// <name> CLKPOL </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40018004) \nClock Polarity.\n0 : idleLo = SCLK idles Low (0) after character transmission/reception.\n1 : idleHi = SCLK idles High (1) after character transmission/reception. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_CTRL ) </loc>
// <o.3..3> CLKPOL
// <0=> 0: idleLo = SCLK idles Low (0) after character transmission/reception.
// <1=> 1: idleHi = SCLK idles High (1) after character transmission/reception.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPIMSS_CTRL_PHASE ---------------------------------
// SVD Line: 8626
// <item> SFDITEM_FIELD__SPIMSS_CTRL_PHASE
// <name> PHASE </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40018004) \nPhase Select.\n0 : activeEdge = Transmit on active edge of SCLK.\n1 : inactiveEdge = Transmit on inactive edge of SCLK. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_CTRL ) </loc>
// <o.4..4> PHASE
// <0=> 0: activeEdge = Transmit on active edge of SCLK.
// <1=> 1: inactiveEdge = Transmit on inactive edge of SCLK.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPIMSS_CTRL_BIRQ ----------------------------------
// SVD Line: 8645
// <item> SFDITEM_FIELD__SPIMSS_CTRL_BIRQ
// <name> BIRQ </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40018004) \nBaud Rate Generator Timer Interrupt Request.\n0 : disable = disable\n1 : enable = enable </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_CTRL ) </loc>
// <o.5..5> BIRQ
// <0=> 0: disable = disable
// <1=> 1: enable = enable
// </combo>
// </item>
//
// ------------------------------- Field Item: SPIMSS_CTRL_STR ----------------------------------
// SVD Line: 8662
// <item> SFDITEM_FIELD__SPIMSS_CTRL_STR
// <name> STR </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40018004) \nStart SPI Interrupt.\n0 : complete = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_CTRL ) </loc>
// <o.6..6> STR
// <0=> 0: complete = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPIMSS_CTRL_IRQE ----------------------------------
// SVD Line: 8681
// <item> SFDITEM_FIELD__SPIMSS_CTRL_IRQE
// <name> IRQE </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40018004) \nInterrupt Request Enable.\n0 : disable = disable\n1 : enable = enable </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_CTRL ) </loc>
// <o.7..7> IRQE
// <0=> 0: disable = disable
// <1=> 1: enable = enable
// </combo>
// </item>
//
// ------------------------------- Register RTree: SPIMSS_CTRL ----------------------------------
// SVD Line: 8551
// <rtree> SFDITEM_REG__SPIMSS_CTRL
// <name> CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40018004) SPI Control Register. </i>
// <loc> ( (unsigned int)((SPIMSS_CTRL >> 0) & 0xFFFFFFFF), ((SPIMSS_CTRL = (SPIMSS_CTRL & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_CTRL_SPIEN </item>
// <item> SFDITEM_FIELD__SPIMSS_CTRL_MMEN </item>
// <item> SFDITEM_FIELD__SPIMSS_CTRL_WOR </item>
// <item> SFDITEM_FIELD__SPIMSS_CTRL_CLKPOL </item>
// <item> SFDITEM_FIELD__SPIMSS_CTRL_PHASE </item>
// <item> SFDITEM_FIELD__SPIMSS_CTRL_BIRQ </item>
// <item> SFDITEM_FIELD__SPIMSS_CTRL_STR </item>
// <item> SFDITEM_FIELD__SPIMSS_CTRL_IRQE </item>
// </rtree>
//
// -------------------------- Register Item Address: SPIMSS_STATUS ------------------------------
// SVD Line: 8700
unsigned int SPIMSS_STATUS __AT (0x40018008);
// ----------------------------- Field Item: SPIMSS_STATUS_SLAS ---------------------------------
// SVD Line: 8706
// <item> SFDITEM_FIELD__SPIMSS_STATUS_SLAS
// <name> SLAS </name>
// <r>
// <i> [Bit 0] RO (@ 0x40018008) \nSlave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.\n0 : selected = selected\n1 : notSelected = notSelected </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_STATUS ) </loc>
// <o.0..0> SLAS
// <0=> 0: selected = selected
// <1=> 1: notSelected = notSelected
// </combo>
// </item>
//
// ----------------------------- Field Item: SPIMSS_STATUS_TXST ---------------------------------
// SVD Line: 8724
// <item> SFDITEM_FIELD__SPIMSS_STATUS_TXST
// <name> TXST </name>
// <r>
// <i> [Bit 1] RO (@ 0x40018008) \nTransmit Status.\n0 : idle = idle\n1 : busy = busy </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_STATUS ) </loc>
// <o.1..1> TXST
// <0=> 0: idle = idle
// <1=> 1: busy = busy
// </combo>
// </item>
//
// ----------------------------- Field Item: SPIMSS_STATUS_TUND ---------------------------------
// SVD Line: 8742
// <item> SFDITEM_FIELD__SPIMSS_STATUS_TUND
// <name> TUND </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40018008) \nTransmit Underrun.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_STATUS ) </loc>
// <o.2..2> TUND
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPIMSS_STATUS_ROVR ---------------------------------
// SVD Line: 8762
// <item> SFDITEM_FIELD__SPIMSS_STATUS_ROVR
// <name> ROVR </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40018008) \nReceive Overrun.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_STATUS ) </loc>
// <o.3..3> ROVR
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPIMSS_STATUS_ABT ---------------------------------
// SVD Line: 8781
// <item> SFDITEM_FIELD__SPIMSS_STATUS_ABT
// <name> ABT </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40018008) \nSlave Mode Transaction Abort.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_STATUS ) </loc>
// <o.4..4> ABT
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPIMSS_STATUS_COL ---------------------------------
// SVD Line: 8800
// <item> SFDITEM_FIELD__SPIMSS_STATUS_COL
// <name> COL </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40018008) \nCollision.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_STATUS ) </loc>
// <o.5..5> COL
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ----------------------------- Field Item: SPIMSS_STATUS_TOVR ---------------------------------
// SVD Line: 8819
// <item> SFDITEM_FIELD__SPIMSS_STATUS_TOVR
// <name> TOVR </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40018008) \nTransmit Overrun.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_STATUS ) </loc>
// <o.6..6> TOVR
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// ------------------------------ Field Item: SPIMSS_STATUS_IRQ ---------------------------------
// SVD Line: 8838
// <item> SFDITEM_FIELD__SPIMSS_STATUS_IRQ
// <name> IRQ </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40018008) \nSPI Interrupt Request.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_STATUS ) </loc>
// <o.7..7> IRQ
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------------ Register RTree: SPIMSS_STATUS ---------------------------------
// SVD Line: 8700
// <rtree> SFDITEM_REG__SPIMSS_STATUS
// <name> STATUS </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40018008) SPI Status Register. </i>
// <loc> ( (unsigned int)((SPIMSS_STATUS >> 0) & 0xFFFFFFFF), ((SPIMSS_STATUS = (SPIMSS_STATUS & ~(0xFCUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFC) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_STATUS_SLAS </item>
// <item> SFDITEM_FIELD__SPIMSS_STATUS_TXST </item>
// <item> SFDITEM_FIELD__SPIMSS_STATUS_TUND </item>
// <item> SFDITEM_FIELD__SPIMSS_STATUS_ROVR </item>
// <item> SFDITEM_FIELD__SPIMSS_STATUS_ABT </item>
// <item> SFDITEM_FIELD__SPIMSS_STATUS_COL </item>
// <item> SFDITEM_FIELD__SPIMSS_STATUS_TOVR </item>
// <item> SFDITEM_FIELD__SPIMSS_STATUS_IRQ </item>
// </rtree>
//
// ---------------------------- Register Item Address: SPIMSS_MOD -------------------------------
// SVD Line: 8860
unsigned int SPIMSS_MOD __AT (0x4001800C);
// ------------------------------- Field Item: SPIMSS_MOD_SSV -----------------------------------
// SVD Line: 8865
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSV
// <name> SSV </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001800C) \nSlave Select Value.\n0 : lo = The SSEL pin will be driven low.\n1 : hi = The SSEL pin will be driven high. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_MOD ) </loc>
// <o.0..0> SSV
// <0=> 0: lo = The SSEL pin will be driven low.
// <1=> 1: hi = The SSEL pin will be driven high.
// </combo>
// </item>
//
// ------------------------------- Field Item: SPIMSS_MOD_SSIO ----------------------------------
// SVD Line: 8884
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSIO
// <name> SSIO </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001800C) \nSlave Select I/O.\n0 : input = input\n1 : output = output </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_MOD ) </loc>
// <o.1..1> SSIO
// <0=> 0: input = input
// <1=> 1: output = output
// </combo>
// </item>
//
// ----------------------------- Field Item: SPIMSS_MOD_NUMBITS ---------------------------------
// SVD Line: 8901
// <item> SFDITEM_FIELD__SPIMSS_MOD_NUMBITS
// <name> NUMBITS </name>
// <rw>
// <i> [Bits 5..2] RW (@ 0x4001800C) \nNUMBITS\n0 : bits16 = bits16\n1 : bits1 = bits1\n2 : bits2 = bits2\n3 : bits3 = bits3\n4 : bits4 = bits4\n5 : bits5 = bits5\n6 : bits6 = bits6\n7 : bits7 = bits7\n8 : bits8 = bits8\n9 : bits9 = bits9\n10 : bits10 = bits10\n11 : bits11 = bits11\n12 : bits12 = bits12\n13 : bits13 = bits13\n14 : bits14 = bits14\n15 : bits15 = bits15 </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_MOD ) </loc>
// <o.5..2> NUMBITS
// <0=> 0: bits16 = bits16
// <1=> 1: bits1 = bits1
// <2=> 2: bits2 = bits2
// <3=> 3: bits3 = bits3
// <4=> 4: bits4 = bits4
// <5=> 5: bits5 = bits5
// <6=> 6: bits6 = bits6
// <7=> 7: bits7 = bits7
// <8=> 8: bits8 = bits8
// <9=> 9: bits9 = bits9
// <10=> 10: bits10 = bits10
// <11=> 11: bits11 = bits11
// <12=> 12: bits12 = bits12
// <13=> 13: bits13 = bits13
// <14=> 14: bits14 = bits14
// <15=> 15: bits15 = bits15
// </combo>
// </item>
//
// ------------------------------ Field Item: SPIMSS_MOD_TX_LJ ----------------------------------
// SVD Line: 8973
// <item> SFDITEM_FIELD__SPIMSS_MOD_TX_LJ
// <name> TX_LJ </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4001800C) \nTransmit Left Justify.\n0 : disable = disable\n1 : enable = enable </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_MOD ) </loc>
// <o.7..7> TX_LJ
// <0=> 0: disable = disable
// <1=> 1: enable = enable
// </combo>
// </item>
//
// ------------------------------- Field Item: SPIMSS_MOD_SSL1 ----------------------------------
// SVD Line: 8990
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSL1
// <name> SSL1 </name>
// <rw>
// <i> [Bit 8] RW (@ 0x4001800C) \nSlave Select 1. If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit.\n0 : hi = High.\n1 : lo = Low. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_MOD ) </loc>
// <o.8..8> SSL1
// <0=> 0: hi = High.
// <1=> 1: lo = Low.
// </combo>
// </item>
//
// ------------------------------- Field Item: SPIMSS_MOD_SSL2 ----------------------------------
// SVD Line: 9009
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSL2
// <name> SSL2 </name>
// <rw>
// <i> [Bit 9] RW (@ 0x4001800C) \nSlave Select 2. If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit.\n0 : hi = High.\n1 : lo = Low. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_MOD ) </loc>
// <o.9..9> SSL2
// <0=> 0: hi = High.
// <1=> 1: lo = Low.
// </combo>
// </item>
//
// ------------------------------- Field Item: SPIMSS_MOD_SSL3 ----------------------------------
// SVD Line: 9028
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSL3
// <name> SSL3 </name>
// <rw>
// <i> [Bit 10] RW (@ 0x4001800C) \nSlave Select 3. If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit.\n0 : hi = High.\n1 : lo = Low. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_MOD ) </loc>
// <o.10..10> SSL3
// <0=> 0: hi = High.
// <1=> 1: lo = Low.
// </combo>
// </item>
//
// ------------------------------- Register RTree: SPIMSS_MOD -----------------------------------
// SVD Line: 8860
// <rtree> SFDITEM_REG__SPIMSS_MOD
// <name> MOD </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001800C) SPI Mode Register. </i>
// <loc> ( (unsigned int)((SPIMSS_MOD >> 0) & 0xFFFFFFFF), ((SPIMSS_MOD = (SPIMSS_MOD & ~(0x7BFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7BF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSV </item>
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSIO </item>
// <item> SFDITEM_FIELD__SPIMSS_MOD_NUMBITS </item>
// <item> SFDITEM_FIELD__SPIMSS_MOD_TX_LJ </item>
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSL1 </item>
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSL2 </item>
// <item> SFDITEM_FIELD__SPIMSS_MOD_SSL3 </item>
// </rtree>
//
// ---------------------------- Register Item Address: SPIMSS_BRG -------------------------------
// SVD Line: 9049
unsigned int SPIMSS_BRG __AT (0x40018014);
// ------------------------------- Field Item: SPIMSS_BRG_BRG -----------------------------------
// SVD Line: 9055
// <item> SFDITEM_FIELD__SPIMSS_BRG_BRG
// <name> BRG </name>
// <rw>
// <i> [Bits 15..0] RW (@ 0x40018014) Baud Rate Reload Value. </i>
// <edit>
// <loc> ( (unsigned short)((SPIMSS_BRG >> 0) & 0xFFFF), ((SPIMSS_BRG = (SPIMSS_BRG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: SPIMSS_BRG -----------------------------------
// SVD Line: 9049
// <rtree> SFDITEM_REG__SPIMSS_BRG
// <name> BRG </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40018014) Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4). </i>
// <loc> ( (unsigned int)((SPIMSS_BRG >> 0) & 0xFFFFFFFF), ((SPIMSS_BRG = (SPIMSS_BRG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_BRG_BRG </item>
// </rtree>
//
// ---------------------------- Register Item Address: SPIMSS_DMA -------------------------------
// SVD Line: 9063
unsigned int SPIMSS_DMA __AT (0x40018018);
// -------------------------- Field Item: SPIMSS_DMA_TX_FIFO_LEVEL ------------------------------
// SVD Line: 9069
// <item> SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_LEVEL
// <name> TX_FIFO_LEVEL </name>
// <rw>
// <i> [Bits 2..0] RW (@ 0x40018018) \nTransmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.\n0 : entry1 = entry1\n1 : entries2 = entries2\n2 : entries3 = entries3\n3 : entries4 = entries4\n4 : entries5 = entries5\n5 : entries6 = entries6\n6 : entries7 = entries7\n7 : entries8 = entries8 </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_DMA ) </loc>
// <o.2..0> TX_FIFO_LEVEL
// <0=> 0: entry1 = entry1
// <1=> 1: entries2 = entries2
// <2=> 2: entries3 = entries3
// <3=> 3: entries4 = entries4
// <4=> 4: entries5 = entries5
// <5=> 5: entries6 = entries6
// <6=> 6: entries7 = entries7
// <7=> 7: entries8 = entries8
// </combo>
// </item>
//
// -------------------------- Field Item: SPIMSS_DMA_TX_FIFO_CLEAR ------------------------------
// SVD Line: 9110
// <item> SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_CLEAR
// <name> TX_FIFO_CLEAR </name>
// <w>
// <i> [Bit 4] WO (@ 0x40018018) \nTransmit FIFO Clear.\n0 : complete = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_DMA ) </loc>
// <o.4..4> TX_FIFO_CLEAR
// <0=> 0: complete = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// --------------------------- Field Item: SPIMSS_DMA_TX_FIFO_CNT -------------------------------
// SVD Line: 9130
// <item> SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_CNT
// <name> TX_FIFO_CNT </name>
// <r>
// <i> [Bits 11..8] RO (@ 0x40018018) Transmit FIFO Count. </i>
// <edit>
// <loc> ( (unsigned char)((SPIMSS_DMA >> 8) & 0xF) ) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: SPIMSS_DMA_TX_DMA_EN --------------------------------
// SVD Line: 9137
// <item> SFDITEM_FIELD__SPIMSS_DMA_TX_DMA_EN
// <name> TX_DMA_EN </name>
// <rw>
// <i> [Bit 15] RW (@ 0x40018018) \nTransmit DMA Enable.\n0 : disable = disable\n1 : enable = enable </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_DMA ) </loc>
// <o.15..15> TX_DMA_EN
// <0=> 0: disable = disable
// <1=> 1: enable = enable
// </combo>
// </item>
//
// -------------------------- Field Item: SPIMSS_DMA_RX_FIFO_LEVEL ------------------------------
// SVD Line: 9154
// <item> SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_LEVEL
// <name> RX_FIFO_LEVEL </name>
// <rw>
// <i> [Bits 18..16] RW (@ 0x40018018) \nReceive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.\n0 : entry1 = entry1\n1 : entries2 = entries2\n2 : entries3 = entries3\n3 : entries4 = entries4\n4 : entries5 = entries5\n5 : entries6 = entries6\n6 : entries7 = entries7\n7 : entries8 = entries8 </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_DMA ) </loc>
// <o.18..16> RX_FIFO_LEVEL
// <0=> 0: entry1 = entry1
// <1=> 1: entries2 = entries2
// <2=> 2: entries3 = entries3
// <3=> 3: entries4 = entries4
// <4=> 4: entries5 = entries5
// <5=> 5: entries6 = entries6
// <6=> 6: entries7 = entries7
// <7=> 7: entries8 = entries8
// </combo>
// </item>
//
// -------------------------- Field Item: SPIMSS_DMA_RX_FIFO_CLEAR ------------------------------
// SVD Line: 9195
// <item> SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_CLEAR
// <name> RX_FIFO_CLEAR </name>
// <rw>
// <i> [Bit 20] RW (@ 0x40018018) \nReceive FIFO Clear.\n0 : complete = No operation/complete.\n1 : start = Start operation. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_DMA ) </loc>
// <o.20..20> RX_FIFO_CLEAR
// <0=> 0: complete = No operation/complete.
// <1=> 1: start = Start operation.
// </combo>
// </item>
//
// --------------------------- Field Item: SPIMSS_DMA_RX_FIFO_CNT -------------------------------
// SVD Line: 9214
// <item> SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_CNT
// <name> RX_FIFO_CNT </name>
// <r>
// <i> [Bits 27..24] RO (@ 0x40018018) Receive FIFO Count. </i>
// <edit>
// <loc> ( (unsigned char)((SPIMSS_DMA >> 24) & 0xF) ) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: SPIMSS_DMA_RX_DMA_EN --------------------------------
// SVD Line: 9221
// <item> SFDITEM_FIELD__SPIMSS_DMA_RX_DMA_EN
// <name> RX_DMA_EN </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40018018) \nReceive DMA Enable.\n0 : disable = disable\n1 : enable = enable </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_DMA ) </loc>
// <o.31..31> RX_DMA_EN
// <0=> 0: disable = disable
// <1=> 1: enable = enable
// </combo>
// </item>
//
// ------------------------------- Register RTree: SPIMSS_DMA -----------------------------------
// SVD Line: 9063
// <rtree> SFDITEM_REG__SPIMSS_DMA
// <name> DMA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40018018) SPI DMA Register. </i>
// <loc> ( (unsigned int)((SPIMSS_DMA >> 0) & 0xFFFFFFFF), ((SPIMSS_DMA = (SPIMSS_DMA & ~(0x80178017UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80178017) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_LEVEL </item>
// <item> SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_CLEAR </item>
// <item> SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_CNT </item>
// <item> SFDITEM_FIELD__SPIMSS_DMA_TX_DMA_EN </item>
// <item> SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_LEVEL </item>
// <item> SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_CLEAR </item>
// <item> SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_CNT </item>
// <item> SFDITEM_FIELD__SPIMSS_DMA_RX_DMA_EN </item>
// </rtree>
//
// ------------------------- Register Item Address: SPIMSS_I2S_CTRL -----------------------------
// SVD Line: 9240
unsigned int SPIMSS_I2S_CTRL __AT (0x4001801C);
// --------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_EN -------------------------------
// SVD Line: 9245
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_EN
// <name> I2S_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001801C) \nI2S Mode Enable.\n0 : disable = disable\n1 : enable = enable </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_I2S_CTRL ) </loc>
// <o.0..0> I2S_EN
// <0=> 0: disable = disable
// <1=> 1: enable = enable
// </combo>
// </item>
//
// -------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_MUTE ------------------------------
// SVD Line: 9262
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_MUTE
// <name> I2S_MUTE </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4001801C) \nI2S Mute transmit.\n0 : normal = Normal Transmit.\n1 : replaced = Transmit data is replaced with 0. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_I2S_CTRL ) </loc>
// <o.1..1> I2S_MUTE
// <0=> 0: normal = Normal Transmit.
// <1=> 1: replaced = Transmit data is replaced with 0.
// </combo>
// </item>
//
// -------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_PAUSE -----------------------------
// SVD Line: 9280
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_PAUSE
// <name> I2S_PAUSE </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4001801C) \nI2S Pause transmit/receive.\n0 : normal = Normal Transmit.\n1 : halt = Halt transmit and receive FIFO and DMA access, transmit 0's. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_I2S_CTRL ) </loc>
// <o.2..2> I2S_PAUSE
// <0=> 0: normal = Normal Transmit.
// <1=> 1: halt = Halt transmit and receive FIFO and DMA access, transmit 0's.
// </combo>
// </item>
//
// -------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_MONO ------------------------------
// SVD Line: 9298
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_MONO
// <name> I2S_MONO </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4001801C) \nI2S Monophonic Audio Mode.\n0 : stereophonic = Stereophonic audio.\n1 : monophonic = Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_I2S_CTRL ) </loc>
// <o.3..3> I2S_MONO
// <0=> 0: stereophonic = Stereophonic audio.
// <1=> 1: monophonic = Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
// </combo>
// </item>
//
// --------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_LJ -------------------------------
// SVD Line: 9316
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_LJ
// <name> I2S_LJ </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4001801C) \nI2S Left Justify.\n0 : normal = Normal I2S audio protocol.\n1 : replaced = Audio data is synchronized with SSEL. </i>
// <combo>
// <loc> ( (unsigned int) SPIMSS_I2S_CTRL ) </loc>
// <o.4..4> I2S_LJ
// <0=> 0: normal = Normal I2S audio protocol.
// <1=> 1: replaced = Audio data is synchronized with SSEL.
// </combo>
// </item>
//
// ----------------------------- Register RTree: SPIMSS_I2S_CTRL --------------------------------
// SVD Line: 9240
// <rtree> SFDITEM_REG__SPIMSS_I2S_CTRL
// <name> I2S_CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001801C) I2S Control Register. </i>
// <loc> ( (unsigned int)((SPIMSS_I2S_CTRL >> 0) & 0xFFFFFFFF), ((SPIMSS_I2S_CTRL = (SPIMSS_I2S_CTRL & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_EN </item>
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_MUTE </item>
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_PAUSE </item>
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_MONO </item>
// <item> SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_LJ </item>
// </rtree>
//
// --------------------------------- Peripheral View: SPIMSS ------------------------------------
// SVD Line: 8507
// <view> SPIMSS
// <name> SPIMSS </name>
// <item> SFDITEM_REG__SPIMSS_DATA16 </item>
// <item> SFDITEM_REG__SPIMSS_DATA8 </item>
// <item> SFDITEM_REG__SPIMSS_CTRL </item>
// <item> SFDITEM_REG__SPIMSS_STATUS </item>
// <item> SFDITEM_REG__SPIMSS_MOD </item>
// <item> SFDITEM_REG__SPIMSS_BRG </item>
// <item> SFDITEM_REG__SPIMSS_DMA </item>
// <item> SFDITEM_REG__SPIMSS_I2S_CTRL </item>
// </view>
//
// ----------------------------- Register Item Address: TMR0_CNT --------------------------------
// SVD Line: 9355
unsigned int TMR0_CNT __AT (0x40010000);
// --------------------------------- Register Item: TMR0_CNT ------------------------------------
// SVD Line: 9355
// <item> SFDITEM_REG__TMR0_CNT
// <name> CNT </name>
// <i> [Bits 31..0] RW (@ 0x40010000) Count. This register stores the current timer count. </i>
// <edit>
// <loc> ( (unsigned int)((TMR0_CNT >> 0) & 0xFFFFFFFF), ((TMR0_CNT = (TMR0_CNT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: TMR0_CMP --------------------------------
// SVD Line: 9361
unsigned int TMR0_CMP __AT (0x40010004);
// --------------------------------- Register Item: TMR0_CMP ------------------------------------
// SVD Line: 9361
// <item> SFDITEM_REG__TMR0_CMP
// <name> CMP </name>
// <i> [Bits 31..0] RW (@ 0x40010004) Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. </i>
// <edit>
// <loc> ( (unsigned int)((TMR0_CMP >> 0) & 0xFFFFFFFF), ((TMR0_CMP = (TMR0_CMP & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: TMR0_PWM --------------------------------
// SVD Line: 9367
unsigned int TMR0_PWM __AT (0x40010008);
// --------------------------------- Register Item: TMR0_PWM ------------------------------------
// SVD Line: 9367
// <item> SFDITEM_REG__TMR0_PWM
// <name> PWM </name>
// <i> [Bits 31..0] RW (@ 0x40010008) PWM. This register stores the value that is compared to the current timer count. </i>
// <edit>
// <loc> ( (unsigned int)((TMR0_PWM >> 0) & 0xFFFFFFFF), ((TMR0_PWM = (TMR0_PWM & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register Item Address: TMR0_INTR --------------------------------
// SVD Line: 9372
unsigned int TMR0_INTR __AT (0x4001000C);
// ------------------------------ Field Item: TMR0_INTR_IRQ_CLR ---------------------------------
// SVD Line: 9378
// <item> SFDITEM_FIELD__TMR0_INTR_IRQ_CLR
// <name> IRQ_CLR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001000C) Clear Interrupt. </i>
// <check>
// <loc> ( (unsigned int) TMR0_INTR ) </loc>
// <o.0..0> IRQ_CLR
// </check>
// </item>
//
// -------------------------------- Register RTree: TMR0_INTR -----------------------------------
// SVD Line: 9372
// <rtree> SFDITEM_REG__TMR0_INTR
// <name> INTR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001000C) Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. </i>
// <loc> ( (unsigned int)((TMR0_INTR >> 0) & 0xFFFFFFFF), ((TMR0_INTR = (TMR0_INTR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR0_INTR_IRQ_CLR </item>
// </rtree>
//
// ----------------------------- Register Item Address: TMR0_CN ---------------------------------
// SVD Line: 9386
unsigned int TMR0_CN __AT (0x40010010);
// -------------------------------- Field Item: TMR0_CN_TMODE -----------------------------------
// SVD Line: 9391
// <item> SFDITEM_FIELD__TMR0_CN_TMODE
// <name> TMODE </name>
// <rw>
// <i> [Bits 2..0] RW (@ 0x40010010) \nTimer Mode.\n0 : oneShot = One Shot Mode.\n1 : continuous = Continuous Mode.\n2 : counter = Counter Mode.\n3 : pwm = PWM Mode.\n4 : capture = Capture Mode.\n5 : compare = Compare Mode.\n6 : gated = Gated Mode.\n7 : captureCompare = Capture/Compare Mode. </i>
// <combo>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.2..0> TMODE
// <0=> 0: oneShot = One Shot Mode.
// <1=> 1: continuous = Continuous Mode.
// <2=> 2: counter = Counter Mode.
// <3=> 3: pwm = PWM Mode.
// <4=> 4: capture = Capture Mode.
// <5=> 5: compare = Compare Mode.
// <6=> 6: gated = Gated Mode.
// <7=> 7: captureCompare = Capture/Compare Mode.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR0_CN_PRES ------------------------------------
// SVD Line: 9439
// <item> SFDITEM_FIELD__TMR0_CN_PRES
// <name> PRES </name>
// <rw>
// <i> [Bits 5..3] RW (@ 0x40010010) \nPrescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].\n0 : div1 = Divide by 1.\n1 : div2 = Divide by 2.\n2 : div4 = Divide by 4.\n3 : div8 = Divide by 8.\n4 : div16 = Divide by 16.\n5 : div32 = Divide by 32.\n6 : div64 = Divide by 64.\n7 : div128 = Divide by 128. </i>
// <combo>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.5..3> PRES
// <0=> 0: div1 = Divide by 1.
// <1=> 1: div2 = Divide by 2.
// <2=> 2: div4 = Divide by 4.
// <3=> 3: div8 = Divide by 8.
// <4=> 4: div16 = Divide by 16.
// <5=> 5: div32 = Divide by 32.
// <6=> 6: div64 = Divide by 64.
// <7=> 7: div128 = Divide by 128.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR0_CN_TPOL ------------------------------------
// SVD Line: 9487
// <item> SFDITEM_FIELD__TMR0_CN_TPOL
// <name> TPOL </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40010010) \nTimer input/output polarity bit.\n0 : activeHi = Active High.\n1 : activeLo = Active Low. </i>
// <combo>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.6..6> TPOL
// <0=> 0: activeHi = Active High.
// <1=> 1: activeLo = Active Low.
// </combo>
// </item>
//
// --------------------------------- Field Item: TMR0_CN_TEN ------------------------------------
// SVD Line: 9505
// <item> SFDITEM_FIELD__TMR0_CN_TEN
// <name> TEN </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40010010) \nTimer Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.7..7> TEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR0_CN_PRES3 -----------------------------------
// SVD Line: 9523
// <item> SFDITEM_FIELD__TMR0_CN_PRES3
// <name> PRES3 </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40010010) MSB of prescaler value. </i>
// <check>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.8..8> PRES3
// </check>
// </item>
//
// ------------------------------- Field Item: TMR0_CN_PWMSYNC ----------------------------------
// SVD Line: 9529
// <item> SFDITEM_FIELD__TMR0_CN_PWMSYNC
// <name> PWMSYNC </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40010010) \nTimer PWM Synchronization Mode Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.9..9> PWMSYNC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR0_CN_NOLHPOL ----------------------------------
// SVD Line: 9547
// <item> SFDITEM_FIELD__TMR0_CN_NOLHPOL
// <name> NOLHPOL </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40010010) \nTimer PWM output 0A polarity bit.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.10..10> NOLHPOL
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR0_CN_NOLLPOL ----------------------------------
// SVD Line: 9565
// <item> SFDITEM_FIELD__TMR0_CN_NOLLPOL
// <name> NOLLPOL </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40010010) \nTimer PWM output 0A' polarity bit.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.11..11> NOLLPOL
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR0_CN_PWMCKBD ----------------------------------
// SVD Line: 9583
// <item> SFDITEM_FIELD__TMR0_CN_PWMCKBD
// <name> PWMCKBD </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40010010) \nTimer PWM output 0A Mode Disable.\n0 : en = Enable.\n1 : dis = Disable. </i>
// <combo>
// <loc> ( (unsigned int) TMR0_CN ) </loc>
// <o.12..12> PWMCKBD
// <0=> 0: en = Enable.
// <1=> 1: dis = Disable.
// </combo>
// </item>
//
// --------------------------------- Register RTree: TMR0_CN ------------------------------------
// SVD Line: 9386
// <rtree> SFDITEM_REG__TMR0_CN
// <name> CN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40010010) Timer Control Register. </i>
// <loc> ( (unsigned int)((TMR0_CN >> 0) & 0xFFFFFFFF), ((TMR0_CN = (TMR0_CN & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR0_CN_TMODE </item>
// <item> SFDITEM_FIELD__TMR0_CN_PRES </item>
// <item> SFDITEM_FIELD__TMR0_CN_TPOL </item>
// <item> SFDITEM_FIELD__TMR0_CN_TEN </item>
// <item> SFDITEM_FIELD__TMR0_CN_PRES3 </item>
// <item> SFDITEM_FIELD__TMR0_CN_PWMSYNC </item>
// <item> SFDITEM_FIELD__TMR0_CN_NOLHPOL </item>
// <item> SFDITEM_FIELD__TMR0_CN_NOLLPOL </item>
// <item> SFDITEM_FIELD__TMR0_CN_PWMCKBD </item>
// </rtree>
//
// --------------------------- Register Item Address: TMR0_NOLCMP -------------------------------
// SVD Line: 9603
unsigned int TMR0_NOLCMP __AT (0x40010014);
// ----------------------------- Field Item: TMR0_NOLCMP_NOLLCMP --------------------------------
// SVD Line: 9608
// <item> SFDITEM_FIELD__TMR0_NOLCMP_NOLLCMP
// <name> NOLLCMP </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40010014) Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. </i>
// <edit>
// <loc> ( (unsigned char)((TMR0_NOLCMP >> 0) & 0xFF), ((TMR0_NOLCMP = (TMR0_NOLCMP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: TMR0_NOLCMP_NOLHCMP --------------------------------
// SVD Line: 9614
// <item> SFDITEM_FIELD__TMR0_NOLCMP_NOLHCMP
// <name> NOLHCMP </name>
// <rw>
// <i> [Bits 15..8] RW (@ 0x40010014) Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. </i>
// <edit>
// <loc> ( (unsigned char)((TMR0_NOLCMP >> 8) & 0xFF), ((TMR0_NOLCMP = (TMR0_NOLCMP & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: TMR0_NOLCMP ----------------------------------
// SVD Line: 9603
// <rtree> SFDITEM_REG__TMR0_NOLCMP
// <name> NOLCMP </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40010014) Timer Non-Overlapping Compare Register. </i>
// <loc> ( (unsigned int)((TMR0_NOLCMP >> 0) & 0xFFFFFFFF), ((TMR0_NOLCMP = (TMR0_NOLCMP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR0_NOLCMP_NOLLCMP </item>
// <item> SFDITEM_FIELD__TMR0_NOLCMP_NOLHCMP </item>
// </rtree>
//
// ---------------------------------- Peripheral View: TMR0 -------------------------------------
// SVD Line: 9339
// <view> TMR0
// <name> TMR0 </name>
// <item> SFDITEM_REG__TMR0_CNT </item>
// <item> SFDITEM_REG__TMR0_CMP </item>
// <item> SFDITEM_REG__TMR0_PWM </item>
// <item> SFDITEM_REG__TMR0_INTR </item>
// <item> SFDITEM_REG__TMR0_CN </item>
// <item> SFDITEM_REG__TMR0_NOLCMP </item>
// </view>
//
// ----------------------------- Register Item Address: TMR1_CNT --------------------------------
// SVD Line: 9355
unsigned int TMR1_CNT __AT (0x40011000);
// --------------------------------- Register Item: TMR1_CNT ------------------------------------
// SVD Line: 9355
// <item> SFDITEM_REG__TMR1_CNT
// <name> CNT </name>
// <i> [Bits 31..0] RW (@ 0x40011000) Count. This register stores the current timer count. </i>
// <edit>
// <loc> ( (unsigned int)((TMR1_CNT >> 0) & 0xFFFFFFFF), ((TMR1_CNT = (TMR1_CNT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: TMR1_CMP --------------------------------
// SVD Line: 9361
unsigned int TMR1_CMP __AT (0x40011004);
// --------------------------------- Register Item: TMR1_CMP ------------------------------------
// SVD Line: 9361
// <item> SFDITEM_REG__TMR1_CMP
// <name> CMP </name>
// <i> [Bits 31..0] RW (@ 0x40011004) Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. </i>
// <edit>
// <loc> ( (unsigned int)((TMR1_CMP >> 0) & 0xFFFFFFFF), ((TMR1_CMP = (TMR1_CMP & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: TMR1_PWM --------------------------------
// SVD Line: 9367
unsigned int TMR1_PWM __AT (0x40011008);
// --------------------------------- Register Item: TMR1_PWM ------------------------------------
// SVD Line: 9367
// <item> SFDITEM_REG__TMR1_PWM
// <name> PWM </name>
// <i> [Bits 31..0] RW (@ 0x40011008) PWM. This register stores the value that is compared to the current timer count. </i>
// <edit>
// <loc> ( (unsigned int)((TMR1_PWM >> 0) & 0xFFFFFFFF), ((TMR1_PWM = (TMR1_PWM & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register Item Address: TMR1_INTR --------------------------------
// SVD Line: 9372
unsigned int TMR1_INTR __AT (0x4001100C);
// ------------------------------ Field Item: TMR1_INTR_IRQ_CLR ---------------------------------
// SVD Line: 9378
// <item> SFDITEM_FIELD__TMR1_INTR_IRQ_CLR
// <name> IRQ_CLR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001100C) Clear Interrupt. </i>
// <check>
// <loc> ( (unsigned int) TMR1_INTR ) </loc>
// <o.0..0> IRQ_CLR
// </check>
// </item>
//
// -------------------------------- Register RTree: TMR1_INTR -----------------------------------
// SVD Line: 9372
// <rtree> SFDITEM_REG__TMR1_INTR
// <name> INTR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001100C) Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. </i>
// <loc> ( (unsigned int)((TMR1_INTR >> 0) & 0xFFFFFFFF), ((TMR1_INTR = (TMR1_INTR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR1_INTR_IRQ_CLR </item>
// </rtree>
//
// ----------------------------- Register Item Address: TMR1_CN ---------------------------------
// SVD Line: 9386
unsigned int TMR1_CN __AT (0x40011010);
// -------------------------------- Field Item: TMR1_CN_TMODE -----------------------------------
// SVD Line: 9391
// <item> SFDITEM_FIELD__TMR1_CN_TMODE
// <name> TMODE </name>
// <rw>
// <i> [Bits 2..0] RW (@ 0x40011010) \nTimer Mode.\n0 : oneShot = One Shot Mode.\n1 : continuous = Continuous Mode.\n2 : counter = Counter Mode.\n3 : pwm = PWM Mode.\n4 : capture = Capture Mode.\n5 : compare = Compare Mode.\n6 : gated = Gated Mode.\n7 : captureCompare = Capture/Compare Mode. </i>
// <combo>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.2..0> TMODE
// <0=> 0: oneShot = One Shot Mode.
// <1=> 1: continuous = Continuous Mode.
// <2=> 2: counter = Counter Mode.
// <3=> 3: pwm = PWM Mode.
// <4=> 4: capture = Capture Mode.
// <5=> 5: compare = Compare Mode.
// <6=> 6: gated = Gated Mode.
// <7=> 7: captureCompare = Capture/Compare Mode.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR1_CN_PRES ------------------------------------
// SVD Line: 9439
// <item> SFDITEM_FIELD__TMR1_CN_PRES
// <name> PRES </name>
// <rw>
// <i> [Bits 5..3] RW (@ 0x40011010) \nPrescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].\n0 : div1 = Divide by 1.\n1 : div2 = Divide by 2.\n2 : div4 = Divide by 4.\n3 : div8 = Divide by 8.\n4 : div16 = Divide by 16.\n5 : div32 = Divide by 32.\n6 : div64 = Divide by 64.\n7 : div128 = Divide by 128. </i>
// <combo>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.5..3> PRES
// <0=> 0: div1 = Divide by 1.
// <1=> 1: div2 = Divide by 2.
// <2=> 2: div4 = Divide by 4.
// <3=> 3: div8 = Divide by 8.
// <4=> 4: div16 = Divide by 16.
// <5=> 5: div32 = Divide by 32.
// <6=> 6: div64 = Divide by 64.
// <7=> 7: div128 = Divide by 128.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR1_CN_TPOL ------------------------------------
// SVD Line: 9487
// <item> SFDITEM_FIELD__TMR1_CN_TPOL
// <name> TPOL </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40011010) \nTimer input/output polarity bit.\n0 : activeHi = Active High.\n1 : activeLo = Active Low. </i>
// <combo>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.6..6> TPOL
// <0=> 0: activeHi = Active High.
// <1=> 1: activeLo = Active Low.
// </combo>
// </item>
//
// --------------------------------- Field Item: TMR1_CN_TEN ------------------------------------
// SVD Line: 9505
// <item> SFDITEM_FIELD__TMR1_CN_TEN
// <name> TEN </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40011010) \nTimer Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.7..7> TEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR1_CN_PRES3 -----------------------------------
// SVD Line: 9523
// <item> SFDITEM_FIELD__TMR1_CN_PRES3
// <name> PRES3 </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40011010) MSB of prescaler value. </i>
// <check>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.8..8> PRES3
// </check>
// </item>
//
// ------------------------------- Field Item: TMR1_CN_PWMSYNC ----------------------------------
// SVD Line: 9529
// <item> SFDITEM_FIELD__TMR1_CN_PWMSYNC
// <name> PWMSYNC </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40011010) \nTimer PWM Synchronization Mode Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.9..9> PWMSYNC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR1_CN_NOLHPOL ----------------------------------
// SVD Line: 9547
// <item> SFDITEM_FIELD__TMR1_CN_NOLHPOL
// <name> NOLHPOL </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40011010) \nTimer PWM output 0A polarity bit.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.10..10> NOLHPOL
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR1_CN_NOLLPOL ----------------------------------
// SVD Line: 9565
// <item> SFDITEM_FIELD__TMR1_CN_NOLLPOL
// <name> NOLLPOL </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40011010) \nTimer PWM output 0A' polarity bit.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.11..11> NOLLPOL
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR1_CN_PWMCKBD ----------------------------------
// SVD Line: 9583
// <item> SFDITEM_FIELD__TMR1_CN_PWMCKBD
// <name> PWMCKBD </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40011010) \nTimer PWM output 0A Mode Disable.\n0 : en = Enable.\n1 : dis = Disable. </i>
// <combo>
// <loc> ( (unsigned int) TMR1_CN ) </loc>
// <o.12..12> PWMCKBD
// <0=> 0: en = Enable.
// <1=> 1: dis = Disable.
// </combo>
// </item>
//
// --------------------------------- Register RTree: TMR1_CN ------------------------------------
// SVD Line: 9386
// <rtree> SFDITEM_REG__TMR1_CN
// <name> CN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40011010) Timer Control Register. </i>
// <loc> ( (unsigned int)((TMR1_CN >> 0) & 0xFFFFFFFF), ((TMR1_CN = (TMR1_CN & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR1_CN_TMODE </item>
// <item> SFDITEM_FIELD__TMR1_CN_PRES </item>
// <item> SFDITEM_FIELD__TMR1_CN_TPOL </item>
// <item> SFDITEM_FIELD__TMR1_CN_TEN </item>
// <item> SFDITEM_FIELD__TMR1_CN_PRES3 </item>
// <item> SFDITEM_FIELD__TMR1_CN_PWMSYNC </item>
// <item> SFDITEM_FIELD__TMR1_CN_NOLHPOL </item>
// <item> SFDITEM_FIELD__TMR1_CN_NOLLPOL </item>
// <item> SFDITEM_FIELD__TMR1_CN_PWMCKBD </item>
// </rtree>
//
// --------------------------- Register Item Address: TMR1_NOLCMP -------------------------------
// SVD Line: 9603
unsigned int TMR1_NOLCMP __AT (0x40011014);
// ----------------------------- Field Item: TMR1_NOLCMP_NOLLCMP --------------------------------
// SVD Line: 9608
// <item> SFDITEM_FIELD__TMR1_NOLCMP_NOLLCMP
// <name> NOLLCMP </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40011014) Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. </i>
// <edit>
// <loc> ( (unsigned char)((TMR1_NOLCMP >> 0) & 0xFF), ((TMR1_NOLCMP = (TMR1_NOLCMP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: TMR1_NOLCMP_NOLHCMP --------------------------------
// SVD Line: 9614
// <item> SFDITEM_FIELD__TMR1_NOLCMP_NOLHCMP
// <name> NOLHCMP </name>
// <rw>
// <i> [Bits 15..8] RW (@ 0x40011014) Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. </i>
// <edit>
// <loc> ( (unsigned char)((TMR1_NOLCMP >> 8) & 0xFF), ((TMR1_NOLCMP = (TMR1_NOLCMP & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: TMR1_NOLCMP ----------------------------------
// SVD Line: 9603
// <rtree> SFDITEM_REG__TMR1_NOLCMP
// <name> NOLCMP </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40011014) Timer Non-Overlapping Compare Register. </i>
// <loc> ( (unsigned int)((TMR1_NOLCMP >> 0) & 0xFFFFFFFF), ((TMR1_NOLCMP = (TMR1_NOLCMP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR1_NOLCMP_NOLLCMP </item>
// <item> SFDITEM_FIELD__TMR1_NOLCMP_NOLHCMP </item>
// </rtree>
//
// ---------------------------------- Peripheral View: TMR1 -------------------------------------
// SVD Line: 9625
// <view> TMR1
// <name> TMR1 </name>
// <item> SFDITEM_REG__TMR1_CNT </item>
// <item> SFDITEM_REG__TMR1_CMP </item>
// <item> SFDITEM_REG__TMR1_PWM </item>
// <item> SFDITEM_REG__TMR1_INTR </item>
// <item> SFDITEM_REG__TMR1_CN </item>
// <item> SFDITEM_REG__TMR1_NOLCMP </item>
// </view>
//
// ----------------------------- Register Item Address: TMR2_CNT --------------------------------
// SVD Line: 9355
unsigned int TMR2_CNT __AT (0x40012000);
// --------------------------------- Register Item: TMR2_CNT ------------------------------------
// SVD Line: 9355
// <item> SFDITEM_REG__TMR2_CNT
// <name> CNT </name>
// <i> [Bits 31..0] RW (@ 0x40012000) Count. This register stores the current timer count. </i>
// <edit>
// <loc> ( (unsigned int)((TMR2_CNT >> 0) & 0xFFFFFFFF), ((TMR2_CNT = (TMR2_CNT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: TMR2_CMP --------------------------------
// SVD Line: 9361
unsigned int TMR2_CMP __AT (0x40012004);
// --------------------------------- Register Item: TMR2_CMP ------------------------------------
// SVD Line: 9361
// <item> SFDITEM_REG__TMR2_CMP
// <name> CMP </name>
// <i> [Bits 31..0] RW (@ 0x40012004) Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. </i>
// <edit>
// <loc> ( (unsigned int)((TMR2_CMP >> 0) & 0xFFFFFFFF), ((TMR2_CMP = (TMR2_CMP & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Register Item Address: TMR2_PWM --------------------------------
// SVD Line: 9367
unsigned int TMR2_PWM __AT (0x40012008);
// --------------------------------- Register Item: TMR2_PWM ------------------------------------
// SVD Line: 9367
// <item> SFDITEM_REG__TMR2_PWM
// <name> PWM </name>
// <i> [Bits 31..0] RW (@ 0x40012008) PWM. This register stores the value that is compared to the current timer count. </i>
// <edit>
// <loc> ( (unsigned int)((TMR2_PWM >> 0) & 0xFFFFFFFF), ((TMR2_PWM = (TMR2_PWM & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register Item Address: TMR2_INTR --------------------------------
// SVD Line: 9372
unsigned int TMR2_INTR __AT (0x4001200C);
// ------------------------------ Field Item: TMR2_INTR_IRQ_CLR ---------------------------------
// SVD Line: 9378
// <item> SFDITEM_FIELD__TMR2_INTR_IRQ_CLR
// <name> IRQ_CLR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4001200C) Clear Interrupt. </i>
// <check>
// <loc> ( (unsigned int) TMR2_INTR ) </loc>
// <o.0..0> IRQ_CLR
// </check>
// </item>
//
// -------------------------------- Register RTree: TMR2_INTR -----------------------------------
// SVD Line: 9372
// <rtree> SFDITEM_REG__TMR2_INTR
// <name> INTR </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4001200C) Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. </i>
// <loc> ( (unsigned int)((TMR2_INTR >> 0) & 0xFFFFFFFF), ((TMR2_INTR = (TMR2_INTR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR2_INTR_IRQ_CLR </item>
// </rtree>
//
// ----------------------------- Register Item Address: TMR2_CN ---------------------------------
// SVD Line: 9386
unsigned int TMR2_CN __AT (0x40012010);
// -------------------------------- Field Item: TMR2_CN_TMODE -----------------------------------
// SVD Line: 9391
// <item> SFDITEM_FIELD__TMR2_CN_TMODE
// <name> TMODE </name>
// <rw>
// <i> [Bits 2..0] RW (@ 0x40012010) \nTimer Mode.\n0 : oneShot = One Shot Mode.\n1 : continuous = Continuous Mode.\n2 : counter = Counter Mode.\n3 : pwm = PWM Mode.\n4 : capture = Capture Mode.\n5 : compare = Compare Mode.\n6 : gated = Gated Mode.\n7 : captureCompare = Capture/Compare Mode. </i>
// <combo>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.2..0> TMODE
// <0=> 0: oneShot = One Shot Mode.
// <1=> 1: continuous = Continuous Mode.
// <2=> 2: counter = Counter Mode.
// <3=> 3: pwm = PWM Mode.
// <4=> 4: capture = Capture Mode.
// <5=> 5: compare = Compare Mode.
// <6=> 6: gated = Gated Mode.
// <7=> 7: captureCompare = Capture/Compare Mode.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR2_CN_PRES ------------------------------------
// SVD Line: 9439
// <item> SFDITEM_FIELD__TMR2_CN_PRES
// <name> PRES </name>
// <rw>
// <i> [Bits 5..3] RW (@ 0x40012010) \nPrescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].\n0 : div1 = Divide by 1.\n1 : div2 = Divide by 2.\n2 : div4 = Divide by 4.\n3 : div8 = Divide by 8.\n4 : div16 = Divide by 16.\n5 : div32 = Divide by 32.\n6 : div64 = Divide by 64.\n7 : div128 = Divide by 128. </i>
// <combo>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.5..3> PRES
// <0=> 0: div1 = Divide by 1.
// <1=> 1: div2 = Divide by 2.
// <2=> 2: div4 = Divide by 4.
// <3=> 3: div8 = Divide by 8.
// <4=> 4: div16 = Divide by 16.
// <5=> 5: div32 = Divide by 32.
// <6=> 6: div64 = Divide by 64.
// <7=> 7: div128 = Divide by 128.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR2_CN_TPOL ------------------------------------
// SVD Line: 9487
// <item> SFDITEM_FIELD__TMR2_CN_TPOL
// <name> TPOL </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40012010) \nTimer input/output polarity bit.\n0 : activeHi = Active High.\n1 : activeLo = Active Low. </i>
// <combo>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.6..6> TPOL
// <0=> 0: activeHi = Active High.
// <1=> 1: activeLo = Active Low.
// </combo>
// </item>
//
// --------------------------------- Field Item: TMR2_CN_TEN ------------------------------------
// SVD Line: 9505
// <item> SFDITEM_FIELD__TMR2_CN_TEN
// <name> TEN </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40012010) \nTimer Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.7..7> TEN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// -------------------------------- Field Item: TMR2_CN_PRES3 -----------------------------------
// SVD Line: 9523
// <item> SFDITEM_FIELD__TMR2_CN_PRES3
// <name> PRES3 </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40012010) MSB of prescaler value. </i>
// <check>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.8..8> PRES3
// </check>
// </item>
//
// ------------------------------- Field Item: TMR2_CN_PWMSYNC ----------------------------------
// SVD Line: 9529
// <item> SFDITEM_FIELD__TMR2_CN_PWMSYNC
// <name> PWMSYNC </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40012010) \nTimer PWM Synchronization Mode Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.9..9> PWMSYNC
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR2_CN_NOLHPOL ----------------------------------
// SVD Line: 9547
// <item> SFDITEM_FIELD__TMR2_CN_NOLHPOL
// <name> NOLHPOL </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40012010) \nTimer PWM output 0A polarity bit.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.10..10> NOLHPOL
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR2_CN_NOLLPOL ----------------------------------
// SVD Line: 9565
// <item> SFDITEM_FIELD__TMR2_CN_NOLLPOL
// <name> NOLLPOL </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40012010) \nTimer PWM output 0A' polarity bit.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.11..11> NOLLPOL
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------- Field Item: TMR2_CN_PWMCKBD ----------------------------------
// SVD Line: 9583
// <item> SFDITEM_FIELD__TMR2_CN_PWMCKBD
// <name> PWMCKBD </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40012010) \nTimer PWM output 0A Mode Disable.\n0 : en = Enable.\n1 : dis = Disable. </i>
// <combo>
// <loc> ( (unsigned int) TMR2_CN ) </loc>
// <o.12..12> PWMCKBD
// <0=> 0: en = Enable.
// <1=> 1: dis = Disable.
// </combo>
// </item>
//
// --------------------------------- Register RTree: TMR2_CN ------------------------------------
// SVD Line: 9386
// <rtree> SFDITEM_REG__TMR2_CN
// <name> CN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40012010) Timer Control Register. </i>
// <loc> ( (unsigned int)((TMR2_CN >> 0) & 0xFFFFFFFF), ((TMR2_CN = (TMR2_CN & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR2_CN_TMODE </item>
// <item> SFDITEM_FIELD__TMR2_CN_PRES </item>
// <item> SFDITEM_FIELD__TMR2_CN_TPOL </item>
// <item> SFDITEM_FIELD__TMR2_CN_TEN </item>
// <item> SFDITEM_FIELD__TMR2_CN_PRES3 </item>
// <item> SFDITEM_FIELD__TMR2_CN_PWMSYNC </item>
// <item> SFDITEM_FIELD__TMR2_CN_NOLHPOL </item>
// <item> SFDITEM_FIELD__TMR2_CN_NOLLPOL </item>
// <item> SFDITEM_FIELD__TMR2_CN_PWMCKBD </item>
// </rtree>
//
// --------------------------- Register Item Address: TMR2_NOLCMP -------------------------------
// SVD Line: 9603
unsigned int TMR2_NOLCMP __AT (0x40012014);
// ----------------------------- Field Item: TMR2_NOLCMP_NOLLCMP --------------------------------
// SVD Line: 9608
// <item> SFDITEM_FIELD__TMR2_NOLCMP_NOLLCMP
// <name> NOLLCMP </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x40012014) Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. </i>
// <edit>
// <loc> ( (unsigned char)((TMR2_NOLCMP >> 0) & 0xFF), ((TMR2_NOLCMP = (TMR2_NOLCMP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: TMR2_NOLCMP_NOLHCMP --------------------------------
// SVD Line: 9614
// <item> SFDITEM_FIELD__TMR2_NOLCMP_NOLHCMP
// <name> NOLHCMP </name>
// <rw>
// <i> [Bits 15..8] RW (@ 0x40012014) Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. </i>
// <edit>
// <loc> ( (unsigned char)((TMR2_NOLCMP >> 8) & 0xFF), ((TMR2_NOLCMP = (TMR2_NOLCMP & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: TMR2_NOLCMP ----------------------------------
// SVD Line: 9603
// <rtree> SFDITEM_REG__TMR2_NOLCMP
// <name> NOLCMP </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40012014) Timer Non-Overlapping Compare Register. </i>
// <loc> ( (unsigned int)((TMR2_NOLCMP >> 0) & 0xFFFFFFFF), ((TMR2_NOLCMP = (TMR2_NOLCMP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__TMR2_NOLCMP_NOLLCMP </item>
// <item> SFDITEM_FIELD__TMR2_NOLCMP_NOLHCMP </item>
// </rtree>
//
// ---------------------------------- Peripheral View: TMR2 -------------------------------------
// SVD Line: 9636
// <view> TMR2
// <name> TMR2 </name>
// <item> SFDITEM_REG__TMR2_CNT </item>
// <item> SFDITEM_REG__TMR2_CMP </item>
// <item> SFDITEM_REG__TMR2_PWM </item>
// <item> SFDITEM_REG__TMR2_INTR </item>
// <item> SFDITEM_REG__TMR2_CN </item>
// <item> SFDITEM_REG__TMR2_NOLCMP </item>
// </view>
//
// ---------------------------- Register Item Address: UART0_CTRL -------------------------------
// SVD Line: 9662
unsigned int UART0_CTRL __AT (0x40042000);
// ------------------------------ Field Item: UART0_CTRL_ENABLE ---------------------------------
// SVD Line: 9668
// <item> SFDITEM_FIELD__UART0_CTRL_ENABLE
// <name> ENABLE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40042000) \nUART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.\n0 : dis = UART disabled. FIFOs are flushed. Clock is gated off for power savings.\n1 : en = UART enabled. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.0..0> ENABLE
// <0=> 0: dis = UART disabled. FIFOs are flushed. Clock is gated off for power savings.
// <1=> 1: en = UART enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: UART0_CTRL_PARITY_EN --------------------------------
// SVD Line: 9686
// <item> SFDITEM_FIELD__UART0_CTRL_PARITY_EN
// <name> PARITY_EN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40042000) \nEnable/disable Parity bit (9th character).\n0 : dis = No Parity\n1 : en = Parity enabled as 9th bit </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.1..1> PARITY_EN
// <0=> 0: dis = No Parity
// <1=> 1: en = Parity enabled as 9th bit
// </combo>
// </item>
//
// ------------------------------ Field Item: UART0_CTRL_PARITY ---------------------------------
// SVD Line: 9704
// <item> SFDITEM_FIELD__UART0_CTRL_PARITY
// <name> PARITY </name>
// <rw>
// <i> [Bits 3..2] RW (@ 0x40042000) \nWhen PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1; Space parity = always 0.\n0 : Even = Even parity selected.\n1 : ODD = Odd parity selected.\n2 : MARK = Mark parity selected.\n3 : SPACE = Space parity selected. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.3..2> PARITY
// <0=> 0: Even = Even parity selected.
// <1=> 1: ODD = Odd parity selected.
// <2=> 2: MARK = Mark parity selected.
// <3=> 3: SPACE = Space parity selected.
// </combo>
// </item>
//
// ------------------------------ Field Item: UART0_CTRL_PARMD ----------------------------------
// SVD Line: 9733
// <item> SFDITEM_FIELD__UART0_CTRL_PARMD
// <name> PARMD </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40042000) \nSelects parity based on 1s or 0s count (when PARITY_EN=1).\n0 : 1 = Parity calculation is based on number of 1s in frame.\n1 : 0 = Parity calculation is based on number of 0s in frame. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.4..4> PARMD
// <0=> 0: 1 = Parity calculation is based on number of 1s in frame.
// <1=> 1: 0 = Parity calculation is based on number of 0s in frame.
// </combo>
// </item>
//
// ----------------------------- Field Item: UART0_CTRL_TX_FLUSH --------------------------------
// SVD Line: 9751
// <item> SFDITEM_FIELD__UART0_CTRL_TX_FLUSH
// <name> TX_FLUSH </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40042000) Flushes the TX FIFO buffer. </i>
// <check>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.5..5> TX_FLUSH
// </check>
// </item>
//
// ----------------------------- Field Item: UART0_CTRL_RX_FLUSH --------------------------------
// SVD Line: 9757
// <item> SFDITEM_FIELD__UART0_CTRL_RX_FLUSH
// <name> RX_FLUSH </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40042000) Flushes the RX FIFO buffer. </i>
// <check>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.6..6> RX_FLUSH
// </check>
// </item>
//
// ------------------------------ Field Item: UART0_CTRL_BITACC ---------------------------------
// SVD Line: 9763
// <item> SFDITEM_FIELD__UART0_CTRL_BITACC
// <name> BITACC </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40042000) \nIf set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.\n0 : FRAME = Frame accuracy.\n1 : BIT = Bit accuracy. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.7..7> BITACC
// <0=> 0: FRAME = Frame accuracy.
// <1=> 1: BIT = Bit accuracy.
// </combo>
// </item>
//
// ---------------------------- Field Item: UART0_CTRL_CHAR_SIZE --------------------------------
// SVD Line: 9781
// <item> SFDITEM_FIELD__UART0_CTRL_CHAR_SIZE
// <name> CHAR_SIZE </name>
// <rw>
// <i> [Bits 9..8] RW (@ 0x40042000) \nSelects UART character size.\n0 : 5 = 5 bits.\n1 : 6 = 6 bits.\n2 : 7 = 7 bits.\n3 : 8 = 8 bits. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.9..8> CHAR_SIZE
// <0=> 0: 5 = 5 bits.
// <1=> 1: 6 = 6 bits.
// <2=> 2: 7 = 7 bits.
// <3=> 3: 8 = 8 bits.
// </combo>
// </item>
//
// ----------------------------- Field Item: UART0_CTRL_STOPBITS --------------------------------
// SVD Line: 9809
// <item> SFDITEM_FIELD__UART0_CTRL_STOPBITS
// <name> STOPBITS </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40042000) \nSelects the number of stop bits that will be generated.\n0 : 1 = 1 stop bit.\n1 : 1_5 = 1.5 stop bits. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.10..10> STOPBITS
// <0=> 0: 1 = 1 stop bit.
// <1=> 1: 1_5 = 1.5 stop bits.
// </combo>
// </item>
//
// ---------------------------- Field Item: UART0_CTRL_FLOW_CTRL --------------------------------
// SVD Line: 9827
// <item> SFDITEM_FIELD__UART0_CTRL_FLOW_CTRL
// <name> FLOW_CTRL </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40042000) \nEnables/disables hardware flow control.\n0 : dis = HW Flow Control disabled\n1 : en = HW Flow Control with RTS/CTS enabled </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.11..11> FLOW_CTRL
// <0=> 0: dis = HW Flow Control disabled
// <1=> 1: en = HW Flow Control with RTS/CTS enabled
// </combo>
// </item>
//
// ----------------------------- Field Item: UART0_CTRL_FLOW_POL --------------------------------
// SVD Line: 9845
// <item> SFDITEM_FIELD__UART0_CTRL_FLOW_POL
// <name> FLOW_POL </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40042000) \nRTS/CTS polarity.\n0 : 0 = RTS/CTS asserted is logic 0.\n1 : 1 = RTS/CTS asserted is logic 1. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.12..12> FLOW_POL
// <0=> 0: 0 = RTS/CTS asserted is logic 0.
// <1=> 1: 1 = RTS/CTS asserted is logic 1.
// </combo>
// </item>
//
// ---------------------------- Field Item: UART0_CTRL_NULL_MODEM -------------------------------
// SVD Line: 9863
// <item> SFDITEM_FIELD__UART0_CTRL_NULL_MODEM
// <name> NULL_MODEM </name>
// <rw>
// <i> [Bit 13] RW (@ 0x40042000) \nNULL Modem Support (RTS/CTS and TXD/RXD swap).\n0 : DIS = Direct convention.\n1 : EN = Null Modem Mode. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.13..13> NULL_MODEM
// <0=> 0: DIS = Direct convention.
// <1=> 1: EN = Null Modem Mode.
// </combo>
// </item>
//
// ------------------------------ Field Item: UART0_CTRL_BREAK ----------------------------------
// SVD Line: 9881
// <item> SFDITEM_FIELD__UART0_CTRL_BREAK
// <name> BREAK </name>
// <rw>
// <i> [Bit 14] RW (@ 0x40042000) \nBreak control bit. It causes a break condition to be transmitted to receiving UART.\n0 : DIS = Break characters are not generated.\n1 : EN = Break characters are sent(all the bits are at '0' including start/parity/stop). </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.14..14> BREAK
// <0=> 0: DIS = Break characters are not generated.
// <1=> 1: EN = Break characters are sent(all the bits are at '0' including start/parity/stop).
// </combo>
// </item>
//
// ------------------------------ Field Item: UART0_CTRL_CLKSEL ---------------------------------
// SVD Line: 9899
// <item> SFDITEM_FIELD__UART0_CTRL_CLKSEL
// <name> CLKSEL </name>
// <rw>
// <i> [Bit 15] RW (@ 0x40042000) \nBaud Rate Clock Source Select. Selects the baud rate clock.\n0 : SYSTEM = System clock.\n1 : ALTERNATE = Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. </i>
// <combo>
// <loc> ( (unsigned int) UART0_CTRL ) </loc>
// <o.15..15> CLKSEL
// <0=> 0: SYSTEM = System clock.
// <1=> 1: ALTERNATE = Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.
// </combo>
// </item>
//
// ------------------------------ Field Item: UART0_CTRL_RX_TO ----------------------------------
// SVD Line: 9917
// <item> SFDITEM_FIELD__UART0_CTRL_RX_TO
// <name> RX_TO </name>
// <rw>
// <i> [Bits 23..16] RW (@ 0x40042000) RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_CTRL >> 16) & 0xFF), ((UART0_CTRL = (UART0_CTRL & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: UART0_CTRL -----------------------------------
// SVD Line: 9662
// <rtree> SFDITEM_REG__UART0_CTRL
// <name> CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40042000) Control Register. </i>
// <loc> ( (unsigned int)((UART0_CTRL >> 0) & 0xFFFFFFFF), ((UART0_CTRL = (UART0_CTRL & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_CTRL_ENABLE </item>
// <item> SFDITEM_FIELD__UART0_CTRL_PARITY_EN </item>
// <item> SFDITEM_FIELD__UART0_CTRL_PARITY </item>
// <item> SFDITEM_FIELD__UART0_CTRL_PARMD </item>
// <item> SFDITEM_FIELD__UART0_CTRL_TX_FLUSH </item>
// <item> SFDITEM_FIELD__UART0_CTRL_RX_FLUSH </item>
// <item> SFDITEM_FIELD__UART0_CTRL_BITACC </item>
// <item> SFDITEM_FIELD__UART0_CTRL_CHAR_SIZE </item>
// <item> SFDITEM_FIELD__UART0_CTRL_STOPBITS </item>
// <item> SFDITEM_FIELD__UART0_CTRL_FLOW_CTRL </item>
// <item> SFDITEM_FIELD__UART0_CTRL_FLOW_POL </item>
// <item> SFDITEM_FIELD__UART0_CTRL_NULL_MODEM </item>
// <item> SFDITEM_FIELD__UART0_CTRL_BREAK </item>
// <item> SFDITEM_FIELD__UART0_CTRL_CLKSEL </item>
// <item> SFDITEM_FIELD__UART0_CTRL_RX_TO </item>
// </rtree>
//
// ------------------------ Register Item Address: UART0_THRESH_CTRL ----------------------------
// SVD Line: 9926
unsigned int UART0_THRESH_CTRL __AT (0x40042004);
// ---------------------- Field Item: UART0_THRESH_CTRL_RX_FIFO_THRESH --------------------------
// SVD Line: 9932
// <item> SFDITEM_FIELD__UART0_THRESH_CTRL_RX_FIFO_THRESH
// <name> RX_FIFO_THRESH </name>
// <rw>
// <i> [Bits 5..0] RW (@ 0x40042004) RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_THRESH_CTRL >> 0) & 0x3F), ((UART0_THRESH_CTRL = (UART0_THRESH_CTRL & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------- Field Item: UART0_THRESH_CTRL_TX_FIFO_THRESH --------------------------
// SVD Line: 9938
// <item> SFDITEM_FIELD__UART0_THRESH_CTRL_TX_FIFO_THRESH
// <name> TX_FIFO_THRESH </name>
// <rw>
// <i> [Bits 13..8] RW (@ 0x40042004) TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_THRESH_CTRL >> 8) & 0x3F), ((UART0_THRESH_CTRL = (UART0_THRESH_CTRL & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------- Field Item: UART0_THRESH_CTRL_RTS_FIFO_THRESH -------------------------
// SVD Line: 9944
// <item> SFDITEM_FIELD__UART0_THRESH_CTRL_RTS_FIFO_THRESH
// <name> RTS_FIFO_THRESH </name>
// <rw>
// <i> [Bits 21..16] RW (@ 0x40042004) RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_THRESH_CTRL >> 16) & 0x3F), ((UART0_THRESH_CTRL = (UART0_THRESH_CTRL & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: UART0_THRESH_CTRL -------------------------------
// SVD Line: 9926
// <rtree> SFDITEM_REG__UART0_THRESH_CTRL
// <name> THRESH_CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40042004) Threshold Control register. </i>
// <loc> ( (unsigned int)((UART0_THRESH_CTRL >> 0) & 0xFFFFFFFF), ((UART0_THRESH_CTRL = (UART0_THRESH_CTRL & ~(0x3F3F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F3F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_THRESH_CTRL_RX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART0_THRESH_CTRL_TX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART0_THRESH_CTRL_RTS_FIFO_THRESH </item>
// </rtree>
//
// --------------------------- Register Item Address: UART0_STATUS ------------------------------
// SVD Line: 9952
unsigned int UART0_STATUS __AT (0x40042008);
// ---------------------------- Field Item: UART0_STATUS_TX_BUSY --------------------------------
// SVD Line: 9959
// <item> SFDITEM_FIELD__UART0_STATUS_TX_BUSY
// <name> TX_BUSY </name>
// <r>
// <i> [Bit 0] RO (@ 0x40042008) Read-only flag indicating the UART transmit status. </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.0..0> TX_BUSY
// </check>
// </item>
//
// ---------------------------- Field Item: UART0_STATUS_RX_BUSY --------------------------------
// SVD Line: 9966
// <item> SFDITEM_FIELD__UART0_STATUS_RX_BUSY
// <name> RX_BUSY </name>
// <r>
// <i> [Bit 1] RO (@ 0x40042008) Read-only flag indicating the UARTreceiver status. </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.1..1> RX_BUSY
// </check>
// </item>
//
// ----------------------------- Field Item: UART0_STATUS_PARITY --------------------------------
// SVD Line: 9973
// <item> SFDITEM_FIELD__UART0_STATUS_PARITY
// <name> PARITY </name>
// <r>
// <i> [Bit 2] RO (@ 0x40042008) 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.2..2> PARITY
// </check>
// </item>
//
// ----------------------------- Field Item: UART0_STATUS_BREAK ---------------------------------
// SVD Line: 9980
// <item> SFDITEM_FIELD__UART0_STATUS_BREAK
// <name> BREAK </name>
// <r>
// <i> [Bit 3] RO (@ 0x40042008) Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.3..3> BREAK
// </check>
// </item>
//
// ---------------------------- Field Item: UART0_STATUS_RX_EMPTY -------------------------------
// SVD Line: 9987
// <item> SFDITEM_FIELD__UART0_STATUS_RX_EMPTY
// <name> RX_EMPTY </name>
// <r>
// <i> [Bit 4] RO (@ 0x40042008) Read-only flag indicating the RX FIFO state. </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.4..4> RX_EMPTY
// </check>
// </item>
//
// ---------------------------- Field Item: UART0_STATUS_RX_FULL --------------------------------
// SVD Line: 9994
// <item> SFDITEM_FIELD__UART0_STATUS_RX_FULL
// <name> RX_FULL </name>
// <r>
// <i> [Bit 5] RO (@ 0x40042008) Read-only flag indicating the RX FIFO state. </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.5..5> RX_FULL
// </check>
// </item>
//
// ---------------------------- Field Item: UART0_STATUS_TX_EMPTY -------------------------------
// SVD Line: 10001
// <item> SFDITEM_FIELD__UART0_STATUS_TX_EMPTY
// <name> TX_EMPTY </name>
// <r>
// <i> [Bit 6] RO (@ 0x40042008) Read-only flag indicating the TX FIFO state. </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.6..6> TX_EMPTY
// </check>
// </item>
//
// ---------------------------- Field Item: UART0_STATUS_TX_FULL --------------------------------
// SVD Line: 10008
// <item> SFDITEM_FIELD__UART0_STATUS_TX_FULL
// <name> TX_FULL </name>
// <r>
// <i> [Bit 7] RO (@ 0x40042008) Read-only flag indicating the TX FIFO state. </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.7..7> TX_FULL
// </check>
// </item>
//
// -------------------------- Field Item: UART0_STATUS_RX_FIFO_CNT ------------------------------
// SVD Line: 10015
// <item> SFDITEM_FIELD__UART0_STATUS_RX_FIFO_CNT
// <name> RX_FIFO_CNT </name>
// <r>
// <i> [Bits 13..8] RO (@ 0x40042008) Indicates the number of bytes currently in the RX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_STATUS >> 8) & 0x3F) ) </loc>
// </edit>
// </item>
//
// -------------------------- Field Item: UART0_STATUS_TX_FIFO_CNT ------------------------------
// SVD Line: 10022
// <item> SFDITEM_FIELD__UART0_STATUS_TX_FIFO_CNT
// <name> TX_FIFO_CNT </name>
// <r>
// <i> [Bits 21..16] RO (@ 0x40042008) Indicates the number of bytes currently in the TX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_STATUS >> 16) & 0x3F) ) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: UART0_STATUS_RX_TO ---------------------------------
// SVD Line: 10029
// <item> SFDITEM_FIELD__UART0_STATUS_RX_TO
// <name> RX_TO </name>
// <r>
// <i> [Bit 24] RO (@ 0x40042008) RX Timeout status. </i>
// <check>
// <loc> ( (unsigned int) UART0_STATUS ) </loc>
// <o.24..24> RX_TO
// </check>
// </item>
//
// ------------------------------ Register RTree: UART0_STATUS ----------------------------------
// SVD Line: 9952
// <rtree> SFDITEM_REG__UART0_STATUS
// <name> STATUS </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40042008) Status Register. </i>
// <loc> ( (unsigned int)((UART0_STATUS >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__UART0_STATUS_TX_BUSY </item>
// <item> SFDITEM_FIELD__UART0_STATUS_RX_BUSY </item>
// <item> SFDITEM_FIELD__UART0_STATUS_PARITY </item>
// <item> SFDITEM_FIELD__UART0_STATUS_BREAK </item>
// <item> SFDITEM_FIELD__UART0_STATUS_RX_EMPTY </item>
// <item> SFDITEM_FIELD__UART0_STATUS_RX_FULL </item>
// <item> SFDITEM_FIELD__UART0_STATUS_TX_EMPTY </item>
// <item> SFDITEM_FIELD__UART0_STATUS_TX_FULL </item>
// <item> SFDITEM_FIELD__UART0_STATUS_RX_FIFO_CNT </item>
// <item> SFDITEM_FIELD__UART0_STATUS_TX_FIFO_CNT </item>
// <item> SFDITEM_FIELD__UART0_STATUS_RX_TO </item>
// </rtree>
//
// --------------------------- Register Item Address: UART0_INT_EN ------------------------------
// SVD Line: 10038
unsigned int UART0_INT_EN __AT (0x4004200C);
// ------------------------- Field Item: UART0_INT_EN_RX_FRAME_ERROR ----------------------------
// SVD Line: 10044
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_FRAME_ERROR
// <name> RX_FRAME_ERROR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4004200C) Enable for RX Frame Error Interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.0..0> RX_FRAME_ERROR
// </check>
// </item>
//
// ------------------------ Field Item: UART0_INT_EN_RX_PARITY_ERROR ----------------------------
// SVD Line: 10050
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_PARITY_ERROR
// <name> RX_PARITY_ERROR </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4004200C) Enable for RX Parity Error interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.1..1> RX_PARITY_ERROR
// </check>
// </item>
//
// --------------------------- Field Item: UART0_INT_EN_CTS_CHANGE ------------------------------
// SVD Line: 10056
// <item> SFDITEM_FIELD__UART0_INT_EN_CTS_CHANGE
// <name> CTS_CHANGE </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4004200C) Enable for CTS signal change interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.2..2> CTS_CHANGE
// </check>
// </item>
//
// --------------------------- Field Item: UART0_INT_EN_RX_OVERRUN ------------------------------
// SVD Line: 10062
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_OVERRUN
// <name> RX_OVERRUN </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4004200C) Enable for RX FIFO OVerrun interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.3..3> RX_OVERRUN
// </check>
// </item>
//
// ------------------------- Field Item: UART0_INT_EN_RX_FIFO_THRESH ----------------------------
// SVD Line: 10068
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_FIFO_THRESH
// <name> RX_FIFO_THRESH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4004200C) Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.4..4> RX_FIFO_THRESH
// </check>
// </item>
//
// ---------------------- Field Item: UART0_INT_EN_TX_FIFO_ALMOST_EMPTY -------------------------
// SVD Line: 10074
// <item> SFDITEM_FIELD__UART0_INT_EN_TX_FIFO_ALMOST_EMPTY
// <name> TX_FIFO_ALMOST_EMPTY </name>
// <rw>
// <i> [Bit 5] RW (@ 0x4004200C) Enable for interrupt when TX FIFO has only one byte remaining. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.5..5> TX_FIFO_ALMOST_EMPTY
// </check>
// </item>
//
// ------------------------- Field Item: UART0_INT_EN_TX_FIFO_THRESH ----------------------------
// SVD Line: 10080
// <item> SFDITEM_FIELD__UART0_INT_EN_TX_FIFO_THRESH
// <name> TX_FIFO_THRESH </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4004200C) Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.6..6> TX_FIFO_THRESH
// </check>
// </item>
//
// ----------------------------- Field Item: UART0_INT_EN_BREAK ---------------------------------
// SVD Line: 10086
// <item> SFDITEM_FIELD__UART0_INT_EN_BREAK
// <name> BREAK </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4004200C) Enable for received BREAK character interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.7..7> BREAK
// </check>
// </item>
//
// --------------------------- Field Item: UART0_INT_EN_RX_TIMEOUT ------------------------------
// SVD Line: 10092
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_TIMEOUT
// <name> RX_TIMEOUT </name>
// <rw>
// <i> [Bit 8] RW (@ 0x4004200C) Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.8..8> RX_TIMEOUT
// </check>
// </item>
//
// --------------------------- Field Item: UART0_INT_EN_LAST_BREAK ------------------------------
// SVD Line: 10098
// <item> SFDITEM_FIELD__UART0_INT_EN_LAST_BREAK
// <name> LAST_BREAK </name>
// <rw>
// <i> [Bit 9] RW (@ 0x4004200C) Enable for Last break character interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_EN ) </loc>
// <o.9..9> LAST_BREAK
// </check>
// </item>
//
// ------------------------------ Register RTree: UART0_INT_EN ----------------------------------
// SVD Line: 10038
// <rtree> SFDITEM_REG__UART0_INT_EN
// <name> INT_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4004200C) Interrupt Enable Register. </i>
// <loc> ( (unsigned int)((UART0_INT_EN >> 0) & 0xFFFFFFFF), ((UART0_INT_EN = (UART0_INT_EN & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_FRAME_ERROR </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_PARITY_ERROR </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_CTS_CHANGE </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_OVERRUN </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_TX_FIFO_ALMOST_EMPTY </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_TX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_BREAK </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_RX_TIMEOUT </item>
// <item> SFDITEM_FIELD__UART0_INT_EN_LAST_BREAK </item>
// </rtree>
//
// --------------------------- Register Item Address: UART0_INT_FL ------------------------------
// SVD Line: 10106
unsigned int UART0_INT_FL __AT (0x40042010);
// ------------------------- Field Item: UART0_INT_FL_RX_FRAME_ERROR ----------------------------
// SVD Line: 10113
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_FRAME_ERROR
// <name> RX_FRAME_ERROR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40042010) FLAG for RX Frame Error Interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.0..0> RX_FRAME_ERROR
// </check>
// </item>
//
// ------------------------ Field Item: UART0_INT_FL_RX_PARITY_ERROR ----------------------------
// SVD Line: 10119
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_PARITY_ERROR
// <name> RX_PARITY_ERROR </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40042010) FLAG for RX Parity Error interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.1..1> RX_PARITY_ERROR
// </check>
// </item>
//
// --------------------------- Field Item: UART0_INT_FL_CTS_CHANGE ------------------------------
// SVD Line: 10125
// <item> SFDITEM_FIELD__UART0_INT_FL_CTS_CHANGE
// <name> CTS_CHANGE </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40042010) FLAG for CTS signal change interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.2..2> CTS_CHANGE
// </check>
// </item>
//
// --------------------------- Field Item: UART0_INT_FL_RX_OVERRUN ------------------------------
// SVD Line: 10131
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_OVERRUN
// <name> RX_OVERRUN </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40042010) FLAG for RX FIFO Overrun interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.3..3> RX_OVERRUN
// </check>
// </item>
//
// ------------------------- Field Item: UART0_INT_FL_RX_FIFO_THRESH ----------------------------
// SVD Line: 10137
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_FIFO_THRESH
// <name> RX_FIFO_THRESH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40042010) FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.4..4> RX_FIFO_THRESH
// </check>
// </item>
//
// ---------------------- Field Item: UART0_INT_FL_TX_FIFO_ALMOST_EMPTY -------------------------
// SVD Line: 10143
// <item> SFDITEM_FIELD__UART0_INT_FL_TX_FIFO_ALMOST_EMPTY
// <name> TX_FIFO_ALMOST_EMPTY </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40042010) FLAG for interrupt when TX FIFO has only one byte remaining. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.5..5> TX_FIFO_ALMOST_EMPTY
// </check>
// </item>
//
// ------------------------- Field Item: UART0_INT_FL_TX_FIFO_THRESH ----------------------------
// SVD Line: 10149
// <item> SFDITEM_FIELD__UART0_INT_FL_TX_FIFO_THRESH
// <name> TX_FIFO_THRESH </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40042010) FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.6..6> TX_FIFO_THRESH
// </check>
// </item>
//
// ----------------------------- Field Item: UART0_INT_FL_BREAK ---------------------------------
// SVD Line: 10155
// <item> SFDITEM_FIELD__UART0_INT_FL_BREAK
// <name> BREAK </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40042010) FLAG for received BREAK character interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.7..7> BREAK
// </check>
// </item>
//
// --------------------------- Field Item: UART0_INT_FL_RX_TIMEOUT ------------------------------
// SVD Line: 10161
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_TIMEOUT
// <name> RX_TIMEOUT </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40042010) FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.8..8> RX_TIMEOUT
// </check>
// </item>
//
// --------------------------- Field Item: UART0_INT_FL_LAST_BREAK ------------------------------
// SVD Line: 10167
// <item> SFDITEM_FIELD__UART0_INT_FL_LAST_BREAK
// <name> LAST_BREAK </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40042010) FLAG for Last break character interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART0_INT_FL ) </loc>
// <o.9..9> LAST_BREAK
// </check>
// </item>
//
// ------------------------------ Register RTree: UART0_INT_FL ----------------------------------
// SVD Line: 10106
// <rtree> SFDITEM_REG__UART0_INT_FL
// <name> INT_FL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40042010) Interrupt Status Flags. </i>
// <loc> ( (unsigned int)((UART0_INT_FL >> 0) & 0xFFFFFFFF), ((UART0_INT_FL = (UART0_INT_FL & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_FRAME_ERROR </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_PARITY_ERROR </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_CTS_CHANGE </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_OVERRUN </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_TX_FIFO_ALMOST_EMPTY </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_TX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_BREAK </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_RX_TIMEOUT </item>
// <item> SFDITEM_FIELD__UART0_INT_FL_LAST_BREAK </item>
// </rtree>
//
// --------------------------- Register Item Address: UART0_BAUD0 -------------------------------
// SVD Line: 10175
unsigned int UART0_BAUD0 __AT (0x40042014);
// ------------------------------ Field Item: UART0_BAUD0_IBAUD ---------------------------------
// SVD Line: 10181
// <item> SFDITEM_FIELD__UART0_BAUD0_IBAUD
// <name> IBAUD </name>
// <rw>
// <i> [Bits 11..0] RW (@ 0x40042014) Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). </i>
// <edit>
// <loc> ( (unsigned short)((UART0_BAUD0 >> 0) & 0xFFF), ((UART0_BAUD0 = (UART0_BAUD0 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: UART0_BAUD0_FACTOR ---------------------------------
// SVD Line: 10187
// <item> SFDITEM_FIELD__UART0_BAUD0_FACTOR
// <name> FACTOR </name>
// <rw>
// <i> [Bits 17..16] RW (@ 0x40042014) \nFACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.\n0 : 128 = Baud Factor 128\n1 : 64 = Baud Factor 64\n2 : 32 = Baud Factor 32\n3 : 16 = Baud Factor 16 </i>
// <combo>
// <loc> ( (unsigned int) UART0_BAUD0 ) </loc>
// <o.17..16> FACTOR
// <0=> 0: 128 = Baud Factor 128
// <1=> 1: 64 = Baud Factor 64
// <2=> 2: 32 = Baud Factor 32
// <3=> 3: 16 = Baud Factor 16
// </combo>
// </item>
//
// ------------------------------- Register RTree: UART0_BAUD0 ----------------------------------
// SVD Line: 10175
// <rtree> SFDITEM_REG__UART0_BAUD0
// <name> BAUD0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40042014) Baud rate register. Integer portion. </i>
// <loc> ( (unsigned int)((UART0_BAUD0 >> 0) & 0xFFFFFFFF), ((UART0_BAUD0 = (UART0_BAUD0 & ~(0x30FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_BAUD0_IBAUD </item>
// <item> SFDITEM_FIELD__UART0_BAUD0_FACTOR </item>
// </rtree>
//
// --------------------------- Register Item Address: UART0_BAUD1 -------------------------------
// SVD Line: 10217
unsigned int UART0_BAUD1 __AT (0x40042018);
// ------------------------------ Field Item: UART0_BAUD1_DBAUD ---------------------------------
// SVD Line: 10223
// <item> SFDITEM_FIELD__UART0_BAUD1_DBAUD
// <name> DBAUD </name>
// <rw>
// <i> [Bits 11..0] RW (@ 0x40042018) Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128. </i>
// <edit>
// <loc> ( (unsigned short)((UART0_BAUD1 >> 0) & 0xFFF), ((UART0_BAUD1 = (UART0_BAUD1 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: UART0_BAUD1 ----------------------------------
// SVD Line: 10217
// <rtree> SFDITEM_REG__UART0_BAUD1
// <name> BAUD1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40042018) Baud rate register. Decimal Setting. </i>
// <loc> ( (unsigned int)((UART0_BAUD1 >> 0) & 0xFFFFFFFF), ((UART0_BAUD1 = (UART0_BAUD1 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_BAUD1_DBAUD </item>
// </rtree>
//
// ---------------------------- Register Item Address: UART0_FIFO -------------------------------
// SVD Line: 10231
unsigned int UART0_FIFO __AT (0x4004201C);
// ------------------------------- Field Item: UART0_FIFO_FIFO ----------------------------------
// SVD Line: 10237
// <item> SFDITEM_FIELD__UART0_FIFO_FIFO
// <name> FIFO </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x4004201C) Load/unload location for TX and RX FIFO buffers. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_FIFO >> 0) & 0xFF), ((UART0_FIFO = (UART0_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: UART0_FIFO -----------------------------------
// SVD Line: 10231
// <rtree> SFDITEM_REG__UART0_FIFO
// <name> FIFO </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4004201C) FIFO Data buffer. </i>
// <loc> ( (unsigned int)((UART0_FIFO >> 0) & 0xFFFFFFFF), ((UART0_FIFO = (UART0_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_FIFO_FIFO </item>
// </rtree>
//
// ---------------------------- Register Item Address: UART0_DMA --------------------------------
// SVD Line: 10245
unsigned int UART0_DMA __AT (0x40042020);
// ----------------------------- Field Item: UART0_DMA_TXDMA_EN ---------------------------------
// SVD Line: 10251
// <item> SFDITEM_FIELD__UART0_DMA_TXDMA_EN
// <name> TXDMA_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40042020) \nTX DMA channel enable.\n0 : dis = DMA is disabled\n1 : en = DMA is enabled </i>
// <combo>
// <loc> ( (unsigned int) UART0_DMA ) </loc>
// <o.0..0> TXDMA_EN
// <0=> 0: dis = DMA is disabled
// <1=> 1: en = DMA is enabled
// </combo>
// </item>
//
// ----------------------------- Field Item: UART0_DMA_RXDMA_EN ---------------------------------
// SVD Line: 10269
// <item> SFDITEM_FIELD__UART0_DMA_RXDMA_EN
// <name> RXDMA_EN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40042020) \nRX DMA channel enable.\n0 : dis = DMA is disabled\n1 : en = DMA is enabled </i>
// <combo>
// <loc> ( (unsigned int) UART0_DMA ) </loc>
// <o.1..1> RXDMA_EN
// <0=> 0: dis = DMA is disabled
// <1=> 1: en = DMA is enabled
// </combo>
// </item>
//
// ---------------------------- Field Item: UART0_DMA_TXDMA_LEVEL -------------------------------
// SVD Line: 10287
// <item> SFDITEM_FIELD__UART0_DMA_TXDMA_LEVEL
// <name> TXDMA_LEVEL </name>
// <rw>
// <i> [Bits 13..8] RW (@ 0x40042020) TX threshold for DMA transmission. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_DMA >> 8) & 0x3F), ((UART0_DMA = (UART0_DMA & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: UART0_DMA_RXDMA_LEVEL -------------------------------
// SVD Line: 10293
// <item> SFDITEM_FIELD__UART0_DMA_RXDMA_LEVEL
// <name> RXDMA_LEVEL </name>
// <rw>
// <i> [Bits 21..16] RW (@ 0x40042020) RX threshold for DMA transmission. </i>
// <edit>
// <loc> ( (unsigned char)((UART0_DMA >> 16) & 0x3F), ((UART0_DMA = (UART0_DMA & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: UART0_DMA -----------------------------------
// SVD Line: 10245
// <rtree> SFDITEM_REG__UART0_DMA
// <name> DMA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40042020) DMA Configuration. </i>
// <loc> ( (unsigned int)((UART0_DMA >> 0) & 0xFFFFFFFF), ((UART0_DMA = (UART0_DMA & ~(0x3F3F03UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F03) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_DMA_TXDMA_EN </item>
// <item> SFDITEM_FIELD__UART0_DMA_RXDMA_EN </item>
// <item> SFDITEM_FIELD__UART0_DMA_TXDMA_LEVEL </item>
// <item> SFDITEM_FIELD__UART0_DMA_RXDMA_LEVEL </item>
// </rtree>
//
// -------------------------- Register Item Address: UART0_TX_FIFO ------------------------------
// SVD Line: 10301
unsigned int UART0_TX_FIFO __AT (0x40042024);
// ----------------------------- Field Item: UART0_TX_FIFO_DATA ---------------------------------
// SVD Line: 10307
// <item> SFDITEM_FIELD__UART0_TX_FIFO_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 6..0] RW (@ 0x40042024) Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned). </i>
// <edit>
// <loc> ( (unsigned char)((UART0_TX_FIFO >> 0) & 0x7F), ((UART0_TX_FIFO = (UART0_TX_FIFO & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: UART0_TX_FIFO ---------------------------------
// SVD Line: 10301
// <rtree> SFDITEM_REG__UART0_TX_FIFO
// <name> TX_FIFO </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40042024) Transmit FIFO Status register. </i>
// <loc> ( (unsigned int)((UART0_TX_FIFO >> 0) & 0xFFFFFFFF), ((UART0_TX_FIFO = (UART0_TX_FIFO & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART0_TX_FIFO_DATA </item>
// </rtree>
//
// --------------------------------- Peripheral View: UART0 -------------------------------------
// SVD Line: 9647
// <view> UART0
// <name> UART0 </name>
// <item> SFDITEM_REG__UART0_CTRL </item>
// <item> SFDITEM_REG__UART0_THRESH_CTRL </item>
// <item> SFDITEM_REG__UART0_STATUS </item>
// <item> SFDITEM_REG__UART0_INT_EN </item>
// <item> SFDITEM_REG__UART0_INT_FL </item>
// <item> SFDITEM_REG__UART0_BAUD0 </item>
// <item> SFDITEM_REG__UART0_BAUD1 </item>
// <item> SFDITEM_REG__UART0_FIFO </item>
// <item> SFDITEM_REG__UART0_DMA </item>
// <item> SFDITEM_REG__UART0_TX_FIFO </item>
// </view>
//
// ---------------------------- Register Item Address: UART1_CTRL -------------------------------
// SVD Line: 9662
unsigned int UART1_CTRL __AT (0x40043000);
// ------------------------------ Field Item: UART1_CTRL_ENABLE ---------------------------------
// SVD Line: 9668
// <item> SFDITEM_FIELD__UART1_CTRL_ENABLE
// <name> ENABLE </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40043000) \nUART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.\n0 : dis = UART disabled. FIFOs are flushed. Clock is gated off for power savings.\n1 : en = UART enabled. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.0..0> ENABLE
// <0=> 0: dis = UART disabled. FIFOs are flushed. Clock is gated off for power savings.
// <1=> 1: en = UART enabled.
// </combo>
// </item>
//
// ---------------------------- Field Item: UART1_CTRL_PARITY_EN --------------------------------
// SVD Line: 9686
// <item> SFDITEM_FIELD__UART1_CTRL_PARITY_EN
// <name> PARITY_EN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40043000) \nEnable/disable Parity bit (9th character).\n0 : dis = No Parity\n1 : en = Parity enabled as 9th bit </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.1..1> PARITY_EN
// <0=> 0: dis = No Parity
// <1=> 1: en = Parity enabled as 9th bit
// </combo>
// </item>
//
// ------------------------------ Field Item: UART1_CTRL_PARITY ---------------------------------
// SVD Line: 9704
// <item> SFDITEM_FIELD__UART1_CTRL_PARITY
// <name> PARITY </name>
// <rw>
// <i> [Bits 3..2] RW (@ 0x40043000) \nWhen PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1; Space parity = always 0.\n0 : Even = Even parity selected.\n1 : ODD = Odd parity selected.\n2 : MARK = Mark parity selected.\n3 : SPACE = Space parity selected. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.3..2> PARITY
// <0=> 0: Even = Even parity selected.
// <1=> 1: ODD = Odd parity selected.
// <2=> 2: MARK = Mark parity selected.
// <3=> 3: SPACE = Space parity selected.
// </combo>
// </item>
//
// ------------------------------ Field Item: UART1_CTRL_PARMD ----------------------------------
// SVD Line: 9733
// <item> SFDITEM_FIELD__UART1_CTRL_PARMD
// <name> PARMD </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40043000) \nSelects parity based on 1s or 0s count (when PARITY_EN=1).\n0 : 1 = Parity calculation is based on number of 1s in frame.\n1 : 0 = Parity calculation is based on number of 0s in frame. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.4..4> PARMD
// <0=> 0: 1 = Parity calculation is based on number of 1s in frame.
// <1=> 1: 0 = Parity calculation is based on number of 0s in frame.
// </combo>
// </item>
//
// ----------------------------- Field Item: UART1_CTRL_TX_FLUSH --------------------------------
// SVD Line: 9751
// <item> SFDITEM_FIELD__UART1_CTRL_TX_FLUSH
// <name> TX_FLUSH </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40043000) Flushes the TX FIFO buffer. </i>
// <check>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.5..5> TX_FLUSH
// </check>
// </item>
//
// ----------------------------- Field Item: UART1_CTRL_RX_FLUSH --------------------------------
// SVD Line: 9757
// <item> SFDITEM_FIELD__UART1_CTRL_RX_FLUSH
// <name> RX_FLUSH </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40043000) Flushes the RX FIFO buffer. </i>
// <check>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.6..6> RX_FLUSH
// </check>
// </item>
//
// ------------------------------ Field Item: UART1_CTRL_BITACC ---------------------------------
// SVD Line: 9763
// <item> SFDITEM_FIELD__UART1_CTRL_BITACC
// <name> BITACC </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40043000) \nIf set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.\n0 : FRAME = Frame accuracy.\n1 : BIT = Bit accuracy. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.7..7> BITACC
// <0=> 0: FRAME = Frame accuracy.
// <1=> 1: BIT = Bit accuracy.
// </combo>
// </item>
//
// ---------------------------- Field Item: UART1_CTRL_CHAR_SIZE --------------------------------
// SVD Line: 9781
// <item> SFDITEM_FIELD__UART1_CTRL_CHAR_SIZE
// <name> CHAR_SIZE </name>
// <rw>
// <i> [Bits 9..8] RW (@ 0x40043000) \nSelects UART character size.\n0 : 5 = 5 bits.\n1 : 6 = 6 bits.\n2 : 7 = 7 bits.\n3 : 8 = 8 bits. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.9..8> CHAR_SIZE
// <0=> 0: 5 = 5 bits.
// <1=> 1: 6 = 6 bits.
// <2=> 2: 7 = 7 bits.
// <3=> 3: 8 = 8 bits.
// </combo>
// </item>
//
// ----------------------------- Field Item: UART1_CTRL_STOPBITS --------------------------------
// SVD Line: 9809
// <item> SFDITEM_FIELD__UART1_CTRL_STOPBITS
// <name> STOPBITS </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40043000) \nSelects the number of stop bits that will be generated.\n0 : 1 = 1 stop bit.\n1 : 1_5 = 1.5 stop bits. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.10..10> STOPBITS
// <0=> 0: 1 = 1 stop bit.
// <1=> 1: 1_5 = 1.5 stop bits.
// </combo>
// </item>
//
// ---------------------------- Field Item: UART1_CTRL_FLOW_CTRL --------------------------------
// SVD Line: 9827
// <item> SFDITEM_FIELD__UART1_CTRL_FLOW_CTRL
// <name> FLOW_CTRL </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40043000) \nEnables/disables hardware flow control.\n0 : dis = HW Flow Control disabled\n1 : en = HW Flow Control with RTS/CTS enabled </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.11..11> FLOW_CTRL
// <0=> 0: dis = HW Flow Control disabled
// <1=> 1: en = HW Flow Control with RTS/CTS enabled
// </combo>
// </item>
//
// ----------------------------- Field Item: UART1_CTRL_FLOW_POL --------------------------------
// SVD Line: 9845
// <item> SFDITEM_FIELD__UART1_CTRL_FLOW_POL
// <name> FLOW_POL </name>
// <rw>
// <i> [Bit 12] RW (@ 0x40043000) \nRTS/CTS polarity.\n0 : 0 = RTS/CTS asserted is logic 0.\n1 : 1 = RTS/CTS asserted is logic 1. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.12..12> FLOW_POL
// <0=> 0: 0 = RTS/CTS asserted is logic 0.
// <1=> 1: 1 = RTS/CTS asserted is logic 1.
// </combo>
// </item>
//
// ---------------------------- Field Item: UART1_CTRL_NULL_MODEM -------------------------------
// SVD Line: 9863
// <item> SFDITEM_FIELD__UART1_CTRL_NULL_MODEM
// <name> NULL_MODEM </name>
// <rw>
// <i> [Bit 13] RW (@ 0x40043000) \nNULL Modem Support (RTS/CTS and TXD/RXD swap).\n0 : DIS = Direct convention.\n1 : EN = Null Modem Mode. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.13..13> NULL_MODEM
// <0=> 0: DIS = Direct convention.
// <1=> 1: EN = Null Modem Mode.
// </combo>
// </item>
//
// ------------------------------ Field Item: UART1_CTRL_BREAK ----------------------------------
// SVD Line: 9881
// <item> SFDITEM_FIELD__UART1_CTRL_BREAK
// <name> BREAK </name>
// <rw>
// <i> [Bit 14] RW (@ 0x40043000) \nBreak control bit. It causes a break condition to be transmitted to receiving UART.\n0 : DIS = Break characters are not generated.\n1 : EN = Break characters are sent(all the bits are at '0' including start/parity/stop). </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.14..14> BREAK
// <0=> 0: DIS = Break characters are not generated.
// <1=> 1: EN = Break characters are sent(all the bits are at '0' including start/parity/stop).
// </combo>
// </item>
//
// ------------------------------ Field Item: UART1_CTRL_CLKSEL ---------------------------------
// SVD Line: 9899
// <item> SFDITEM_FIELD__UART1_CTRL_CLKSEL
// <name> CLKSEL </name>
// <rw>
// <i> [Bit 15] RW (@ 0x40043000) \nBaud Rate Clock Source Select. Selects the baud rate clock.\n0 : SYSTEM = System clock.\n1 : ALTERNATE = Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. </i>
// <combo>
// <loc> ( (unsigned int) UART1_CTRL ) </loc>
// <o.15..15> CLKSEL
// <0=> 0: SYSTEM = System clock.
// <1=> 1: ALTERNATE = Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.
// </combo>
// </item>
//
// ------------------------------ Field Item: UART1_CTRL_RX_TO ----------------------------------
// SVD Line: 9917
// <item> SFDITEM_FIELD__UART1_CTRL_RX_TO
// <name> RX_TO </name>
// <rw>
// <i> [Bits 23..16] RW (@ 0x40043000) RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_CTRL >> 16) & 0xFF), ((UART1_CTRL = (UART1_CTRL & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: UART1_CTRL -----------------------------------
// SVD Line: 9662
// <rtree> SFDITEM_REG__UART1_CTRL
// <name> CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40043000) Control Register. </i>
// <loc> ( (unsigned int)((UART1_CTRL >> 0) & 0xFFFFFFFF), ((UART1_CTRL = (UART1_CTRL & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_CTRL_ENABLE </item>
// <item> SFDITEM_FIELD__UART1_CTRL_PARITY_EN </item>
// <item> SFDITEM_FIELD__UART1_CTRL_PARITY </item>
// <item> SFDITEM_FIELD__UART1_CTRL_PARMD </item>
// <item> SFDITEM_FIELD__UART1_CTRL_TX_FLUSH </item>
// <item> SFDITEM_FIELD__UART1_CTRL_RX_FLUSH </item>
// <item> SFDITEM_FIELD__UART1_CTRL_BITACC </item>
// <item> SFDITEM_FIELD__UART1_CTRL_CHAR_SIZE </item>
// <item> SFDITEM_FIELD__UART1_CTRL_STOPBITS </item>
// <item> SFDITEM_FIELD__UART1_CTRL_FLOW_CTRL </item>
// <item> SFDITEM_FIELD__UART1_CTRL_FLOW_POL </item>
// <item> SFDITEM_FIELD__UART1_CTRL_NULL_MODEM </item>
// <item> SFDITEM_FIELD__UART1_CTRL_BREAK </item>
// <item> SFDITEM_FIELD__UART1_CTRL_CLKSEL </item>
// <item> SFDITEM_FIELD__UART1_CTRL_RX_TO </item>
// </rtree>
//
// ------------------------ Register Item Address: UART1_THRESH_CTRL ----------------------------
// SVD Line: 9926
unsigned int UART1_THRESH_CTRL __AT (0x40043004);
// ---------------------- Field Item: UART1_THRESH_CTRL_RX_FIFO_THRESH --------------------------
// SVD Line: 9932
// <item> SFDITEM_FIELD__UART1_THRESH_CTRL_RX_FIFO_THRESH
// <name> RX_FIFO_THRESH </name>
// <rw>
// <i> [Bits 5..0] RW (@ 0x40043004) RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_THRESH_CTRL >> 0) & 0x3F), ((UART1_THRESH_CTRL = (UART1_THRESH_CTRL & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------- Field Item: UART1_THRESH_CTRL_TX_FIFO_THRESH --------------------------
// SVD Line: 9938
// <item> SFDITEM_FIELD__UART1_THRESH_CTRL_TX_FIFO_THRESH
// <name> TX_FIFO_THRESH </name>
// <rw>
// <i> [Bits 13..8] RW (@ 0x40043004) TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_THRESH_CTRL >> 8) & 0x3F), ((UART1_THRESH_CTRL = (UART1_THRESH_CTRL & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------- Field Item: UART1_THRESH_CTRL_RTS_FIFO_THRESH -------------------------
// SVD Line: 9944
// <item> SFDITEM_FIELD__UART1_THRESH_CTRL_RTS_FIFO_THRESH
// <name> RTS_FIFO_THRESH </name>
// <rw>
// <i> [Bits 21..16] RW (@ 0x40043004) RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_THRESH_CTRL >> 16) & 0x3F), ((UART1_THRESH_CTRL = (UART1_THRESH_CTRL & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Register RTree: UART1_THRESH_CTRL -------------------------------
// SVD Line: 9926
// <rtree> SFDITEM_REG__UART1_THRESH_CTRL
// <name> THRESH_CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40043004) Threshold Control register. </i>
// <loc> ( (unsigned int)((UART1_THRESH_CTRL >> 0) & 0xFFFFFFFF), ((UART1_THRESH_CTRL = (UART1_THRESH_CTRL & ~(0x3F3F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F3F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_THRESH_CTRL_RX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART1_THRESH_CTRL_TX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART1_THRESH_CTRL_RTS_FIFO_THRESH </item>
// </rtree>
//
// --------------------------- Register Item Address: UART1_STATUS ------------------------------
// SVD Line: 9952
unsigned int UART1_STATUS __AT (0x40043008);
// ---------------------------- Field Item: UART1_STATUS_TX_BUSY --------------------------------
// SVD Line: 9959
// <item> SFDITEM_FIELD__UART1_STATUS_TX_BUSY
// <name> TX_BUSY </name>
// <r>
// <i> [Bit 0] RO (@ 0x40043008) Read-only flag indicating the UART transmit status. </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.0..0> TX_BUSY
// </check>
// </item>
//
// ---------------------------- Field Item: UART1_STATUS_RX_BUSY --------------------------------
// SVD Line: 9966
// <item> SFDITEM_FIELD__UART1_STATUS_RX_BUSY
// <name> RX_BUSY </name>
// <r>
// <i> [Bit 1] RO (@ 0x40043008) Read-only flag indicating the UARTreceiver status. </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.1..1> RX_BUSY
// </check>
// </item>
//
// ----------------------------- Field Item: UART1_STATUS_PARITY --------------------------------
// SVD Line: 9973
// <item> SFDITEM_FIELD__UART1_STATUS_PARITY
// <name> PARITY </name>
// <r>
// <i> [Bit 2] RO (@ 0x40043008) 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.2..2> PARITY
// </check>
// </item>
//
// ----------------------------- Field Item: UART1_STATUS_BREAK ---------------------------------
// SVD Line: 9980
// <item> SFDITEM_FIELD__UART1_STATUS_BREAK
// <name> BREAK </name>
// <r>
// <i> [Bit 3] RO (@ 0x40043008) Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.3..3> BREAK
// </check>
// </item>
//
// ---------------------------- Field Item: UART1_STATUS_RX_EMPTY -------------------------------
// SVD Line: 9987
// <item> SFDITEM_FIELD__UART1_STATUS_RX_EMPTY
// <name> RX_EMPTY </name>
// <r>
// <i> [Bit 4] RO (@ 0x40043008) Read-only flag indicating the RX FIFO state. </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.4..4> RX_EMPTY
// </check>
// </item>
//
// ---------------------------- Field Item: UART1_STATUS_RX_FULL --------------------------------
// SVD Line: 9994
// <item> SFDITEM_FIELD__UART1_STATUS_RX_FULL
// <name> RX_FULL </name>
// <r>
// <i> [Bit 5] RO (@ 0x40043008) Read-only flag indicating the RX FIFO state. </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.5..5> RX_FULL
// </check>
// </item>
//
// ---------------------------- Field Item: UART1_STATUS_TX_EMPTY -------------------------------
// SVD Line: 10001
// <item> SFDITEM_FIELD__UART1_STATUS_TX_EMPTY
// <name> TX_EMPTY </name>
// <r>
// <i> [Bit 6] RO (@ 0x40043008) Read-only flag indicating the TX FIFO state. </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.6..6> TX_EMPTY
// </check>
// </item>
//
// ---------------------------- Field Item: UART1_STATUS_TX_FULL --------------------------------
// SVD Line: 10008
// <item> SFDITEM_FIELD__UART1_STATUS_TX_FULL
// <name> TX_FULL </name>
// <r>
// <i> [Bit 7] RO (@ 0x40043008) Read-only flag indicating the TX FIFO state. </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.7..7> TX_FULL
// </check>
// </item>
//
// -------------------------- Field Item: UART1_STATUS_RX_FIFO_CNT ------------------------------
// SVD Line: 10015
// <item> SFDITEM_FIELD__UART1_STATUS_RX_FIFO_CNT
// <name> RX_FIFO_CNT </name>
// <r>
// <i> [Bits 13..8] RO (@ 0x40043008) Indicates the number of bytes currently in the RX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_STATUS >> 8) & 0x3F) ) </loc>
// </edit>
// </item>
//
// -------------------------- Field Item: UART1_STATUS_TX_FIFO_CNT ------------------------------
// SVD Line: 10022
// <item> SFDITEM_FIELD__UART1_STATUS_TX_FIFO_CNT
// <name> TX_FIFO_CNT </name>
// <r>
// <i> [Bits 21..16] RO (@ 0x40043008) Indicates the number of bytes currently in the TX FIFO. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_STATUS >> 16) & 0x3F) ) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: UART1_STATUS_RX_TO ---------------------------------
// SVD Line: 10029
// <item> SFDITEM_FIELD__UART1_STATUS_RX_TO
// <name> RX_TO </name>
// <r>
// <i> [Bit 24] RO (@ 0x40043008) RX Timeout status. </i>
// <check>
// <loc> ( (unsigned int) UART1_STATUS ) </loc>
// <o.24..24> RX_TO
// </check>
// </item>
//
// ------------------------------ Register RTree: UART1_STATUS ----------------------------------
// SVD Line: 9952
// <rtree> SFDITEM_REG__UART1_STATUS
// <name> STATUS </name>
// <r>
// <i> [Bits 31..0] RO (@ 0x40043008) Status Register. </i>
// <loc> ( (unsigned int)((UART1_STATUS >> 0) & 0xFFFFFFFF) ) </loc>
// <item> SFDITEM_FIELD__UART1_STATUS_TX_BUSY </item>
// <item> SFDITEM_FIELD__UART1_STATUS_RX_BUSY </item>
// <item> SFDITEM_FIELD__UART1_STATUS_PARITY </item>
// <item> SFDITEM_FIELD__UART1_STATUS_BREAK </item>
// <item> SFDITEM_FIELD__UART1_STATUS_RX_EMPTY </item>
// <item> SFDITEM_FIELD__UART1_STATUS_RX_FULL </item>
// <item> SFDITEM_FIELD__UART1_STATUS_TX_EMPTY </item>
// <item> SFDITEM_FIELD__UART1_STATUS_TX_FULL </item>
// <item> SFDITEM_FIELD__UART1_STATUS_RX_FIFO_CNT </item>
// <item> SFDITEM_FIELD__UART1_STATUS_TX_FIFO_CNT </item>
// <item> SFDITEM_FIELD__UART1_STATUS_RX_TO </item>
// </rtree>
//
// --------------------------- Register Item Address: UART1_INT_EN ------------------------------
// SVD Line: 10038
unsigned int UART1_INT_EN __AT (0x4004300C);
// ------------------------- Field Item: UART1_INT_EN_RX_FRAME_ERROR ----------------------------
// SVD Line: 10044
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_FRAME_ERROR
// <name> RX_FRAME_ERROR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x4004300C) Enable for RX Frame Error Interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.0..0> RX_FRAME_ERROR
// </check>
// </item>
//
// ------------------------ Field Item: UART1_INT_EN_RX_PARITY_ERROR ----------------------------
// SVD Line: 10050
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_PARITY_ERROR
// <name> RX_PARITY_ERROR </name>
// <rw>
// <i> [Bit 1] RW (@ 0x4004300C) Enable for RX Parity Error interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.1..1> RX_PARITY_ERROR
// </check>
// </item>
//
// --------------------------- Field Item: UART1_INT_EN_CTS_CHANGE ------------------------------
// SVD Line: 10056
// <item> SFDITEM_FIELD__UART1_INT_EN_CTS_CHANGE
// <name> CTS_CHANGE </name>
// <rw>
// <i> [Bit 2] RW (@ 0x4004300C) Enable for CTS signal change interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.2..2> CTS_CHANGE
// </check>
// </item>
//
// --------------------------- Field Item: UART1_INT_EN_RX_OVERRUN ------------------------------
// SVD Line: 10062
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_OVERRUN
// <name> RX_OVERRUN </name>
// <rw>
// <i> [Bit 3] RW (@ 0x4004300C) Enable for RX FIFO OVerrun interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.3..3> RX_OVERRUN
// </check>
// </item>
//
// ------------------------- Field Item: UART1_INT_EN_RX_FIFO_THRESH ----------------------------
// SVD Line: 10068
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_FIFO_THRESH
// <name> RX_FIFO_THRESH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x4004300C) Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.4..4> RX_FIFO_THRESH
// </check>
// </item>
//
// ---------------------- Field Item: UART1_INT_EN_TX_FIFO_ALMOST_EMPTY -------------------------
// SVD Line: 10074
// <item> SFDITEM_FIELD__UART1_INT_EN_TX_FIFO_ALMOST_EMPTY
// <name> TX_FIFO_ALMOST_EMPTY </name>
// <rw>
// <i> [Bit 5] RW (@ 0x4004300C) Enable for interrupt when TX FIFO has only one byte remaining. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.5..5> TX_FIFO_ALMOST_EMPTY
// </check>
// </item>
//
// ------------------------- Field Item: UART1_INT_EN_TX_FIFO_THRESH ----------------------------
// SVD Line: 10080
// <item> SFDITEM_FIELD__UART1_INT_EN_TX_FIFO_THRESH
// <name> TX_FIFO_THRESH </name>
// <rw>
// <i> [Bit 6] RW (@ 0x4004300C) Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.6..6> TX_FIFO_THRESH
// </check>
// </item>
//
// ----------------------------- Field Item: UART1_INT_EN_BREAK ---------------------------------
// SVD Line: 10086
// <item> SFDITEM_FIELD__UART1_INT_EN_BREAK
// <name> BREAK </name>
// <rw>
// <i> [Bit 7] RW (@ 0x4004300C) Enable for received BREAK character interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.7..7> BREAK
// </check>
// </item>
//
// --------------------------- Field Item: UART1_INT_EN_RX_TIMEOUT ------------------------------
// SVD Line: 10092
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_TIMEOUT
// <name> RX_TIMEOUT </name>
// <rw>
// <i> [Bit 8] RW (@ 0x4004300C) Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.8..8> RX_TIMEOUT
// </check>
// </item>
//
// --------------------------- Field Item: UART1_INT_EN_LAST_BREAK ------------------------------
// SVD Line: 10098
// <item> SFDITEM_FIELD__UART1_INT_EN_LAST_BREAK
// <name> LAST_BREAK </name>
// <rw>
// <i> [Bit 9] RW (@ 0x4004300C) Enable for Last break character interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_EN ) </loc>
// <o.9..9> LAST_BREAK
// </check>
// </item>
//
// ------------------------------ Register RTree: UART1_INT_EN ----------------------------------
// SVD Line: 10038
// <rtree> SFDITEM_REG__UART1_INT_EN
// <name> INT_EN </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4004300C) Interrupt Enable Register. </i>
// <loc> ( (unsigned int)((UART1_INT_EN >> 0) & 0xFFFFFFFF), ((UART1_INT_EN = (UART1_INT_EN & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_FRAME_ERROR </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_PARITY_ERROR </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_CTS_CHANGE </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_OVERRUN </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_TX_FIFO_ALMOST_EMPTY </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_TX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_BREAK </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_RX_TIMEOUT </item>
// <item> SFDITEM_FIELD__UART1_INT_EN_LAST_BREAK </item>
// </rtree>
//
// --------------------------- Register Item Address: UART1_INT_FL ------------------------------
// SVD Line: 10106
unsigned int UART1_INT_FL __AT (0x40043010);
// ------------------------- Field Item: UART1_INT_FL_RX_FRAME_ERROR ----------------------------
// SVD Line: 10113
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_FRAME_ERROR
// <name> RX_FRAME_ERROR </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40043010) FLAG for RX Frame Error Interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.0..0> RX_FRAME_ERROR
// </check>
// </item>
//
// ------------------------ Field Item: UART1_INT_FL_RX_PARITY_ERROR ----------------------------
// SVD Line: 10119
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_PARITY_ERROR
// <name> RX_PARITY_ERROR </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40043010) FLAG for RX Parity Error interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.1..1> RX_PARITY_ERROR
// </check>
// </item>
//
// --------------------------- Field Item: UART1_INT_FL_CTS_CHANGE ------------------------------
// SVD Line: 10125
// <item> SFDITEM_FIELD__UART1_INT_FL_CTS_CHANGE
// <name> CTS_CHANGE </name>
// <rw>
// <i> [Bit 2] RW (@ 0x40043010) FLAG for CTS signal change interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.2..2> CTS_CHANGE
// </check>
// </item>
//
// --------------------------- Field Item: UART1_INT_FL_RX_OVERRUN ------------------------------
// SVD Line: 10131
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_OVERRUN
// <name> RX_OVERRUN </name>
// <rw>
// <i> [Bit 3] RW (@ 0x40043010) FLAG for RX FIFO Overrun interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.3..3> RX_OVERRUN
// </check>
// </item>
//
// ------------------------- Field Item: UART1_INT_FL_RX_FIFO_THRESH ----------------------------
// SVD Line: 10137
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_FIFO_THRESH
// <name> RX_FIFO_THRESH </name>
// <rw>
// <i> [Bit 4] RW (@ 0x40043010) FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.4..4> RX_FIFO_THRESH
// </check>
// </item>
//
// ---------------------- Field Item: UART1_INT_FL_TX_FIFO_ALMOST_EMPTY -------------------------
// SVD Line: 10143
// <item> SFDITEM_FIELD__UART1_INT_FL_TX_FIFO_ALMOST_EMPTY
// <name> TX_FIFO_ALMOST_EMPTY </name>
// <rw>
// <i> [Bit 5] RW (@ 0x40043010) FLAG for interrupt when TX FIFO has only one byte remaining. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.5..5> TX_FIFO_ALMOST_EMPTY
// </check>
// </item>
//
// ------------------------- Field Item: UART1_INT_FL_TX_FIFO_THRESH ----------------------------
// SVD Line: 10149
// <item> SFDITEM_FIELD__UART1_INT_FL_TX_FIFO_THRESH
// <name> TX_FIFO_THRESH </name>
// <rw>
// <i> [Bit 6] RW (@ 0x40043010) FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.6..6> TX_FIFO_THRESH
// </check>
// </item>
//
// ----------------------------- Field Item: UART1_INT_FL_BREAK ---------------------------------
// SVD Line: 10155
// <item> SFDITEM_FIELD__UART1_INT_FL_BREAK
// <name> BREAK </name>
// <rw>
// <i> [Bit 7] RW (@ 0x40043010) FLAG for received BREAK character interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.7..7> BREAK
// </check>
// </item>
//
// --------------------------- Field Item: UART1_INT_FL_RX_TIMEOUT ------------------------------
// SVD Line: 10161
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_TIMEOUT
// <name> RX_TIMEOUT </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40043010) FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.8..8> RX_TIMEOUT
// </check>
// </item>
//
// --------------------------- Field Item: UART1_INT_FL_LAST_BREAK ------------------------------
// SVD Line: 10167
// <item> SFDITEM_FIELD__UART1_INT_FL_LAST_BREAK
// <name> LAST_BREAK </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40043010) FLAG for Last break character interrupt. </i>
// <check>
// <loc> ( (unsigned int) UART1_INT_FL ) </loc>
// <o.9..9> LAST_BREAK
// </check>
// </item>
//
// ------------------------------ Register RTree: UART1_INT_FL ----------------------------------
// SVD Line: 10106
// <rtree> SFDITEM_REG__UART1_INT_FL
// <name> INT_FL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40043010) Interrupt Status Flags. </i>
// <loc> ( (unsigned int)((UART1_INT_FL >> 0) & 0xFFFFFFFF), ((UART1_INT_FL = (UART1_INT_FL & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_FRAME_ERROR </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_PARITY_ERROR </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_CTS_CHANGE </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_OVERRUN </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_TX_FIFO_ALMOST_EMPTY </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_TX_FIFO_THRESH </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_BREAK </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_RX_TIMEOUT </item>
// <item> SFDITEM_FIELD__UART1_INT_FL_LAST_BREAK </item>
// </rtree>
//
// --------------------------- Register Item Address: UART1_BAUD0 -------------------------------
// SVD Line: 10175
unsigned int UART1_BAUD0 __AT (0x40043014);
// ------------------------------ Field Item: UART1_BAUD0_IBAUD ---------------------------------
// SVD Line: 10181
// <item> SFDITEM_FIELD__UART1_BAUD0_IBAUD
// <name> IBAUD </name>
// <rw>
// <i> [Bits 11..0] RW (@ 0x40043014) Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). </i>
// <edit>
// <loc> ( (unsigned short)((UART1_BAUD0 >> 0) & 0xFFF), ((UART1_BAUD0 = (UART1_BAUD0 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ----------------------------- Field Item: UART1_BAUD0_FACTOR ---------------------------------
// SVD Line: 10187
// <item> SFDITEM_FIELD__UART1_BAUD0_FACTOR
// <name> FACTOR </name>
// <rw>
// <i> [Bits 17..16] RW (@ 0x40043014) \nFACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.\n0 : 128 = Baud Factor 128\n1 : 64 = Baud Factor 64\n2 : 32 = Baud Factor 32\n3 : 16 = Baud Factor 16 </i>
// <combo>
// <loc> ( (unsigned int) UART1_BAUD0 ) </loc>
// <o.17..16> FACTOR
// <0=> 0: 128 = Baud Factor 128
// <1=> 1: 64 = Baud Factor 64
// <2=> 2: 32 = Baud Factor 32
// <3=> 3: 16 = Baud Factor 16
// </combo>
// </item>
//
// ------------------------------- Register RTree: UART1_BAUD0 ----------------------------------
// SVD Line: 10175
// <rtree> SFDITEM_REG__UART1_BAUD0
// <name> BAUD0 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40043014) Baud rate register. Integer portion. </i>
// <loc> ( (unsigned int)((UART1_BAUD0 >> 0) & 0xFFFFFFFF), ((UART1_BAUD0 = (UART1_BAUD0 & ~(0x30FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_BAUD0_IBAUD </item>
// <item> SFDITEM_FIELD__UART1_BAUD0_FACTOR </item>
// </rtree>
//
// --------------------------- Register Item Address: UART1_BAUD1 -------------------------------
// SVD Line: 10217
unsigned int UART1_BAUD1 __AT (0x40043018);
// ------------------------------ Field Item: UART1_BAUD1_DBAUD ---------------------------------
// SVD Line: 10223
// <item> SFDITEM_FIELD__UART1_BAUD1_DBAUD
// <name> DBAUD </name>
// <rw>
// <i> [Bits 11..0] RW (@ 0x40043018) Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128. </i>
// <edit>
// <loc> ( (unsigned short)((UART1_BAUD1 >> 0) & 0xFFF), ((UART1_BAUD1 = (UART1_BAUD1 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: UART1_BAUD1 ----------------------------------
// SVD Line: 10217
// <rtree> SFDITEM_REG__UART1_BAUD1
// <name> BAUD1 </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40043018) Baud rate register. Decimal Setting. </i>
// <loc> ( (unsigned int)((UART1_BAUD1 >> 0) & 0xFFFFFFFF), ((UART1_BAUD1 = (UART1_BAUD1 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_BAUD1_DBAUD </item>
// </rtree>
//
// ---------------------------- Register Item Address: UART1_FIFO -------------------------------
// SVD Line: 10231
unsigned int UART1_FIFO __AT (0x4004301C);
// ------------------------------- Field Item: UART1_FIFO_FIFO ----------------------------------
// SVD Line: 10237
// <item> SFDITEM_FIELD__UART1_FIFO_FIFO
// <name> FIFO </name>
// <rw>
// <i> [Bits 7..0] RW (@ 0x4004301C) Load/unload location for TX and RX FIFO buffers. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_FIFO >> 0) & 0xFF), ((UART1_FIFO = (UART1_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------- Register RTree: UART1_FIFO -----------------------------------
// SVD Line: 10231
// <rtree> SFDITEM_REG__UART1_FIFO
// <name> FIFO </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x4004301C) FIFO Data buffer. </i>
// <loc> ( (unsigned int)((UART1_FIFO >> 0) & 0xFFFFFFFF), ((UART1_FIFO = (UART1_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_FIFO_FIFO </item>
// </rtree>
//
// ---------------------------- Register Item Address: UART1_DMA --------------------------------
// SVD Line: 10245
unsigned int UART1_DMA __AT (0x40043020);
// ----------------------------- Field Item: UART1_DMA_TXDMA_EN ---------------------------------
// SVD Line: 10251
// <item> SFDITEM_FIELD__UART1_DMA_TXDMA_EN
// <name> TXDMA_EN </name>
// <rw>
// <i> [Bit 0] RW (@ 0x40043020) \nTX DMA channel enable.\n0 : dis = DMA is disabled\n1 : en = DMA is enabled </i>
// <combo>
// <loc> ( (unsigned int) UART1_DMA ) </loc>
// <o.0..0> TXDMA_EN
// <0=> 0: dis = DMA is disabled
// <1=> 1: en = DMA is enabled
// </combo>
// </item>
//
// ----------------------------- Field Item: UART1_DMA_RXDMA_EN ---------------------------------
// SVD Line: 10269
// <item> SFDITEM_FIELD__UART1_DMA_RXDMA_EN
// <name> RXDMA_EN </name>
// <rw>
// <i> [Bit 1] RW (@ 0x40043020) \nRX DMA channel enable.\n0 : dis = DMA is disabled\n1 : en = DMA is enabled </i>
// <combo>
// <loc> ( (unsigned int) UART1_DMA ) </loc>
// <o.1..1> RXDMA_EN
// <0=> 0: dis = DMA is disabled
// <1=> 1: en = DMA is enabled
// </combo>
// </item>
//
// ---------------------------- Field Item: UART1_DMA_TXDMA_LEVEL -------------------------------
// SVD Line: 10287
// <item> SFDITEM_FIELD__UART1_DMA_TXDMA_LEVEL
// <name> TXDMA_LEVEL </name>
// <rw>
// <i> [Bits 13..8] RW (@ 0x40043020) TX threshold for DMA transmission. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_DMA >> 8) & 0x3F), ((UART1_DMA = (UART1_DMA & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) )) </loc>
// </edit>
// </item>
//
// ---------------------------- Field Item: UART1_DMA_RXDMA_LEVEL -------------------------------
// SVD Line: 10293
// <item> SFDITEM_FIELD__UART1_DMA_RXDMA_LEVEL
// <name> RXDMA_LEVEL </name>
// <rw>
// <i> [Bits 21..16] RW (@ 0x40043020) RX threshold for DMA transmission. </i>
// <edit>
// <loc> ( (unsigned char)((UART1_DMA >> 16) & 0x3F), ((UART1_DMA = (UART1_DMA & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: UART1_DMA -----------------------------------
// SVD Line: 10245
// <rtree> SFDITEM_REG__UART1_DMA
// <name> DMA </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40043020) DMA Configuration. </i>
// <loc> ( (unsigned int)((UART1_DMA >> 0) & 0xFFFFFFFF), ((UART1_DMA = (UART1_DMA & ~(0x3F3F03UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F03) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_DMA_TXDMA_EN </item>
// <item> SFDITEM_FIELD__UART1_DMA_RXDMA_EN </item>
// <item> SFDITEM_FIELD__UART1_DMA_TXDMA_LEVEL </item>
// <item> SFDITEM_FIELD__UART1_DMA_RXDMA_LEVEL </item>
// </rtree>
//
// -------------------------- Register Item Address: UART1_TX_FIFO ------------------------------
// SVD Line: 10301
unsigned int UART1_TX_FIFO __AT (0x40043024);
// ----------------------------- Field Item: UART1_TX_FIFO_DATA ---------------------------------
// SVD Line: 10307
// <item> SFDITEM_FIELD__UART1_TX_FIFO_DATA
// <name> DATA </name>
// <rw>
// <i> [Bits 6..0] RW (@ 0x40043024) Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned). </i>
// <edit>
// <loc> ( (unsigned char)((UART1_TX_FIFO >> 0) & 0x7F), ((UART1_TX_FIFO = (UART1_TX_FIFO & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// ------------------------------ Register RTree: UART1_TX_FIFO ---------------------------------
// SVD Line: 10301
// <rtree> SFDITEM_REG__UART1_TX_FIFO
// <name> TX_FIFO </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40043024) Transmit FIFO Status register. </i>
// <loc> ( (unsigned int)((UART1_TX_FIFO >> 0) & 0xFFFFFFFF), ((UART1_TX_FIFO = (UART1_TX_FIFO & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__UART1_TX_FIFO_DATA </item>
// </rtree>
//
// --------------------------------- Peripheral View: UART1 -------------------------------------
// SVD Line: 10319
// <view> UART1
// <name> UART1 </name>
// <item> SFDITEM_REG__UART1_CTRL </item>
// <item> SFDITEM_REG__UART1_THRESH_CTRL </item>
// <item> SFDITEM_REG__UART1_STATUS </item>
// <item> SFDITEM_REG__UART1_INT_EN </item>
// <item> SFDITEM_REG__UART1_INT_FL </item>
// <item> SFDITEM_REG__UART1_BAUD0 </item>
// <item> SFDITEM_REG__UART1_BAUD1 </item>
// <item> SFDITEM_REG__UART1_FIFO </item>
// <item> SFDITEM_REG__UART1_DMA </item>
// <item> SFDITEM_REG__UART1_TX_FIFO </item>
// </view>
//
// ---------------------------- Register Item Address: WDT0_CTRL --------------------------------
// SVD Line: 10344
unsigned int WDT0_CTRL __AT (0x40003000);
// ---------------------------- Field Item: WDT0_CTRL_INT_PERIOD --------------------------------
// SVD Line: 10350
// <item> SFDITEM_FIELD__WDT0_CTRL_INT_PERIOD
// <name> INT_PERIOD </name>
// <rw>
// <i> [Bits 3..0] RW (@ 0x40003000) \nWatchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.\n0 : wdt2pow31 = 2**31 clock cycles.\n1 : wdt2pow30 = 2**30 clock cycles.\n2 : wdt2pow29 = 2**29 clock cycles.\n3 : wdt2pow28 = 2**28 clock cycles.\n4 : wdt2pow27 = 2^27 clock cycles.\n5 : wdt2pow26 = 2**26 clock cycles.\n6 : wdt2pow25 = 2**25 clock cycles.\n7 : wdt2pow24 = 2**24 clock cycles.\n8 : wdt2pow23 = 2**23 clock cycles.\n9 : wdt2pow22 = 2**22 clock cycles.\n10 : wdt2pow21 = 2**21 clock cycles.\n11 : wdt2pow20 = 2**20 clock cycles.\n12 : wdt2pow19 = 2**19 clock cycles.\n13 : wdt2pow18 = 2**18 clock cycles.\n14 : wdt2pow17 = 2**17 clock cycles.\n15 : wdt2pow16 = 2**16 clock cycles. </i>
// <combo>
// <loc> ( (unsigned int) WDT0_CTRL ) </loc>
// <o.3..0> INT_PERIOD
// <0=> 0: wdt2pow31 = 2**31 clock cycles.
// <1=> 1: wdt2pow30 = 2**30 clock cycles.
// <2=> 2: wdt2pow29 = 2**29 clock cycles.
// <3=> 3: wdt2pow28 = 2**28 clock cycles.
// <4=> 4: wdt2pow27 = 2^27 clock cycles.
// <5=> 5: wdt2pow26 = 2**26 clock cycles.
// <6=> 6: wdt2pow25 = 2**25 clock cycles.
// <7=> 7: wdt2pow24 = 2**24 clock cycles.
// <8=> 8: wdt2pow23 = 2**23 clock cycles.
// <9=> 9: wdt2pow22 = 2**22 clock cycles.
// <10=> 10: wdt2pow21 = 2**21 clock cycles.
// <11=> 11: wdt2pow20 = 2**20 clock cycles.
// <12=> 12: wdt2pow19 = 2**19 clock cycles.
// <13=> 13: wdt2pow18 = 2**18 clock cycles.
// <14=> 14: wdt2pow17 = 2**17 clock cycles.
// <15=> 15: wdt2pow16 = 2**16 clock cycles.
// </combo>
// </item>
//
// ---------------------------- Field Item: WDT0_CTRL_RST_PERIOD --------------------------------
// SVD Line: 10438
// <item> SFDITEM_FIELD__WDT0_CTRL_RST_PERIOD
// <name> RST_PERIOD </name>
// <rw>
// <i> [Bits 7..4] RW (@ 0x40003000) \nWatchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.\n0 : wdt2pow31 = 2**31 clock cycles.\n1 : wdt2pow30 = 2**30 clock cycles.\n2 : wdt2pow29 = 2**29 clock cycles.\n3 : wdt2pow28 = 2**28 clock cycles.\n4 : wdt2pow27 = 2^27 clock cycles.\n5 : wdt2pow26 = 2**26 clock cycles.\n6 : wdt2pow25 = 2**25 clock cycles.\n7 : wdt2pow24 = 2**24 clock cycles.\n8 : wdt2pow23 = 2**23 clock cycles.\n9 : wdt2pow22 = 2**22 clock cycles.\n10 : wdt2pow21 = 2**21 clock cycles.\n11 : wdt2pow20 = 2**20 clock cycles.\n12 : wdt2pow19 = 2**19 clock cycles.\n13 : wdt2pow18 = 2**18 clock cycles.\n14 : wdt2pow17 = 2**17 clock cycles.\n15 : wdt2pow16 = 2**16 clock cycles. </i>
// <combo>
// <loc> ( (unsigned int) WDT0_CTRL ) </loc>
// <o.7..4> RST_PERIOD
// <0=> 0: wdt2pow31 = 2**31 clock cycles.
// <1=> 1: wdt2pow30 = 2**30 clock cycles.
// <2=> 2: wdt2pow29 = 2**29 clock cycles.
// <3=> 3: wdt2pow28 = 2**28 clock cycles.
// <4=> 4: wdt2pow27 = 2^27 clock cycles.
// <5=> 5: wdt2pow26 = 2**26 clock cycles.
// <6=> 6: wdt2pow25 = 2**25 clock cycles.
// <7=> 7: wdt2pow24 = 2**24 clock cycles.
// <8=> 8: wdt2pow23 = 2**23 clock cycles.
// <9=> 9: wdt2pow22 = 2**22 clock cycles.
// <10=> 10: wdt2pow21 = 2**21 clock cycles.
// <11=> 11: wdt2pow20 = 2**20 clock cycles.
// <12=> 12: wdt2pow19 = 2**19 clock cycles.
// <13=> 13: wdt2pow18 = 2**18 clock cycles.
// <14=> 14: wdt2pow17 = 2**17 clock cycles.
// <15=> 15: wdt2pow16 = 2**16 clock cycles.
// </combo>
// </item>
//
// ------------------------------ Field Item: WDT0_CTRL_WDT_EN ----------------------------------
// SVD Line: 10526
// <item> SFDITEM_FIELD__WDT0_CTRL_WDT_EN
// <name> WDT_EN </name>
// <rw>
// <i> [Bit 8] RW (@ 0x40003000) \nWatchdog Timer Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) WDT0_CTRL ) </loc>
// <o.8..8> WDT_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ----------------------------- Field Item: WDT0_CTRL_INT_FLAG ---------------------------------
// SVD Line: 10544
// <item> SFDITEM_FIELD__WDT0_CTRL_INT_FLAG
// <name> INT_FLAG </name>
// <rw>
// <i> [Bit 9] RW (@ 0x40003000) \nWatchdog Timer Interrupt Flag.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. </i>
// <combo>
// <loc> ( (unsigned int) WDT0_CTRL ) </loc>
// <o.9..9> INT_FLAG
// <0=> 0: inactive = No interrupt is pending.
// <1=> 1: pending = An interrupt is pending.
// </combo>
// </item>
//
// ------------------------------ Field Item: WDT0_CTRL_INT_EN ----------------------------------
// SVD Line: 10563
// <item> SFDITEM_FIELD__WDT0_CTRL_INT_EN
// <name> INT_EN </name>
// <rw>
// <i> [Bit 10] RW (@ 0x40003000) \nWatchdog Timer Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) WDT0_CTRL ) </loc>
// <o.10..10> INT_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ------------------------------ Field Item: WDT0_CTRL_RST_EN ----------------------------------
// SVD Line: 10581
// <item> SFDITEM_FIELD__WDT0_CTRL_RST_EN
// <name> RST_EN </name>
// <rw>
// <i> [Bit 11] RW (@ 0x40003000) \nWatchdog Timer Reset Enable.\n0 : dis = Disable.\n1 : en = Enable. </i>
// <combo>
// <loc> ( (unsigned int) WDT0_CTRL ) </loc>
// <o.11..11> RST_EN
// <0=> 0: dis = Disable.
// <1=> 1: en = Enable.
// </combo>
// </item>
//
// ----------------------------- Field Item: WDT0_CTRL_RST_FLAG ---------------------------------
// SVD Line: 10599
// <item> SFDITEM_FIELD__WDT0_CTRL_RST_FLAG
// <name> RST_FLAG </name>
// <rw>
// <i> [Bit 31] RW (@ 0x40003000) \nWatchdog Timer Reset Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. </i>
// <combo>
// <loc> ( (unsigned int) WDT0_CTRL ) </loc>
// <o.31..31> RST_FLAG
// <0=> 0: noEvent = The event has not occurred.
// <1=> 1: occurred = The event has occurred.
// </combo>
// </item>
//
// -------------------------------- Register RTree: WDT0_CTRL -----------------------------------
// SVD Line: 10344
// <rtree> SFDITEM_REG__WDT0_CTRL
// <name> CTRL </name>
// <rw>
// <i> [Bits 31..0] RW (@ 0x40003000) Watchdog Timer Control Register. </i>
// <loc> ( (unsigned int)((WDT0_CTRL >> 0) & 0xFFFFFFFF), ((WDT0_CTRL = (WDT0_CTRL & ~(0x80000FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80000FFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__WDT0_CTRL_INT_PERIOD </item>
// <item> SFDITEM_FIELD__WDT0_CTRL_RST_PERIOD </item>
// <item> SFDITEM_FIELD__WDT0_CTRL_WDT_EN </item>
// <item> SFDITEM_FIELD__WDT0_CTRL_INT_FLAG </item>
// <item> SFDITEM_FIELD__WDT0_CTRL_INT_EN </item>
// <item> SFDITEM_FIELD__WDT0_CTRL_RST_EN </item>
// <item> SFDITEM_FIELD__WDT0_CTRL_RST_FLAG </item>
// </rtree>
//
// ----------------------------- Register Item Address: WDT0_RST --------------------------------
// SVD Line: 10620
unsigned int WDT0_RST __AT (0x40003004);
// ------------------------------ Field Item: WDT0_RST_WDT_RST ----------------------------------
// SVD Line: 10626
// <item> SFDITEM_FIELD__WDT0_RST_WDT_RST
// <name> WDT_RST </name>
// <w>
// <i> [Bits 7..0] WO (@ 0x40003004) Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. </i>
// <edit>
// <loc> ( (unsigned char)((WDT0_RST >> 0) & 0x0), ((WDT0_RST = (WDT0_RST & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) </loc>
// </edit>
// </item>
//
// -------------------------------- Register RTree: WDT0_RST ------------------------------------
// SVD Line: 10620
// <rtree> SFDITEM_REG__WDT0_RST
// <name> RST </name>
// <w>
// <i> [Bits 31..0] WO (@ 0x40003004) Watchdog Timer Reset Register. </i>
// <loc> ( (unsigned int)((WDT0_RST >> 0) & 0xFFFFFFFF), ((WDT0_RST = (WDT0_RST & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) </loc>
// <item> SFDITEM_FIELD__WDT0_RST_WDT_RST </item>
// </rtree>
//
// ---------------------------------- Peripheral View: WDT0 -------------------------------------
// SVD Line: 10330
// <view> WDT0
// <name> WDT0 </name>
// <item> SFDITEM_REG__WDT0_CTRL </item>
// <item> SFDITEM_REG__WDT0_RST </item>
// </view>
//
// ------------------------------ IRQ Num definition: max32660 ---------------------------------
// SVD Line: 2
// ------------------------------------------------------------------------------------------------
// ----- Interrupt Number Definition -----
// ------------------------------------------------------------------------------------------------
// ------------------------ ARM Cortex-M4 Specific Interrupt Numbers ----------------------------
// <qitem> Reset_IRQ
// <name> Reset </name>
// <i> Reset Vector, invoked on Power up and warm reset </i>
// <loc> 1 </loc>
// </qitem>
//
// <qitem> NonMaskableInt_IRQ
// <name> NonMaskableInt </name>
// <i> Non maskable Interrupt, cannot be stopped or preempted </i>
// <loc> 2 </loc>
// </qitem>
//
// <qitem> HardFault_IRQ
// <name> HardFault </name>
// <i> Hard Fault, all classes of Fault </i>
// <loc> 3 </loc>
// </qitem>
//
// <qitem> MemoryManagement_IRQ
// <name> MemoryManagement </name>
// <i> Memory Management, MPU mismatch, including Access Violation and No Match </i>
// <loc> 4 </loc>
// </qitem>
//
// <qitem> BusFault_IRQ
// <name> BusFault </name>
// <i> Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault </i>
// <loc> 5 </loc>
// </qitem>
//
// <qitem> UsageFault_IRQ
// <name> UsageFault </name>
// <i> Usage Fault, i.e. Undef Instruction, Illegal State Transition </i>
// <loc> 6 </loc>
// </qitem>
//
// <qitem> SVCall_IRQ
// <name> SVCall </name>
// <i> System Service Call via SVC instruction </i>
// <loc> 11 </loc>
// </qitem>
//
// <qitem> DebugMonitor_IRQ
// <name> DebugMonitor </name>
// <i> Debug Monitor </i>
// <loc> 12 </loc>
// </qitem>
//
// <qitem> PendSV_IRQ
// <name> PendSV </name>
// <i> Pendable request for system service </i>
// <loc> 14 </loc>
// </qitem>
//
// <qitem> SysTick_IRQ
// <name> SysTick </name>
// <i> System Tick Timer </i>
// <loc> 15 </loc>
// </qitem>
//
// --------------------------- max32660 Specific Interrupt Numbers ------------------------------
// <qitem> WDT0_IRQ
// <name> WDT0 </name>
// <i> WDT0 </i>
// <loc> 17 </loc>
// </qitem>
//
// <qitem> RTC_IRQ
// <name> RTC </name>
// <i> RTC interrupt. </i>
// <loc> 19 </loc>
// </qitem>
//
// <qitem> TMR0_IRQ
// <name> TMR0 </name>
// <i> TMR0 IRQ </i>
// <loc> 21 </loc>
// </qitem>
//
// <qitem> TMR1_IRQ
// <name> TMR1 </name>
// <i> TMR1 IRQ </i>
// <loc> 22 </loc>
// </qitem>
//
// <qitem> TMR2_IRQ
// <name> TMR2 </name>
// <i> TMR2 IRQ </i>
// <loc> 23 </loc>
// </qitem>
//
// <qitem> I2C0_IRQ
// <name> I2C0 </name>
// <i> I2C0 IRQ </i>
// <loc> 29 </loc>
// </qitem>
//
// <qitem> UART0_IRQ
// <name> UART0 </name>
// <i> UART0 IRQ </i>
// <loc> 30 </loc>
// </qitem>
//
// <qitem> UART1_IRQ
// <name> UART1 </name>
// <i> UART1 IRQ </i>
// <loc> 31 </loc>
// </qitem>
//
// <qitem> SPI0_IRQ
// <name> SPI0 </name>
// <i> SPI0 </i>
// <loc> 32 </loc>
// </qitem>
//
// <qitem> Flash_Controller_IRQ
// <name> Flash_Controller </name>
// <i> Flash Controller interrupt. </i>
// <loc> 39 </loc>
// </qitem>
//
// <qitem> GPIO0_IRQ
// <name> GPIO0 </name>
// <i> GPIO0 interrupt. </i>
// <loc> 40 </loc>
// </qitem>
//
// <qitem> DMA0_IRQ
// <name> DMA0 </name>
// <i> DMA0 </i>
// <loc> 44 </loc>
// </qitem>
//
// <qitem> DMA1_IRQ
// <name> DMA1 </name>
// <i> DMA1 </i>
// <loc> 45 </loc>
// </qitem>
//
// <qitem> DMA2_IRQ
// <name> DMA2 </name>
// <i> DMA2 </i>
// <loc> 46 </loc>
// </qitem>
//
// <qitem> DMA3_IRQ
// <name> DMA3 </name>
// <i> DMA3 </i>
// <loc> 47 </loc>
// </qitem>
//
// <qitem> I2C1_IRQ
// <name> I2C1 </name>
// <i> I2C1 IRQ </i>
// <loc> 52 </loc>
// </qitem>
//
// <qitem> DMA4_IRQ
// <name> DMA4 </name>
// <i> DMA4 </i>
// <loc> 84 </loc>
// </qitem>
//
// <qitem> DMA5_IRQ
// <name> DMA5 </name>
// <i> DMA5 </i>
// <loc> 85 </loc>
// </qitem>
//
// <qitem> DMA6_IRQ
// <name> DMA6 </name>
// <i> DMA6 </i>
// <loc> 86 </loc>
// </qitem>
//
// <qitem> DMA7_IRQ
// <name> DMA7 </name>
// <i> DMA7 </i>
// <loc> 87 </loc>
// </qitem>
//
// <qitem> DMA8_IRQ
// <name> DMA8 </name>
// <i> DMA8 </i>
// <loc> 88 </loc>
// </qitem>
//
// <qitem> DMA9_IRQ
// <name> DMA9 </name>
// <i> DMA9 </i>
// <loc> 89 </loc>
// </qitem>
//
// <qitem> DMA10_IRQ
// <name> DMA10 </name>
// <i> DMA10 </i>
// <loc> 90 </loc>
// </qitem>
//
// <qitem> DMA11_IRQ
// <name> DMA11 </name>
// <i> DMA11 </i>
// <loc> 91 </loc>
// </qitem>
//
// <qitem> DMA12_IRQ
// <name> DMA12 </name>
// <i> DMA12 </i>
// <loc> 92 </loc>
// </qitem>
//
// <qitem> DMA13_IRQ
// <name> DMA13 </name>
// <i> DMA13 </i>
// <loc> 93 </loc>
// </qitem>
//
// <qitem> DMA14_IRQ
// <name> DMA14 </name>
// <i> DMA14 </i>
// <loc> 94 </loc>
// </qitem>
//
// <qitem> DMA15_IRQ
// <name> DMA15 </name>
// <i> DMA15 </i>
// <loc> 95 </loc>
// </qitem>
//
// <irqtable> max32660_IRQTable
// <name> max32660 Interrupt Table </name>
// <nvicPrioBits> 3 </nvicPrioBits>
// <qitem> Reset_IRQ </qitem>
// <qitem> NonMaskableInt_IRQ </qitem>
// <qitem> HardFault_IRQ </qitem>
// <qitem> MemoryManagement_IRQ </qitem>
// <qitem> BusFault_IRQ </qitem>
// <qitem> UsageFault_IRQ </qitem>
// <qitem> SVCall_IRQ </qitem>
// <qitem> DebugMonitor_IRQ </qitem>
// <qitem> PendSV_IRQ </qitem>
// <qitem> SysTick_IRQ </qitem>
// <qitem> WDT0_IRQ </qitem>
// <qitem> RTC_IRQ </qitem>
// <qitem> TMR0_IRQ </qitem>
// <qitem> TMR1_IRQ </qitem>
// <qitem> TMR2_IRQ </qitem>
// <qitem> I2C0_IRQ </qitem>
// <qitem> UART0_IRQ </qitem>
// <qitem> UART1_IRQ </qitem>
// <qitem> SPI0_IRQ </qitem>
// <qitem> Flash_Controller_IRQ </qitem>
// <qitem> GPIO0_IRQ </qitem>
// <qitem> DMA0_IRQ </qitem>
// <qitem> DMA1_IRQ </qitem>
// <qitem> DMA2_IRQ </qitem>
// <qitem> DMA3_IRQ </qitem>
// <qitem> I2C1_IRQ </qitem>
// <qitem> DMA4_IRQ </qitem>
// <qitem> DMA5_IRQ </qitem>
// <qitem> DMA6_IRQ </qitem>
// <qitem> DMA7_IRQ </qitem>
// <qitem> DMA8_IRQ </qitem>
// <qitem> DMA9_IRQ </qitem>
// <qitem> DMA10_IRQ </qitem>
// <qitem> DMA11_IRQ </qitem>
// <qitem> DMA12_IRQ </qitem>
// <qitem> DMA13_IRQ </qitem>
// <qitem> DMA14_IRQ </qitem>
// <qitem> DMA15_IRQ </qitem>
// </irqtable>
// ------------------------------------- Menu: max32660 ----------------------------------------
// SVD Line: 2
// ------------------------------- Peripheral Menu: 'max32660' ----------------------------------
// ------------------------------------------------------------------------------------------------
// ----- Main Menu -----
// ------------------------------------------------------------------------------------------------
// <b> BBFC
// <m> BBFC </m>
// </b>
//
// <b> BBSIR
// <m> BBSIR </m>
// </b>
//
// <b> DMA
// <m> DMA </m>
// </b>
//
// <b> FLC
// <m> FLC </m>
// </b>
//
// <b> GCR
// <m> GCR </m>
// </b>
//
// <b> GPIO
// <m> GPIO0 </m>
// </b>
//
// <b> I2C
// <m> I2C0 </m>
// <m> I2C1 </m>
// </b>
//
// <b> ICC
// <m> ICC0 </m>
// <m> ICC1 </m>
// </b>
//
// <b> PWRSEQ
// <m> PWRSEQ </m>
// </b>
//
// <b> RTC
// <m> RTC </m>
// </b>
//
// <b> SIR
// <m> SIR </m>
// </b>
//
// <b> SMON
// <m> SMON </m>
// </b>
//
// <b> SPI
// <m> SPI17Y </m>
// <m> SPIMSS </m>
// </b>
//
// <b> Timers
// <m> TMR0 </m>
// <m> TMR1 </m>
// <m> TMR2 </m>
// </b>
//
// <b> UART
// <m> UART0 </m>
// <m> UART1 </m>
// </b>
//
// <b> WDT
// <m> WDT0 </m>
// </b>
//