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AKM_Demo_Board
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imbis 6 months ago
commit e562e43699
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1
.gitignore vendored
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Project/Compiler/Objects

38
Project/Application/board_config.h
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/** \file board_config.h */
#if !defined(BOARD_CONFIG_H__F1656892_AD9D_4187_8FC7_917D59CAB6DB__INCLUDED_)
#define BOARD_CONFIG_H__F1656892_AD9D_4187_8FC7_917D59CAB6DB__INCLUDED_
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stddef.h>
#include <math.h>
#include <stdbool.h>
#include <assert.h>
#include "max32660.h"
#include "mxc_errors.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "i2c.h"
#include "gpio.h"
#include "tmr.h"
#include "lp.h"
#include "flc.h"
#include "uart.h"
#include "icc.h"
#include "wdt.h"
#include "define.h"
#endif

38
Project/Application/define.h
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/** \file define.h */
#if !defined(DEFINE_H__CB0AACBA_D47E_488E_8E4E_28E3D3453B8C__INCLUDED_)
#define DEFINE_H__CB0AACBA_D47E_488E_8E4E_28E3D3453B8C__INCLUDED_
#define LOW 0
#define HIGH 1
#define SUCCESS 0
#define FAIL !SUCCESS
#define STOP 0
#define START !START
#define DISABLE 0
#define ENABLE !DISABLE
#define SETBIT(ADDRESS,BIT) (ADDRESS |= (1<<BIT))
#define CLEARBIT(ADDRESS,BIT) (ADDRESS &= ~(1<<BIT))
#define TESTBIT(ADDRESS,BIT) ((ADDRESS & (1<<BIT)) ? 1 : 0)
#define TOGGLEBIT(ADDRESS, BIT) (ADDRESS ^= (1<<BIT))
typedef signed char int8_t;
typedef short int16_t;
typedef int int32_t;
typedef long long int64_t;
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long uint64_t;
#endif

4
Project/Application/interrput_handler.c
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#include "interrput_handler.h"

8
Project/Application/interrput_handler.h
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/** \file interrput_handler.h */
#if !defined(INTERRPUT_HANDLER_H__5C2098BD_505C_4D9E_A6CB_E5EADB82029F__INCLUDED_)
#define INTERRPUT_HANDLER_H__5C2098BD_505C_4D9E_A6CB_E5EADB82029F__INCLUDED_
#include "board_config.h"
#endif

27
Project/Application/main.c
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#include "main.h"
#include "system_func.h"
#include "struct.h"
int main(void)
{
SystemCoreClockSet(HIRC_24MHZ);
ICC_Enable();
__enable_irq();
while(1)
{
}
return 0;
}

8
Project/Application/main.h
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/** \file main.h */
#if !defined(MAIN_H__9A06B09C_7F73_41DC_9460_C7BDFE53C852__INCLUDED_)
#define MAIN_H__9A06B09C_7F73_41DC_9460_C7BDFE53C852__INCLUDED_
#include "board_config.h"
#endif

8
Project/Application/struct.h
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/** \file struct.h */
#if !defined(STRUCT_H__5B92A8C1_B61E_49DA_9111_311A0DEC5AF3__INCLUDED_)
#define STRUCT_H__5B92A8C1_B61E_49DA_9111_311A0DEC5AF3__INCLUDED_
#include "board_config.h"
#endif

30
Project/Application/system_func.c
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#include "system_func.h"
static volatile uint8_t usTickCountDiv;
void SystemCoreClockSet(SYSTEM_CORE_CLOCK_LIST clock)
{
switch(clock)
{
case HIRC_96MHZ:
usTickCountDiv = 48;
LP_SetOperatingVoltage(LP_OVR_1_1);
break;
case HIRC_48MHZ:
usTickCountDiv = 24;
LP_SetOperatingVoltage(LP_OVR_1_0);
break;
case HIRC_24MHZ:
usTickCountDiv = 12;
LP_SetOperatingVoltage(LP_OVR_0_9);
break;
default:
usTickCountDiv = 48;
LP_SetOperatingVoltage(LP_OVR_1_1);
break;;
}
}

16
Project/Application/system_func.h
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/** \file system_func.h */
#if !defined(SYSTEM_FUNC_H__78DAA660_0CE8_4BE5_B564_B28E6D65148D__INCLUDED_)
#define SYSTEM_FUNC_H__78DAA660_0CE8_4BE5_B564_B28E6D65148D__INCLUDED_
#include "board_config.h"
typedef enum
{
HIRC_96MHZ,
HIRC_48MHZ,
HIRC_24MHZ,
}SYSTEM_CORE_CLOCK_LIST;
void SystemCoreClockSet(SYSTEM_CORE_CLOCK_LIST clock);
#endif

1905
Project/Compiler/AKM_Temperature_Demo.uvguix.befs
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540
Project/Compiler/AKM_Temperature_Demo.uvoptx
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Demo Board</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"" -O206 -S0 -C0 -P00000000 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0MAX32660.FLM -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MAX32660 -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>1000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>Application</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
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<bDave2>0</bDave2>
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/**
* @file arm_common_tables.h
* @brief External declaration for common tables like Bitreverse, reciprocal etc.
*/
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.1
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.1
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
};
#endif

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/**
* @file bbfc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _BBFC_REGS_H_
#define _BBFC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup bbfc
* @defgroup bbfc_registers BBFC_Registers
* @brief Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module.
* @details Battery-Backed Function Control.
*/
/**
* @ingroup bbfc_registers
* Structure type to access the BBFC Registers.
*/
typedef struct {
__IO uint32_t bbfcr0; /**< <tt>\b 0x00:</tt> BBFC BBFCR0 Register */
} mxc_bbfc_regs_t;
/* Register offsets for module BBFC */
/**
* @ingroup bbfc_registers
* @defgroup BBFC_Register_Offsets Register Offsets
* @brief BBFC Peripheral Register Offsets from the BBFC Base Peripheral Address.
* @{
*/
#define MXC_R_BBFC_BBFCR0 ((uint32_t)0x00000000UL) /**< Offset from BBFC Base Address: <tt> 0x0000</tt> */
/**@} end of group bbfc_registers */
/**
* @ingroup bbfc_registers
* @defgroup BBFC_BBFCR0 BBFC_BBFCR0
* @brief Function Control Register 0.
* @{
*/
#define MXC_F_BBFC_BBFCR0_CKPDRV_POS 0 /**< BBFCR0_CKPDRV Position */
#define MXC_F_BBFC_BBFCR0_CKPDRV ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKPDRV_POS)) /**< BBFCR0_CKPDRV Mask */
#define MXC_F_BBFC_BBFCR0_CKNPDRV_POS 4 /**< BBFCR0_CKNPDRV Position */
#define MXC_F_BBFC_BBFCR0_CKNPDRV ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKNPDRV_POS)) /**< BBFCR0_CKNPDRV Mask */
#define MXC_F_BBFC_BBFCR0_RDSDLLEN_POS 8 /**< BBFCR0_RDSDLLEN Position */
#define MXC_F_BBFC_BBFCR0_RDSDLLEN ((uint32_t)(0x1UL << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS)) /**< BBFCR0_RDSDLLEN Mask */
#define MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS ((uint32_t)0x0UL) /**< BBFCR0_RDSDLLEN_DIS Value */
#define MXC_S_BBFC_BBFCR0_RDSDLLEN_DIS (MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_DIS Setting */
#define MXC_V_BBFC_BBFCR0_RDSDLLEN_EN ((uint32_t)0x1UL) /**< BBFCR0_RDSDLLEN_EN Value */
#define MXC_S_BBFC_BBFCR0_RDSDLLEN_EN (MXC_V_BBFC_BBFCR0_RDSDLLEN_EN << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_EN Setting */
/**@} end of group BBFC_BBFCR0_Register */
#ifdef __cplusplus
}
#endif
#endif /* _BBFC_REGS_H_ */

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/**
* @file bbsir_regs.h
* @brief Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _BBSIR_REGS_H_
#define _BBSIR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup bbsir
* @defgroup bbsir_registers BBSIR_Registers
* @brief Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module.
* @details Battery-Backed Registers.
*/
/**
* @ingroup bbsir_registers
* Structure type to access the BBSIR Registers.
*/
typedef struct {
__IO uint32_t rsv0; /**< <tt>\b 0x00:</tt> BBSIR RSV0 Register */
__R uint32_t rsv_0x4;
__I uint32_t bb_sir2; /**< <tt>\b 0x08:</tt> BBSIR BB_SIR2 Register */
__I uint32_t bb_sir3; /**< <tt>\b 0x0C:</tt> BBSIR BB_SIR3 Register */
} mxc_bbsir_regs_t;
/* Register offsets for module BBSIR */
/**
* @ingroup bbsir_registers
* @defgroup BBSIR_Register_Offsets Register Offsets
* @brief BBSIR Peripheral Register Offsets from the BBSIR Base Peripheral Address.
* @{
*/
#define MXC_R_BBSIR_RSV0 ((uint32_t)0x00000000UL) /**< Offset from BBSIR Base Address: <tt> 0x0000</tt> */
#define MXC_R_BBSIR_BB_SIR2 ((uint32_t)0x00000008UL) /**< Offset from BBSIR Base Address: <tt> 0x0008</tt> */
#define MXC_R_BBSIR_BB_SIR3 ((uint32_t)0x0000000CUL) /**< Offset from BBSIR Base Address: <tt> 0x000C</tt> */
/**@} end of group bbsir_registers */
#ifdef __cplusplus
}
#endif
#endif /* _BBSIR_REGS_H_ */

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/**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V3.20
* @date 25. February 2013
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM4_SIMD_H
#define __CORE_CM4_SIMD_H
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_iar.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
#include <cmsis_ccs.h>
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SSAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT16(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
{
uint32_t result;
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLALD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLALDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
{
uint32_t result;
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
#define __SMLSLD(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
#define __SMLSLDX(ARG1,ARG2,ARG3) \
({ \
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
{
uint32_t result;
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return(result);
}
#define __PKHBT(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
#define __PKHTB(ARG1,ARG2,ARG3) \
({ \
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
if (ARG3 == 0) \
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
else \
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
__RES; \
})
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
int32_t result;
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
return(result);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
/* not yet supported */
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CORE_CM4_SIMD_H */
#ifdef __cplusplus
}
#endif

633
Project/SDK/Device/Include/core_cmFunc.h
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@ -0,0 +1,633 @@
/**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** @ingroup CMSIS_Core_FunctionInterface
@defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** @brief Get Control Register
This function returns the content of the Control Register.
@return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** @brief Set Control Register
This function writes the given value to the Control Register.
@param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** @brief Get IPSR Register
This function returns the content of the IPSR Register.
@return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** @brief Get APSR Register
This function returns the content of the APSR Register.
@return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** @brief Get xPSR Register
This function returns the content of the xPSR Register.
@return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** @brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
@return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** @brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
@param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** @brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
@return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** @brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
@param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** @brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
@return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** @brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
@param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** @brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** @brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** @brief Get Base Priority
This function returns the current value of the Base Priority register.
@return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** @brief Set Base Priority
This function assigns the given value to the Base Priority register.
@param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** @brief Get Fault Mask
This function returns the current value of the Fault Mask register.
@return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** @brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
@param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** @brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
@return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** @brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
@param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** @brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** @brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** @brief Get Control Register
This function returns the content of the Control Register.
@return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** @brief Set Control Register
This function writes the given value to the Control Register.
@param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** @brief Get IPSR Register
This function returns the content of the IPSR Register.
@return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** @brief Get APSR Register
This function returns the content of the APSR Register.
@return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** @brief Get xPSR Register
This function returns the content of the xPSR Register.
@return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** @brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
@return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** @brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
@param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** @brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
@return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** @brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
@param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** @brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
@return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** @brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
@param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** @brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** @brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** @brief Get Base Priority
This function returns the current value of the Base Priority register.
@return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** @brief Set Base Priority
This function assigns the given value to the Base Priority register.
@param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** @brief Get Fault Mask
This function returns the current value of the Fault Mask register.
@return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** @brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
@param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** @brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
@return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** @brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
@param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**
* @file dma_regs.h
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _DMA_REGS_H_
#define _DMA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup dma
* @defgroup dma_registers DMA_Registers
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
* @details DMA Controller Fully programmable, chaining capable DMA channels.
*/
/**
* @ingroup dma_registers
* Structure type to access the DMA Registers.
*/
typedef struct {
__IO uint32_t cfg; /**< <tt>\b 0x100:</tt> DMA CFG Register */
__IO uint32_t st; /**< <tt>\b 0x104:</tt> DMA ST Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t src_rld; /**< <tt>\b 0x114:</tt> DMA SRC_RLD Register */
__IO uint32_t dst_rld; /**< <tt>\b 0x118:</tt> DMA DST_RLD Register */
__IO uint32_t cnt_rld; /**< <tt>\b 0x11C:</tt> DMA CNT_RLD Register */
} mxc_dma_ch_regs_t;
typedef struct {
__IO uint32_t cn; /**< <tt>\b 0x000:</tt> DMA CN Register */
__I uint32_t intr; /**< <tt>\b 0x004:</tt> DMA INTR Register */
__R uint32_t rsv_0x8_0xff[62];
__IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */
} mxc_dma_regs_t;
/* Register offsets for module DMA */
/**
* @ingroup dma_registers
* @defgroup DMA_Register_Offsets Register Offsets
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{
*/
#define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_ST ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_CN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_INTR ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
/**@} end of group dma_registers */
/**
* @ingroup dma_registers
* @defgroup DMA_CN DMA_CN
* @brief DMA Control Register.
* @{
*/
#define MXC_F_DMA_CN_CH0_IEN_POS 0 /**< CN_CH0_IEN Position */
#define MXC_F_DMA_CN_CH0_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) /**< CN_CH0_IEN Mask */
#define MXC_V_DMA_CN_CH0_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH0_IEN_DIS Value */
#define MXC_S_DMA_CN_CH0_IEN_DIS (MXC_V_DMA_CN_CH0_IEN_DIS << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_DIS Setting */
#define MXC_V_DMA_CN_CH0_IEN_EN ((uint32_t)0x1UL) /**< CN_CH0_IEN_EN Value */
#define MXC_S_DMA_CN_CH0_IEN_EN (MXC_V_DMA_CN_CH0_IEN_EN << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_EN Setting */
#define MXC_F_DMA_CN_CH1_IEN_POS 1 /**< CN_CH1_IEN Position */
#define MXC_F_DMA_CN_CH1_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) /**< CN_CH1_IEN Mask */
#define MXC_F_DMA_CN_CH2_IEN_POS 2 /**< CN_CH2_IEN Position */
#define MXC_F_DMA_CN_CH2_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) /**< CN_CH2_IEN Mask */
#define MXC_F_DMA_CN_CH3_IEN_POS 3 /**< CN_CH3_IEN Position */
#define MXC_F_DMA_CN_CH3_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) /**< CN_CH3_IEN Mask */
/**@} end of group DMA_CN_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_INTR DMA_INTR
* @brief DMA Interrupt Register.
* @{
*/
#define MXC_F_DMA_INTR_CH0_IPEND_POS 0 /**< INTR_CH0_IPEND Position */
#define MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) /**< INTR_CH0_IPEND Mask */
#define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH0_IPEND_INACTIVE Value */
#define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_INACTIVE Setting */
#define MXC_V_DMA_INTR_CH0_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH0_IPEND_PENDING Value */
#define MXC_S_DMA_INTR_CH0_IPEND_PENDING (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_PENDING Setting */
#define MXC_F_DMA_INTR_CH1_IPEND_POS 1 /**< INTR_CH1_IPEND Position */
#define MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) /**< INTR_CH1_IPEND Mask */
#define MXC_F_DMA_INTR_CH2_IPEND_POS 2 /**< INTR_CH2_IPEND Position */
#define MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) /**< INTR_CH2_IPEND Mask */
#define MXC_F_DMA_INTR_CH3_IPEND_POS 3 /**< INTR_CH3_IPEND Position */
#define MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) /**< INTR_CH3_IPEND Mask */
/**@} end of group DMA_INTR_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CFG DMA_CFG
* @brief DMA Channel Configuration Register.
* @{
*/
#define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */
#define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */
#define MXC_V_DMA_CFG_CHEN_DIS ((uint32_t)0x0UL) /**< CFG_CHEN_DIS Value */
#define MXC_S_DMA_CFG_CHEN_DIS (MXC_V_DMA_CFG_CHEN_DIS << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_DIS Setting */
#define MXC_V_DMA_CFG_CHEN_EN ((uint32_t)0x1UL) /**< CFG_CHEN_EN Value */
#define MXC_S_DMA_CFG_CHEN_EN (MXC_V_DMA_CFG_CHEN_EN << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_EN Setting */
#define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */
#define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */
#define MXC_V_DMA_CFG_RLDEN_DIS ((uint32_t)0x0UL) /**< CFG_RLDEN_DIS Value */
#define MXC_S_DMA_CFG_RLDEN_DIS (MXC_V_DMA_CFG_RLDEN_DIS << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_DIS Setting */
#define MXC_V_DMA_CFG_RLDEN_EN ((uint32_t)0x1UL) /**< CFG_RLDEN_EN Value */
#define MXC_S_DMA_CFG_RLDEN_EN (MXC_V_DMA_CFG_RLDEN_EN << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_EN Setting */
#define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */
#define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */
#define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */
#define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */
#define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */
#define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */
#define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */
#define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */
#define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */
#define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */
#define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */
#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */
#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */
#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */
#define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */
#define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */
#define MXC_V_DMA_CFG_REQWAIT_DIS ((uint32_t)0x0UL) /**< CFG_REQWAIT_DIS Value */
#define MXC_S_DMA_CFG_REQWAIT_DIS (MXC_V_DMA_CFG_REQWAIT_DIS << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_DIS Setting */
#define MXC_V_DMA_CFG_REQWAIT_EN ((uint32_t)0x1UL) /**< CFG_REQWAIT_EN Value */
#define MXC_S_DMA_CFG_REQWAIT_EN (MXC_V_DMA_CFG_REQWAIT_EN << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_EN Setting */
#define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */
#define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */
#define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */
#define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */
#define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */
#define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */
#define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */
#define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */
#define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */
#define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */
#define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */
#define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */
#define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */
#define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */
#define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */
#define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */
#define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */
#define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */
#define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */
#define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */
#define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */
#define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */
#define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */
#define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */
#define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */
#define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */
#define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */
#define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */
#define MXC_V_DMA_CFG_SRCINC_DIS ((uint32_t)0x0UL) /**< CFG_SRCINC_DIS Value */
#define MXC_S_DMA_CFG_SRCINC_DIS (MXC_V_DMA_CFG_SRCINC_DIS << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_DIS Setting */
#define MXC_V_DMA_CFG_SRCINC_EN ((uint32_t)0x1UL) /**< CFG_SRCINC_EN Value */
#define MXC_S_DMA_CFG_SRCINC_EN (MXC_V_DMA_CFG_SRCINC_EN << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_EN Setting */
#define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */
#define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */
#define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */
#define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */
#define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */
#define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */
#define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */
#define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */
#define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */
#define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */
#define MXC_V_DMA_CFG_DSTINC_DIS ((uint32_t)0x0UL) /**< CFG_DSTINC_DIS Value */
#define MXC_S_DMA_CFG_DSTINC_DIS (MXC_V_DMA_CFG_DSTINC_DIS << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_DIS Setting */
#define MXC_V_DMA_CFG_DSTINC_EN ((uint32_t)0x1UL) /**< CFG_DSTINC_EN Value */
#define MXC_S_DMA_CFG_DSTINC_EN (MXC_V_DMA_CFG_DSTINC_EN << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_EN Setting */
#define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */
#define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */
#define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */
#define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */
#define MXC_V_DMA_CFG_CHDIEN_DIS ((uint32_t)0x0UL) /**< CFG_CHDIEN_DIS Value */
#define MXC_S_DMA_CFG_CHDIEN_DIS (MXC_V_DMA_CFG_CHDIEN_DIS << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_DIS Setting */
#define MXC_V_DMA_CFG_CHDIEN_EN ((uint32_t)0x1UL) /**< CFG_CHDIEN_EN Value */
#define MXC_S_DMA_CFG_CHDIEN_EN (MXC_V_DMA_CFG_CHDIEN_EN << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_EN Setting */
#define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */
#define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */
#define MXC_V_DMA_CFG_CTZIEN_DIS ((uint32_t)0x0UL) /**< CFG_CTZIEN_DIS Value */
#define MXC_S_DMA_CFG_CTZIEN_DIS (MXC_V_DMA_CFG_CTZIEN_DIS << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_DIS Setting */
#define MXC_V_DMA_CFG_CTZIEN_EN ((uint32_t)0x1UL) /**< CFG_CTZIEN_EN Value */
#define MXC_S_DMA_CFG_CTZIEN_EN (MXC_V_DMA_CFG_CTZIEN_EN << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_EN Setting */
/**@} end of group DMA_CFG_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_ST DMA_ST
* @brief DMA Channel Status Register.
* @{
*/
#define MXC_F_DMA_ST_CH_ST_POS 0 /**< ST_CH_ST Position */
#define MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS)) /**< ST_CH_ST Mask */
#define MXC_V_DMA_ST_CH_ST_DIS ((uint32_t)0x0UL) /**< ST_CH_ST_DIS Value */
#define MXC_S_DMA_ST_CH_ST_DIS (MXC_V_DMA_ST_CH_ST_DIS << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_DIS Setting */
#define MXC_V_DMA_ST_CH_ST_EN ((uint32_t)0x1UL) /**< ST_CH_ST_EN Value */
#define MXC_S_DMA_ST_CH_ST_EN (MXC_V_DMA_ST_CH_ST_EN << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_EN Setting */
#define MXC_F_DMA_ST_IPEND_POS 1 /**< ST_IPEND Position */
#define MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS)) /**< ST_IPEND Mask */
#define MXC_V_DMA_ST_IPEND_INACTIVE ((uint32_t)0x0UL) /**< ST_IPEND_INACTIVE Value */
#define MXC_S_DMA_ST_IPEND_INACTIVE (MXC_V_DMA_ST_IPEND_INACTIVE << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_INACTIVE Setting */
#define MXC_V_DMA_ST_IPEND_PENDING ((uint32_t)0x1UL) /**< ST_IPEND_PENDING Value */
#define MXC_S_DMA_ST_IPEND_PENDING (MXC_V_DMA_ST_IPEND_PENDING << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_PENDING Setting */
#define MXC_F_DMA_ST_CTZ_ST_POS 2 /**< ST_CTZ_ST Position */
#define MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS)) /**< ST_CTZ_ST Mask */
#define MXC_V_DMA_ST_CTZ_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_CTZ_ST_NOEVENT Value */
#define MXC_S_DMA_ST_CTZ_ST_NOEVENT (MXC_V_DMA_ST_CTZ_ST_NOEVENT << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_NOEVENT Setting */
#define MXC_V_DMA_ST_CTZ_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_CTZ_ST_OCCURRED Value */
#define MXC_S_DMA_ST_CTZ_ST_OCCURRED (MXC_V_DMA_ST_CTZ_ST_OCCURRED << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_OCCURRED Setting */
#define MXC_V_DMA_ST_CTZ_ST_CLEAR ((uint32_t)0x1UL) /**< ST_CTZ_ST_CLEAR Value */
#define MXC_S_DMA_ST_CTZ_ST_CLEAR (MXC_V_DMA_ST_CTZ_ST_CLEAR << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_CLEAR Setting */
#define MXC_F_DMA_ST_RLD_ST_POS 3 /**< ST_RLD_ST Position */
#define MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS)) /**< ST_RLD_ST Mask */
#define MXC_V_DMA_ST_RLD_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_RLD_ST_NOEVENT Value */
#define MXC_S_DMA_ST_RLD_ST_NOEVENT (MXC_V_DMA_ST_RLD_ST_NOEVENT << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_NOEVENT Setting */
#define MXC_V_DMA_ST_RLD_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_RLD_ST_OCCURRED Value */
#define MXC_S_DMA_ST_RLD_ST_OCCURRED (MXC_V_DMA_ST_RLD_ST_OCCURRED << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_OCCURRED Setting */
#define MXC_V_DMA_ST_RLD_ST_CLEAR ((uint32_t)0x1UL) /**< ST_RLD_ST_CLEAR Value */
#define MXC_S_DMA_ST_RLD_ST_CLEAR (MXC_V_DMA_ST_RLD_ST_CLEAR << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_CLEAR Setting */
#define MXC_F_DMA_ST_BUS_ERR_POS 4 /**< ST_BUS_ERR Position */
#define MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS)) /**< ST_BUS_ERR Mask */
#define MXC_V_DMA_ST_BUS_ERR_NOEVENT ((uint32_t)0x0UL) /**< ST_BUS_ERR_NOEVENT Value */
#define MXC_S_DMA_ST_BUS_ERR_NOEVENT (MXC_V_DMA_ST_BUS_ERR_NOEVENT << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_NOEVENT Setting */
#define MXC_V_DMA_ST_BUS_ERR_OCCURRED ((uint32_t)0x1UL) /**< ST_BUS_ERR_OCCURRED Value */
#define MXC_S_DMA_ST_BUS_ERR_OCCURRED (MXC_V_DMA_ST_BUS_ERR_OCCURRED << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_OCCURRED Setting */
#define MXC_V_DMA_ST_BUS_ERR_CLEAR ((uint32_t)0x1UL) /**< ST_BUS_ERR_CLEAR Value */
#define MXC_S_DMA_ST_BUS_ERR_CLEAR (MXC_V_DMA_ST_BUS_ERR_CLEAR << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_CLEAR Setting */
#define MXC_F_DMA_ST_TO_ST_POS 6 /**< ST_TO_ST Position */
#define MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS)) /**< ST_TO_ST Mask */
#define MXC_V_DMA_ST_TO_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_TO_ST_NOEVENT Value */
#define MXC_S_DMA_ST_TO_ST_NOEVENT (MXC_V_DMA_ST_TO_ST_NOEVENT << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_NOEVENT Setting */
#define MXC_V_DMA_ST_TO_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_TO_ST_OCCURRED Value */
#define MXC_S_DMA_ST_TO_ST_OCCURRED (MXC_V_DMA_ST_TO_ST_OCCURRED << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_OCCURRED Setting */
#define MXC_V_DMA_ST_TO_ST_CLEAR ((uint32_t)0x1UL) /**< ST_TO_ST_CLEAR Value */
#define MXC_S_DMA_ST_TO_ST_CLEAR (MXC_V_DMA_ST_TO_ST_CLEAR << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_CLEAR Setting */
/**@} end of group DMA_ST_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_SRC DMA_SRC
* @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or
* 4, depending on the data width of each AHB cycle. For peripheral transfers, some
* or all of the actual address bits are fixed. If SRCINC=0, this register remains
* constant. In the case where a count-to-zero condition occurs while RLDEN=1, the
* register is reloaded with the contents of DMA_SRC_RLD.
* @{
*/
#define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */
#define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */
/**@} end of group DMA_SRC_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_DST DMA_DST
* @brief Destination Device Address. For peripheral transfers, some or all of the actual
* address bits are fixed. If DSTINC=1, this register is incremented on every AHB
* write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the
* data width of each AHB cycle. In the case where a count-to-zero condition occurs
* while RLDEN=1, the register is reloaded with DMA_DST_RLD.
* @{
*/
#define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */
#define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */
/**@} end of group DMA_DST_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CNT DMA_CNT
* @brief DMA Counter. The user loads this register with the number of bytes to transfer.
* This counter decreases on every AHB cycle into the DMA FIFO. The decrement will
* be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter
* reaches 0, a count-to-zero condition is triggered.
* @{
*/
#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */
#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */
/**@} end of group DMA_CNT_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_SRC_RLD DMA_SRC_RLD
* @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC
* upon a count-to-zero condition.
* @{
*/
#define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */
#define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */
/**@} end of group DMA_SRC_RLD_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_DST_RLD DMA_DST_RLD
* @brief Destination Address Reload Value. The value of this register is loaded into
* DMA0_DST upon a count-to-zero condition.
* @{
*/
#define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */
#define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */
/**@} end of group DMA_DST_RLD_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CNT_RLD DMA_CNT_RLD
* @brief DMA Channel Count Reload Register.
* @{
*/
#define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */
#define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */
#define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */
#define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */
#define MXC_V_DMA_CNT_RLD_RLDEN_DIS ((uint32_t)0x0UL) /**< CNT_RLD_RLDEN_DIS Value */
#define MXC_S_DMA_CNT_RLD_RLDEN_DIS (MXC_V_DMA_CNT_RLD_RLDEN_DIS << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_DIS Setting */
#define MXC_V_DMA_CNT_RLD_RLDEN_EN ((uint32_t)0x1UL) /**< CNT_RLD_RLDEN_EN Value */
#define MXC_S_DMA_CNT_RLD_RLDEN_EN (MXC_V_DMA_CNT_RLD_RLDEN_EN << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_EN Setting */
/**@} end of group DMA_CNT_RLD_Register */
#ifdef __cplusplus
}
#endif
#endif /* _DMA_REGS_H_ */

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Project/SDK/Device/Include/flc_regs.h
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/**
* @file flc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _FLC_REGS_H_
#define _FLC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup flc
* @defgroup flc_registers FLC_Registers
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
* @details Flash Memory Control.
*/
/**
* @ingroup flc_registers
* Structure type to access the FLC Registers.
*/
typedef struct {
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
__IO uint32_t cn; /**< <tt>\b 0x08:</tt> FLC CN Register */
__R uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
__R uint32_t rsv_0x28_0x2f[2];
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
__O uint32_t acntl; /**< <tt>\b 0x40:</tt> FLC ACNTL Register */
} mxc_flc_regs_t;
/* Register offsets for module FLC */
/**
* @ingroup flc_registers
* @defgroup FLC_Register_Offsets Register Offsets
* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
* @{
*/
#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
/**@} end of group flc_registers */
/**
* @ingroup flc_registers
* @defgroup FLC_ADDR FLC_ADDR
* @brief Flash Write Address.
* @{
*/
#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group FLC_ADDR_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_CLKDIV FLC_CLKDIV
* @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
* MHz clock for Flash controller.
* @{
*/
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group FLC_CLKDIV_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_CN FLC_CN
* @brief Flash Control Register.
* @{
*/
#define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */
#define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
#define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value */
#define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */
#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */
#define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
#define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */
#define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
#define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */
#define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
#define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */
#define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
#define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
#define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
#define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value */
#define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
#define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */
#define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
#define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
#define MXC_S_FLC_CN_ERASE_CODE_NOP (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */
#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */
#define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */
#define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */
#define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */
#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
#define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
#define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
#define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */
#define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */
#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
#define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting */
#define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
#define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
#define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
#define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
#define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value */
#define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
#define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
#define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
#define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
#define MXC_S_FLC_CN_UNLOCK_UNLOCKED (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
#define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */
#define MXC_S_FLC_CN_UNLOCK_LOCKED (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */
/**@} end of group FLC_CN_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_INTR FLC_INTR
* @brief Flash Interrupt Register.
* @{
*/
#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
#define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
#define MXC_S_FLC_INTR_DONE_INACTIVE (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
#define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
#define MXC_S_FLC_INTR_DONE_PENDING (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
#define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
#define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
#define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
#define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
#define MXC_S_FLC_INTR_DONEIE_DISABLE (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
#define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
#define MXC_S_FLC_INTR_DONEIE_ENABLE (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
/**@} end of group FLC_INTR_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_DATA FLC_DATA
* @brief Flash Write Data.
* @{
*/
#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group FLC_DATA_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_ACNTL FLC_ACNTL
* @brief Access Control Register. Writing the ACNTL register with the following values in
* the order shown, allows read and write access to the system and user Information
* block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl =
* 0x9608b2c1. When unlocked, a write of any word will disable access to system and
* user information block. Readback of this register is always zero.
* @{
*/
#define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */
#define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
/**@} end of group FLC_ACNTL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_REGS_H_ */

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/**
* @file gcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GCR_REGS_H_
#define _GCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gcr
* @defgroup gcr_registers GCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
* @details Global Control Registers.
*/
/**
* @ingroup gcr_registers
* Structure type to access the GCR Registers.
*/
typedef struct {
__IO uint32_t scon; /**< <tt>\b 0x00:</tt> GCR SCON Register */
__IO uint32_t rstr0; /**< <tt>\b 0x04:</tt> GCR RSTR0 Register */
__IO uint32_t clkcn; /**< <tt>\b 0x08:</tt> GCR CLKCN Register */
__IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
__R uint32_t rsv_0x10_0x17[2];
__IO uint32_t pckdiv; /**< <tt>\b 0x18:</tt> GCR PCKDIV Register */
__R uint32_t rsv_0x1c_0x23[2];
__IO uint32_t perckcn0; /**< <tt>\b 0x24:</tt> GCR PERCKCN0 Register */
__IO uint32_t memckcn; /**< <tt>\b 0x28:</tt> GCR MEMCKCN Register */
__IO uint32_t memzcn; /**< <tt>\b 0x2C:</tt> GCR MEMZCN Register */
__R uint32_t rsv_0x30;
__IO uint32_t scck; /**< <tt>\b 0x34:</tt> GCR SCCK Register */
__IO uint32_t mpri0; /**< <tt>\b 0x38:</tt> GCR MPRI0 Register */
__IO uint32_t mpri1; /**< <tt>\b 0x3C:</tt> GCR MPRI1 Register */
__IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */
__IO uint32_t rstr1; /**< <tt>\b 0x44:</tt> GCR RSTR1 Register */
__IO uint32_t perckcn1; /**< <tt>\b 0x48:</tt> GCR PERCKCN1 Register */
__IO uint32_t evten; /**< <tt>\b 0x4C:</tt> GCR EVTEN Register */
__I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */
__IO uint32_t syssie; /**< <tt>\b 0x54:</tt> GCR SYSSIE Register */
} mxc_gcr_regs_t;
/* Register offsets for module GCR */
/**
* @ingroup gcr_registers
* @defgroup GCR_Register_Offsets Register Offsets
* @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
* @{
*/
#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */
#define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */
#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */
#define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */
#define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */
#define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */
#define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */
#define MXC_R_GCR_SCCK ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt> 0x0034</tt> */
#define MXC_R_GCR_MPRI0 ((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt> 0x0038</tt> */
#define MXC_R_GCR_MPRI1 ((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt> 0x003C</tt> */
#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */
#define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */
#define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */
#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */
#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */
#define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */
/**@} end of group gcr_registers */
/**
* @ingroup gcr_registers
* @defgroup GCR_SCON GCR_SCON
* @brief System Control.
* @{
*/
#define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */
#define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
#define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */
#define MXC_S_GCR_SCON_SBUSARB_FIX (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
#define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */
#define MXC_S_GCR_SCON_SBUSARB_ROUND (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */
#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */
#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */
#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
#define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
#define MXC_V_GCR_SCON_FPU_DIS_ENABLE ((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */
#define MXC_S_GCR_SCON_FPU_DIS_ENABLE (MXC_V_GCR_SCON_FPU_DIS_ENABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */
#define MXC_V_GCR_SCON_FPU_DIS_DISABLE ((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */
#define MXC_S_GCR_SCON_FPU_DIS_DISABLE (MXC_V_GCR_SCON_FPU_DIS_DISABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */
#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
#define MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */
#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */
#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */
#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */
#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
#define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
#define MXC_V_GCR_SCON_SWD_DIS_ENABLE ((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */
#define MXC_S_GCR_SCON_SWD_DIS_ENABLE (MXC_V_GCR_SCON_SWD_DIS_ENABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */
#define MXC_V_GCR_SCON_SWD_DIS_DISABLE ((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */
#define MXC_S_GCR_SCON_SWD_DIS_DISABLE (MXC_V_GCR_SCON_SWD_DIS_DISABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */
/**@} end of group GCR_SCON_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_RSTR0 GCR_RSTR0
* @brief Reset.
* @{
*/
#define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */
#define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
#define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */
#define MXC_S_GCR_RSTR0_DMA_RFU (MXC_V_GCR_RSTR0_DMA_RFU << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */
#define MXC_V_GCR_RSTR0_DMA_RESET ((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */
#define MXC_S_GCR_RSTR0_DMA_RESET (MXC_V_GCR_RSTR0_DMA_RESET << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */
#define MXC_V_GCR_RSTR0_DMA_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_DMA_RESET_DONE (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_DMA_BUSY ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value */
#define MXC_S_GCR_RSTR0_DMA_BUSY (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
#define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */
#define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
#define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */
#define MXC_S_GCR_RSTR0_WDT_RFU (MXC_V_GCR_RSTR0_WDT_RFU << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */
#define MXC_V_GCR_RSTR0_WDT_RESET ((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */
#define MXC_S_GCR_RSTR0_WDT_RESET (MXC_V_GCR_RSTR0_WDT_RESET << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */
#define MXC_V_GCR_RSTR0_WDT_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_WDT_RESET_DONE (MXC_V_GCR_RSTR0_WDT_RESET_DONE << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_WDT_BUSY ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value */
#define MXC_S_GCR_RSTR0_WDT_BUSY (MXC_V_GCR_RSTR0_WDT_BUSY << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */
#define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */
#define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
#define MXC_V_GCR_RSTR0_GPIO0_RFU ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */
#define MXC_S_GCR_RSTR0_GPIO0_RFU (MXC_V_GCR_RSTR0_GPIO0_RFU << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */
#define MXC_V_GCR_RSTR0_GPIO0_RESET ((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */
#define MXC_S_GCR_RSTR0_GPIO0_RESET (MXC_V_GCR_RSTR0_GPIO0_RESET << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */
#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_GPIO0_BUSY ((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */
#define MXC_S_GCR_RSTR0_GPIO0_BUSY (MXC_V_GCR_RSTR0_GPIO0_BUSY << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */
#define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */
#define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
#define MXC_V_GCR_RSTR0_TIMER0_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */
#define MXC_S_GCR_RSTR0_TIMER0_RFU (MXC_V_GCR_RSTR0_TIMER0_RFU << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */
#define MXC_V_GCR_RSTR0_TIMER0_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */
#define MXC_S_GCR_RSTR0_TIMER0_RESET (MXC_V_GCR_RSTR0_TIMER0_RESET << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */
#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE (MXC_V_GCR_RSTR0_TIMER0_RESET_DONE << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_TIMER0_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */
#define MXC_S_GCR_RSTR0_TIMER0_BUSY (MXC_V_GCR_RSTR0_TIMER0_BUSY << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */
#define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */
#define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
#define MXC_V_GCR_RSTR0_TIMER1_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */
#define MXC_S_GCR_RSTR0_TIMER1_RFU (MXC_V_GCR_RSTR0_TIMER1_RFU << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */
#define MXC_V_GCR_RSTR0_TIMER1_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */
#define MXC_S_GCR_RSTR0_TIMER1_RESET (MXC_V_GCR_RSTR0_TIMER1_RESET << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */
#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE (MXC_V_GCR_RSTR0_TIMER1_RESET_DONE << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_TIMER1_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */
#define MXC_S_GCR_RSTR0_TIMER1_BUSY (MXC_V_GCR_RSTR0_TIMER1_BUSY << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */
#define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */
#define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
#define MXC_V_GCR_RSTR0_TIMER2_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */
#define MXC_S_GCR_RSTR0_TIMER2_RFU (MXC_V_GCR_RSTR0_TIMER2_RFU << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */
#define MXC_V_GCR_RSTR0_TIMER2_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */
#define MXC_S_GCR_RSTR0_TIMER2_RESET (MXC_V_GCR_RSTR0_TIMER2_RESET << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */
#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE (MXC_V_GCR_RSTR0_TIMER2_RESET_DONE << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_TIMER2_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */
#define MXC_S_GCR_RSTR0_TIMER2_BUSY (MXC_V_GCR_RSTR0_TIMER2_BUSY << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */
#define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */
#define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
#define MXC_V_GCR_RSTR0_UART0_RFU ((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */
#define MXC_S_GCR_RSTR0_UART0_RFU (MXC_V_GCR_RSTR0_UART0_RFU << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */
#define MXC_V_GCR_RSTR0_UART0_RESET ((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */
#define MXC_S_GCR_RSTR0_UART0_RESET (MXC_V_GCR_RSTR0_UART0_RESET << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */
#define MXC_V_GCR_RSTR0_UART0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_UART0_RESET_DONE (MXC_V_GCR_RSTR0_UART0_RESET_DONE << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_UART0_BUSY ((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */
#define MXC_S_GCR_RSTR0_UART0_BUSY (MXC_V_GCR_RSTR0_UART0_BUSY << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */
#define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */
#define MXC_F_GCR_RSTR0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */
#define MXC_V_GCR_RSTR0_UART1_RFU ((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */
#define MXC_S_GCR_RSTR0_UART1_RFU (MXC_V_GCR_RSTR0_UART1_RFU << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */
#define MXC_V_GCR_RSTR0_UART1_RESET ((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */
#define MXC_S_GCR_RSTR0_UART1_RESET (MXC_V_GCR_RSTR0_UART1_RESET << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */
#define MXC_V_GCR_RSTR0_UART1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_UART1_RESET_DONE (MXC_V_GCR_RSTR0_UART1_RESET_DONE << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_UART1_BUSY ((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */
#define MXC_S_GCR_RSTR0_UART1_BUSY (MXC_V_GCR_RSTR0_UART1_BUSY << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */
#define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */
#define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */
#define MXC_V_GCR_RSTR0_SPI0_RFU ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value */
#define MXC_S_GCR_RSTR0_SPI0_RFU (MXC_V_GCR_RSTR0_SPI0_RFU << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */
#define MXC_V_GCR_RSTR0_SPI0_RESET ((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */
#define MXC_S_GCR_RSTR0_SPI0_RESET (MXC_V_GCR_RSTR0_SPI0_RESET << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */
#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE (MXC_V_GCR_RSTR0_SPI0_RESET_DONE << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_SPI0_BUSY ((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */
#define MXC_S_GCR_RSTR0_SPI0_BUSY (MXC_V_GCR_RSTR0_SPI0_BUSY << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */
#define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */
#define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */
#define MXC_V_GCR_RSTR0_SPI1_RFU ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value */
#define MXC_S_GCR_RSTR0_SPI1_RFU (MXC_V_GCR_RSTR0_SPI1_RFU << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */
#define MXC_V_GCR_RSTR0_SPI1_RESET ((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */
#define MXC_S_GCR_RSTR0_SPI1_RESET (MXC_V_GCR_RSTR0_SPI1_RESET << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */
#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE (MXC_V_GCR_RSTR0_SPI1_RESET_DONE << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_SPI1_BUSY ((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */
#define MXC_S_GCR_RSTR0_SPI1_BUSY (MXC_V_GCR_RSTR0_SPI1_BUSY << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */
#define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */
#define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */
#define MXC_V_GCR_RSTR0_I2C0_RFU ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value */
#define MXC_S_GCR_RSTR0_I2C0_RFU (MXC_V_GCR_RSTR0_I2C0_RFU << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */
#define MXC_V_GCR_RSTR0_I2C0_RESET ((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */
#define MXC_S_GCR_RSTR0_I2C0_RESET (MXC_V_GCR_RSTR0_I2C0_RESET << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */
#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE (MXC_V_GCR_RSTR0_I2C0_RESET_DONE << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_I2C0_BUSY ((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */
#define MXC_S_GCR_RSTR0_I2C0_BUSY (MXC_V_GCR_RSTR0_I2C0_BUSY << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */
#define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */
#define MXC_F_GCR_RSTR0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */
#define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */
#define MXC_S_GCR_RSTR0_RTC_RFU (MXC_V_GCR_RSTR0_RTC_RFU << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */
#define MXC_V_GCR_RSTR0_RTC_RESET ((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */
#define MXC_S_GCR_RSTR0_RTC_RESET (MXC_V_GCR_RSTR0_RTC_RESET << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */
#define MXC_V_GCR_RSTR0_RTC_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_RTC_RESET_DONE (MXC_V_GCR_RSTR0_RTC_RESET_DONE << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_RTC_BUSY ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value */
#define MXC_S_GCR_RSTR0_RTC_BUSY (MXC_V_GCR_RSTR0_RTC_BUSY << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */
#define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */
#define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */
#define MXC_V_GCR_RSTR0_SRST_RFU ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value */
#define MXC_S_GCR_RSTR0_SRST_RFU (MXC_V_GCR_RSTR0_SRST_RFU << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */
#define MXC_V_GCR_RSTR0_SRST_RESET ((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */
#define MXC_S_GCR_RSTR0_SRST_RESET (MXC_V_GCR_RSTR0_SRST_RESET << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */
#define MXC_V_GCR_RSTR0_SRST_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_SRST_RESET_DONE (MXC_V_GCR_RSTR0_SRST_RESET_DONE << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_SRST_BUSY ((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */
#define MXC_S_GCR_RSTR0_SRST_BUSY (MXC_V_GCR_RSTR0_SRST_BUSY << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */
#define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */
#define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */
#define MXC_V_GCR_RSTR0_PRST_RFU ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value */
#define MXC_S_GCR_RSTR0_PRST_RFU (MXC_V_GCR_RSTR0_PRST_RFU << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */
#define MXC_V_GCR_RSTR0_PRST_RESET ((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */
#define MXC_S_GCR_RSTR0_PRST_RESET (MXC_V_GCR_RSTR0_PRST_RESET << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */
#define MXC_V_GCR_RSTR0_PRST_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_PRST_RESET_DONE (MXC_V_GCR_RSTR0_PRST_RESET_DONE << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_PRST_BUSY ((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */
#define MXC_S_GCR_RSTR0_PRST_BUSY (MXC_V_GCR_RSTR0_PRST_BUSY << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */
#define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */
#define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
#define MXC_V_GCR_RSTR0_SYSTEM_RFU ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */
#define MXC_S_GCR_RSTR0_SYSTEM_RFU (MXC_V_GCR_RSTR0_SYSTEM_RFU << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */
#define MXC_V_GCR_RSTR0_SYSTEM_RESET ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */
#define MXC_S_GCR_RSTR0_SYSTEM_RESET (MXC_V_GCR_RSTR0_SYSTEM_RESET << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */
#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE (MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_SYSTEM_BUSY ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */
#define MXC_S_GCR_RSTR0_SYSTEM_BUSY (MXC_V_GCR_RSTR0_SYSTEM_BUSY << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */
/**@} end of group GCR_RSTR0_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_CLKCN GCR_CLKCN
* @brief Clock Control.
* @{
*/
#define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */
#define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */
#define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV128 (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
#define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */
#define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
#define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */
#define MXC_S_GCR_CLKCN_CLKSEL_HIRC (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
#define MXC_V_GCR_CLKCN_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */
#define MXC_S_GCR_CLKCN_CLKSEL_NANORING (MXC_V_GCR_CLKCN_CLKSEL_NANORING << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */
#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */
#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN (MXC_V_GCR_CLKCN_CLKSEL_HFXIN << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */
#define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */
#define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
#define MXC_V_GCR_CLKCN_CKRDY_BUSY ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */
#define MXC_S_GCR_CLKCN_CKRDY_BUSY (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
#define MXC_V_GCR_CLKCN_CKRDY_READY ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */
#define MXC_S_GCR_CLKCN_CKRDY_READY (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
#define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */
#define MXC_F_GCR_CLKCN_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */
#define MXC_V_GCR_CLKCN_X32K_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */
#define MXC_S_GCR_CLKCN_X32K_EN_DIS (MXC_V_GCR_CLKCN_X32K_EN_DIS << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */
#define MXC_V_GCR_CLKCN_X32K_EN_EN ((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */
#define MXC_S_GCR_CLKCN_X32K_EN_EN (MXC_V_GCR_CLKCN_X32K_EN_EN << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */
#define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */
#define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
#define MXC_V_GCR_CLKCN_HIRC_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */
#define MXC_S_GCR_CLKCN_HIRC_EN_DIS (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
#define MXC_V_GCR_CLKCN_HIRC_EN_EN ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */
#define MXC_S_GCR_CLKCN_HIRC_EN_EN (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
#define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */
#define MXC_F_GCR_CLKCN_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */
#define MXC_V_GCR_CLKCN_X32K_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */
#define MXC_S_GCR_CLKCN_X32K_RDY_NOT (MXC_V_GCR_CLKCN_X32K_RDY_NOT << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */
#define MXC_V_GCR_CLKCN_X32K_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */
#define MXC_S_GCR_CLKCN_X32K_RDY_READY (MXC_V_GCR_CLKCN_X32K_RDY_READY << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */
#define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */
#define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */
#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
#define MXC_V_GCR_CLKCN_HIRC_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */
#define MXC_S_GCR_CLKCN_HIRC_RDY_READY (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
#define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
#define MXC_F_GCR_CLKCN_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */
#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */
#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT (MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting */
#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */
#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY (MXC_V_GCR_CLKCN_LIRC8K_RDY_READY << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY Setting */
/**@} end of group GCR_CLKCN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PM GCR_PM
* @brief Power Management.
* @{
*/
#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
#define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */
#define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
#define MXC_V_GCR_PM_GPIOWKEN_DIS ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */
#define MXC_S_GCR_PM_GPIOWKEN_DIS (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */
#define MXC_V_GCR_PM_GPIOWKEN_EN ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value */
#define MXC_S_GCR_PM_GPIOWKEN_EN (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */
#define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */
#define MXC_F_GCR_PM_RTCWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask */
#define MXC_V_GCR_PM_RTCWKEN_DIS ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value */
#define MXC_S_GCR_PM_RTCWKEN_DIS (MXC_V_GCR_PM_RTCWKEN_DIS << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_DIS Setting */
#define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */
#define MXC_S_GCR_PM_RTCWKEN_EN (MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */
#define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */
#define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
#define MXC_V_GCR_PM_HIRCPD_ACTIVE ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */
#define MXC_S_GCR_PM_HIRCPD_ACTIVE (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */
#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
/**@} end of group GCR_PM_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PCKDIV GCR_PCKDIV
* @brief Peripheral Clock Divider.
* @{
*/
#define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */
#define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */
#define MXC_S_GCR_PCKDIV_AONCD_DIV_4 (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */
#define MXC_S_GCR_PCKDIV_AONCD_DIV_8 (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */
#define MXC_S_GCR_PCKDIV_AONCD_DIV_16 (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */
#define MXC_S_GCR_PCKDIV_AONCD_DIV_32 (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
/**@} end of group GCR_PCKDIV_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PERCKCN0 GCR_PERCKCN0
* @brief Peripheral Clock Disable.
* @{
*/
#define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */
#define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */
#define MXC_V_GCR_PERCKCN0_GPIO0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */
#define MXC_S_GCR_PERCKCN0_GPIO0D_EN (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */
#define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
#define MXC_V_GCR_PERCKCN0_DMAD_EN ((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */
#define MXC_S_GCR_PERCKCN0_DMAD_EN (MXC_V_GCR_PERCKCN0_DMAD_EN << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */
#define MXC_V_GCR_PERCKCN0_DMAD_DIS ((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */
#define MXC_S_GCR_PERCKCN0_DMAD_DIS (MXC_V_GCR_PERCKCN0_DMAD_DIS << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */
#define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */
#define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
#define MXC_V_GCR_PERCKCN0_SPI0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */
#define MXC_S_GCR_PERCKCN0_SPI0D_EN (MXC_V_GCR_PERCKCN0_SPI0D_EN << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_SPI0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_SPI0D_DIS (MXC_V_GCR_PERCKCN0_SPI0D_DIS << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */
#define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
#define MXC_V_GCR_PERCKCN0_SPI1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */
#define MXC_S_GCR_PERCKCN0_SPI1D_EN (MXC_V_GCR_PERCKCN0_SPI1D_EN << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */
#define MXC_V_GCR_PERCKCN0_SPI1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */
#define MXC_S_GCR_PERCKCN0_SPI1D_DIS (MXC_V_GCR_PERCKCN0_SPI1D_DIS << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */
#define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */
#define MXC_V_GCR_PERCKCN0_UART0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */
#define MXC_S_GCR_PERCKCN0_UART0D_EN (MXC_V_GCR_PERCKCN0_UART0D_EN << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_UART0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_UART0D_DIS (MXC_V_GCR_PERCKCN0_UART0D_DIS << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */
#define MXC_F_GCR_PERCKCN0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D Mask */
#define MXC_V_GCR_PERCKCN0_UART1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */
#define MXC_S_GCR_PERCKCN0_UART1D_EN (MXC_V_GCR_PERCKCN0_UART1D_EN << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */
#define MXC_V_GCR_PERCKCN0_UART1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */
#define MXC_S_GCR_PERCKCN0_UART1D_DIS (MXC_V_GCR_PERCKCN0_UART1D_DIS << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */
#define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
#define MXC_V_GCR_PERCKCN0_I2C0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */
#define MXC_S_GCR_PERCKCN0_I2C0D_EN (MXC_V_GCR_PERCKCN0_I2C0D_EN << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_I2C0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_I2C0D_DIS (MXC_V_GCR_PERCKCN0_I2C0D_DIS << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */
#define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
#define MXC_V_GCR_PERCKCN0_T0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */
#define MXC_S_GCR_PERCKCN0_T0D_EN (MXC_V_GCR_PERCKCN0_T0D_EN << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_T0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_T0D_DIS (MXC_V_GCR_PERCKCN0_T0D_DIS << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */
#define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
#define MXC_V_GCR_PERCKCN0_T1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */
#define MXC_S_GCR_PERCKCN0_T1D_EN (MXC_V_GCR_PERCKCN0_T1D_EN << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */
#define MXC_V_GCR_PERCKCN0_T1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */
#define MXC_S_GCR_PERCKCN0_T1D_DIS (MXC_V_GCR_PERCKCN0_T1D_DIS << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */
#define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
#define MXC_V_GCR_PERCKCN0_T2D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */
#define MXC_S_GCR_PERCKCN0_T2D_EN (MXC_V_GCR_PERCKCN0_T2D_EN << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */
#define MXC_V_GCR_PERCKCN0_T2D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */
#define MXC_S_GCR_PERCKCN0_T2D_DIS (MXC_V_GCR_PERCKCN0_T2D_DIS << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */
#define MXC_F_GCR_PERCKCN0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */
#define MXC_V_GCR_PERCKCN0_I2C1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */
#define MXC_S_GCR_PERCKCN0_I2C1D_EN (MXC_V_GCR_PERCKCN0_I2C1D_EN << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */
#define MXC_V_GCR_PERCKCN0_I2C1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */
#define MXC_S_GCR_PERCKCN0_I2C1D_DIS (MXC_V_GCR_PERCKCN0_I2C1D_DIS << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */
/**@} end of group GCR_PERCKCN0_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_MEMCKCN GCR_MEMCKCN
* @brief Memory Clock Control Register.
* @{
*/
#define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */
#define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */
#define MXC_F_GCR_MEMCKCN_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS Mask */
#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */
#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */
#define MXC_F_GCR_MEMCKCN_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */
#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Setting */
#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */
#define MXC_F_GCR_MEMCKCN_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */
#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Setting */
#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */
#define MXC_F_GCR_MEMCKCN_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */
#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Setting */
#define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */
#define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */
#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE (MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Setting */
/**@} end of group GCR_MEMCKCN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_MEMZCN GCR_MEMZCN
* @brief Memory Zeroize Control.
* @{
*/
#define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */
#define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */
#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
#define MXC_V_GCR_MEMZCN_SRAM0Z_START ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */
#define MXC_S_GCR_MEMZCN_SRAM0Z_START (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
#define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */
#define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP ((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */
#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP (MXC_V_GCR_MEMZCN_ICACHEZ_NOP << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */
#define MXC_V_GCR_MEMZCN_ICACHEZ_START ((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */
#define MXC_S_GCR_MEMZCN_ICACHEZ_START (MXC_V_GCR_MEMZCN_ICACHEZ_START << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */
/**@} end of group GCR_MEMZCN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_SYSST GCR_SYSST
* @brief System Status Register.
* @{
*/
#define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */
#define MXC_F_GCR_SYSST_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
#define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */
#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */
#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED (MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */
#define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */
#define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */
#define MXC_V_GCR_SYSST_CODEINTERR_NORM ((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */
#define MXC_S_GCR_SYSST_CODEINTERR_NORM (MXC_V_GCR_SYSST_CODEINTERR_NORM << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting */
#define MXC_V_GCR_SYSST_CODEINTERR_CODE ((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */
#define MXC_S_GCR_SYSST_CODEINTERR_CODE (MXC_V_GCR_SYSST_CODEINTERR_CODE << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_CODE Setting */
#define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */
#define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */
#define MXC_V_GCR_SYSST_SCMEMF_NORM ((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */
#define MXC_S_GCR_SYSST_SCMEMF_NORM (MXC_V_GCR_SYSST_SCMEMF_NORM << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */
#define MXC_V_GCR_SYSST_SCMEMF_MEMORY ((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */
#define MXC_S_GCR_SYSST_SCMEMF_MEMORY (MXC_V_GCR_SYSST_SCMEMF_MEMORY << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */
/**@} end of group GCR_SYSST_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_RSTR1 GCR_RSTR1
* @brief Reset 1.
* @{
*/
#define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */
#define MXC_F_GCR_RSTR1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask */
#define MXC_V_GCR_RSTR1_I2C1_RFU ((uint32_t)0x0UL) /**< RSTR1_I2C1_RFU Value */
#define MXC_S_GCR_RSTR1_I2C1_RFU (MXC_V_GCR_RSTR1_I2C1_RFU << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RFU Setting */
#define MXC_V_GCR_RSTR1_I2C1_RESET ((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */
#define MXC_S_GCR_RSTR1_I2C1_RESET (MXC_V_GCR_RSTR1_I2C1_RESET << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */
#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */
#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE (MXC_V_GCR_RSTR1_I2C1_RESET_DONE << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */
#define MXC_V_GCR_RSTR1_I2C1_BUSY ((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */
#define MXC_S_GCR_RSTR1_I2C1_BUSY (MXC_V_GCR_RSTR1_I2C1_BUSY << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */
/**@} end of group GCR_RSTR1_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PERCKCN1 GCR_PERCKCN1
* @brief Peripheral Clock Disable.
* @{
*/
#define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */
#define MXC_F_GCR_PERCKCN1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */
#define MXC_V_GCR_PERCKCN1_FLCD_EN ((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */
#define MXC_S_GCR_PERCKCN1_FLCD_EN (MXC_V_GCR_PERCKCN1_FLCD_EN << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */
#define MXC_V_GCR_PERCKCN1_FLCD_DIS ((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */
#define MXC_S_GCR_PERCKCN1_FLCD_DIS (MXC_V_GCR_PERCKCN1_FLCD_DIS << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */
#define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
#define MXC_F_GCR_PERCKCN1_ICACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */
#define MXC_V_GCR_PERCKCN1_ICACHED_EN ((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */
#define MXC_S_GCR_PERCKCN1_ICACHED_EN (MXC_V_GCR_PERCKCN1_ICACHED_EN << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting */
#define MXC_V_GCR_PERCKCN1_ICACHED_DIS ((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */
#define MXC_S_GCR_PERCKCN1_ICACHED_DIS (MXC_V_GCR_PERCKCN1_ICACHED_DIS << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting */
/**@} end of group GCR_PERCKCN1_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_EVTEN GCR_EVTEN
* @brief Event Enable Register.
* @{
*/
#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
#define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
#define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */
#define MXC_F_GCR_EVTEN_RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */
/**@} end of group GCR_EVTEN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_REVISION GCR_REVISION
* @brief Revision Register.
* @{
*/
#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
#define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */
/**@} end of group GCR_REVISION_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_SYSSIE GCR_SYSSIE
* @brief System Status Interrupt Enable Register.
* @{
*/
#define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */
#define MXC_F_GCR_SYSSIE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
#define MXC_V_GCR_SYSSIE_ICEULIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */
#define MXC_S_GCR_SYSSIE_ICEULIE_DIS (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
#define MXC_V_GCR_SYSSIE_ICEULIE_EN ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */
#define MXC_S_GCR_SYSSIE_ICEULIE_EN (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
#define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */
#define MXC_F_GCR_SYSSIE_CIEIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */
#define MXC_V_GCR_SYSSIE_CIEIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */
#define MXC_S_GCR_SYSSIE_CIEIE_DIS (MXC_V_GCR_SYSSIE_CIEIE_DIS << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */
#define MXC_V_GCR_SYSSIE_CIEIE_EN ((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */
#define MXC_S_GCR_SYSSIE_CIEIE_EN (MXC_V_GCR_SYSSIE_CIEIE_EN << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */
#define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */
#define MXC_F_GCR_SYSSIE_SCMFIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */
#define MXC_V_GCR_SYSSIE_SCMFIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */
#define MXC_S_GCR_SYSSIE_SCMFIE_DIS (MXC_V_GCR_SYSSIE_SCMFIE_DIS << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */
#define MXC_V_GCR_SYSSIE_SCMFIE_EN ((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */
#define MXC_S_GCR_SYSSIE_SCMFIE_EN (MXC_V_GCR_SYSSIE_SCMFIE_EN << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */
/**@} end of group GCR_SYSSIE_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GCR_REGS_H_ */

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/**
* @file gpio_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gpio
* @defgroup gpio_registers GPIO_Registers
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @details Individual I/O for each GPIO
*/
/**
* @ingroup gpio_registers
* Structure type to access the GPIO Registers.
*/
typedef struct {
__IO uint32_t en; /**< <tt>\b 0x00:</tt> GPIO EN Register */
__IO uint32_t en_set; /**< <tt>\b 0x04:</tt> GPIO EN_SET Register */
__IO uint32_t en_clr; /**< <tt>\b 0x08:</tt> GPIO EN_CLR Register */
__IO uint32_t out_en; /**< <tt>\b 0x0C:</tt> GPIO OUT_EN Register */
__IO uint32_t out_en_set; /**< <tt>\b 0x10:</tt> GPIO OUT_EN_SET Register */
__IO uint32_t out_en_clr; /**< <tt>\b 0x14:</tt> GPIO OUT_EN_CLR Register */
__IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */
__O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */
__O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */
__I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */
__IO uint32_t int_mod; /**< <tt>\b 0x28:</tt> GPIO INT_MOD Register */
__IO uint32_t int_pol; /**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */
__R uint32_t rsv_0x30;
__IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
__IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
__I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
__R uint32_t rsv_0x44;
__IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */
__IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */
__IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */
__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */
__R uint32_t rsv_0x58;
__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */
__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */
__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */
__IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
__IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
__IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
__R uint32_t rsv_0x80_0xa7[10];
__IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */
__IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */
__IO uint32_t ds; /**< <tt>\b 0xB0:</tt> GPIO DS Register */
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
__R uint32_t rsv_0xbc;
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
} mxc_gpio_regs_t;
/* Register offsets for module GPIO */
/**
* @ingroup gpio_registers
* @defgroup GPIO_Register_Offsets Register Offsets
* @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.
* @{
*/
#define MXC_R_GPIO_EN ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
#define MXC_R_GPIO_EN_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
#define MXC_R_GPIO_EN_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
#define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
#define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
#define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
#define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
#define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
#define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
#define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
#define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
#define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
#define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
#define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
#define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
#define MXC_R_GPIO_DS ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
#define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */
/**@} end of group gpio_registers */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN GPIO_EN
* @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
* GPIO pin on the associated port.
* @{
*/
#define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */
#define MXC_F_GPIO_EN_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */
#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */
#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */
#define MXC_V_GPIO_EN_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */
#define MXC_S_GPIO_EN_GPIO_EN_GPIO (MXC_V_GPIO_EN_GPIO_EN_GPIO << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */
/**@} end of group GPIO_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN_SET GPIO_EN_SET
* @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
* register sets the bits in the same positions in GPIO_EN to 1, without affecting
* other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */
#define MXC_F_GPIO_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */
/**@} end of group GPIO_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN_CLR GPIO_EN_CLR
* @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */
#define MXC_F_GPIO_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */
/**@} end of group GPIO_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN GPIO_OUT_EN
* @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one
* GPIO pin in the associated port.
* @{
*/
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */
/**@} end of group GPIO_OUT_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET
* @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits
* in this register sets the bits in the same positions in GPIO_OUT_EN to 1,
* without affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
#define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
/**@} end of group GPIO_OUT_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR
* @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more
* bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0,
* without affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
#define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
/**@} end of group GPIO_OUT_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT GPIO_OUT
* @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the
* associated port. This register can be written either directly, or by using the
* GPIO_OUT_SET and GPIO_OUT_CLR registers.
* @{
*/
#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
/**@} end of group GPIO_OUT_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_SET GPIO_OUT_SET
* @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits
* in the same positions in GPIO_OUT to 1, without affecting other bits in that
* register.
* @{
*/
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
/**@} end of group GPIO_OUT_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_CLR GPIO_OUT_CLR
* @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_OUT to 0, without affecting other bits in
* that register.
* @{
*/
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
/**@} end of group GPIO_OUT_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_IN GPIO_IN
* @brief GPIO Input Register. Read-only register to read from the logic states of the
* GPIO pins on this port.
* @{
*/
#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
/**@} end of group GPIO_IN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_MOD GPIO_INT_MOD
* @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt
* mode setting for the associated GPIO pin on this port.
* @{
*/
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */
/**@} end of group GPIO_INT_MOD_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_POL GPIO_INT_POL
* @brief GPIO Interrupt Polarity Register. Each bit in this register controls the
* interrupt polarity setting for one GPIO pin in the associated port.
* @{
*/
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */
/**@} end of group GPIO_INT_POL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN GPIO_INT_EN
* @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO
* interrupt enable for the associated pin on the GPIO port.
* @{
*/
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */
/**@} end of group GPIO_INT_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET
* @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets
* the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits
* in that register.
* @{
*/
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */
/**@} end of group GPIO_INT_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR
* @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_INT_EN to 0, without affecting
* other bits in that register.
* @{
*/
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */
/**@} end of group GPIO_INT_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_STAT GPIO_INT_STAT
* @brief GPIO Interrupt Status Register. Each bit in this register contains the pending
* interrupt status for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */
/**@} end of group GPIO_INT_STAT_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_CLR GPIO_INT_CLR
* @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits
* in that register.
* @{
*/
#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
#define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
/**@} end of group GPIO_INT_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN GPIO_WAKE_EN
* @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup
* enable for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */
/**@} end of group GPIO_WAKE_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET
* @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the
* bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in
* that register.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
#define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */
/**@} end of group GPIO_WAKE_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR
* @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears
* the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
#define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */
/**@} end of group GPIO_WAKE_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE
* @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual
* edge mode for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */
/**@} end of group GPIO_INT_DUAL_EDGE_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1
* @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */
/**@} end of group GPIO_PAD_CFG1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2
* @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */
/**@} end of group GPIO_PAD_CFG2_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1 GPIO_EN1
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
/**@} end of group GPIO_EN1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_SET GPIO_EN1_SET
* @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN1 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
/**@} end of group GPIO_EN1_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_CLR GPIO_EN1_CLR
* @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_EN1 to 0, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
/**@} end of group GPIO_EN1_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2 GPIO_EN2
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
/**@} end of group GPIO_EN2_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_SET GPIO_EN2_SET
* @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN2 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
/**@} end of group GPIO_EN2_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_CLR GPIO_EN2_CLR
* @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN2 to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
/**@} end of group GPIO_EN2_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS GPIO_DS
* @brief GPIO Drive Strength Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
* @{
*/
#define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */
#define MXC_F_GPIO_DS_DS ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */
#define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */
#define MXC_S_GPIO_DS_DS_LD (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */
#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */
#define MXC_S_GPIO_DS_DS_HD (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */
/**@} end of group GPIO_DS_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS1 GPIO_DS1
* @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
* @{
*/
#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
/**@} end of group GPIO_DS1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PS GPIO_PS
* @brief GPIO Pull Select Mode.
* @{
*/
#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */
/**@} end of group GPIO_PS_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_VSSEL GPIO_VSSEL
* @brief GPIO Voltage Select.
* @{
*/
#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
#define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
/**@} end of group GPIO_VSSEL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_REGS_H_ */

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Project/SDK/Device/Include/i2c_regs.h
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/**
* @file i2c_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _I2C_REGS_H_
#define _I2C_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup i2c
* @defgroup i2c_registers I2C_Registers
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
* @details Inter-Integrated Circuit.
*/
/**
* @ingroup i2c_registers
* Structure type to access the I2C Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */
__IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */
__IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */
__IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */
__IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */
__IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */
__IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */
__IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */
__IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */
__IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */
__IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
__IO uint32_t master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */
__IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */
__IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */
__IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */
__IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
__IO uint32_t slave_addr; /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */
__IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */
} mxc_i2c_regs_t;
/* Register offsets for module I2C */
/**
* @ingroup i2c_registers
* @defgroup I2C_Register_Offsets Register Offsets
* @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
* @{
*/
#define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */
#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */
#define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */
#define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */
#define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */
#define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */
#define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */
#define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */
#define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */
#define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */
#define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */
#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */
#define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */
#define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */
#define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */
#define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */
#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */
#define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */
#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */
/**@} end of group i2c_registers */
/**
* @ingroup i2c_registers
* @defgroup I2C_CTRL I2C_CTRL
* @brief Control Register0.
* @{
*/
#define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */
#define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */
#define MXC_V_I2C_CTRL_I2C_EN_DIS ((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */
#define MXC_S_I2C_CTRL_I2C_EN_DIS (MXC_V_I2C_CTRL_I2C_EN_DIS << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */
#define MXC_V_I2C_CTRL_I2C_EN_EN ((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value */
#define MXC_S_I2C_CTRL_I2C_EN_EN (MXC_V_I2C_CTRL_I2C_EN_EN << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */
#define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */
#define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */
#define MXC_V_I2C_CTRL_MST_SLAVE_MODE ((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */
#define MXC_S_I2C_CTRL_MST_SLAVE_MODE (MXC_V_I2C_CTRL_MST_SLAVE_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */
#define MXC_V_I2C_CTRL_MST_MASTER_MODE ((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */
#define MXC_S_I2C_CTRL_MST_MASTER_MODE (MXC_V_I2C_CTRL_MST_MASTER_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */
#define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */
#define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR Mask */
#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS ((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */
#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS (MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS Setting */
#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN ((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */
#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN (MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN Setting */
#define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */
#define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */
#define MXC_V_I2C_CTRL_RX_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */
#define MXC_S_I2C_CTRL_RX_MODE_DIS (MXC_V_I2C_CTRL_RX_MODE_DIS << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */
#define MXC_V_I2C_CTRL_RX_MODE_EN ((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */
#define MXC_S_I2C_CTRL_RX_MODE_EN (MXC_V_I2C_CTRL_RX_MODE_EN << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */
#define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */
#define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK Mask */
#define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK ((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */
#define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK (MXC_V_I2C_CTRL_RX_MODE_ACK_ACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting */
#define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK ((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */
#define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK (MXC_V_I2C_CTRL_RX_MODE_ACK_NACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting */
#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */
#define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
#define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW ((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */
#define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW (MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Setting */
#define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL ((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */
#define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL (MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting */
#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */
#define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
#define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW ((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */
#define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW (MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Setting */
#define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA ((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */
#define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA (MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting */
#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */
#define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */
#define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
#define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */
#define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */
#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE ((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */
#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Setting */
#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE ((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */
#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Setting */
#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */
#define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
#define MXC_V_I2C_CTRL_READ_WRITE ((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */
#define MXC_S_I2C_CTRL_READ_WRITE (MXC_V_I2C_CTRL_READ_WRITE << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */
#define MXC_V_I2C_CTRL_READ_READ ((uint32_t)0x1UL) /**< CTRL_READ_READ Value */
#define MXC_S_I2C_CTRL_READ_READ (MXC_V_I2C_CTRL_READ_READ << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */
#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS 12 /**< CTRL_SCL_CLK_STRECH_DIS Position */
#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**< CTRL_SCL_CLK_STRECH_DIS Mask */
#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN ((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */
#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_EN Setting */
#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS ((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */
#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Setting */
#define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */
#define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE Mask */
#define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */
#define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS (MXC_V_I2C_CTRL_SCL_PP_MODE_DIS << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting */
#define MXC_V_I2C_CTRL_SCL_PP_MODE_EN ((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */
#define MXC_S_I2C_CTRL_SCL_PP_MODE_EN (MXC_V_I2C_CTRL_SCL_PP_MODE_EN << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting */
#define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */
#define MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */
#define MXC_V_I2C_CTRL_HS_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */
#define MXC_S_I2C_CTRL_HS_MODE_DIS (MXC_V_I2C_CTRL_HS_MODE_DIS << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */
#define MXC_V_I2C_CTRL_HS_MODE_EN ((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */
#define MXC_S_I2C_CTRL_HS_MODE_EN (MXC_V_I2C_CTRL_HS_MODE_EN << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */
/**@} end of group I2C_CTRL_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_STATUS I2C_STATUS
* @brief Status Register.
* @{
*/
#define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */
#define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask */
#define MXC_V_I2C_STATUS_BUS_IDLE ((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */
#define MXC_S_I2C_STATUS_BUS_IDLE (MXC_V_I2C_STATUS_BUS_IDLE << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */
#define MXC_V_I2C_STATUS_BUS_BUSY ((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */
#define MXC_S_I2C_STATUS_BUS_BUSY (MXC_V_I2C_STATUS_BUS_BUSY << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */
#define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */
#define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */
#define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */
#define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY Setting */
#define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */
#define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting */
#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */
#define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
#define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL ((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */
#define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL (MXC_V_I2C_STATUS_RX_FULL_NOT_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting */
#define MXC_V_I2C_STATUS_RX_FULL_FULL ((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */
#define MXC_S_I2C_STATUS_RX_FULL_FULL (MXC_V_I2C_STATUS_RX_FULL_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */
#define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */
#define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */
#define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */
#define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY Setting */
#define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */
#define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting */
#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */
#define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
#define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */
#define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY (MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY Setting */
#define MXC_V_I2C_STATUS_TX_FULL_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */
#define MXC_S_I2C_STATUS_TX_FULL_EMPTY (MXC_V_I2C_STATUS_TX_FULL_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */
#define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */
#define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */
#define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Value */
#define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Setting */
#define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Value */
#define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Setting */
#define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */
#define MXC_F_I2C_STATUS_STATUS ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
#define MXC_V_I2C_STATUS_STATUS_IDLE ((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */
#define MXC_S_I2C_STATUS_STATUS_IDLE (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */
#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_TX ((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */
#define MXC_S_I2C_STATUS_STATUS_TX (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */
#define MXC_V_I2C_STATUS_STATUS_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_RX_ACK (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_RX ((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */
#define MXC_S_I2C_STATUS_STATUS_RX (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */
#define MXC_V_I2C_STATUS_STATUS_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_TX_ACK (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_NACK ((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */
#define MXC_S_I2C_STATUS_STATUS_NACK (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */
#define MXC_V_I2C_STATUS_STATUS_BY_ST ((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */
#define MXC_S_I2C_STATUS_STATUS_BY_ST (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */
/**@} end of group I2C_STATUS_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INT_FL0 I2C_INT_FL0
* @brief Interrupt Status Register.
* @{
*/
#define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */
#define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */
#define MXC_V_I2C_INT_FL0_DONE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_DONE_INACTIVE (MXC_V_I2C_INT_FL0_DONE_INACTIVE << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_DONE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */
#define MXC_S_I2C_INT_FL0_DONE_PENDING (MXC_V_I2C_INT_FL0_DONE_PENDING << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */
#define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */
#define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE Mask */
#define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE (MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_RX_MODE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */
#define MXC_S_I2C_INT_FL0_RX_MODE_PENDING (MXC_V_I2C_INT_FL0_RX_MODE_PENDING << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING Setting */
#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 /**< INT_FL0_GEN_CALL_ADDR Position */
#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< INT_FL0_GEN_CALL_ADDR Mask */
#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING ((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */
#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_PENDING Setting */
#define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */
#define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH Mask */
#define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */
#define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING (MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING Setting */
#define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */
#define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH Mask */
#define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */
#define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING (MXC_V_I2C_INT_FL0_RX_THRESH_PENDING << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING Setting */
#define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */
#define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH Mask */
#define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */
#define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING (MXC_V_I2C_INT_FL0_TX_THRESH_PENDING << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING Setting */
#define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */
#define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */
#define MXC_V_I2C_INT_FL0_STOP_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_STOP_INACTIVE (MXC_V_I2C_INT_FL0_STOP_INACTIVE << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_STOP_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */
#define MXC_S_I2C_INT_FL0_STOP_PENDING (MXC_V_I2C_INT_FL0_STOP_PENDING << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */
#define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */
#define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK Mask */
#define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */
#define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING (MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING Setting */
#define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */
#define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */
#define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE (MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_ARB_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_ARB_ER_PENDING (MXC_V_I2C_INT_FL0_ARB_ER_PENDING << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */
#define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */
#define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE (MXC_V_I2C_INT_FL0_TO_ER_INACTIVE << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_TO_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_TO_ER_PENDING (MXC_V_I2C_INT_FL0_TO_ER_PENDING << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 /**< INT_FL0_ADDR_NACK_ER Position */
#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< INT_FL0_ADDR_NACK_ER Mask */
#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */
#define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER Mask */
#define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE (MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_DATA_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_DATA_ER_PENDING (MXC_V_I2C_INT_FL0_DATA_ER_PENDING << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 /**< INT_FL0_DO_NOT_RESP_ER Position */
#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< INT_FL0_DO_NOT_RESP_ER Mask */
#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */
#define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER Mask */
#define MXC_V_I2C_INT_FL0_START_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_START_ER_INACTIVE (MXC_V_I2C_INT_FL0_START_ER_INACTIVE << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_START_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_START_ER_PENDING (MXC_V_I2C_INT_FL0_START_ER_PENDING << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */
#define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER Mask */
#define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE (MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_STOP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_STOP_ER_PENDING (MXC_V_I2C_INT_FL0_STOP_ER_PENDING << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 /**< INT_FL0_TX_LOCK_OUT Position */
#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */
/**@} end of group I2C_INT_FL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INT_EN0 I2C_INT_EN0
* @brief Interrupt Enable Register.
* @{
*/
#define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */
#define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */
#define MXC_V_I2C_INT_EN0_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */
#define MXC_S_I2C_INT_EN0_DONE_DIS (MXC_V_I2C_INT_EN0_DONE_DIS << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */
#define MXC_V_I2C_INT_EN0_DONE_EN ((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */
#define MXC_S_I2C_INT_EN0_DONE_EN (MXC_V_I2C_INT_EN0_DONE_EN << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */
#define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */
#define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE Mask */
#define MXC_V_I2C_INT_EN0_RX_MODE_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */
#define MXC_S_I2C_INT_EN0_RX_MODE_DIS (MXC_V_I2C_INT_EN0_RX_MODE_DIS << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */
#define MXC_V_I2C_INT_EN0_RX_MODE_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */
#define MXC_S_I2C_INT_EN0_RX_MODE_EN (MXC_V_I2C_INT_EN0_RX_MODE_EN << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */
#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS 2 /**< INT_EN0_GEN_CTRL_ADDR Position */
#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**< INT_EN0_GEN_CTRL_ADDR Mask */
#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS ((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */
#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_DIS Setting */
#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN ((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */
#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN Setting */
#define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */
#define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH Mask */
#define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */
#define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS (MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS Setting */
#define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */
#define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN (MXC_V_I2C_INT_EN0_ADDR_MATCH_EN << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN Setting */
#define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */
#define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH Mask */
#define MXC_V_I2C_INT_EN0_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */
#define MXC_S_I2C_INT_EN0_RX_THRESH_DIS (MXC_V_I2C_INT_EN0_RX_THRESH_DIS << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS Setting */
#define MXC_V_I2C_INT_EN0_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */
#define MXC_S_I2C_INT_EN0_RX_THRESH_EN (MXC_V_I2C_INT_EN0_RX_THRESH_EN << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting */
#define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */
#define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH Mask */
#define MXC_V_I2C_INT_EN0_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */
#define MXC_S_I2C_INT_EN0_TX_THRESH_DIS (MXC_V_I2C_INT_EN0_TX_THRESH_DIS << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS Setting */
#define MXC_V_I2C_INT_EN0_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */
#define MXC_S_I2C_INT_EN0_TX_THRESH_EN (MXC_V_I2C_INT_EN0_TX_THRESH_EN << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting */
#define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */
#define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */
#define MXC_V_I2C_INT_EN0_STOP_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */
#define MXC_S_I2C_INT_EN0_STOP_DIS (MXC_V_I2C_INT_EN0_STOP_DIS << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */
#define MXC_V_I2C_INT_EN0_STOP_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */
#define MXC_S_I2C_INT_EN0_STOP_EN (MXC_V_I2C_INT_EN0_STOP_EN << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */
#define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */
#define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK Mask */
#define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */
#define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS (MXC_V_I2C_INT_EN0_ADDR_ACK_DIS << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting */
#define MXC_V_I2C_INT_EN0_ADDR_ACK_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */
#define MXC_S_I2C_INT_EN0_ADDR_ACK_EN (MXC_V_I2C_INT_EN0_ADDR_ACK_EN << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting */
#define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */
#define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */
#define MXC_V_I2C_INT_EN0_ARB_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_ARB_ER_DIS (MXC_V_I2C_INT_EN0_ARB_ER_DIS << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_ARB_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */
#define MXC_S_I2C_INT_EN0_ARB_ER_EN (MXC_V_I2C_INT_EN0_ARB_ER_EN << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */
#define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */
#define MXC_V_I2C_INT_EN0_TO_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_TO_ER_DIS (MXC_V_I2C_INT_EN0_TO_ER_DIS << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_TO_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */
#define MXC_S_I2C_INT_EN0_TO_ER_EN (MXC_V_I2C_INT_EN0_TO_ER_EN << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */
#define MXC_F_I2C_INT_EN0_ADDR_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER Mask */
#define MXC_V_I2C_INT_EN0_ADDR_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_ADDR_ER_DIS (MXC_V_I2C_INT_EN0_ADDR_ER_DIS << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_ADDR_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */
#define MXC_S_I2C_INT_EN0_ADDR_ER_EN (MXC_V_I2C_INT_EN0_ADDR_ER_EN << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */
#define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER Mask */
#define MXC_V_I2C_INT_EN0_DATA_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_DATA_ER_DIS (MXC_V_I2C_INT_EN0_DATA_ER_DIS << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_DATA_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */
#define MXC_S_I2C_INT_EN0_DATA_ER_EN (MXC_V_I2C_INT_EN0_DATA_ER_EN << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 /**< INT_EN0_DO_NOT_RESP_ER Position */
#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< INT_EN0_DO_NOT_RESP_ER Mask */
#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */
#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */
#define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER Mask */
#define MXC_V_I2C_INT_EN0_START_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_START_ER_DIS (MXC_V_I2C_INT_EN0_START_ER_DIS << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_START_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */
#define MXC_S_I2C_INT_EN0_START_ER_EN (MXC_V_I2C_INT_EN0_START_ER_EN << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */
#define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER Mask */
#define MXC_V_I2C_INT_EN0_STOP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_STOP_ER_DIS (MXC_V_I2C_INT_EN0_STOP_ER_DIS << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_STOP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */
#define MXC_S_I2C_INT_EN0_STOP_ER_EN (MXC_V_I2C_INT_EN0_STOP_ER_EN << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 /**< INT_EN0_TX_LOCK_OUT Position */
#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */
#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */
#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS Setting */
#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */
#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN Setting */
/**@} end of group I2C_INT_EN0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INT_FL1 I2C_INT_FL1
* @brief Interrupt Status Register 1.
* @{
*/
#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 /**< INT_FL1_RX_OVERFLOW Position */
#define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< INT_FL1_RX_OVERFLOW Mask */
#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */
#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_INACTIVE Setting */
#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */
#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING (MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_PENDING Setting */
#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 /**< INT_FL1_TX_UNDERFLOW Position */
#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */
#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */
#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Setting */
#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */
#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_PENDING Setting */
/**@} end of group I2C_INT_FL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INT_EN1 I2C_INT_EN1
* @brief Interrupt Staus Register 1.
* @{
*/
#define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 /**< INT_EN1_RX_OVERFLOW Position */
#define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< INT_EN1_RX_OVERFLOW Mask */
#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */
#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS (MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS Setting */
#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */
#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN (MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN Setting */
#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 /**< INT_EN1_TX_UNDERFLOW Position */
#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */
#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */
#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS Setting */
#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */
#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN Setting */
/**@} end of group I2C_INT_EN1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_FIFO_LEN I2C_FIFO_LEN
* @brief FIFO Configuration Register.
* @{
*/
#define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */
#define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN Mask */
#define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */
#define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN Mask */
/**@} end of group I2C_FIFO_LEN_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0
* @brief Receive Control Register 0.
* @{
*/
#define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */
#define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */
#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND ((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */
#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */
#define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY ((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */
#define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY (MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Setting */
#define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */
#define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH Mask */
#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */
#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED (MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Setting */
#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */
#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH (MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH Setting */
#define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */
#define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH Mask */
/**@} end of group I2C_RX_CTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1
* @brief Receive Control Register 1.
* @{
*/
#define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */
#define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT Mask */
#define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */
#define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO Mask */
/**@} end of group I2C_RX_CTRL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0
* @brief Transmit Control Register 0.
* @{
*/
#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 /**< TX_CTRL0_TX_PRELOAD Position */
#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< TX_CTRL0_TX_PRELOAD Mask */
#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 /**< TX_CTRL0_TX_READY_MODE Position */
#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */
#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN ((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */
#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_EN Setting */
#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS ((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */
#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_DIS Setting */
#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */
#define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */
#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */
#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED (MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Setting */
#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */
#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH (MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH Setting */
#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */
#define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH Mask */
/**@} end of group I2C_TX_CTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1
* @brief Transmit Control Register 1.
* @{
*/
#define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */
#define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY Mask */
#define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */
#define MXC_F_I2C_TX_CTRL1_TX_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST Mask */
#define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW ((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */
#define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW (MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Setting */
#define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION ((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */
#define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION (MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Setting */
#define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */
#define MXC_F_I2C_TX_CTRL1_TX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO Mask */
/**@} end of group I2C_TX_CTRL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_FIFO I2C_FIFO
* @brief Data Register.
* @{
*/
#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
/**@} end of group I2C_FIFO_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_MASTER_CTRL I2C_MASTER_CTRL
* @brief Master Control Register.
* @{
*/
#define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */
#define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START Mask */
#define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 /**< MASTER_CTRL_RESTART Position */
#define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< MASTER_CTRL_RESTART Mask */
#define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */
#define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP Mask */
#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 /**< MASTER_CTRL_SL_EX_ADDR Position */
#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< MASTER_CTRL_SL_EX_ADDR Mask */
#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */
#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Setting */
#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */
#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Setting */
#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS 8 /**< MASTER_CTRL_MASTER_CODE Position */
#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**< MASTER_CTRL_MASTER_CODE Mask */
#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 /**< MASTER_CTRL_SCL_SPEED_UP Position */
#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**< MASTER_CTRL_SCL_SPEED_UP Mask */
#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN ((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */
#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_EN Setting */
#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS ((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */
#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Setting */
/**@} end of group I2C_MASTER_CTRL_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_CLK_LO I2C_CLK_LO
* @brief Clock Low Register.
* @{
*/
#define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */
#define MXC_F_I2C_CLK_LO_CLK_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */
/**@} end of group I2C_CLK_LO_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_CLK_HI I2C_CLK_HI
* @brief Clock high Register.
* @{
*/
#define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */
#define MXC_F_I2C_CLK_HI_CKH ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */
/**@} end of group I2C_CLK_HI_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_HS_CLK I2C_HS_CLK
* @brief HS-Mode Clock Control Register
* @{
*/
#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
#define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */
#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
#define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */
/**@} end of group I2C_HS_CLK_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TIMEOUT I2C_TIMEOUT
* @brief Timeout Register
* @{
*/
#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
#define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
/**@} end of group I2C_TIMEOUT_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_SLAVE_ADDR I2C_SLAVE_ADDR
* @brief Slave Address Register.
* @{
*/
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_DIS Mask */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_IDX Mask */
#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 /**< SLAVE_ADDR_EX_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */
#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */
#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */
#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */
#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */
/**@} end of group I2C_SLAVE_ADDR_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_DMA I2C_DMA
* @brief DMA Register.
* @{
*/
#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */
#define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
#define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */
#define MXC_S_I2C_DMA_TX_EN_DIS (MXC_V_I2C_DMA_TX_EN_DIS << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */
#define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */
#define MXC_S_I2C_DMA_TX_EN_EN (MXC_V_I2C_DMA_TX_EN_EN << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */
#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */
#define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
#define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */
#define MXC_S_I2C_DMA_RX_EN_DIS (MXC_V_I2C_DMA_RX_EN_DIS << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */
#define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */
#define MXC_S_I2C_DMA_RX_EN_EN (MXC_V_I2C_DMA_RX_EN_EN << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */
/**@} end of group I2C_DMA_Register */
#ifdef __cplusplus
}
#endif
#endif /* _I2C_REGS_H_ */

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/**
* @file icc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _ICC_REGS_H_
#define _ICC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup icc
* @defgroup icc_registers ICC_Registers
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
* @details Instruction Cache Controller Registers
*/
/**
* @ingroup icc_registers
* Structure type to access the ICC Registers.
*/
typedef struct {
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
__I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> ICC MEMCFG Register */
__R uint32_t rsv_0x8_0xff[62];
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
__R uint32_t rsv_0x104_0x6ff[383];
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
} mxc_icc_regs_t;
/* Register offsets for module ICC */
/**
* @ingroup icc_registers
* @defgroup ICC_Register_Offsets Register Offsets
* @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address.
* @{
*/
#define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */
#define MXC_R_ICC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */
#define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */
#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */
/**@} end of group icc_registers */
/**
* @ingroup icc_registers
* @defgroup ICC_CACHE_ID ICC_CACHE_ID
* @brief Cache ID Register.
* @{
*/
#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
#define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
#define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
#define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
/**@} end of group ICC_CACHE_ID_Register */
/**
* @ingroup icc_registers
* @defgroup ICC_MEMCFG ICC_MEMCFG
* @brief Memory Configuration Register.
* @{
*/
#define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
#define MXC_F_ICC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
#define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
#define MXC_F_ICC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
/**@} end of group ICC_MEMCFG_Register */
/**
* @ingroup icc_registers
* @defgroup ICC_CACHE_CTRL ICC_CACHE_CTRL
* @brief Cache Control and Status Register.
* @{
*/
#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */
#define MXC_F_ICC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */
#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS Setting */
#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN Setting */
#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */
#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */
#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Setting */
#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_READY Setting */
/**@} end of group ICC_CACHE_CTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _ICC_REGS_H_ */

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/**
* @file max32660.h
* @brief Device-specific perhiperal header file
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#ifndef _MAX32660_REGS_H_
#define _MAX32660_REGS_H_
#ifndef TARGET_NUM
#define TARGET_NUM 32660
#endif
#include <stdint.h>
#ifndef FALSE
#define FALSE (0)
#endif
#ifndef TRUE
#define TRUE (1)
#endif
#if !defined (__GNUC__)
#define CMSIS_VECTAB_VIRTUAL
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
#endif /* !__GNUC__ */
/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
#if defined ( __GNUC__ ) /* GCC */
#define __weak __attribute__((weak))
#elif defined ( __CC_ARM) /* Keil */
#define inline __inline
#pragma anon_unions
#endif
typedef enum {
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
/* Device-specific interrupt sources (external to ARM core) */
/* table entry number */
/* |||| */
/* |||| table offset address */
/* vvvv vvvvvv */
PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */
RTC_IRQn, /* 0x13 0x004C 19: RTC */
RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */
TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */
RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */
RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */
RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */
RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */
I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
SPI17Y_IRQn, /* 0x20 0x0080 32: SPI17Y */
SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */
RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */
RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */
RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */
RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */
RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */
FLC_IRQn, /* 0x27 0x009C 39: FLC */
GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */
RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */
RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */
DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */
RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */
RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */
RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */
I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */
RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */
RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */
RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */
RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */
RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */
RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */
RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */
RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */
RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */
RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */
RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */
RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */
RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */
RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */
RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */
RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */
GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
MXC_IRQ_EXT_COUNT,
} IRQn_Type;
#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present or not */
#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
#include "system_max32660.h" /*!< System Header */
/* ================================================================================ */
/* ================== Device Specific Memory Section ================== */
/* ================================================================================ */
#define MXC_FLASH_MEM_BASE 0x00000000UL
#define MXC_FLASH_PAGE_SIZE 0x00002000UL
#define MXC_FLASH_MEM_SIZE 0x00040000UL
#define MXC_INFO_MEM_BASE 0x00040000UL
#define MXC_INFO_MEM_SIZE 0x00001000UL
#define MXC_SRAM_MEM_BASE 0x20000000UL
#define MXC_SRAM_MEM_SIZE 0x00018000UL
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/*
Base addresses and configuration settings for all MAX32660 peripheral modules.
*/
/******************************************************************************/
/* Global control */
#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
/******************************************************************************/
/* Non-battery backed SI Registers */
#define MXC_BASE_SIR ((uint32_t)0x40000400UL)
#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
/******************************************************************************/
/* Watchdog */
#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
/******************************************************************************/
/* Real Time Clock */
#define MXC_BASE_RTC ((uint32_t)0x40006000UL)
#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
/******************************************************************************/
/* Power Sequencer */
#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
/******************************************************************************/
/* GPIO */
#define MXC_CFG_GPIO_INSTANCES (1)
#define MXC_CFG_GPIO_PINS_PORT (14)
#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 :-1)
#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0)
#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0)
/******************************************************************************/
/* Timer */
#define MXC_CFG_TMR_INSTANCES (3)
#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
(i) == 1 ? TMR1_IRQn : \
(i) == 2 ? TMR2_IRQn : 0)
#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
(i) == 1 ? MXC_BASE_TMR1 : \
(i) == 2 ? MXC_BASE_TMR2 : 0)
#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
(i) == 1 ? MXC_TMR1 : \
(i) == 2 ? MXC_TMR2 : 0)
#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
(p) == MXC_TMR1 ? 1 : \
(p) == MXC_TMR2 ? 2 : -1)
/******************************************************************************/
/* SPIMSS */
#define MXC_SPIMSS_INSTANCES (1)
#define MXC_SPIMSS_FIFO_DEPTH (8)
#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL)
#define MXC_SPIMSS ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS)
#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1)
#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0)
/******************************************************************************/
/* I2C */
#define MXC_I2C_INSTANCES (2)
#define MXC_I2C_FIFO_DEPTH (8)
#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0)
#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1)
#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \
(i) == 1 ? I2C1_IRQn : 0)
#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \
(i) == 1 ? MXC_BASE_I2C1 : 0)
#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \
(i) == 1 ? MXC_I2C1 : 0)
#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \
(p) == MXC_I2C1 ? 1 : -1)
/******************************************************************************/
/* DMA */
#define MXC_DMA_CHANNELS (4)
#define MXC_BASE_DMA ((uint32_t)0x40028000UL)
#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA)
/******************************************************************************/
/* FLC */
#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
#define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC)
/******************************************************************************/
/* Instruction Cache */
#define MXC_BASE_ICC ((uint32_t)0x4002A000UL)
#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC)
/******************************************************************************/
/* UART / Serial Port Interface */
#define MXC_UART_INSTANCES (2)
#define MXC_UART_FIFO_DEPTH (8)
#define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
#define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
(i) == 1 ? UART1_IRQn : 0)
#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
(i) == 1 ? MXC_BASE_UART1 : 0)
#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
(i) == 1 ? MXC_UART1 : 0)
#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
(p) == MXC_UART1 ? 1 : -1)
/******************************************************************************/
/* SPI */
#define MXC_SPI17Y_INSTANCES (4)
#define MXC_SPI17Y_SS_INSTANCES (1)
#define MXC_SPI17Y_FIFO_DEPTH (32)
#define MXC_BASE_SPI17Y ((uint32_t)0x40046000UL)
#define MXC_SPI17Y ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y)
#define MXC_SPI17Y_GET_IDX(p) ((p) == MXC_SPI17Y ? 0 : -1)
#define MXC_SPI17Y_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI17Y : 0)
#define MXC_SPI17Y_GET_SPI17Y(i) ((i) == 0 ? MXC_SPI17Y : 0)
/******************************************************************************/
/* Bit Shifting */
#define MXC_F_BIT_0 (1 << 0)
#define MXC_F_BIT_1 (1 << 1)
#define MXC_F_BIT_2 (1 << 2)
#define MXC_F_BIT_3 (1 << 3)
#define MXC_F_BIT_4 (1 << 4)
#define MXC_F_BIT_5 (1 << 5)
#define MXC_F_BIT_6 (1 << 6)
#define MXC_F_BIT_7 (1 << 7)
#define MXC_F_BIT_8 (1 << 8)
#define MXC_F_BIT_9 (1 << 9)
#define MXC_F_BIT_10 (1 << 10)
#define MXC_F_BIT_11 (1 << 11)
#define MXC_F_BIT_12 (1 << 12)
#define MXC_F_BIT_13 (1 << 13)
#define MXC_F_BIT_14 (1 << 14)
#define MXC_F_BIT_15 (1 << 15)
#define MXC_F_BIT_16 (1 << 16)
#define MXC_F_BIT_17 (1 << 17)
#define MXC_F_BIT_18 (1 << 18)
#define MXC_F_BIT_19 (1 << 19)
#define MXC_F_BIT_20 (1 << 20)
#define MXC_F_BIT_21 (1 << 21)
#define MXC_F_BIT_22 (1 << 22)
#define MXC_F_BIT_23 (1 << 23)
#define MXC_F_BIT_24 (1 << 24)
#define MXC_F_BIT_25 (1 << 25)
#define MXC_F_BIT_26 (1 << 26)
#define MXC_F_BIT_27 (1 << 27)
#define MXC_F_BIT_28 (1 << 28)
#define MXC_F_BIT_29 (1 << 29)
#define MXC_F_BIT_30 (1 << 30)
#define MXC_F_BIT_31 (1 << 31)
/******************************************************************************/
/* Bit Banding */
#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
(((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask))
/******************************************************************************/
/* SCB CPACR */
/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
#endif /* _MAX32660_REGS_H_ */

72
Project/SDK/Device/Include/mxc_device.h
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/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
/**
* @file mxc_device.h
* @brief contains device and revision specific definitions
*/
#ifndef _MXC_DEVICE_H_
#define _MXC_DEVICE_H_
#include "max32660.h"
#ifndef TARGET
#error TARGET NOT DEFINED
#endif
// Create a string definition for the TARGET
#define STRING_ARG(arg) #arg
#define STRING_NAME(name) STRING_ARG(name)
#define TARGET_NAME STRING_NAME(TARGET)
// Define which revisions of the IP we are using
#ifndef TARGET_REV
#error TARGET_REV NOT DEFINED
#endif
#if(TARGET_REV == 0x4131)
// A1
#define MXC_PBM_REV 0
#define MXC_TMR_REV 0
#define MXC_UART_REV 1
#else
#error TARGET_REV NOT SUPPORTED
#endif // if(TARGET_REV == ...)
#endif /* _MXC_DEVICE_H_ */

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/**
* @file pwrseq_regs.h
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _PWRSEQ_REGS_H_
#define _PWRSEQ_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup pwrseq
* @defgroup pwrseq_registers PWRSEQ_Registers
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
* @details Power Sequencer / Low Power Control Register.
*/
/**
* @ingroup pwrseq_registers
* Structure type to access the PWRSEQ Registers.
*/
typedef struct {
__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
__R uint32_t rsv_0xc_0x3f[13];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
} mxc_pwrseq_regs_t;
/* Register offsets for module PWRSEQ */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_Register_Offsets Register Offsets
* @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address.
* @{
*/
#define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */
#define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */
#define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
/**@} end of group pwrseq_registers */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LP_CTRL PWRSEQ_LP_CTRL
* @brief Low Power Control Register.
* @{
*/
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
#define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */
#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */
#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting */
#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_EN Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_DIS Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_EN Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_DIS Setting */
/**@} end of group PWRSEQ_LP_CTRL_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LP_WAKEFL PWRSEQ_LP_WAKEFL
* @brief Low Power Mode Wakeup Flags for GPIO0
* @{
*/
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */
/**@} end of group PWRSEQ_LP_WAKEFL_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LPWK_EN PWRSEQ_LPWK_EN
* @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup
* functionality for GPIO0.
* @{
*/
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */
/**@} end of group PWRSEQ_LPWK_EN_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD
* @brief Low Power Memory Shutdown Control.
* @{
*/
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Setting */
/**@} end of group PWRSEQ_LPMEMSD_Register */
#ifdef __cplusplus
}
#endif
#endif /* _PWRSEQ_REGS_H_ */

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Project/SDK/Device/Include/rtc_regs.h
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/**
* @file rtc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _RTC_REGS_H_
#define _RTC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup rtc
* @defgroup rtc_registers RTC_Registers
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
* @details Real Time Clock and Alarm.
*/
/**
* @ingroup rtc_registers
* Structure type to access the RTC Registers.
*/
typedef struct {
__IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */
__IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */
__IO uint32_t ras; /**< <tt>\b 0x08:</tt> RTC RAS Register */
__IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> RTC RSSA Register */
__IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */
__IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */
__IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */
} mxc_rtc_regs_t;
/* Register offsets for module RTC */
/**
* @ingroup rtc_registers
* @defgroup RTC_Register_Offsets Register Offsets
* @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address.
* @{
*/
#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
#define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
#define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
/**@} end of group rtc_registers */
/**
* @ingroup rtc_registers
* @defgroup RTC_SSEC RTC_SSEC
* @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented
* when this register rolls over from 0xFF to 0x00.
* @{
*/
#define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */
#define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */
/**@} end of group RTC_SSEC_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_RAS RTC_RAS
* @brief Time-of-day Alarm.
* @{
*/
#define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */
#define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */
/**@} end of group RTC_RAS_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_RSSA RTC_RSSA
* @brief RTC sub-second alarm. This register contains the reload value for the sub-
* second alarm.
* @{
*/
#define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */
#define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */
/**@} end of group RTC_RSSA_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_CTRL RTC_CTRL
* @brief RTC Control Register.
* @{
*/
#define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */
#define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */
#define MXC_V_RTC_CTRL_RTCE_DIS ((uint32_t)0x0UL) /**< CTRL_RTCE_DIS Value */
#define MXC_S_RTC_CTRL_RTCE_DIS (MXC_V_RTC_CTRL_RTCE_DIS << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_DIS Setting */
#define MXC_V_RTC_CTRL_RTCE_EN ((uint32_t)0x1UL) /**< CTRL_RTCE_EN Value */
#define MXC_S_RTC_CTRL_RTCE_EN (MXC_V_RTC_CTRL_RTCE_EN << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_EN Setting */
#define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */
#define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */
#define MXC_V_RTC_CTRL_ADE_DIS ((uint32_t)0x0UL) /**< CTRL_ADE_DIS Value */
#define MXC_S_RTC_CTRL_ADE_DIS (MXC_V_RTC_CTRL_ADE_DIS << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_DIS Setting */
#define MXC_V_RTC_CTRL_ADE_EN ((uint32_t)0x1UL) /**< CTRL_ADE_EN Value */
#define MXC_S_RTC_CTRL_ADE_EN (MXC_V_RTC_CTRL_ADE_EN << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_EN Setting */
#define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */
#define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */
#define MXC_V_RTC_CTRL_ASE_DIS ((uint32_t)0x0UL) /**< CTRL_ASE_DIS Value */
#define MXC_S_RTC_CTRL_ASE_DIS (MXC_V_RTC_CTRL_ASE_DIS << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_DIS Setting */
#define MXC_V_RTC_CTRL_ASE_EN ((uint32_t)0x1UL) /**< CTRL_ASE_EN Value */
#define MXC_S_RTC_CTRL_ASE_EN (MXC_V_RTC_CTRL_ASE_EN << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_EN Setting */
#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */
#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
#define MXC_V_RTC_CTRL_BUSY_IDLE ((uint32_t)0x0UL) /**< CTRL_BUSY_IDLE Value */
#define MXC_S_RTC_CTRL_BUSY_IDLE (MXC_V_RTC_CTRL_BUSY_IDLE << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_IDLE Setting */
#define MXC_V_RTC_CTRL_BUSY_BUSY ((uint32_t)0x1UL) /**< CTRL_BUSY_BUSY Value */
#define MXC_S_RTC_CTRL_BUSY_BUSY (MXC_V_RTC_CTRL_BUSY_BUSY << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_BUSY Setting */
#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */
#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
#define MXC_V_RTC_CTRL_RDY_BUSY ((uint32_t)0x0UL) /**< CTRL_RDY_BUSY Value */
#define MXC_S_RTC_CTRL_RDY_BUSY (MXC_V_RTC_CTRL_RDY_BUSY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_BUSY Setting */
#define MXC_V_RTC_CTRL_RDY_READY ((uint32_t)0x1UL) /**< CTRL_RDY_READY Value */
#define MXC_S_RTC_CTRL_RDY_READY (MXC_V_RTC_CTRL_RDY_READY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_READY Setting */
#define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */
#define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */
#define MXC_V_RTC_CTRL_RDYE_DIS ((uint32_t)0x0UL) /**< CTRL_RDYE_DIS Value */
#define MXC_S_RTC_CTRL_RDYE_DIS (MXC_V_RTC_CTRL_RDYE_DIS << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_DIS Setting */
#define MXC_V_RTC_CTRL_RDYE_EN ((uint32_t)0x1UL) /**< CTRL_RDYE_EN Value */
#define MXC_S_RTC_CTRL_RDYE_EN (MXC_V_RTC_CTRL_RDYE_EN << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_EN Setting */
#define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */
#define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */
#define MXC_V_RTC_CTRL_ALDF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALDF_INACTIVE Value */
#define MXC_S_RTC_CTRL_ALDF_INACTIVE (MXC_V_RTC_CTRL_ALDF_INACTIVE << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_INACTIVE Setting */
#define MXC_V_RTC_CTRL_ALDF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALDF_PENDING Value */
#define MXC_S_RTC_CTRL_ALDF_PENDING (MXC_V_RTC_CTRL_ALDF_PENDING << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_PENDING Setting */
#define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */
#define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */
#define MXC_V_RTC_CTRL_ALSF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALSF_INACTIVE Value */
#define MXC_S_RTC_CTRL_ALSF_INACTIVE (MXC_V_RTC_CTRL_ALSF_INACTIVE << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_INACTIVE Setting */
#define MXC_V_RTC_CTRL_ALSF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALSF_PENDING Value */
#define MXC_S_RTC_CTRL_ALSF_PENDING (MXC_V_RTC_CTRL_ALSF_PENDING << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_PENDING Setting */
#define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */
#define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */
#define MXC_V_RTC_CTRL_SQE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_SQE_INACTIVE Value */
#define MXC_S_RTC_CTRL_SQE_INACTIVE (MXC_V_RTC_CTRL_SQE_INACTIVE << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_INACTIVE Setting */
#define MXC_V_RTC_CTRL_SQE_PENDING ((uint32_t)0x1UL) /**< CTRL_SQE_PENDING Value */
#define MXC_S_RTC_CTRL_SQE_PENDING (MXC_V_RTC_CTRL_SQE_PENDING << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_PENDING Setting */
#define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */
#define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */
#define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */
#define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */
#define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */
#define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */
#define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */
#define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */
#define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */
#define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */
#define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */
#define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */
#define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */
#define MXC_V_RTC_CTRL_WE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_WE_INACTIVE Value */
#define MXC_S_RTC_CTRL_WE_INACTIVE (MXC_V_RTC_CTRL_WE_INACTIVE << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_INACTIVE Setting */
#define MXC_V_RTC_CTRL_WE_PENDING ((uint32_t)0x1UL) /**< CTRL_WE_PENDING Value */
#define MXC_S_RTC_CTRL_WE_PENDING (MXC_V_RTC_CTRL_WE_PENDING << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_PENDING Setting */
/**@} end of group RTC_CTRL_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_TRIM RTC_TRIM
* @brief RTC Trim Register.
* @{
*/
#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */
#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
#define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */
#define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */
/**@} end of group RTC_TRIM_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_OSCCTRL RTC_OSCCTRL
* @brief RTC Oscillator Control Register.
* @{
*/
#define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */
#define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */
#define MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X ((uint32_t)0x0UL) /**< OSCCTRL_IBIAS_SEL_2X Value */
#define MXC_S_RTC_OSCCTRL_IBIAS_SEL_2X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_2X Setting */
#define MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X ((uint32_t)0x1UL) /**< OSCCTRL_IBIAS_SEL_4X Value */
#define MXC_S_RTC_OSCCTRL_IBIAS_SEL_4X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_4X Setting */
#define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */
#define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */
#define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */
#define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */
#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */
#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
#define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */
#define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */
/**@} end of group RTC_OSCCTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _RTC_REGS_H_ */

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Project/SDK/Device/Include/sir_regs.h
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/**
* @file sir_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SIR_REGS_H_
#define _SIR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup sir
* @defgroup sir_registers SIR_Registers
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
* @details System Initialization Registers.
*/
/**
* @ingroup sir_registers
* Structure type to access the SIR Registers.
*/
typedef struct {
__I uint32_t sistat; /**< <tt>\b 0x00:</tt> SIR SISTAT Register */
__I uint32_t erraddr; /**< <tt>\b 0x04:</tt> SIR ERRADDR Register */
__R uint32_t rsv_0x8_0xff[62];
__I uint32_t fstat; /**< <tt>\b 0x100:</tt> SIR FSTAT Register */
__I uint32_t sfstat; /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */
} mxc_sir_regs_t;
/* Register offsets for module SIR */
/**
* @ingroup sir_registers
* @defgroup SIR_Register_Offsets Register Offsets
* @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address.
* @{
*/
#define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */
#define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */
#define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */
#define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */
/**@} end of group sir_registers */
/**
* @ingroup sir_registers
* @defgroup SIR_SISTAT SIR_SISTAT
* @brief System Initialization Status Register.
* @{
*/
#define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */
#define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */
#define MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET ((uint32_t)0x0UL) /**< SISTAT_MAGIC_MAGICNOTSET Value */
#define MXC_S_SIR_SISTAT_MAGIC_MAGICNOTSET (MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICNOTSET Setting */
#define MXC_V_SIR_SISTAT_MAGIC_MAGICSET ((uint32_t)0x1UL) /**< SISTAT_MAGIC_MAGICSET Value */
#define MXC_S_SIR_SISTAT_MAGIC_MAGICSET (MXC_V_SIR_SISTAT_MAGIC_MAGICSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICSET Setting */
#define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */
#define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */
#define MXC_V_SIR_SISTAT_CRCERR_NOERROR ((uint32_t)0x0UL) /**< SISTAT_CRCERR_NOERROR Value */
#define MXC_S_SIR_SISTAT_CRCERR_NOERROR (MXC_V_SIR_SISTAT_CRCERR_NOERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_NOERROR Setting */
#define MXC_V_SIR_SISTAT_CRCERR_ERROR ((uint32_t)0x1UL) /**< SISTAT_CRCERR_ERROR Value */
#define MXC_S_SIR_SISTAT_CRCERR_ERROR (MXC_V_SIR_SISTAT_CRCERR_ERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_ERROR Setting */
/**@} end of group SIR_SISTAT_Register */
/**
* @ingroup sir_registers
* @defgroup SIR_ERRADDR SIR_ERRADDR
* @brief Read-only field set by the SIB block if a CRC error occurs during the read of
* the OTP memory. Contains the failing address in OTP memory (when CRCERR equals
* 1).
* @{
*/
#define MXC_F_SIR_ERRADDR_ERRADDR_POS 0 /**< ERRADDR_ERRADDR Position */
#define MXC_F_SIR_ERRADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ERRADDR_ERRADDR_POS)) /**< ERRADDR_ERRADDR Mask */
/**@} end of group SIR_ERRADDR_Register */
/**
* @ingroup sir_registers
* @defgroup SIR_FSTAT SIR_FSTAT
* @brief funcstat register.
* @{
*/
#define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */
#define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */
#define MXC_V_SIR_FSTAT_FPU_NO ((uint32_t)0x0UL) /**< FSTAT_FPU_NO Value */
#define MXC_S_SIR_FSTAT_FPU_NO (MXC_V_SIR_FSTAT_FPU_NO << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_NO Setting */
#define MXC_V_SIR_FSTAT_FPU_YES ((uint32_t)0x1UL) /**< FSTAT_FPU_YES Value */
#define MXC_S_SIR_FSTAT_FPU_YES (MXC_V_SIR_FSTAT_FPU_YES << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_YES Setting */
#define MXC_F_SIR_FSTAT_USB_POS 1 /**< FSTAT_USB Position */
#define MXC_F_SIR_FSTAT_USB ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */
#define MXC_V_SIR_FSTAT_USB_NO ((uint32_t)0x0UL) /**< FSTAT_USB_NO Value */
#define MXC_S_SIR_FSTAT_USB_NO (MXC_V_SIR_FSTAT_USB_NO << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_NO Setting */
#define MXC_V_SIR_FSTAT_USB_YES ((uint32_t)0x1UL) /**< FSTAT_USB_YES Value */
#define MXC_S_SIR_FSTAT_USB_YES (MXC_V_SIR_FSTAT_USB_YES << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_YES Setting */
#define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */
#define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */
#define MXC_V_SIR_FSTAT_ADC_NO ((uint32_t)0x0UL) /**< FSTAT_ADC_NO Value */
#define MXC_S_SIR_FSTAT_ADC_NO (MXC_V_SIR_FSTAT_ADC_NO << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_NO Setting */
#define MXC_V_SIR_FSTAT_ADC_YES ((uint32_t)0x1UL) /**< FSTAT_ADC_YES Value */
#define MXC_S_SIR_FSTAT_ADC_YES (MXC_V_SIR_FSTAT_ADC_YES << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_YES Setting */
#define MXC_F_SIR_FSTAT_XIP_POS 3 /**< FSTAT_XIP Position */
#define MXC_F_SIR_FSTAT_XIP ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_XIP_POS)) /**< FSTAT_XIP Mask */
#define MXC_V_SIR_FSTAT_XIP_NO ((uint32_t)0x0UL) /**< FSTAT_XIP_NO Value */
#define MXC_S_SIR_FSTAT_XIP_NO (MXC_V_SIR_FSTAT_XIP_NO << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_NO Setting */
#define MXC_V_SIR_FSTAT_XIP_YES ((uint32_t)0x1UL) /**< FSTAT_XIP_YES Value */
#define MXC_S_SIR_FSTAT_XIP_YES (MXC_V_SIR_FSTAT_XIP_YES << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_YES Setting */
#define MXC_F_SIR_FSTAT_PBM_POS 4 /**< FSTAT_PBM Position */
#define MXC_F_SIR_FSTAT_PBM ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_PBM_POS)) /**< FSTAT_PBM Mask */
#define MXC_V_SIR_FSTAT_PBM_NO ((uint32_t)0x0UL) /**< FSTAT_PBM_NO Value */
#define MXC_S_SIR_FSTAT_PBM_NO (MXC_V_SIR_FSTAT_PBM_NO << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_NO Setting */
#define MXC_V_SIR_FSTAT_PBM_YES ((uint32_t)0x1UL) /**< FSTAT_PBM_YES Value */
#define MXC_S_SIR_FSTAT_PBM_YES (MXC_V_SIR_FSTAT_PBM_YES << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_YES Setting */
#define MXC_F_SIR_FSTAT_HBC_POS 5 /**< FSTAT_HBC Position */
#define MXC_F_SIR_FSTAT_HBC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_HBC_POS)) /**< FSTAT_HBC Mask */
#define MXC_V_SIR_FSTAT_HBC_NO ((uint32_t)0x0UL) /**< FSTAT_HBC_NO Value */
#define MXC_S_SIR_FSTAT_HBC_NO (MXC_V_SIR_FSTAT_HBC_NO << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_NO Setting */
#define MXC_V_SIR_FSTAT_HBC_YES ((uint32_t)0x1UL) /**< FSTAT_HBC_YES Value */
#define MXC_S_SIR_FSTAT_HBC_YES (MXC_V_SIR_FSTAT_HBC_YES << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_YES Setting */
#define MXC_F_SIR_FSTAT_SDHC_POS 6 /**< FSTAT_SDHC Position */
#define MXC_F_SIR_FSTAT_SDHC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SDHC_POS)) /**< FSTAT_SDHC Mask */
#define MXC_V_SIR_FSTAT_SDHC_NO ((uint32_t)0x0UL) /**< FSTAT_SDHC_NO Value */
#define MXC_S_SIR_FSTAT_SDHC_NO (MXC_V_SIR_FSTAT_SDHC_NO << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_NO Setting */
#define MXC_V_SIR_FSTAT_SDHC_YES ((uint32_t)0x1UL) /**< FSTAT_SDHC_YES Value */
#define MXC_S_SIR_FSTAT_SDHC_YES (MXC_V_SIR_FSTAT_SDHC_YES << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_YES Setting */
#define MXC_F_SIR_FSTAT_SMPHR_POS 7 /**< FSTAT_SMPHR Position */
#define MXC_F_SIR_FSTAT_SMPHR ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */
#define MXC_V_SIR_FSTAT_SMPHR_NO ((uint32_t)0x0UL) /**< FSTAT_SMPHR_NO Value */
#define MXC_S_SIR_FSTAT_SMPHR_NO (MXC_V_SIR_FSTAT_SMPHR_NO << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_NO Setting */
#define MXC_V_SIR_FSTAT_SMPHR_YES ((uint32_t)0x1UL) /**< FSTAT_SMPHR_YES Value */
#define MXC_S_SIR_FSTAT_SMPHR_YES (MXC_V_SIR_FSTAT_SMPHR_YES << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_YES Setting */
#define MXC_F_SIR_FSTAT_SCACHE_POS 8 /**< FSTAT_SCACHE Position */
#define MXC_F_SIR_FSTAT_SCACHE ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SCACHE_POS)) /**< FSTAT_SCACHE Mask */
#define MXC_V_SIR_FSTAT_SCACHE_NO ((uint32_t)0x0UL) /**< FSTAT_SCACHE_NO Value */
#define MXC_S_SIR_FSTAT_SCACHE_NO (MXC_V_SIR_FSTAT_SCACHE_NO << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_NO Setting */
#define MXC_V_SIR_FSTAT_SCACHE_YES ((uint32_t)0x1UL) /**< FSTAT_SCACHE_YES Value */
#define MXC_S_SIR_FSTAT_SCACHE_YES (MXC_V_SIR_FSTAT_SCACHE_YES << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_YES Setting */
/**@} end of group SIR_FSTAT_Register */
/**
* @ingroup sir_registers
* @defgroup SIR_SFSTAT SIR_SFSTAT
* @brief secfuncstat register.
* @{
*/
#define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */
#define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */
#define MXC_V_SIR_SFSTAT_TRNG_NO ((uint32_t)0x0UL) /**< SFSTAT_TRNG_NO Value */
#define MXC_S_SIR_SFSTAT_TRNG_NO (MXC_V_SIR_SFSTAT_TRNG_NO << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_NO Setting */
#define MXC_V_SIR_SFSTAT_TRNG_YES ((uint32_t)0x1UL) /**< SFSTAT_TRNG_YES Value */
#define MXC_S_SIR_SFSTAT_TRNG_YES (MXC_V_SIR_SFSTAT_TRNG_YES << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_YES Setting */
#define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */
#define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */
#define MXC_V_SIR_SFSTAT_AES_NO ((uint32_t)0x0UL) /**< SFSTAT_AES_NO Value */
#define MXC_S_SIR_SFSTAT_AES_NO (MXC_V_SIR_SFSTAT_AES_NO << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_NO Setting */
#define MXC_V_SIR_SFSTAT_AES_YES ((uint32_t)0x1UL) /**< SFSTAT_AES_YES Value */
#define MXC_S_SIR_SFSTAT_AES_YES (MXC_V_SIR_SFSTAT_AES_YES << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_YES Setting */
#define MXC_F_SIR_SFSTAT_SHA_POS 4 /**< SFSTAT_SHA Position */
#define MXC_F_SIR_SFSTAT_SHA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHA_POS)) /**< SFSTAT_SHA Mask */
#define MXC_V_SIR_SFSTAT_SHA_NO ((uint32_t)0x0UL) /**< SFSTAT_SHA_NO Value */
#define MXC_S_SIR_SFSTAT_SHA_NO (MXC_V_SIR_SFSTAT_SHA_NO << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_NO Setting */
#define MXC_V_SIR_SFSTAT_SHA_YES ((uint32_t)0x1UL) /**< SFSTAT_SHA_YES Value */
#define MXC_S_SIR_SFSTAT_SHA_YES (MXC_V_SIR_SFSTAT_SHA_YES << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_YES Setting */
#define MXC_F_SIR_SFSTAT_MAA_POS 5 /**< SFSTAT_MAA Position */
#define MXC_F_SIR_SFSTAT_MAA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_MAA_POS)) /**< SFSTAT_MAA Mask */
#define MXC_V_SIR_SFSTAT_MAA_NO ((uint32_t)0x0UL) /**< SFSTAT_MAA_NO Value */
#define MXC_S_SIR_SFSTAT_MAA_NO (MXC_V_SIR_SFSTAT_MAA_NO << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_NO Setting */
#define MXC_V_SIR_SFSTAT_MAA_YES ((uint32_t)0x1UL) /**< SFSTAT_MAA_YES Value */
#define MXC_S_SIR_SFSTAT_MAA_YES (MXC_V_SIR_SFSTAT_MAA_YES << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_YES Setting */
/**@} end of group SIR_SFSTAT_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SIR_REGS_H_ */

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Project/SDK/Device/Include/smon_regs.h
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/**
* @file smon_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SMON_REGS_H_
#define _SMON_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup smon
* @defgroup smon_registers SMON_Registers
* @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module.
* @details The Security Monitor block used to monitor system threat conditions.
*/
/**
* @ingroup smon_registers
* Structure type to access the SMON Registers.
*/
typedef struct {
__IO uint32_t extscn; /**< <tt>\b 0x00:</tt> SMON EXTSCN Register */
__IO uint32_t intscn; /**< <tt>\b 0x04:</tt> SMON INTSCN Register */
__IO uint32_t secalm; /**< <tt>\b 0x08:</tt> SMON SECALM Register */
__I uint32_t secdiag; /**< <tt>\b 0x0C:</tt> SMON SECDIAG Register */
__I uint32_t dlrtc; /**< <tt>\b 0x10:</tt> SMON DLRTC Register */
__R uint32_t rsv_0x14_0x33[8];
__I uint32_t secst; /**< <tt>\b 0x34:</tt> SMON SECST Register */
} mxc_smon_regs_t;
/* Register offsets for module SMON */
/**
* @ingroup smon_registers
* @defgroup SMON_Register_Offsets Register Offsets
* @brief SMON Peripheral Register Offsets from the SMON Base Peripheral Address.
* @{
*/
#define MXC_R_SMON_EXTSCN ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: <tt> 0x0000</tt> */
#define MXC_R_SMON_INTSCN ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: <tt> 0x0004</tt> */
#define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: <tt> 0x0008</tt> */
#define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: <tt> 0x000C</tt> */
#define MXC_R_SMON_DLRTC ((uint32_t)0x00000010UL) /**< Offset from SMON Base Address: <tt> 0x0010</tt> */
#define MXC_R_SMON_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: <tt> 0x0034</tt> */
/**@} end of group smon_registers */
/**
* @ingroup smon_registers
* @defgroup SMON_EXTSCN SMON_EXTSCN
* @brief External Sensor Control Register.
* @{
*/
#define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0 /**< EXTSCN_EXTS_EN0 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN0_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN0_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN0_DIS (MXC_V_SMON_EXTSCN_EXTS_EN0_DIS << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN0_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN0_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN0_EN (MXC_V_SMON_EXTSCN_EXTS_EN0_EN << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1 /**< EXTSCN_EXTS_EN1 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN1_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN1_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN1_DIS (MXC_V_SMON_EXTSCN_EXTS_EN1_DIS << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN1_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN1_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN1_EN (MXC_V_SMON_EXTSCN_EXTS_EN1_EN << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2 /**< EXTSCN_EXTS_EN2 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN2_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN2_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN2_DIS (MXC_V_SMON_EXTSCN_EXTS_EN2_DIS << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN2_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN2_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN2_EN (MXC_V_SMON_EXTSCN_EXTS_EN2_EN << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3 /**< EXTSCN_EXTS_EN3 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN3_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN3_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN3_DIS (MXC_V_SMON_EXTSCN_EXTS_EN3_DIS << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN3_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN3_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN3_EN (MXC_V_SMON_EXTSCN_EXTS_EN3_EN << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4 /**< EXTSCN_EXTS_EN4 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN4_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN4_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN4_DIS (MXC_V_SMON_EXTSCN_EXTS_EN4_DIS << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN4_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN4_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN4_EN (MXC_V_SMON_EXTSCN_EXTS_EN4_EN << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5 /**< EXTSCN_EXTS_EN5 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN5_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN5_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN5_DIS (MXC_V_SMON_EXTSCN_EXTS_EN5_DIS << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN5_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN5_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN5_EN (MXC_V_SMON_EXTSCN_EXTS_EN5_EN << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTCNT_POS 16 /**< EXTSCN_EXTCNT Position */
#define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */
#define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21 /**< EXTSCN_EXTFRQ Position */
#define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_RFU (MXC_V_SMON_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */
#define MXC_F_SMON_EXTSCN_DIVCLK_POS 24 /**< EXTSCN_DIVCLK Position */
#define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */
#define MXC_F_SMON_EXTSCN_BUSY_POS 30 /**< EXTSCN_BUSY Position */
#define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */
#define MXC_V_SMON_EXTSCN_BUSY_IDLE ((uint32_t)0x0UL) /**< EXTSCN_BUSY_IDLE Value */
#define MXC_S_SMON_EXTSCN_BUSY_IDLE (MXC_V_SMON_EXTSCN_BUSY_IDLE << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_IDLE Setting */
#define MXC_V_SMON_EXTSCN_BUSY_BUSY ((uint32_t)0x1UL) /**< EXTSCN_BUSY_BUSY Value */
#define MXC_S_SMON_EXTSCN_BUSY_BUSY (MXC_V_SMON_EXTSCN_BUSY_BUSY << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_BUSY Setting */
#define MXC_F_SMON_EXTSCN_LOCK_POS 31 /**< EXTSCN_LOCK Position */
#define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */
#define MXC_V_SMON_EXTSCN_LOCK_UNLOCKED ((uint32_t)0x0UL) /**< EXTSCN_LOCK_UNLOCKED Value */
#define MXC_S_SMON_EXTSCN_LOCK_UNLOCKED (MXC_V_SMON_EXTSCN_LOCK_UNLOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_UNLOCKED Setting */
#define MXC_V_SMON_EXTSCN_LOCK_LOCKED ((uint32_t)0x1UL) /**< EXTSCN_LOCK_LOCKED Value */
#define MXC_S_SMON_EXTSCN_LOCK_LOCKED (MXC_V_SMON_EXTSCN_LOCK_LOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_LOCKED Setting */
/**@} end of group SMON_EXTSCN_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_INTSCN SMON_INTSCN
* @brief Internal Sensor Control Register.
* @{
*/
#define MXC_F_SMON_INTSCN_SHIELD_EN_POS 0 /**< INTSCN_SHIELD_EN Position */
#define MXC_F_SMON_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */
#define MXC_V_SMON_INTSCN_SHIELD_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_SHIELD_EN_DIS Value */
#define MXC_S_SMON_INTSCN_SHIELD_EN_DIS (MXC_V_SMON_INTSCN_SHIELD_EN_DIS << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_DIS Setting */
#define MXC_V_SMON_INTSCN_SHIELD_EN_EN ((uint32_t)0x1UL) /**< INTSCN_SHIELD_EN_EN Value */
#define MXC_S_SMON_INTSCN_SHIELD_EN_EN (MXC_V_SMON_INTSCN_SHIELD_EN_EN << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_EN Setting */
#define MXC_F_SMON_INTSCN_TEMP_EN_POS 1 /**< INTSCN_TEMP_EN Position */
#define MXC_F_SMON_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */
#define MXC_V_SMON_INTSCN_TEMP_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_TEMP_EN_DIS Value */
#define MXC_S_SMON_INTSCN_TEMP_EN_DIS (MXC_V_SMON_INTSCN_TEMP_EN_DIS << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_DIS Setting */
#define MXC_V_SMON_INTSCN_TEMP_EN_EN ((uint32_t)0x1UL) /**< INTSCN_TEMP_EN_EN Value */
#define MXC_S_SMON_INTSCN_TEMP_EN_EN (MXC_V_SMON_INTSCN_TEMP_EN_EN << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_EN Setting */
#define MXC_F_SMON_INTSCN_VBAT_EN_POS 2 /**< INTSCN_VBAT_EN Position */
#define MXC_F_SMON_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */
#define MXC_V_SMON_INTSCN_VBAT_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_VBAT_EN_DIS Value */
#define MXC_S_SMON_INTSCN_VBAT_EN_DIS (MXC_V_SMON_INTSCN_VBAT_EN_DIS << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_DIS Setting */
#define MXC_V_SMON_INTSCN_VBAT_EN_EN ((uint32_t)0x1UL) /**< INTSCN_VBAT_EN_EN Value */
#define MXC_S_SMON_INTSCN_VBAT_EN_EN (MXC_V_SMON_INTSCN_VBAT_EN_EN << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_EN Setting */
#define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS 16 /**< INTSCN_LOTEMP_SEL Position */
#define MXC_F_SMON_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */
#define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C ((uint32_t)0x0UL) /**< INTSCN_LOTEMP_SEL_NEG50C Value */
#define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG50C (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG50C Setting */
#define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C ((uint32_t)0x1UL) /**< INTSCN_LOTEMP_SEL_NEG30C Value */
#define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG30C (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG30C Setting */
#define MXC_F_SMON_INTSCN_VCORELOEN_POS 18 /**< INTSCN_VCORELOEN Position */
#define MXC_F_SMON_INTSCN_VCORELOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCORELOEN_POS)) /**< INTSCN_VCORELOEN Mask */
#define MXC_V_SMON_INTSCN_VCORELOEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VCORELOEN_DIS Value */
#define MXC_S_SMON_INTSCN_VCORELOEN_DIS (MXC_V_SMON_INTSCN_VCORELOEN_DIS << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VCORELOEN_EN ((uint32_t)0x1UL) /**< INTSCN_VCORELOEN_EN Value */
#define MXC_S_SMON_INTSCN_VCORELOEN_EN (MXC_V_SMON_INTSCN_VCORELOEN_EN << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_EN Setting */
#define MXC_F_SMON_INTSCN_VCOREHIEN_POS 19 /**< INTSCN_VCOREHIEN Position */
#define MXC_F_SMON_INTSCN_VCOREHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCOREHIEN_POS)) /**< INTSCN_VCOREHIEN Mask */
#define MXC_V_SMON_INTSCN_VCOREHIEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VCOREHIEN_DIS Value */
#define MXC_S_SMON_INTSCN_VCOREHIEN_DIS (MXC_V_SMON_INTSCN_VCOREHIEN_DIS << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VCOREHIEN_EN ((uint32_t)0x1UL) /**< INTSCN_VCOREHIEN_EN Value */
#define MXC_S_SMON_INTSCN_VCOREHIEN_EN (MXC_V_SMON_INTSCN_VCOREHIEN_EN << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_EN Setting */
#define MXC_F_SMON_INTSCN_VDDLOEN_POS 20 /**< INTSCN_VDDLOEN Position */
#define MXC_F_SMON_INTSCN_VDDLOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDLOEN_POS)) /**< INTSCN_VDDLOEN Mask */
#define MXC_V_SMON_INTSCN_VDDLOEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VDDLOEN_DIS Value */
#define MXC_S_SMON_INTSCN_VDDLOEN_DIS (MXC_V_SMON_INTSCN_VDDLOEN_DIS << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VDDLOEN_EN ((uint32_t)0x1UL) /**< INTSCN_VDDLOEN_EN Value */
#define MXC_S_SMON_INTSCN_VDDLOEN_EN (MXC_V_SMON_INTSCN_VDDLOEN_EN << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_EN Setting */
#define MXC_F_SMON_INTSCN_VDDHIEN_POS 21 /**< INTSCN_VDDHIEN Position */
#define MXC_F_SMON_INTSCN_VDDHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDHIEN_POS)) /**< INTSCN_VDDHIEN Mask */
#define MXC_V_SMON_INTSCN_VDDHIEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VDDHIEN_DIS Value */
#define MXC_S_SMON_INTSCN_VDDHIEN_DIS (MXC_V_SMON_INTSCN_VDDHIEN_DIS << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VDDHIEN_EN ((uint32_t)0x1UL) /**< INTSCN_VDDHIEN_EN Value */
#define MXC_S_SMON_INTSCN_VDDHIEN_EN (MXC_V_SMON_INTSCN_VDDHIEN_EN << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_EN Setting */
#define MXC_F_SMON_INTSCN_VGLEN_POS 22 /**< INTSCN_VGLEN Position */
#define MXC_F_SMON_INTSCN_VGLEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VGLEN_POS)) /**< INTSCN_VGLEN Mask */
#define MXC_V_SMON_INTSCN_VGLEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VGLEN_DIS Value */
#define MXC_S_SMON_INTSCN_VGLEN_DIS (MXC_V_SMON_INTSCN_VGLEN_DIS << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VGLEN_EN ((uint32_t)0x1UL) /**< INTSCN_VGLEN_EN Value */
#define MXC_S_SMON_INTSCN_VGLEN_EN (MXC_V_SMON_INTSCN_VGLEN_EN << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_EN Setting */
#define MXC_F_SMON_INTSCN_LOCK_POS 31 /**< INTSCN_LOCK Position */
#define MXC_F_SMON_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */
#define MXC_V_SMON_INTSCN_LOCK_UNLOCKED ((uint32_t)0x0UL) /**< INTSCN_LOCK_UNLOCKED Value */
#define MXC_S_SMON_INTSCN_LOCK_UNLOCKED (MXC_V_SMON_INTSCN_LOCK_UNLOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_UNLOCKED Setting */
#define MXC_V_SMON_INTSCN_LOCK_LOCKED ((uint32_t)0x1UL) /**< INTSCN_LOCK_LOCKED Value */
#define MXC_S_SMON_INTSCN_LOCK_LOCKED (MXC_V_SMON_INTSCN_LOCK_LOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_LOCKED Setting */
/**@} end of group SMON_INTSCN_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_SECALM SMON_SECALM
* @brief Security Alarm Register.
* @{
*/
#define MXC_F_SMON_SECALM_DRS_POS 0 /**< SECALM_DRS Position */
#define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */
#define MXC_V_SMON_SECALM_DRS_COMPLETE ((uint32_t)0x0UL) /**< SECALM_DRS_COMPLETE Value */
#define MXC_S_SMON_SECALM_DRS_COMPLETE (MXC_V_SMON_SECALM_DRS_COMPLETE << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_COMPLETE Setting */
#define MXC_V_SMON_SECALM_DRS_START ((uint32_t)0x1UL) /**< SECALM_DRS_START Value */
#define MXC_S_SMON_SECALM_DRS_START (MXC_V_SMON_SECALM_DRS_START << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_START Setting */
#define MXC_F_SMON_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */
#define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */
#define MXC_V_SMON_SECALM_KEYWIPE_COMPLETE ((uint32_t)0x0UL) /**< SECALM_KEYWIPE_COMPLETE Value */
#define MXC_S_SMON_SECALM_KEYWIPE_COMPLETE (MXC_V_SMON_SECALM_KEYWIPE_COMPLETE << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_COMPLETE Setting */
#define MXC_V_SMON_SECALM_KEYWIPE_START ((uint32_t)0x1UL) /**< SECALM_KEYWIPE_START Value */
#define MXC_S_SMON_SECALM_KEYWIPE_START (MXC_V_SMON_SECALM_KEYWIPE_START << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_START Setting */
#define MXC_F_SMON_SECALM_SHIELDF_POS 2 /**< SECALM_SHIELDF Position */
#define MXC_F_SMON_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */
#define MXC_V_SMON_SECALM_SHIELDF_NOEVENT ((uint32_t)0x0UL) /**< SECALM_SHIELDF_NOEVENT Value */
#define MXC_S_SMON_SECALM_SHIELDF_NOEVENT (MXC_V_SMON_SECALM_SHIELDF_NOEVENT << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_NOEVENT Setting */
#define MXC_V_SMON_SECALM_SHIELDF_OCCURRED ((uint32_t)0x1UL) /**< SECALM_SHIELDF_OCCURRED Value */
#define MXC_S_SMON_SECALM_SHIELDF_OCCURRED (MXC_V_SMON_SECALM_SHIELDF_OCCURRED << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_OCCURRED Setting */
#define MXC_F_SMON_SECALM_LOTEMP_POS 3 /**< SECALM_LOTEMP Position */
#define MXC_F_SMON_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */
#define MXC_V_SMON_SECALM_LOTEMP_NOEVENT ((uint32_t)0x0UL) /**< SECALM_LOTEMP_NOEVENT Value */
#define MXC_S_SMON_SECALM_LOTEMP_NOEVENT (MXC_V_SMON_SECALM_LOTEMP_NOEVENT << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_NOEVENT Setting */
#define MXC_V_SMON_SECALM_LOTEMP_OCCURRED ((uint32_t)0x1UL) /**< SECALM_LOTEMP_OCCURRED Value */
#define MXC_S_SMON_SECALM_LOTEMP_OCCURRED (MXC_V_SMON_SECALM_LOTEMP_OCCURRED << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_OCCURRED Setting */
#define MXC_F_SMON_SECALM_HITEMP_POS 4 /**< SECALM_HITEMP Position */
#define MXC_F_SMON_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */
#define MXC_V_SMON_SECALM_HITEMP_NOEVENT ((uint32_t)0x0UL) /**< SECALM_HITEMP_NOEVENT Value */
#define MXC_S_SMON_SECALM_HITEMP_NOEVENT (MXC_V_SMON_SECALM_HITEMP_NOEVENT << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_NOEVENT Setting */
#define MXC_V_SMON_SECALM_HITEMP_OCCURRED ((uint32_t)0x1UL) /**< SECALM_HITEMP_OCCURRED Value */
#define MXC_S_SMON_SECALM_HITEMP_OCCURRED (MXC_V_SMON_SECALM_HITEMP_OCCURRED << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_OCCURRED Setting */
#define MXC_F_SMON_SECALM_BATLO_POS 5 /**< SECALM_BATLO Position */
#define MXC_F_SMON_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */
#define MXC_V_SMON_SECALM_BATLO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_BATLO_NOEVENT Value */
#define MXC_S_SMON_SECALM_BATLO_NOEVENT (MXC_V_SMON_SECALM_BATLO_NOEVENT << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_NOEVENT Setting */
#define MXC_V_SMON_SECALM_BATLO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_BATLO_OCCURRED Value */
#define MXC_S_SMON_SECALM_BATLO_OCCURRED (MXC_V_SMON_SECALM_BATLO_OCCURRED << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_OCCURRED Setting */
#define MXC_F_SMON_SECALM_BATHI_POS 6 /**< SECALM_BATHI Position */
#define MXC_F_SMON_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */
#define MXC_V_SMON_SECALM_BATHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_BATHI_NOEVENT Value */
#define MXC_S_SMON_SECALM_BATHI_NOEVENT (MXC_V_SMON_SECALM_BATHI_NOEVENT << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_NOEVENT Setting */
#define MXC_V_SMON_SECALM_BATHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_BATHI_OCCURRED Value */
#define MXC_S_SMON_SECALM_BATHI_OCCURRED (MXC_V_SMON_SECALM_BATHI_OCCURRED << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTF_POS 7 /**< SECALM_EXTF Position */
#define MXC_F_SMON_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */
#define MXC_V_SMON_SECALM_EXTF_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTF_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTF_NOEVENT (MXC_V_SMON_SECALM_EXTF_NOEVENT << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTF_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTF_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTF_OCCURRED (MXC_V_SMON_SECALM_EXTF_OCCURRED << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VDDLO_POS 8 /**< SECALM_VDDLO Position */
#define MXC_F_SMON_SECALM_VDDLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDLO_POS)) /**< SECALM_VDDLO Mask */
#define MXC_V_SMON_SECALM_VDDLO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VDDLO_NOEVENT Value */
#define MXC_S_SMON_SECALM_VDDLO_NOEVENT (MXC_V_SMON_SECALM_VDDLO_NOEVENT << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VDDLO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VDDLO_OCCURRED Value */
#define MXC_S_SMON_SECALM_VDDLO_OCCURRED (MXC_V_SMON_SECALM_VDDLO_OCCURRED << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VCORELO_POS 9 /**< SECALM_VCORELO Position */
#define MXC_F_SMON_SECALM_VCORELO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCORELO_POS)) /**< SECALM_VCORELO Mask */
#define MXC_V_SMON_SECALM_VCORELO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VCORELO_NOEVENT Value */
#define MXC_S_SMON_SECALM_VCORELO_NOEVENT (MXC_V_SMON_SECALM_VCORELO_NOEVENT << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VCORELO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VCORELO_OCCURRED Value */
#define MXC_S_SMON_SECALM_VCORELO_OCCURRED (MXC_V_SMON_SECALM_VCORELO_OCCURRED << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VCOREHI_POS 10 /**< SECALM_VCOREHI Position */
#define MXC_F_SMON_SECALM_VCOREHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_POS)) /**< SECALM_VCOREHI Mask */
#define MXC_V_SMON_SECALM_VCOREHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VCOREHI_NOEVENT Value */
#define MXC_S_SMON_SECALM_VCOREHI_NOEVENT (MXC_V_SMON_SECALM_VCOREHI_NOEVENT << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VCOREHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VCOREHI_OCCURRED Value */
#define MXC_S_SMON_SECALM_VCOREHI_OCCURRED (MXC_V_SMON_SECALM_VCOREHI_OCCURRED << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VDDHI_POS 11 /**< SECALM_VDDHI Position */
#define MXC_F_SMON_SECALM_VDDHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_POS)) /**< SECALM_VDDHI Mask */
#define MXC_V_SMON_SECALM_VDDHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VDDHI_NOEVENT Value */
#define MXC_S_SMON_SECALM_VDDHI_NOEVENT (MXC_V_SMON_SECALM_VDDHI_NOEVENT << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VDDHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VDDHI_OCCURRED Value */
#define MXC_S_SMON_SECALM_VDDHI_OCCURRED (MXC_V_SMON_SECALM_VDDHI_OCCURRED << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VGL_POS 12 /**< SECALM_VGL Position */
#define MXC_F_SMON_SECALM_VGL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_POS)) /**< SECALM_VGL Mask */
#define MXC_V_SMON_SECALM_VGL_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VGL_NOEVENT Value */
#define MXC_S_SMON_SECALM_VGL_NOEVENT (MXC_V_SMON_SECALM_VGL_NOEVENT << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VGL_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VGL_OCCURRED Value */
#define MXC_S_SMON_SECALM_VGL_OCCURRED (MXC_V_SMON_SECALM_VGL_OCCURRED << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT0_POS 16 /**< SECALM_EXTSTAT0 Position */
#define MXC_F_SMON_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT0_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT0_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT0_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT0_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT1_POS 17 /**< SECALM_EXTSTAT1 Position */
#define MXC_F_SMON_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT1_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT1_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT1_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT1_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT2_POS 18 /**< SECALM_EXTSTAT2 Position */
#define MXC_F_SMON_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT2_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT2_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT2_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT2_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT3_POS 19 /**< SECALM_EXTSTAT3 Position */
#define MXC_F_SMON_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT3_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT3_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT3_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT3_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT4_POS 20 /**< SECALM_EXTSTAT4 Position */
#define MXC_F_SMON_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT4_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT4_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT4_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT4_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT5_POS 21 /**< SECALM_EXTSTAT5 Position */
#define MXC_F_SMON_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT5_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT5_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT5_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT5_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN0_POS 24 /**< SECALM_EXTSWARN0 Position */
#define MXC_F_SMON_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN0_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN0_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN0_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN0_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN1_POS 25 /**< SECALM_EXTSWARN1 Position */
#define MXC_F_SMON_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN1_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN1_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN1_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN1_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN2_POS 26 /**< SECALM_EXTSWARN2 Position */
#define MXC_F_SMON_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN2_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN2_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN2_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN2_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN3_POS 27 /**< SECALM_EXTSWARN3 Position */
#define MXC_F_SMON_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN3_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN3_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN3_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN3_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN4_POS 28 /**< SECALM_EXTSWARN4 Position */
#define MXC_F_SMON_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN4_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN4_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN4_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN4_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN5_POS 29 /**< SECALM_EXTSWARN5 Position */
#define MXC_F_SMON_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN5_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN5_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN5_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN5_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_OCCURRED Setting */
/**@} end of group SMON_SECALM_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_SECDIAG SMON_SECDIAG
* @brief Security Diagnostic Register.
* @{
*/
#define MXC_F_SMON_SECDIAG_BORF_POS 0 /**< SECDIAG_BORF Position */
#define MXC_F_SMON_SECDIAG_BORF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BORF_POS)) /**< SECDIAG_BORF Mask */
#define MXC_V_SMON_SECDIAG_BORF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BORF_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_BORF_NOEVENT (MXC_V_SMON_SECDIAG_BORF_NOEVENT << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_BORF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BORF_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_BORF_OCCURRED (MXC_V_SMON_SECDIAG_BORF_OCCURRED << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_SHIELDF_POS 2 /**< SECDIAG_SHIELDF Position */
#define MXC_F_SMON_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */
#define MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_SHIELDF_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_SHIELDF_NOEVENT (MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_SHIELDF_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_SHIELDF_OCCURRED (MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_LOTEMP_POS 3 /**< SECDIAG_LOTEMP Position */
#define MXC_F_SMON_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */
#define MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_LOTEMP_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_LOTEMP_NOEVENT (MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_LOTEMP_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_LOTEMP_OCCURRED (MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_HITEMP_POS 4 /**< SECDIAG_HITEMP Position */
#define MXC_F_SMON_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */
#define MXC_V_SMON_SECDIAG_HITEMP_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_HITEMP_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_HITEMP_NOEVENT (MXC_V_SMON_SECDIAG_HITEMP_NOEVENT << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_HITEMP_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_HITEMP_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_HITEMP_OCCURRED (MXC_V_SMON_SECDIAG_HITEMP_OCCURRED << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_BATLO_POS 5 /**< SECDIAG_BATLO Position */
#define MXC_F_SMON_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */
#define MXC_V_SMON_SECDIAG_BATLO_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BATLO_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_BATLO_NOEVENT (MXC_V_SMON_SECDIAG_BATLO_NOEVENT << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_BATLO_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BATLO_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_BATLO_OCCURRED (MXC_V_SMON_SECDIAG_BATLO_OCCURRED << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_BATHI_POS 6 /**< SECDIAG_BATHI Position */
#define MXC_F_SMON_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */
#define MXC_V_SMON_SECDIAG_BATHI_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BATHI_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_BATHI_NOEVENT (MXC_V_SMON_SECDIAG_BATHI_NOEVENT << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_BATHI_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BATHI_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_BATHI_OCCURRED (MXC_V_SMON_SECDIAG_BATHI_OCCURRED << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_DYNF_POS 7 /**< SECDIAG_DYNF Position */
#define MXC_F_SMON_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */
#define MXC_V_SMON_SECDIAG_DYNF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_DYNF_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_DYNF_NOEVENT (MXC_V_SMON_SECDIAG_DYNF_NOEVENT << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_DYNF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_DYNF_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_DYNF_OCCURRED (MXC_V_SMON_SECDIAG_DYNF_OCCURRED << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_AESKT_POS 8 /**< SECDIAG_AESKT Position */
#define MXC_F_SMON_SECDIAG_AESKT ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_POS)) /**< SECDIAG_AESKT Mask */
#define MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE ((uint32_t)0x0UL) /**< SECDIAG_AESKT_INCOMPLETE Value */
#define MXC_S_SMON_SECDIAG_AESKT_INCOMPLETE (MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_INCOMPLETE Setting */
#define MXC_V_SMON_SECDIAG_AESKT_COMPLETE ((uint32_t)0x1UL) /**< SECDIAG_AESKT_COMPLETE Value */
#define MXC_S_SMON_SECDIAG_AESKT_COMPLETE (MXC_V_SMON_SECDIAG_AESKT_COMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_COMPLETE Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT0_POS 16 /**< SECDIAG_EXTSTAT0 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT0_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT0_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT0_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT0_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT1_POS 17 /**< SECDIAG_EXTSTAT1 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT1_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT1_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT1_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT1_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT2_POS 18 /**< SECDIAG_EXTSTAT2 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT2_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT2_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT2_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT2_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT3_POS 19 /**< SECDIAG_EXTSTAT3 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT3_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT3_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT3_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT3_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT4_POS 20 /**< SECDIAG_EXTSTAT4 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT4_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT4_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT4_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT4_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT5_POS 21 /**< SECDIAG_EXTSTAT5 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT5_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT5_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT5_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT5_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_OCCURRED Setting */
/**@} end of group SMON_SECDIAG_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_DLRTC SMON_DLRTC
* @brief DRS Log RTC Value. This register contains the 32 bit value in the RTC second
* register when the last DRS event occurred.
* @{
*/
#define MXC_F_SMON_DLRTC_DLRTC_POS 0 /**< DLRTC_DLRTC Position */
#define MXC_F_SMON_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */
/**@} end of group SMON_DLRTC_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_SECST SMON_SECST
* @brief Security Monitor Status Register.
* @{
*/
#define MXC_F_SMON_SECST_EXTSRS_POS 0 /**< SECST_EXTSRS Position */
#define MXC_F_SMON_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */
#define MXC_V_SMON_SECST_EXTSRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_EXTSRS_ALLOWED Value */
#define MXC_S_SMON_SECST_EXTSRS_ALLOWED (MXC_V_SMON_SECST_EXTSRS_ALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_ALLOWED Setting */
#define MXC_V_SMON_SECST_EXTSRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_EXTSRS_NOTALLOWED Value */
#define MXC_S_SMON_SECST_EXTSRS_NOTALLOWED (MXC_V_SMON_SECST_EXTSRS_NOTALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_NOTALLOWED Setting */
#define MXC_F_SMON_SECST_INTSRS_POS 1 /**< SECST_INTSRS Position */
#define MXC_F_SMON_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */
#define MXC_V_SMON_SECST_INTSRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_INTSRS_ALLOWED Value */
#define MXC_S_SMON_SECST_INTSRS_ALLOWED (MXC_V_SMON_SECST_INTSRS_ALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_ALLOWED Setting */
#define MXC_V_SMON_SECST_INTSRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_INTSRS_NOTALLOWED Value */
#define MXC_S_SMON_SECST_INTSRS_NOTALLOWED (MXC_V_SMON_SECST_INTSRS_NOTALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_NOTALLOWED Setting */
#define MXC_F_SMON_SECST_SECALRS_POS 2 /**< SECST_SECALRS Position */
#define MXC_F_SMON_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */
#define MXC_V_SMON_SECST_SECALRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_SECALRS_ALLOWED Value */
#define MXC_S_SMON_SECST_SECALRS_ALLOWED (MXC_V_SMON_SECST_SECALRS_ALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_ALLOWED Setting */
#define MXC_V_SMON_SECST_SECALRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_SECALRS_NOTALLOWED Value */
#define MXC_S_SMON_SECST_SECALRS_NOTALLOWED (MXC_V_SMON_SECST_SECALRS_NOTALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_NOTALLOWED Setting */
/**@} end of group SMON_SECST_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SMON_REGS_H_ */

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/**
* @file spi17y_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SPI17Y_REGS_H_
#define _SPI17Y_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup spi17y
* @defgroup spi17y_registers SPI17Y_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module.
* @details SPI peripheral.
*/
/**
* @ingroup spi17y_registers
* Structure type to access the SPI17Y Registers.
*/
typedef struct {
union{
__IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPI17Y DATA32 Register */
__IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPI17Y DATA16 Register */
__IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPI17Y DATA8 Register */
};
__IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI17Y CTRL0 Register */
__IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI17Y CTRL1 Register */
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI17Y CTRL2 Register */
__IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI17Y SS_TIME Register */
__IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI17Y CLK_CFG Register */
__R uint32_t rsv_0x18;
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI17Y DMA Register */
__IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI17Y INT_FL Register */
__IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI17Y INT_EN Register */
__IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPI17Y WAKE_FL Register */
__IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPI17Y WAKE_EN Register */
__I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI17Y STAT Register */
} mxc_spi17y_regs_t;
/* Register offsets for module SPI17Y */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_Register_Offsets Register Offsets
* @brief SPI17Y Peripheral Register Offsets from the SPI17Y Base Peripheral Address.
* @{
*/
#define MXC_R_SPI17Y_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI17Y_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI17Y_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI17Y_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI17Y Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPI17Y_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI17Y Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPI17Y_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI17Y Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPI17Y_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI17Y Base Address: <tt> 0x0010</tt> */
#define MXC_R_SPI17Y_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI17Y Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPI17Y_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI17Y Base Address: <tt> 0x001C</tt> */
#define MXC_R_SPI17Y_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI17Y Base Address: <tt> 0x0020</tt> */
#define MXC_R_SPI17Y_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI17Y Base Address: <tt> 0x0024</tt> */
#define MXC_R_SPI17Y_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI17Y Base Address: <tt> 0x0028</tt> */
#define MXC_R_SPI17Y_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI17Y Base Address: <tt> 0x002C</tt> */
#define MXC_R_SPI17Y_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI17Y Base Address: <tt> 0x0030</tt> */
/**@} end of group spi17y_registers */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_DATA32 SPI17Y_DATA32
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI17Y_DATA32_DATA_POS 0 /**< DATA32_DATA Position */
#define MXC_F_SPI17Y_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI17Y_DATA32_DATA_POS)) /**< DATA32_DATA Mask */
/**@} end of group SPI17Y_DATA32_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_DATA16 SPI17Y_DATA16
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI17Y_DATA16_DATA_POS 0 /**< DATA16_DATA Position */
#define MXC_F_SPI17Y_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI17Y_DATA16_DATA_POS)) /**< DATA16_DATA Mask */
/**@} end of group SPI17Y_DATA16_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_DATA8 SPI17Y_DATA8
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI17Y_DATA8_DATA_POS 0 /**< DATA8_DATA Position */
#define MXC_F_SPI17Y_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI17Y_DATA8_DATA_POS)) /**< DATA8_DATA Mask */
/**@} end of group SPI17Y_DATA8_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_CTRL0 SPI17Y_CTRL0
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI17Y_CTRL0_EN_POS 0 /**< CTRL0_EN Position */
#define MXC_F_SPI17Y_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_EN_POS)) /**< CTRL0_EN Mask */
#define MXC_V_SPI17Y_CTRL0_EN_DIS ((uint32_t)0x0UL) /**< CTRL0_EN_DIS Value */
#define MXC_S_SPI17Y_CTRL0_EN_DIS (MXC_V_SPI17Y_CTRL0_EN_DIS << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_DIS Setting */
#define MXC_V_SPI17Y_CTRL0_EN_EN ((uint32_t)0x1UL) /**< CTRL0_EN_EN Value */
#define MXC_S_SPI17Y_CTRL0_EN_EN (MXC_V_SPI17Y_CTRL0_EN_EN << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_EN Setting */
#define MXC_F_SPI17Y_CTRL0_MASTER_POS 1 /**< CTRL0_MASTER Position */
#define MXC_F_SPI17Y_CTRL0_MASTER ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_MASTER_POS)) /**< CTRL0_MASTER Mask */
#define MXC_V_SPI17Y_CTRL0_MASTER_DIS ((uint32_t)0x0UL) /**< CTRL0_MASTER_DIS Value */
#define MXC_S_SPI17Y_CTRL0_MASTER_DIS (MXC_V_SPI17Y_CTRL0_MASTER_DIS << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_DIS Setting */
#define MXC_V_SPI17Y_CTRL0_MASTER_EN ((uint32_t)0x1UL) /**< CTRL0_MASTER_EN Value */
#define MXC_S_SPI17Y_CTRL0_MASTER_EN (MXC_V_SPI17Y_CTRL0_MASTER_EN << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_EN Setting */
#define MXC_F_SPI17Y_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */
#define MXC_F_SPI17Y_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
#define MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT ((uint32_t)0x0UL) /**< CTRL0_SS_IO_OUTPUT Value */
#define MXC_S_SPI17Y_CTRL0_SS_IO_OUTPUT (MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_OUTPUT Setting */
#define MXC_V_SPI17Y_CTRL0_SS_IO_INPUT ((uint32_t)0x1UL) /**< CTRL0_SS_IO_INPUT Value */
#define MXC_S_SPI17Y_CTRL0_SS_IO_INPUT (MXC_V_SPI17Y_CTRL0_SS_IO_INPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_INPUT Setting */
#define MXC_F_SPI17Y_CTRL0_START_POS 5 /**< CTRL0_START Position */
#define MXC_F_SPI17Y_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_START_POS)) /**< CTRL0_START Mask */
#define MXC_V_SPI17Y_CTRL0_START_START ((uint32_t)0x1UL) /**< CTRL0_START_START Value */
#define MXC_S_SPI17Y_CTRL0_START_START (MXC_V_SPI17Y_CTRL0_START_START << MXC_F_SPI17Y_CTRL0_START_POS) /**< CTRL0_START_START Setting */
#define MXC_F_SPI17Y_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */
#define MXC_F_SPI17Y_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
#define MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT ((uint32_t)0x0UL) /**< CTRL0_SS_CTRL_DEASSERT Value */
#define MXC_S_SPI17Y_CTRL0_SS_CTRL_DEASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_DEASSERT Setting */
#define MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT ((uint32_t)0x1UL) /**< CTRL0_SS_CTRL_ASSERT Value */
#define MXC_S_SPI17Y_CTRL0_SS_CTRL_ASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_ASSERT Setting */
#define MXC_F_SPI17Y_CTRL0_SS_POS 16 /**< CTRL0_SS Position */
#define MXC_F_SPI17Y_CTRL0_SS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL0_SS_POS)) /**< CTRL0_SS Mask */
#define MXC_V_SPI17Y_CTRL0_SS_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SS0 Value */
#define MXC_S_SPI17Y_CTRL0_SS_SS0 (MXC_V_SPI17Y_CTRL0_SS_SS0 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS0 Setting */
#define MXC_V_SPI17Y_CTRL0_SS_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SS1 Value */
#define MXC_S_SPI17Y_CTRL0_SS_SS1 (MXC_V_SPI17Y_CTRL0_SS_SS1 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS1 Setting */
#define MXC_V_SPI17Y_CTRL0_SS_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SS2 Value */
#define MXC_S_SPI17Y_CTRL0_SS_SS2 (MXC_V_SPI17Y_CTRL0_SS_SS2 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS2 Setting */
#define MXC_V_SPI17Y_CTRL0_SS_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SS3 Value */
#define MXC_S_SPI17Y_CTRL0_SS_SS3 (MXC_V_SPI17Y_CTRL0_SS_SS3 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS3 Setting */
/**@} end of group SPI17Y_CTRL0_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_CTRL1 SPI17Y_CTRL1
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */
#define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
#define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */
#define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
/**@} end of group SPI17Y_CTRL1_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_CTRL2 SPI17Y_CTRL2
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI17Y_CTRL2_CPHA_POS 0 /**< CTRL2_CPHA Position */
#define MXC_F_SPI17Y_CTRL2_CPHA ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */
#define MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE ((uint32_t)0x0UL) /**< CTRL2_CPHA_RISING_EDGE Value */
#define MXC_S_SPI17Y_CTRL2_CPHA_RISING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_RISING_EDGE Setting */
#define MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE ((uint32_t)0x1UL) /**< CTRL2_CPHA_FALLING_EDGE Value */
#define MXC_S_SPI17Y_CTRL2_CPHA_FALLING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_FALLING_EDGE Setting */
#define MXC_F_SPI17Y_CTRL2_CPOL_POS 1 /**< CTRL2_CPOL Position */
#define MXC_F_SPI17Y_CTRL2_CPOL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */
#define MXC_V_SPI17Y_CTRL2_CPOL_NORMAL ((uint32_t)0x0UL) /**< CTRL2_CPOL_NORMAL Value */
#define MXC_S_SPI17Y_CTRL2_CPOL_NORMAL (MXC_V_SPI17Y_CTRL2_CPOL_NORMAL << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_NORMAL Setting */
#define MXC_V_SPI17Y_CTRL2_CPOL_INVERTED ((uint32_t)0x1UL) /**< CTRL2_CPOL_INVERTED Value */
#define MXC_S_SPI17Y_CTRL2_CPOL_INVERTED (MXC_V_SPI17Y_CTRL2_CPOL_INVERTED << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_INVERTED Setting */
#define MXC_F_SPI17Y_CTRL2_SCLK_INV_POS 4 /**< CTRL2_SCLK_INV Position */
#define MXC_F_SPI17Y_CTRL2_SCLK_INV ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_SCLK_INV_POS)) /**< CTRL2_SCLK_INV Mask */
#define MXC_F_SPI17Y_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */
#define MXC_F_SPI17Y_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */
#define MXC_V_SPI17Y_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */
#define MXC_S_SPI17Y_CTRL2_NUMBITS_0 (MXC_V_SPI17Y_CTRL2_NUMBITS_0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */
#define MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */
#define MXC_F_SPI17Y_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
#define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
#define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
#define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
#define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
#define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
#define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
#define MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */
#define MXC_F_SPI17Y_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
#define MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS ((uint32_t)0x0UL) /**< CTRL2_THREE_WIRE_DIS Value */
#define MXC_S_SPI17Y_CTRL2_THREE_WIRE_DIS (MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_DIS Setting */
#define MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN ((uint32_t)0x1UL) /**< CTRL2_THREE_WIRE_EN Value */
#define MXC_S_SPI17Y_CTRL2_THREE_WIRE_EN (MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_EN Setting */
#define MXC_F_SPI17Y_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */
#define MXC_F_SPI17Y_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
#define MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */
#define MXC_F_SPI17Y_CTRL2_SRPOL_POS 24 /**< CTRL2_SRPOL Position */
#define MXC_F_SPI17Y_CTRL2_SRPOL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SRPOL_POS)) /**< CTRL2_SRPOL Mask */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SRPOL_SR0_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR0_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR0_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SRPOL_SR1_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR1_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR1_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SRPOL_SR2_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR2_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR2_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SRPOL_SR3_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR3_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR3_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH ((uint32_t)0x10UL) /**< CTRL2_SRPOL_SR4_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR4_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR4_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH ((uint32_t)0x20UL) /**< CTRL2_SRPOL_SR5_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR5_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR5_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH ((uint32_t)0x40UL) /**< CTRL2_SRPOL_SR6_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR6_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR6_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH ((uint32_t)0x80UL) /**< CTRL2_SRPOL_SR7_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR7_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR7_HIGH Setting */
/**@} end of group SPI17Y_CTRL2_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_SS_TIME SPI17Y_SS_TIME
* @brief Register for controlling SPI peripheral/Slave Select Timing.
* @{
*/
#define MXC_F_SPI17Y_SS_TIME_PRE_POS 0 /**< SS_TIME_PRE Position */
#define MXC_F_SPI17Y_SS_TIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_PRE_POS)) /**< SS_TIME_PRE Mask */
#define MXC_V_SPI17Y_SS_TIME_PRE_256 ((uint32_t)0x0UL) /**< SS_TIME_PRE_256 Value */
#define MXC_S_SPI17Y_SS_TIME_PRE_256 (MXC_V_SPI17Y_SS_TIME_PRE_256 << MXC_F_SPI17Y_SS_TIME_PRE_POS) /**< SS_TIME_PRE_256 Setting */
#define MXC_F_SPI17Y_SS_TIME_POST_POS 8 /**< SS_TIME_POST Position */
#define MXC_F_SPI17Y_SS_TIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_POST_POS)) /**< SS_TIME_POST Mask */
#define MXC_V_SPI17Y_SS_TIME_POST_256 ((uint32_t)0x0UL) /**< SS_TIME_POST_256 Value */
#define MXC_S_SPI17Y_SS_TIME_POST_256 (MXC_V_SPI17Y_SS_TIME_POST_256 << MXC_F_SPI17Y_SS_TIME_POST_POS) /**< SS_TIME_POST_256 Setting */
#define MXC_F_SPI17Y_SS_TIME_INACT_POS 16 /**< SS_TIME_INACT Position */
#define MXC_F_SPI17Y_SS_TIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_INACT_POS)) /**< SS_TIME_INACT Mask */
#define MXC_V_SPI17Y_SS_TIME_INACT_256 ((uint32_t)0x0UL) /**< SS_TIME_INACT_256 Value */
#define MXC_S_SPI17Y_SS_TIME_INACT_256 (MXC_V_SPI17Y_SS_TIME_INACT_256 << MXC_F_SPI17Y_SS_TIME_INACT_POS) /**< SS_TIME_INACT_256 Setting */
/**@} end of group SPI17Y_SS_TIME_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_CLK_CFG SPI17Y_CLK_CFG
* @brief Register for controlling SPI clock rate.
* @{
*/
#define MXC_F_SPI17Y_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */
#define MXC_F_SPI17Y_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */
#define MXC_V_SPI17Y_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */
#define MXC_S_SPI17Y_CLK_CFG_LO_DIS (MXC_V_SPI17Y_CLK_CFG_LO_DIS << MXC_F_SPI17Y_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */
#define MXC_F_SPI17Y_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */
#define MXC_F_SPI17Y_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */
#define MXC_V_SPI17Y_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */
#define MXC_S_SPI17Y_CLK_CFG_HI_DIS (MXC_V_SPI17Y_CLK_CFG_HI_DIS << MXC_F_SPI17Y_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */
#define MXC_F_SPI17Y_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */
#define MXC_F_SPI17Y_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI17Y_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */
/**@} end of group SPI17Y_CLK_CFG_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_DMA SPI17Y_DMA
* @brief Register for controlling DMA.
* @{
*/
#define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */
#define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
#define MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */
#define MXC_F_SPI17Y_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
#define MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_FIFO_EN_DIS Value */
#define MXC_S_SPI17Y_DMA_TX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_DIS Setting */
#define MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_FIFO_EN_EN Value */
#define MXC_S_SPI17Y_DMA_TX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_EN Setting */
#define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */
#define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
#define MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_CLEAR Value */
#define MXC_S_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_CLEAR Setting */
#define MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
#define MXC_F_SPI17Y_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
#define MXC_F_SPI17Y_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
#define MXC_F_SPI17Y_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
#define MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */
#define MXC_S_SPI17Y_DMA_TX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */
#define MXC_V_SPI17Y_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */
#define MXC_S_SPI17Y_DMA_TX_DMA_EN_EN (MXC_V_SPI17Y_DMA_TX_DMA_EN_EN << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */
#define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */
#define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
#define MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */
#define MXC_F_SPI17Y_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
#define MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_FIFO_EN_DIS Value */
#define MXC_S_SPI17Y_DMA_RX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_DIS Setting */
#define MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_FIFO_EN_EN Value */
#define MXC_S_SPI17Y_DMA_RX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_EN Setting */
#define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */
#define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
#define MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_CLEAR Value */
#define MXC_S_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_CLEAR Setting */
#define MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
#define MXC_F_SPI17Y_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
#define MXC_F_SPI17Y_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
#define MXC_F_SPI17Y_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
#define MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */
#define MXC_S_SPI17Y_DMA_RX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */
#define MXC_V_SPI17Y_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */
#define MXC_S_SPI17Y_DMA_RX_DMA_EN_EN (MXC_V_SPI17Y_DMA_RX_DMA_EN_EN << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */
/**@} end of group SPI17Y_DMA_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_INT_FL SPI17Y_INT_FL
* @brief Register for reading and clearing interrupt flags. All bits are write 1 to
* clear.
* @{
*/
#define MXC_F_SPI17Y_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */
#define MXC_F_SPI17Y_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */
#define MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_THRESH_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS) /**< INT_FL_TX_THRESH_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */
#define MXC_F_SPI17Y_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */
#define MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_EMPTY_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS) /**< INT_FL_TX_EMPTY_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */
#define MXC_F_SPI17Y_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */
#define MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_THRESH_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS) /**< INT_FL_RX_THRESH_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */
#define MXC_F_SPI17Y_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */
#define MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_FULL_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_INT_FL_RX_FULL_POS) /**< INT_FL_RX_FULL_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */
#define MXC_F_SPI17Y_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */
#define MXC_V_SPI17Y_INT_FL_SSA_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSA_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_SSA_CLEAR (MXC_V_SPI17Y_INT_FL_SSA_CLEAR << MXC_F_SPI17Y_INT_FL_SSA_POS) /**< INT_FL_SSA_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */
#define MXC_F_SPI17Y_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */
#define MXC_V_SPI17Y_INT_FL_SSD_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSD_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_SSD_CLEAR (MXC_V_SPI17Y_INT_FL_SSD_CLEAR << MXC_F_SPI17Y_INT_FL_SSD_POS) /**< INT_FL_SSD_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */
#define MXC_F_SPI17Y_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */
#define MXC_V_SPI17Y_INT_FL_FAULT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_FAULT_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_FAULT_CLEAR (MXC_V_SPI17Y_INT_FL_FAULT_CLEAR << MXC_F_SPI17Y_INT_FL_FAULT_POS) /**< INT_FL_FAULT_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */
#define MXC_F_SPI17Y_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */
#define MXC_V_SPI17Y_INT_FL_ABORT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_ABORT_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_ABORT_CLEAR (MXC_V_SPI17Y_INT_FL_ABORT_CLEAR << MXC_F_SPI17Y_INT_FL_ABORT_POS) /**< INT_FL_ABORT_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */
#define MXC_F_SPI17Y_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */
#define MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_M_DONE_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_M_DONE_CLEAR (MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR << MXC_F_SPI17Y_INT_FL_M_DONE_POS) /**< INT_FL_M_DONE_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */
#define MXC_F_SPI17Y_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */
#define MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_OVR_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_TX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_TX_OVR_POS) /**< INT_FL_TX_OVR_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */
#define MXC_F_SPI17Y_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */
#define MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_UND_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_TX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_TX_UND_POS) /**< INT_FL_TX_UND_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */
#define MXC_F_SPI17Y_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
#define MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_RX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */
#define MXC_F_SPI17Y_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */
#define MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_UND_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_RX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_RX_UND_POS) /**< INT_FL_RX_UND_CLEAR Setting */
/**@} end of group SPI17Y_INT_FL_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_INT_EN SPI17Y_INT_EN
* @brief Register for enabling interrupts.
* @{
*/
#define MXC_F_SPI17Y_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */
#define MXC_F_SPI17Y_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */
#define MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_THRESH_DIS Value */
#define MXC_S_SPI17Y_INT_EN_TX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_TX_THRESH_EN Value */
#define MXC_S_SPI17Y_INT_EN_TX_THRESH_EN (MXC_V_SPI17Y_INT_EN_TX_THRESH_EN << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_EN Setting */
#define MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */
#define MXC_F_SPI17Y_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */
#define MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_EMPTY_DIS Value */
#define MXC_S_SPI17Y_INT_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< INT_EN_TX_EMPTY_EN Value */
#define MXC_S_SPI17Y_INT_EN_TX_EMPTY_EN (MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_EN Setting */
#define MXC_F_SPI17Y_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */
#define MXC_F_SPI17Y_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */
#define MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_THRESH_DIS Value */
#define MXC_S_SPI17Y_INT_EN_RX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_RX_THRESH_EN Value */
#define MXC_S_SPI17Y_INT_EN_RX_THRESH_EN (MXC_V_SPI17Y_INT_EN_RX_THRESH_EN << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_EN Setting */
#define MXC_F_SPI17Y_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */
#define MXC_F_SPI17Y_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */
#define MXC_V_SPI17Y_INT_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FULL_DIS Value */
#define MXC_S_SPI17Y_INT_EN_RX_FULL_DIS (MXC_V_SPI17Y_INT_EN_RX_FULL_DIS << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FULL_EN Value */
#define MXC_S_SPI17Y_INT_EN_RX_FULL_EN (MXC_V_SPI17Y_INT_EN_RX_FULL_EN << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_EN Setting */
#define MXC_F_SPI17Y_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */
#define MXC_F_SPI17Y_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */
#define MXC_V_SPI17Y_INT_EN_SSA_DIS ((uint32_t)0x0UL) /**< INT_EN_SSA_DIS Value */
#define MXC_S_SPI17Y_INT_EN_SSA_DIS (MXC_V_SPI17Y_INT_EN_SSA_DIS << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_SSA_EN ((uint32_t)0x1UL) /**< INT_EN_SSA_EN Value */
#define MXC_S_SPI17Y_INT_EN_SSA_EN (MXC_V_SPI17Y_INT_EN_SSA_EN << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_EN Setting */
#define MXC_F_SPI17Y_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */
#define MXC_F_SPI17Y_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */
#define MXC_V_SPI17Y_INT_EN_SSD_DIS ((uint32_t)0x0UL) /**< INT_EN_SSD_DIS Value */
#define MXC_S_SPI17Y_INT_EN_SSD_DIS (MXC_V_SPI17Y_INT_EN_SSD_DIS << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_SSD_EN ((uint32_t)0x1UL) /**< INT_EN_SSD_EN Value */
#define MXC_S_SPI17Y_INT_EN_SSD_EN (MXC_V_SPI17Y_INT_EN_SSD_EN << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_EN Setting */
#define MXC_F_SPI17Y_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */
#define MXC_F_SPI17Y_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */
#define MXC_V_SPI17Y_INT_EN_FAULT_DIS ((uint32_t)0x0UL) /**< INT_EN_FAULT_DIS Value */
#define MXC_S_SPI17Y_INT_EN_FAULT_DIS (MXC_V_SPI17Y_INT_EN_FAULT_DIS << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_FAULT_EN ((uint32_t)0x1UL) /**< INT_EN_FAULT_EN Value */
#define MXC_S_SPI17Y_INT_EN_FAULT_EN (MXC_V_SPI17Y_INT_EN_FAULT_EN << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_EN Setting */
#define MXC_F_SPI17Y_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */
#define MXC_F_SPI17Y_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */
#define MXC_V_SPI17Y_INT_EN_ABORT_DIS ((uint32_t)0x0UL) /**< INT_EN_ABORT_DIS Value */
#define MXC_S_SPI17Y_INT_EN_ABORT_DIS (MXC_V_SPI17Y_INT_EN_ABORT_DIS << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_ABORT_EN ((uint32_t)0x1UL) /**< INT_EN_ABORT_EN Value */
#define MXC_S_SPI17Y_INT_EN_ABORT_EN (MXC_V_SPI17Y_INT_EN_ABORT_EN << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_EN Setting */
#define MXC_F_SPI17Y_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */
#define MXC_F_SPI17Y_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */
#define MXC_V_SPI17Y_INT_EN_M_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN_M_DONE_DIS Value */
#define MXC_S_SPI17Y_INT_EN_M_DONE_DIS (MXC_V_SPI17Y_INT_EN_M_DONE_DIS << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_M_DONE_EN ((uint32_t)0x1UL) /**< INT_EN_M_DONE_EN Value */
#define MXC_S_SPI17Y_INT_EN_M_DONE_EN (MXC_V_SPI17Y_INT_EN_M_DONE_EN << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_EN Setting */
#define MXC_F_SPI17Y_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */
#define MXC_F_SPI17Y_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */
#define MXC_V_SPI17Y_INT_EN_TX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_OVR_DIS Value */
#define MXC_S_SPI17Y_INT_EN_TX_OVR_DIS (MXC_V_SPI17Y_INT_EN_TX_OVR_DIS << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_TX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_TX_OVR_EN Value */
#define MXC_S_SPI17Y_INT_EN_TX_OVR_EN (MXC_V_SPI17Y_INT_EN_TX_OVR_EN << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_EN Setting */
#define MXC_F_SPI17Y_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */
#define MXC_F_SPI17Y_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */
#define MXC_V_SPI17Y_INT_EN_TX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_UND_DIS Value */
#define MXC_S_SPI17Y_INT_EN_TX_UND_DIS (MXC_V_SPI17Y_INT_EN_TX_UND_DIS << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_TX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_TX_UND_EN Value */
#define MXC_S_SPI17Y_INT_EN_TX_UND_EN (MXC_V_SPI17Y_INT_EN_TX_UND_EN << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_EN Setting */
#define MXC_F_SPI17Y_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */
#define MXC_F_SPI17Y_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */
#define MXC_V_SPI17Y_INT_EN_RX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_OVR_DIS Value */
#define MXC_S_SPI17Y_INT_EN_RX_OVR_DIS (MXC_V_SPI17Y_INT_EN_RX_OVR_DIS << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_RX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_OVR_EN Value */
#define MXC_S_SPI17Y_INT_EN_RX_OVR_EN (MXC_V_SPI17Y_INT_EN_RX_OVR_EN << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_EN Setting */
#define MXC_F_SPI17Y_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */
#define MXC_F_SPI17Y_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */
#define MXC_V_SPI17Y_INT_EN_RX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_UND_DIS Value */
#define MXC_S_SPI17Y_INT_EN_RX_UND_DIS (MXC_V_SPI17Y_INT_EN_RX_UND_DIS << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_RX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_RX_UND_EN Value */
#define MXC_S_SPI17Y_INT_EN_RX_UND_EN (MXC_V_SPI17Y_INT_EN_RX_UND_EN << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_EN Setting */
/**@} end of group SPI17Y_INT_EN_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_WAKE_FL SPI17Y_WAKE_FL
* @brief Register for wake up flags. All bits in this register are write 1 to clear.
* @{
*/
#define MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */
#define MXC_F_SPI17Y_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */
#define MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_THRESH_CLEAR Value */
#define MXC_S_SPI17Y_WAKE_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS) /**< WAKE_FL_TX_THRESH_CLEAR Setting */
#define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */
#define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */
#define MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_EMPTY_CLEAR Value */
#define MXC_S_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS) /**< WAKE_FL_TX_EMPTY_CLEAR Setting */
#define MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */
#define MXC_F_SPI17Y_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */
#define MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_THRESH_CLEAR Value */
#define MXC_S_SPI17Y_WAKE_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS) /**< WAKE_FL_RX_THRESH_CLEAR Setting */
#define MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */
#define MXC_F_SPI17Y_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */
#define MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_FULL_CLEAR Value */
#define MXC_S_SPI17Y_WAKE_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS) /**< WAKE_FL_RX_FULL_CLEAR Setting */
/**@} end of group SPI17Y_WAKE_FL_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_WAKE_EN SPI17Y_WAKE_EN
* @brief Register for wake up enable.
* @{
*/
#define MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */
#define MXC_F_SPI17Y_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */
#define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_THRESH_DIS Value */
#define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_DIS Setting */
#define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_THRESH_EN Value */
#define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_EN Setting */
#define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */
#define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */
#define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_EMPTY_DIS Value */
#define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_DIS Setting */
#define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_EMPTY_EN Value */
#define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_EN (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_EN Setting */
#define MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */
#define MXC_F_SPI17Y_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */
#define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_THRESH_DIS Value */
#define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_DIS Setting */
#define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_THRESH_EN Value */
#define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_EN Setting */
#define MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */
#define MXC_F_SPI17Y_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */
#define MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_FULL_DIS Value */
#define MXC_S_SPI17Y_WAKE_EN_RX_FULL_DIS (MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_DIS Setting */
#define MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_FULL_EN Value */
#define MXC_S_SPI17Y_WAKE_EN_RX_FULL_EN (MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_EN Setting */
/**@} end of group SPI17Y_WAKE_EN_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_STAT SPI17Y_STAT
* @brief SPI Status register.
* @{
*/
#define MXC_F_SPI17Y_STAT_BUSY_POS 0 /**< STAT_BUSY Position */
#define MXC_F_SPI17Y_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI17Y_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
#define MXC_V_SPI17Y_STAT_BUSY_NOT ((uint32_t)0x0UL) /**< STAT_BUSY_NOT Value */
#define MXC_S_SPI17Y_STAT_BUSY_NOT (MXC_V_SPI17Y_STAT_BUSY_NOT << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_NOT Setting */
#define MXC_V_SPI17Y_STAT_BUSY_ACTIVE ((uint32_t)0x1UL) /**< STAT_BUSY_ACTIVE Value */
#define MXC_S_SPI17Y_STAT_BUSY_ACTIVE (MXC_V_SPI17Y_STAT_BUSY_ACTIVE << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_ACTIVE Setting */
/**@} end of group SPI17Y_STAT_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SPI17Y_REGS_H_ */

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Project/SDK/Device/Include/spimss_regs.h
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/**
* @file spimss_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SPIMSS_REGS_H_
#define _SPIMSS_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup spimss
* @defgroup spimss_registers SPIMSS_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
* @details Serial Peripheral Interface.
*/
/**
* @ingroup spimss_registers
* Structure type to access the SPIMSS Registers.
*/
typedef struct {
union{
__IO uint16_t data16; /**< <tt>\b 0x00:</tt> SPIMSS DATA16 Register */
__IO uint8_t data8[2]; /**< <tt>\b 0x00:</tt> SPIMSS DATA8 Register */
};
__R uint16_t rsv_0x2;
__IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x08:</tt> SPIMSS STATUS Register */
__IO uint32_t mod; /**< <tt>\b 0x0C:</tt> SPIMSS MOD Register */
__R uint32_t rsv_0x10;
__IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
__IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
__IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */
} mxc_spimss_regs_t;
/* Register offsets for module SPIMSS */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_Register_Offsets Register Offsets
* @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address.
* @{
*/
#define MXC_R_SPIMSS_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPIMSS_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPIMSS_STATUS ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPIMSS_MOD ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */
#define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */
/**@} end of group spimss_registers */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DATA16 SPIMSS_DATA16
* @brief SPI 16-bit Data Access
* @{
*/
#define MXC_F_SPIMSS_DATA16_DATA_POS 0 /**< DATA16_DATA Position */
#define MXC_F_SPIMSS_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA16_DATA_POS)) /**< DATA16_DATA Mask */
/**@} end of group SPIMSS_DATA16_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DATA8 SPIMSS_DATA8
* @brief SPI Data 8-bit access
* @{
*/
#define MXC_F_SPIMSS_DATA8_DATA_POS 0 /**< DATA8_DATA Position */
#define MXC_F_SPIMSS_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIMSS_DATA8_DATA_POS)) /**< DATA8_DATA Mask */
/**@} end of group SPIMSS_DATA8_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_CTRL SPIMSS_CTRL
* @brief SPI Control Register.
* @{
*/
#define MXC_F_SPIMSS_CTRL_SPIEN_POS 0 /**< CTRL_SPIEN Position */
#define MXC_F_SPIMSS_CTRL_SPIEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_SPIEN_POS)) /**< CTRL_SPIEN Mask */
#define MXC_V_SPIMSS_CTRL_SPIEN_DISABLE ((uint32_t)0x0UL) /**< CTRL_SPIEN_DISABLE Value */
#define MXC_S_SPIMSS_CTRL_SPIEN_DISABLE (MXC_V_SPIMSS_CTRL_SPIEN_DISABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_DISABLE Setting */
#define MXC_V_SPIMSS_CTRL_SPIEN_ENABLE ((uint32_t)0x1UL) /**< CTRL_SPIEN_ENABLE Value */
#define MXC_S_SPIMSS_CTRL_SPIEN_ENABLE (MXC_V_SPIMSS_CTRL_SPIEN_ENABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_ENABLE Setting */
#define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */
#define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */
#define MXC_V_SPIMSS_CTRL_MMEN_SLAVE ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */
#define MXC_S_SPIMSS_CTRL_MMEN_SLAVE (MXC_V_SPIMSS_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */
#define MXC_V_SPIMSS_CTRL_MMEN_MASTER ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */
#define MXC_S_SPIMSS_CTRL_MMEN_MASTER (MXC_V_SPIMSS_CTRL_MMEN_MASTER << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */
#define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */
#define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */
#define MXC_V_SPIMSS_CTRL_WOR_DISABLE ((uint32_t)0x0UL) /**< CTRL_WOR_DISABLE Value */
#define MXC_S_SPIMSS_CTRL_WOR_DISABLE (MXC_V_SPIMSS_CTRL_WOR_DISABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_DISABLE Setting */
#define MXC_V_SPIMSS_CTRL_WOR_ENABLE ((uint32_t)0x1UL) /**< CTRL_WOR_ENABLE Value */
#define MXC_S_SPIMSS_CTRL_WOR_ENABLE (MXC_V_SPIMSS_CTRL_WOR_ENABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_ENABLE Setting */
#define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */
#define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */
#define MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */
#define MXC_S_SPIMSS_CTRL_CLKPOL_IDLELO (MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */
#define MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */
#define MXC_S_SPIMSS_CTRL_CLKPOL_IDLEHI (MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */
#define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */
#define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */
#define MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */
#define MXC_S_SPIMSS_CTRL_PHASE_ACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */
#define MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */
#define MXC_S_SPIMSS_CTRL_PHASE_INACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */
#define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */
#define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */
#define MXC_V_SPIMSS_CTRL_BIRQ_DISABLE ((uint32_t)0x0UL) /**< CTRL_BIRQ_DISABLE Value */
#define MXC_S_SPIMSS_CTRL_BIRQ_DISABLE (MXC_V_SPIMSS_CTRL_BIRQ_DISABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DISABLE Setting */
#define MXC_V_SPIMSS_CTRL_BIRQ_ENABLE ((uint32_t)0x1UL) /**< CTRL_BIRQ_ENABLE Value */
#define MXC_S_SPIMSS_CTRL_BIRQ_ENABLE (MXC_V_SPIMSS_CTRL_BIRQ_ENABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_ENABLE Setting */
#define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */
#define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */
#define MXC_V_SPIMSS_CTRL_STR_COMPLETE ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */
#define MXC_S_SPIMSS_CTRL_STR_COMPLETE (MXC_V_SPIMSS_CTRL_STR_COMPLETE << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */
#define MXC_V_SPIMSS_CTRL_STR_START ((uint32_t)0x1UL) /**< CTRL_STR_START Value */
#define MXC_S_SPIMSS_CTRL_STR_START (MXC_V_SPIMSS_CTRL_STR_START << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_START Setting */
#define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */
#define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */
#define MXC_V_SPIMSS_CTRL_IRQE_DISABLE ((uint32_t)0x0UL) /**< CTRL_IRQE_DISABLE Value */
#define MXC_S_SPIMSS_CTRL_IRQE_DISABLE (MXC_V_SPIMSS_CTRL_IRQE_DISABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_DISABLE Setting */
#define MXC_V_SPIMSS_CTRL_IRQE_ENABLE ((uint32_t)0x1UL) /**< CTRL_IRQE_ENABLE Value */
#define MXC_S_SPIMSS_CTRL_IRQE_ENABLE (MXC_V_SPIMSS_CTRL_IRQE_ENABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_ENABLE Setting */
/**@} end of group SPIMSS_CTRL_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_STATUS SPIMSS_STATUS
* @brief SPI Status Register.
* @{
*/
#define MXC_F_SPIMSS_STATUS_SLAS_POS 0 /**< STATUS_SLAS Position */
#define MXC_F_SPIMSS_STATUS_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_SLAS_POS)) /**< STATUS_SLAS Mask */
#define MXC_V_SPIMSS_STATUS_SLAS_SELECTED ((uint32_t)0x0UL) /**< STATUS_SLAS_SELECTED Value */
#define MXC_S_SPIMSS_STATUS_SLAS_SELECTED (MXC_V_SPIMSS_STATUS_SLAS_SELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_SELECTED Setting */
#define MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED ((uint32_t)0x1UL) /**< STATUS_SLAS_NOTSELECTED Value */
#define MXC_S_SPIMSS_STATUS_SLAS_NOTSELECTED (MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_NOTSELECTED Setting */
#define MXC_F_SPIMSS_STATUS_TXST_POS 1 /**< STATUS_TXST Position */
#define MXC_F_SPIMSS_STATUS_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TXST_POS)) /**< STATUS_TXST Mask */
#define MXC_V_SPIMSS_STATUS_TXST_IDLE ((uint32_t)0x0UL) /**< STATUS_TXST_IDLE Value */
#define MXC_S_SPIMSS_STATUS_TXST_IDLE (MXC_V_SPIMSS_STATUS_TXST_IDLE << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_IDLE Setting */
#define MXC_V_SPIMSS_STATUS_TXST_BUSY ((uint32_t)0x1UL) /**< STATUS_TXST_BUSY Value */
#define MXC_S_SPIMSS_STATUS_TXST_BUSY (MXC_V_SPIMSS_STATUS_TXST_BUSY << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_BUSY Setting */
#define MXC_F_SPIMSS_STATUS_TUND_POS 2 /**< STATUS_TUND Position */
#define MXC_F_SPIMSS_STATUS_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TUND_POS)) /**< STATUS_TUND Mask */
#define MXC_V_SPIMSS_STATUS_TUND_NOEVENT ((uint32_t)0x0UL) /**< STATUS_TUND_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_TUND_NOEVENT (MXC_V_SPIMSS_STATUS_TUND_NOEVENT << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_TUND_OCCURRED ((uint32_t)0x1UL) /**< STATUS_TUND_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_TUND_OCCURRED (MXC_V_SPIMSS_STATUS_TUND_OCCURRED << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_ROVR_POS 3 /**< STATUS_ROVR Position */
#define MXC_F_SPIMSS_STATUS_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ROVR_POS)) /**< STATUS_ROVR Mask */
#define MXC_V_SPIMSS_STATUS_ROVR_NOEVENT ((uint32_t)0x0UL) /**< STATUS_ROVR_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_ROVR_NOEVENT (MXC_V_SPIMSS_STATUS_ROVR_NOEVENT << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_ROVR_OCCURRED ((uint32_t)0x1UL) /**< STATUS_ROVR_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_ROVR_OCCURRED (MXC_V_SPIMSS_STATUS_ROVR_OCCURRED << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_ABT_POS 4 /**< STATUS_ABT Position */
#define MXC_F_SPIMSS_STATUS_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ABT_POS)) /**< STATUS_ABT Mask */
#define MXC_V_SPIMSS_STATUS_ABT_NOEVENT ((uint32_t)0x0UL) /**< STATUS_ABT_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_ABT_NOEVENT (MXC_V_SPIMSS_STATUS_ABT_NOEVENT << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_ABT_OCCURRED ((uint32_t)0x1UL) /**< STATUS_ABT_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_ABT_OCCURRED (MXC_V_SPIMSS_STATUS_ABT_OCCURRED << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_COL_POS 5 /**< STATUS_COL Position */
#define MXC_F_SPIMSS_STATUS_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_COL_POS)) /**< STATUS_COL Mask */
#define MXC_V_SPIMSS_STATUS_COL_NOEVENT ((uint32_t)0x0UL) /**< STATUS_COL_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_COL_NOEVENT (MXC_V_SPIMSS_STATUS_COL_NOEVENT << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_COL_OCCURRED ((uint32_t)0x1UL) /**< STATUS_COL_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_COL_OCCURRED (MXC_V_SPIMSS_STATUS_COL_OCCURRED << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_TOVR_POS 6 /**< STATUS_TOVR Position */
#define MXC_F_SPIMSS_STATUS_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TOVR_POS)) /**< STATUS_TOVR Mask */
#define MXC_V_SPIMSS_STATUS_TOVR_NOEVENT ((uint32_t)0x0UL) /**< STATUS_TOVR_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_TOVR_NOEVENT (MXC_V_SPIMSS_STATUS_TOVR_NOEVENT << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_TOVR_OCCURRED ((uint32_t)0x1UL) /**< STATUS_TOVR_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_TOVR_OCCURRED (MXC_V_SPIMSS_STATUS_TOVR_OCCURRED << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_IRQ_POS 7 /**< STATUS_IRQ Position */
#define MXC_F_SPIMSS_STATUS_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_IRQ_POS)) /**< STATUS_IRQ Mask */
#define MXC_V_SPIMSS_STATUS_IRQ_INACTIVE ((uint32_t)0x0UL) /**< STATUS_IRQ_INACTIVE Value */
#define MXC_S_SPIMSS_STATUS_IRQ_INACTIVE (MXC_V_SPIMSS_STATUS_IRQ_INACTIVE << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_INACTIVE Setting */
#define MXC_V_SPIMSS_STATUS_IRQ_PENDING ((uint32_t)0x1UL) /**< STATUS_IRQ_PENDING Value */
#define MXC_S_SPIMSS_STATUS_IRQ_PENDING (MXC_V_SPIMSS_STATUS_IRQ_PENDING << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_PENDING Setting */
/**@} end of group SPIMSS_STATUS_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_MOD SPIMSS_MOD
* @brief SPI Mode Register.
* @{
*/
#define MXC_F_SPIMSS_MOD_SSV_POS 0 /**< MOD_SSV Position */
#define MXC_F_SPIMSS_MOD_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSV_POS)) /**< MOD_SSV Mask */
#define MXC_V_SPIMSS_MOD_SSV_LO ((uint32_t)0x0UL) /**< MOD_SSV_LO Value */
#define MXC_S_SPIMSS_MOD_SSV_LO (MXC_V_SPIMSS_MOD_SSV_LO << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_LO Setting */
#define MXC_V_SPIMSS_MOD_SSV_HI ((uint32_t)0x1UL) /**< MOD_SSV_HI Value */
#define MXC_S_SPIMSS_MOD_SSV_HI (MXC_V_SPIMSS_MOD_SSV_HI << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_HI Setting */
#define MXC_F_SPIMSS_MOD_SSIO_POS 1 /**< MOD_SSIO Position */
#define MXC_F_SPIMSS_MOD_SSIO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSIO_POS)) /**< MOD_SSIO Mask */
#define MXC_V_SPIMSS_MOD_SSIO_INPUT ((uint32_t)0x0UL) /**< MOD_SSIO_INPUT Value */
#define MXC_S_SPIMSS_MOD_SSIO_INPUT (MXC_V_SPIMSS_MOD_SSIO_INPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_INPUT Setting */
#define MXC_V_SPIMSS_MOD_SSIO_OUTPUT ((uint32_t)0x1UL) /**< MOD_SSIO_OUTPUT Value */
#define MXC_S_SPIMSS_MOD_SSIO_OUTPUT (MXC_V_SPIMSS_MOD_SSIO_OUTPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_OUTPUT Setting */
#define MXC_F_SPIMSS_MOD_NUMBITS_POS 2 /**< MOD_NUMBITS Position */
#define MXC_F_SPIMSS_MOD_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MOD_NUMBITS_POS)) /**< MOD_NUMBITS Mask */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MOD_NUMBITS_BITS16 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS16 (MXC_V_SPIMSS_MOD_NUMBITS_BITS16 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS16 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MOD_NUMBITS_BITS1 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS1 (MXC_V_SPIMSS_MOD_NUMBITS_BITS1 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS1 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MOD_NUMBITS_BITS2 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS2 (MXC_V_SPIMSS_MOD_NUMBITS_BITS2 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS2 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MOD_NUMBITS_BITS3 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS3 (MXC_V_SPIMSS_MOD_NUMBITS_BITS3 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS3 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MOD_NUMBITS_BITS4 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS4 (MXC_V_SPIMSS_MOD_NUMBITS_BITS4 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS4 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MOD_NUMBITS_BITS5 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS5 (MXC_V_SPIMSS_MOD_NUMBITS_BITS5 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS5 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MOD_NUMBITS_BITS6 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS6 (MXC_V_SPIMSS_MOD_NUMBITS_BITS6 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS6 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MOD_NUMBITS_BITS7 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS7 (MXC_V_SPIMSS_MOD_NUMBITS_BITS7 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS7 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MOD_NUMBITS_BITS8 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS8 (MXC_V_SPIMSS_MOD_NUMBITS_BITS8 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS8 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MOD_NUMBITS_BITS9 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS9 (MXC_V_SPIMSS_MOD_NUMBITS_BITS9 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS9 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MOD_NUMBITS_BITS10 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS10 (MXC_V_SPIMSS_MOD_NUMBITS_BITS10 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS10 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MOD_NUMBITS_BITS11 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS11 (MXC_V_SPIMSS_MOD_NUMBITS_BITS11 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS11 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MOD_NUMBITS_BITS12 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS12 (MXC_V_SPIMSS_MOD_NUMBITS_BITS12 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS12 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MOD_NUMBITS_BITS13 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS13 (MXC_V_SPIMSS_MOD_NUMBITS_BITS13 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS13 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MOD_NUMBITS_BITS14 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS14 (MXC_V_SPIMSS_MOD_NUMBITS_BITS14 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS14 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MOD_NUMBITS_BITS15 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS15 (MXC_V_SPIMSS_MOD_NUMBITS_BITS15 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS15 Setting */
#define MXC_F_SPIMSS_MOD_TX_LJ_POS 7 /**< MOD_TX_LJ Position */
#define MXC_F_SPIMSS_MOD_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_TX_LJ_POS)) /**< MOD_TX_LJ Mask */
#define MXC_V_SPIMSS_MOD_TX_LJ_DISABLE ((uint32_t)0x0UL) /**< MOD_TX_LJ_DISABLE Value */
#define MXC_S_SPIMSS_MOD_TX_LJ_DISABLE (MXC_V_SPIMSS_MOD_TX_LJ_DISABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_DISABLE Setting */
#define MXC_V_SPIMSS_MOD_TX_LJ_ENABLE ((uint32_t)0x1UL) /**< MOD_TX_LJ_ENABLE Value */
#define MXC_S_SPIMSS_MOD_TX_LJ_ENABLE (MXC_V_SPIMSS_MOD_TX_LJ_ENABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_ENABLE Setting */
#define MXC_F_SPIMSS_MOD_SSL1_POS 8 /**< MOD_SSL1 Position */
#define MXC_F_SPIMSS_MOD_SSL1 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL1_POS)) /**< MOD_SSL1 Mask */
#define MXC_V_SPIMSS_MOD_SSL1_HI ((uint32_t)0x0UL) /**< MOD_SSL1_HI Value */
#define MXC_S_SPIMSS_MOD_SSL1_HI (MXC_V_SPIMSS_MOD_SSL1_HI << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_HI Setting */
#define MXC_V_SPIMSS_MOD_SSL1_LO ((uint32_t)0x1UL) /**< MOD_SSL1_LO Value */
#define MXC_S_SPIMSS_MOD_SSL1_LO (MXC_V_SPIMSS_MOD_SSL1_LO << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_LO Setting */
#define MXC_F_SPIMSS_MOD_SSL2_POS 9 /**< MOD_SSL2 Position */
#define MXC_F_SPIMSS_MOD_SSL2 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL2_POS)) /**< MOD_SSL2 Mask */
#define MXC_V_SPIMSS_MOD_SSL2_HI ((uint32_t)0x0UL) /**< MOD_SSL2_HI Value */
#define MXC_S_SPIMSS_MOD_SSL2_HI (MXC_V_SPIMSS_MOD_SSL2_HI << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_HI Setting */
#define MXC_V_SPIMSS_MOD_SSL2_LO ((uint32_t)0x1UL) /**< MOD_SSL2_LO Value */
#define MXC_S_SPIMSS_MOD_SSL2_LO (MXC_V_SPIMSS_MOD_SSL2_LO << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_LO Setting */
#define MXC_F_SPIMSS_MOD_SSL3_POS 10 /**< MOD_SSL3 Position */
#define MXC_F_SPIMSS_MOD_SSL3 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL3_POS)) /**< MOD_SSL3 Mask */
#define MXC_V_SPIMSS_MOD_SSL3_HI ((uint32_t)0x0UL) /**< MOD_SSL3_HI Value */
#define MXC_S_SPIMSS_MOD_SSL3_HI (MXC_V_SPIMSS_MOD_SSL3_HI << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_HI Setting */
#define MXC_V_SPIMSS_MOD_SSL3_LO ((uint32_t)0x1UL) /**< MOD_SSL3_LO Value */
#define MXC_S_SPIMSS_MOD_SSL3_LO (MXC_V_SPIMSS_MOD_SSL3_LO << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_LO Setting */
/**@} end of group SPIMSS_MOD_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_BRG SPIMSS_BRG
* @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for
* the SPI Baud Rate Generator. The reload value must be greater than or equal to
* 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by
* 4).
* @{
*/
#define MXC_F_SPIMSS_BRG_BRG_POS 0 /**< BRG_BRG Position */
#define MXC_F_SPIMSS_BRG_BRG ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_BRG_POS)) /**< BRG_BRG Mask */
/**@} end of group SPIMSS_BRG_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DMA SPIMSS_DMA
* @brief SPI DMA Register.
* @{
*/
#define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Setting */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS 4 /**< DMA_TX_FIFO_CLEAR Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
#define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE ((uint32_t)0x0UL) /**< DMA_TX_FIFO_CLEAR_COMPLETE Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_COMPLETE Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_START Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_START (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_START Setting */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
#define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
#define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
#define MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DISABLE Value */
#define MXC_S_SPIMSS_DMA_TX_DMA_EN_DISABLE (MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DISABLE Setting */
#define MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_ENABLE Value */
#define MXC_S_SPIMSS_DMA_TX_DMA_EN_ENABLE (MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_ENABLE Setting */
#define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Setting */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS 20 /**< DMA_RX_FIFO_CLEAR Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
#define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE ((uint32_t)0x0UL) /**< DMA_RX_FIFO_CLEAR_COMPLETE Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_COMPLETE Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_START Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_START (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_START Setting */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
#define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
#define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
#define MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DISABLE Value */
#define MXC_S_SPIMSS_DMA_RX_DMA_EN_DISABLE (MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DISABLE Setting */
#define MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_ENABLE Value */
#define MXC_S_SPIMSS_DMA_RX_DMA_EN_ENABLE (MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_ENABLE Setting */
/**@} end of group SPIMSS_DMA_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL
* @brief I2S Control Register.
* @{
*/
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DISABLE Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_DISABLE (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DISABLE Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_ENABLE Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_ENABLE (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_ENABLE Setting */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_REPLACED Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_REPLACED Setting */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_HALT Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_HALT Setting */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Setting */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_NORMAL Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_NORMAL Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_REPLACED Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_REPLACED Setting */
/**@} end of group SPIMSS_I2S_CTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SPIMSS_REGS_H_ */

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Project/SDK/Device/Include/system_max32660.h
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/**
* @file system_max32660.h
* @brief System-specific header file
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#ifndef _SYSTEM_MAX32660_H_
#define _SYSTEM_MAX32660_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifndef HFX_FREQ
#define HFX_FREQ 32768
#endif
#ifndef NANORING_FREQ
#define NANORING_FREQ 8000
#endif
#ifndef HIRC96_FREQ
#define HIRC96_FREQ 96000000
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
#ifndef PeripheralClock
#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */
#endif
/*
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void);
/*
* Update SystemCoreClock variable
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_MAX32660_H_ */

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/**
* @file tmr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _TMR_REGS_H_
#define _TMR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup tmr
* @defgroup tmr_registers TMR_Registers
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
* @details 32-bit reloadable timer that can be used for timing and event counting.
*/
/**
* @ingroup tmr_registers
* Structure type to access the TMR Registers.
*/
typedef struct {
__IO uint32_t cnt; /**< <tt>\b 0x00:</tt> TMR CNT Register */
__IO uint32_t cmp; /**< <tt>\b 0x04:</tt> TMR CMP Register */
__IO uint32_t pwm; /**< <tt>\b 0x08:</tt> TMR PWM Register */
__IO uint32_t intr; /**< <tt>\b 0x0C:</tt> TMR INTR Register */
__IO uint32_t cn; /**< <tt>\b 0x10:</tt> TMR CN Register */
__IO uint32_t nolcmp; /**< <tt>\b 0x14:</tt> TMR NOLCMP Register */
} mxc_tmr_regs_t;
/* Register offsets for module TMR */
/**
* @ingroup tmr_registers
* @defgroup TMR_Register_Offsets Register Offsets
* @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address.
* @{
*/
#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */
#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */
#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */
#define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */
#define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */
#define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */
/**@} end of group tmr_registers */
/**
* @ingroup tmr_registers
* @defgroup TMR_INTR TMR_INTR
* @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the
* associated interrupt.
* @{
*/
#define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */
#define MXC_F_TMR_INTR_IRQ_CLR ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */
/**@} end of group TMR_INTR_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_CN TMR_CN
* @brief Timer Control Register.
* @{
*/
#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
#define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
#define MXC_V_TMR_CN_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
#define MXC_S_TMR_CN_TMODE_ONESHOT (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
#define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
#define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
#define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
#define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
#define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
#define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
#define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
#define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
#define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
#define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */
#define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
#define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */
#define MXC_S_TMR_CN_PRES_DIV1 (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */
#define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
#define MXC_S_TMR_CN_PRES_DIV2 (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */
#define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
#define MXC_S_TMR_CN_PRES_DIV4 (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */
#define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
#define MXC_S_TMR_CN_PRES_DIV8 (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */
#define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
#define MXC_S_TMR_CN_PRES_DIV16 (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */
#define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
#define MXC_S_TMR_CN_PRES_DIV32 (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */
#define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
#define MXC_S_TMR_CN_PRES_DIV64 (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
#define MXC_V_TMR_CN_PRES_DIV128 ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */
#define MXC_S_TMR_CN_PRES_DIV128 (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
#define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
#define MXC_V_TMR_CN_TPOL_ACTIVEHI ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */
#define MXC_S_TMR_CN_TPOL_ACTIVEHI (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */
#define MXC_V_TMR_CN_TPOL_ACTIVELO ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */
#define MXC_S_TMR_CN_TPOL_ACTIVELO (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */
#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
#define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */
#define MXC_S_TMR_CN_TEN_DIS (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */
#define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */
#define MXC_S_TMR_CN_TEN_EN (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting */
#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
#define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
#define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */
#define MXC_V_TMR_CN_PWMSYNC_DIS ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value */
#define MXC_S_TMR_CN_PWMSYNC_DIS (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */
#define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */
#define MXC_S_TMR_CN_PWMSYNC_EN (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */
#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
#define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */
#define MXC_V_TMR_CN_NOLHPOL_DIS ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value */
#define MXC_S_TMR_CN_NOLHPOL_DIS (MXC_V_TMR_CN_NOLHPOL_DIS << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */
#define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */
#define MXC_S_TMR_CN_NOLHPOL_EN (MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */
#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
#define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */
#define MXC_V_TMR_CN_NOLLPOL_DIS ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value */
#define MXC_S_TMR_CN_NOLLPOL_DIS (MXC_V_TMR_CN_NOLLPOL_DIS << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */
#define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */
#define MXC_S_TMR_CN_NOLLPOL_EN (MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */
#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
#define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */
#define MXC_V_TMR_CN_PWMCKBD_DIS ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value */
#define MXC_S_TMR_CN_PWMCKBD_DIS (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */
#define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */
#define MXC_S_TMR_CN_PWMCKBD_EN (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */
/**@} end of group TMR_CN_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_NOLCMP TMR_NOLCMP
* @brief Timer Non-Overlapping Compare Register.
* @{
*/
#define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */
#define MXC_F_TMR_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
#define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */
#define MXC_F_TMR_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
/**@} end of group TMR_NOLCMP_Register */
#ifdef __cplusplus
}
#endif
#endif /* _TMR_REGS_H_ */

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/**
* @file uart_regs.h
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup uart
* @defgroup uart_registers UART_Registers
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
* @details UART
*/
/**
* @ingroup uart_registers
* Structure type to access the UART Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> UART CTRL Register */
__IO uint32_t thresh_ctrl; /**< <tt>\b 0x04:</tt> UART THRESH_CTRL Register */
__I uint32_t status; /**< <tt>\b 0x08:</tt> UART STATUS Register */
__IO uint32_t int_en; /**< <tt>\b 0x0C:</tt> UART INT_EN Register */
__IO uint32_t int_fl; /**< <tt>\b 0x10:</tt> UART INT_FL Register */
__IO uint32_t baud0; /**< <tt>\b 0x14:</tt> UART BAUD0 Register */
__IO uint32_t baud1; /**< <tt>\b 0x18:</tt> UART BAUD1 Register */
__IO uint32_t fifo; /**< <tt>\b 0x1C:</tt> UART FIFO Register */
__IO uint32_t dma; /**< <tt>\b 0x20:</tt> UART DMA Register */
__IO uint32_t tx_fifo; /**< <tt>\b 0x24:</tt> UART TX_FIFO Register */
} mxc_uart_regs_t;
/* Register offsets for module UART */
/**
* @ingroup uart_registers
* @defgroup UART_Register_Offsets Register Offsets
* @brief UART Peripheral Register Offsets from the UART Base Peripheral Address.
* @{
*/
#define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */
#define MXC_R_UART_THRESH_CTRL ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */
#define MXC_R_UART_STATUS ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */
#define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */
#define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */
#define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */
#define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */
#define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */
#define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */
#define MXC_R_UART_TX_FIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */
/**@} end of group uart_registers */
/**
* @ingroup uart_registers
* @defgroup UART_CTRL UART_CTRL
* @brief Control Register.
* @{
*/
#define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
#define MXC_F_UART_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
#define MXC_V_UART_CTRL_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */
#define MXC_S_UART_CTRL_ENABLE_DIS (MXC_V_UART_CTRL_ENABLE_DIS << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */
#define MXC_V_UART_CTRL_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value */
#define MXC_S_UART_CTRL_ENABLE_EN (MXC_V_UART_CTRL_ENABLE_EN << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */
#define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */
#define MXC_F_UART_CTRL_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */
#define MXC_V_UART_CTRL_PARITY_EN_DIS ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */
#define MXC_S_UART_CTRL_PARITY_EN_DIS (MXC_V_UART_CTRL_PARITY_EN_DIS << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */
#define MXC_V_UART_CTRL_PARITY_EN_EN ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */
#define MXC_S_UART_CTRL_PARITY_EN_EN (MXC_V_UART_CTRL_PARITY_EN_EN << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */
#define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */
#define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */
#define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */
#define MXC_S_UART_CTRL_PARITY_EVEN (MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */
#define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */
#define MXC_S_UART_CTRL_PARITY_ODD (MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */
#define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */
#define MXC_S_UART_CTRL_PARITY_MARK (MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */
#define MXC_V_UART_CTRL_PARITY_SPACE ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */
#define MXC_S_UART_CTRL_PARITY_SPACE (MXC_V_UART_CTRL_PARITY_SPACE << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */
#define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */
#define MXC_F_UART_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */
#define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */
#define MXC_S_UART_CTRL_PARMD_1 (MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */
#define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */
#define MXC_S_UART_CTRL_PARMD_0 (MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */
#define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */
#define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
#define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */
#define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
#define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */
#define MXC_F_UART_CTRL_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */
#define MXC_V_UART_CTRL_BITACC_FRAME ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */
#define MXC_S_UART_CTRL_BITACC_FRAME (MXC_V_UART_CTRL_BITACC_FRAME << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */
#define MXC_V_UART_CTRL_BITACC_BIT ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */
#define MXC_S_UART_CTRL_BITACC_BIT (MXC_V_UART_CTRL_BITACC_BIT << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */
#define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */
#define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
#define MXC_V_UART_CTRL_CHAR_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_5 (MXC_V_UART_CTRL_CHAR_SIZE_5 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_6 (MXC_V_UART_CTRL_CHAR_SIZE_6 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_7 (MXC_V_UART_CTRL_CHAR_SIZE_7 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_8 (MXC_V_UART_CTRL_CHAR_SIZE_8 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */
#define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */
#define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
#define MXC_V_UART_CTRL_STOPBITS_1 ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */
#define MXC_S_UART_CTRL_STOPBITS_1 (MXC_V_UART_CTRL_STOPBITS_1 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */
#define MXC_V_UART_CTRL_STOPBITS_1_5 ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */
#define MXC_S_UART_CTRL_STOPBITS_1_5 (MXC_V_UART_CTRL_STOPBITS_1_5 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */
#define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */
#define MXC_F_UART_CTRL_FLOW_CTRL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */
#define MXC_V_UART_CTRL_FLOW_CTRL_EN ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */
#define MXC_S_UART_CTRL_FLOW_CTRL_EN (MXC_V_UART_CTRL_FLOW_CTRL_EN << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */
#define MXC_V_UART_CTRL_FLOW_CTRL_DIS ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */
#define MXC_S_UART_CTRL_FLOW_CTRL_DIS (MXC_V_UART_CTRL_FLOW_CTRL_DIS << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */
#define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */
#define MXC_F_UART_CTRL_FLOW_POL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */
#define MXC_V_UART_CTRL_FLOW_POL_0 ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */
#define MXC_S_UART_CTRL_FLOW_POL_0 (MXC_V_UART_CTRL_FLOW_POL_0 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */
#define MXC_V_UART_CTRL_FLOW_POL_1 ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */
#define MXC_S_UART_CTRL_FLOW_POL_1 (MXC_V_UART_CTRL_FLOW_POL_1 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */
#define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */
#define MXC_F_UART_CTRL_NULL_MODEM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM Mask */
#define MXC_V_UART_CTRL_NULL_MODEM_DIS ((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */
#define MXC_S_UART_CTRL_NULL_MODEM_DIS (MXC_V_UART_CTRL_NULL_MODEM_DIS << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting */
#define MXC_V_UART_CTRL_NULL_MODEM_EN ((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */
#define MXC_S_UART_CTRL_NULL_MODEM_EN (MXC_V_UART_CTRL_NULL_MODEM_EN << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */
#define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */
#define MXC_F_UART_CTRL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask */
#define MXC_V_UART_CTRL_BREAK_DIS ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value */
#define MXC_S_UART_CTRL_BREAK_DIS (MXC_V_UART_CTRL_BREAK_DIS << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */
#define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */
#define MXC_S_UART_CTRL_BREAK_EN (MXC_V_UART_CTRL_BREAK_EN << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */
#define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */
#define MXC_F_UART_CTRL_CLKSEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
#define MXC_V_UART_CTRL_CLKSEL_SYSTEM ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */
#define MXC_S_UART_CTRL_CLKSEL_SYSTEM (MXC_V_UART_CTRL_CLKSEL_SYSTEM << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */
#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */
#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE (MXC_V_UART_CTRL_CLKSEL_ALTERNATE << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */
#define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */
#define MXC_F_UART_CTRL_RX_TO ((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */
/**@} end of group UART_CTRL_Register */
/**
* @ingroup uart_registers
* @defgroup UART_THRESH_CTRL UART_THRESH_CTRL
* @brief Threshold Control register.
* @{
*/
#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */
#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< THRESH_CTRL_RX_FIFO_THRESH Mask */
#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */
#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< THRESH_CTRL_TX_FIFO_THRESH Mask */
#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */
#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< THRESH_CTRL_RTS_FIFO_THRESH Mask */
/**@} end of group UART_THRESH_CTRL_Register */
/**
* @ingroup uart_registers
* @defgroup UART_STATUS UART_STATUS
* @brief Status Register.
* @{
*/
#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
#define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */
#define MXC_F_UART_STATUS_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */
#define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */
#define MXC_F_UART_STATUS_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */
#define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */
#define MXC_F_UART_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */
#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
#define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
#define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */
#define MXC_F_UART_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */
#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
#define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS 8 /**< STATUS_RX_FIFO_CNT Position */
#define MXC_F_UART_STATUS_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */
#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS 16 /**< STATUS_TX_FIFO_CNT Position */
#define MXC_F_UART_STATUS_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */
#define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */
#define MXC_F_UART_STATUS_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */
/**@} end of group UART_STATUS_Register */
/**
* @ingroup uart_registers
* @defgroup UART_INT_EN UART_INT_EN
* @brief Interrupt Enable Register.
* @{
*/
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */
#define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */
#define MXC_F_UART_INT_EN_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE Mask */
#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
#define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */
#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS 4 /**< INT_EN_RX_FIFO_THRESH Position */
#define MXC_F_UART_INT_EN_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */
#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */
#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */
#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS 6 /**< INT_EN_TX_FIFO_THRESH Position */
#define MXC_F_UART_INT_EN_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< INT_EN_TX_FIFO_THRESH Mask */
#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
#define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
#define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */
#define MXC_F_UART_INT_EN_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT Mask */
#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
#define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */
/**@} end of group UART_INT_EN_Register */
/**
* @ingroup uart_registers
* @defgroup UART_INT_FL UART_INT_FL
* @brief Interrupt Status Flags.
* @{
*/
#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS 0 /**< INT_FL_RX_FRAME_ERROR Position */
#define MXC_F_UART_INT_FL_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */
#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS 1 /**< INT_FL_RX_PARITY_ERROR Position */
#define MXC_F_UART_INT_FL_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */
#define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */
#define MXC_F_UART_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */
#define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */
#define MXC_F_UART_INT_FL_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */
#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS 4 /**< INT_FL_RX_FIFO_THRESH Position */
#define MXC_F_UART_INT_FL_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */
#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */
#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */
#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS 6 /**< INT_FL_TX_FIFO_THRESH Position */
#define MXC_F_UART_INT_FL_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< INT_FL_TX_FIFO_THRESH Mask */
#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
#define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
#define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */
#define MXC_F_UART_INT_FL_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT Mask */
#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
#define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */
/**@} end of group UART_INT_FL_Register */
/**
* @ingroup uart_registers
* @defgroup UART_BAUD0 UART_BAUD0
* @brief Baud rate register. Integer portion.
* @{
*/
#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
#define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
#define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */
#define MXC_F_UART_BAUD0_FACTOR ((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */
#define MXC_V_UART_BAUD0_FACTOR_128 ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */
#define MXC_S_UART_BAUD0_FACTOR_128 (MXC_V_UART_BAUD0_FACTOR_128 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */
#define MXC_V_UART_BAUD0_FACTOR_64 ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */
#define MXC_S_UART_BAUD0_FACTOR_64 (MXC_V_UART_BAUD0_FACTOR_64 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */
#define MXC_V_UART_BAUD0_FACTOR_32 ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */
#define MXC_S_UART_BAUD0_FACTOR_32 (MXC_V_UART_BAUD0_FACTOR_32 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */
#define MXC_V_UART_BAUD0_FACTOR_16 ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */
#define MXC_S_UART_BAUD0_FACTOR_16 (MXC_V_UART_BAUD0_FACTOR_16 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */
/**@} end of group UART_BAUD0_Register */
/**
* @ingroup uart_registers
* @defgroup UART_BAUD1 UART_BAUD1
* @brief Baud rate register. Decimal Setting.
* @{
*/
#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
#define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
/**@} end of group UART_BAUD1_Register */
/**
* @ingroup uart_registers
* @defgroup UART_FIFO UART_FIFO
* @brief FIFO Data buffer.
* @{
*/
#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
#define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */
/**@} end of group UART_FIFO_Register */
/**
* @ingroup uart_registers
* @defgroup UART_DMA UART_DMA
* @brief DMA Configuration.
* @{
*/
#define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */
#define MXC_F_UART_DMA_TDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
#define MXC_V_UART_DMA_TDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */
#define MXC_S_UART_DMA_TDMA_EN_DIS (MXC_V_UART_DMA_TDMA_EN_DIS << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */
#define MXC_V_UART_DMA_TDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value */
#define MXC_S_UART_DMA_TDMA_EN_EN (MXC_V_UART_DMA_TDMA_EN_EN << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */
#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
#define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
#define MXC_V_UART_DMA_RXDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */
#define MXC_S_UART_DMA_RXDMA_EN_DIS (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */
#define MXC_V_UART_DMA_RXDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */
#define MXC_S_UART_DMA_RXDMA_EN_EN (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */
#define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */
#define MXC_F_UART_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */
#define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */
#define MXC_F_UART_DMA_RXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */
/**@} end of group UART_DMA_Register */
/**
* @ingroup uart_registers
* @defgroup UART_TX_FIFO UART_TX_FIFO
* @brief Transmit FIFO Status register.
* @{
*/
#define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */
#define MXC_F_UART_TX_FIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */
/**@} end of group UART_TX_FIFO_Register */
#ifdef __cplusplus
}
#endif
#endif /* _UART_REGS_H_ */

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Project/SDK/Device/Include/wdt_regs.h
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/**
* @file wdt_regs.h
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _WDT_REGS_H_
#define _WDT_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup wdt
* @defgroup wdt_registers WDT_Registers
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
* @details Watchdog Timer 0
*/
/**
* @ingroup wdt_registers
* Structure type to access the WDT Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> WDT CTRL Register */
__O uint32_t rst; /**< <tt>\b 0x04:</tt> WDT RST Register */
} mxc_wdt_regs_t;
/* Register offsets for module WDT */
/**
* @ingroup wdt_registers
* @defgroup WDT_Register_Offsets Register Offsets
* @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address.
* @{
*/
#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */
#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */
/**@} end of group wdt_registers */
/**
* @ingroup wdt_registers
* @defgroup WDT_CTRL WDT_CTRL
* @brief Watchdog Timer Control Register.
* @{
*/
#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
#define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
#define MXC_V_WDT_CTRL_WDT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */
#define MXC_S_WDT_CTRL_WDT_EN_DIS (MXC_V_WDT_CTRL_WDT_EN_DIS << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */
#define MXC_V_WDT_CTRL_WDT_EN_EN ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value */
#define MXC_S_WDT_CTRL_WDT_EN_EN (MXC_V_WDT_CTRL_WDT_EN_EN << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */
#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
#define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE ((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */
#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE (MXC_V_WDT_CTRL_INT_FLAG_INACTIVE << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting */
#define MXC_V_WDT_CTRL_INT_FLAG_PENDING ((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */
#define MXC_S_WDT_CTRL_INT_FLAG_PENDING (MXC_V_WDT_CTRL_INT_FLAG_PENDING << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */
#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
#define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
#define MXC_V_WDT_CTRL_INT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */
#define MXC_S_WDT_CTRL_INT_EN_DIS (MXC_V_WDT_CTRL_INT_EN_DIS << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */
#define MXC_V_WDT_CTRL_INT_EN_EN ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value */
#define MXC_S_WDT_CTRL_INT_EN_EN (MXC_V_WDT_CTRL_INT_EN_EN << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */
#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
#define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
#define MXC_V_WDT_CTRL_RST_EN_DIS ((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */
#define MXC_S_WDT_CTRL_RST_EN_DIS (MXC_V_WDT_CTRL_RST_EN_DIS << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */
#define MXC_V_WDT_CTRL_RST_EN_EN ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value */
#define MXC_S_WDT_CTRL_RST_EN_EN (MXC_V_WDT_CTRL_RST_EN_EN << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */
#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
#define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT ((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */
#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */
#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED ((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */
#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED (MXC_V_WDT_CTRL_RST_FLAG_OCCURRED << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting */
/**@} end of group WDT_CTRL_Register */
/**
* @ingroup wdt_registers
* @defgroup WDT_RST WDT_RST
* @brief Watchdog Timer Reset Register.
* @{
*/
#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
#define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
#define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
#define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
#define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
#define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
/**@} end of group WDT_RST_Register */
#ifdef __cplusplus
}
#endif
#endif /* _WDT_REGS_H_ */

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/**
* @file system_max32660.c
* @brief System-level initialization implementation file
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include "max32660.h"
#include "gcr_regs.h"
#include "pwrseq_regs.h"
#include "tmr_regs.h"
#include "wdt_regs.h"
#include "mxc_sys.h"
extern void (* const __isr_vector[])(void);
uint32_t SystemCoreClock = HIRC96_FREQ;
__weak void SystemCoreClockUpdate(void)
{
uint32_t base_freq, div, clk_src,ovr;
// Get the clock source and frequency
clk_src = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL);
if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_HFXIN) {
base_freq = HFX_FREQ;
} else {
if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_NANORING) {
base_freq = NANORING_FREQ;
} else {
ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) {
base_freq = HIRC96_FREQ/4;
} else {
if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) {
base_freq = HIRC96_FREQ/2;
} else {
base_freq = HIRC96_FREQ;
}
}
}
}
// Get the clock divider
div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
SystemCoreClock = base_freq >> div;
}
/* This function is called before C runtime initialization and can be
* implemented by the application for early initializations. If a value other
* than '0' is returned, the C runtime initialization will be skipped.
*
* You may over-ride this function in your program by defining a custom
* PreInit(), but care should be taken to reproduce the initilization steps
* or a non-functional system may result.
*/
__weak int PreInit(void)
{
/* Do nothing */
return 0;
}
/* This function can be implemented by the application to initialize the board */
__weak int Board_Init(void)
{
/* Do nothing */
return 0;
}
/* This function is called just before control is transferred to main().
*
* You may over-ride this function in your program by defining a custom
* SystemInit(), but care should be taken to reproduce the initialization
* steps or a non-functional system may result.
*/
__weak void SystemInit(void)
{
/* Configure the interrupt controller to use the application vector table in */
/* the application space */
/* IAR & Keil must set vector table after all memory initialization. */
SCB->VTOR = (unsigned long)__isr_vector;
MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
__DSB();
__ISB();
/* Switch system clock to HIRC */
SYS_Clock_Select(SYS_CLOCK_HIRC, MXC_TMR0);
/* Disable clocks to peripherals by default to reduce power */
SYS_ClockDisable(SYS_PERIPH_CLOCK_DMA);
SYS_ClockDisable(SYS_PERIPH_CLOCK_SPI17Y);
SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS);
SYS_ClockDisable(SYS_PERIPH_CLOCK_UART0);
SYS_ClockDisable(SYS_PERIPH_CLOCK_UART1);
SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C0);
SYS_ClockDisable(SYS_PERIPH_CLOCK_T0);
SYS_ClockDisable(SYS_PERIPH_CLOCK_T1);
SYS_ClockDisable(SYS_PERIPH_CLOCK_T2);
SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C1);
Board_Init();
}
#if defined ( __CC_ARM )
/* Global variable initialization does not occur until post scatterload in Keil tools.*/
/* External function called after our post scatterload function implementation. */
extern void $Super$$__main_after_scatterload(void);
/**
* @brief Initialization function for SystemCoreClock and Board_Init.
* @details $Sub$$__main_after_scatterload is called during system startup in the Keil
* toolset. Global variable and static variable space must be set up by the compiler
* prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
* require global memory for variable storage and are called from this function in
* the Keil tool chain.
*/
void $Sub$$__main_after_scatterload(void)
{
SystemInit();
$Super$$__main_after_scatterload();
}
#endif /* __CC_ARM */

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/**
* @file
* @brief Direct Memory Access (DMA) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-07-01 11:06:19 -0500 (Mon, 01 Jul 2019) $
* $Revision: 44383 $
*
*************************************************************************** */
#ifndef _DMA_H_
#define _DMA_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "dma_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup dma Direct Memory Access (DMA)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* Enumeration for the DMA Channel's priority level.
*/
typedef enum {
DMA_PRIO_HIGH = MXC_S_DMA_CFG_PRI_HIGH, /**< High Priority */
DMA_PRIO_MEDHIGH = MXC_S_DMA_CFG_PRI_MEDHIGH, /**< Medium High Priority */
DMA_PRIO_MEDLOW = MXC_S_DMA_CFG_PRI_MEDLOW, /**< Medium Low Priority */
DMA_PRIO_LOW = MXC_S_DMA_CFG_PRI_LOW, /**< Low Priority */
} dma_priority_t;
/** @brief DMA request select */
typedef enum {
DMA_REQSEL_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, /**< Memory to Memory DMA Request Selection */
DMA_REQSEL_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, /**< SPI0 Receive DMA Request Selection */
DMA_REQSEL_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, /**< SPI1 Receive DMA Request Selection */
DMA_REQSEL_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, /**< UART0 Receive DMA Request Selection */
DMA_REQSEL_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, /**< UART1 Receive DMA Request Selection */
DMA_REQSEL_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, /**< I2C0 Receive DMA Request Selection */
DMA_REQSEL_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, /**< I2C1 Receive DMA Request Selection */
DMA_REQSEL_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, /**< SPI0 Transmit DMA Request Selection */
DMA_REQSEL_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, /**< SPI1 Transmit DMA Request Selection */
DMA_REQSEL_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, /**< UART0 Transmit DMA Request Selection */
DMA_REQSEL_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, /**< UART1 Transmit DMA Request Selection */
DMA_REQSEL_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, /**< I2C0 Transmit DMA Request Selection */
DMA_REQSEL_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, /**< I2C1 Transmit DMA Request Selection */
} dma_reqsel_t;
/** @brief Enumeration for the DMA prescaler */
typedef enum {
DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, /**< Prescaler disabled */
DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, /**< Divide by 256 */
DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, /**< Divide by 65,536 */
DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, /**< Divide by 16,777,216 */
} dma_prescale_t;
/** @brief Enumeration for the DMA timeout value */
typedef enum {
DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, /**< DMA timeout of 4 clocks */
DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, /**< DMA timeout of 8 clocks */
DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, /**< DMA timeout of 16 clocks */
DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, /**< DMA timeout of 32 clocks */
DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, /**< DMA timeout of 64 clocks */
DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, /**< DMA timeout of 128 clocks */
DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, /**< DMA timeout of 256 clocks */
DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, /**< DMA timeout of 512 clocks */
} dma_timeout_t;
/** @brief DMA transfer data width */
typedef enum {
/* Using the '_V_' define instead of the '_S_' since these same values will be used to
specify the DSTWD also. The API functions will shift the value the correct amount
prior to writing the cfg register. */
DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, /**< DMA transfer in bytes */
DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, /**< DMA transfer in 16-bit half-words */
DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, /**< DMA transfer in 32-bit words */
} dma_width_t;
/** @brief Convenience defines for options */
#define DMA_FALSE 0 /**< Define for passing 0 to DMA functions */
#define DMA_TRUE 1 /**< Define for passing 1 to DMA functions */
/* **** Function Prototypes **** */
/**
* @brief Initialize DMA resources
* @details This initialization is required before using the DMA driver functions.
* @return #E_NO_ERROR if successful
*/
int DMA_Init(void);
/**
* @brief Request DMA channel
* @details Returns a handle to the first free DMA channel, which can be used via API calls
* or direct access to channel registers using the DMA_GetCHRegs(int ch) function.
* @return Non-negative channel handle (inclusive of zero).
* @return #E_NONE_AVAIL All channels in use.
* @return #E_BAD_STATE DMA is not initialized, call DMA_Init() first.
* @return #E_BUSY DMA is currently busy (locked), try again later.
*/
int DMA_AcquireChannel(void);
/**
* @brief Release DMA channel
* @details Stops any DMA operation on the channel and returns it to the pool of free channels.
*
* @param ch channel handle to release
*
* @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise
*/
int DMA_ReleaseChannel(int ch);
/**
* @brief Configure the DMA channel
* @details Configures the channel, which was previously requested by DMA_Getchannel()
*
* @param ch The channel to configure
* @param prio The channel's priority
* @param reqsel Select the DMA request line
* @param reqwait_en The enable delay before request
* @param tosel The transfer timer timeout select
* @param pssel The transfer timer prescale select
* @param srcwd The size of the read transactions
* @param srcinc_en Enable auto-increment source pointer
* @param dstwd The size of write transactions
* @param dstinc_en Enable auto-increment destination pointer
* @param burst_size The number of bytes transferred in one transaction
* @param chdis_inten The channel disable interrupt enable
* @param ctz_inten The count-to-zero interrupt enable
*
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_ConfigChannel(int ch,
dma_priority_t prio,
dma_reqsel_t reqsel, unsigned int reqwait_en,
dma_timeout_t tosel, dma_prescale_t pssel,
dma_width_t srcwd, unsigned int srcinc_en,
dma_width_t dstwd, unsigned int dstinc_en,
unsigned int burst_size, unsigned int chdis_inten,
unsigned int ctz_inten);
/**
* @brief Set channel source, destination, and count for transfer
* @param ch channel handle
* @param src_addr source address (*)
* @param dst_addr destination address (*)
* @param count number of bytes to transfer
* @details This function is used to set the source and destination addresses and the number
* of bytes to transfer using the channel, @p ch.
* @note Unless the channel request select is #DMA_REQSEL_MEMTOMEM,
* either src_addr or dst_addr will be ignored by the DMA engine.
* In these cases, the address is a don't-care. See the User's
* Guide for more information.
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_SetSrcDstCnt(int ch,
void *src_addr,
void *dst_addr,
unsigned int count);
/**
* @brief Set channel reload values
* @param ch channel handle
* @param src_addr_reload source address
* @param dst_addr_reload destination address
* @param count_reload number of bytes to transfer
* @details This function will set the values which will be loaded after the
* channel count register reaches zero. After enabling, call with
* count_reload set to zero to disable reload.
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_SetReload(int ch,
void *src_addr_reload,
void *dst_addr_reload,
unsigned int count_reload);
/**
* @brief Set channel interrupt callback
* @param ch channel handle
* @param callback Pointer to a function to call when the channel
* interrupt flag is set and interrupts are enabled or
* when DMA is shutdown by the driver.
* @details Configures the channel interrupt callback. The @p callback
* function is called for two conditions:
* -# When the channel's interrupt flag is set and DMA interrupts
* are enabled.
* -# If the driver calls the DMA_Shutdown() function. The
* callback function prototype is:
* @code
* void callback_fn(int ch, int reason);
* @endcode
* @p ch indicates the channel that generated the callback, @p
* reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN
* if the DMA is being shutdown.
*
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_SetCallback(int ch, void (*callback)(int, int));
/**
* @brief Enable channel interrupt
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_EnableInterrupt(int ch);
/**
* @brief Disable channel interrupt
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_DisableInterrupt(int ch);
/**
* @brief Read channel interrupt flags
* @param ch channel handle
* @param fl flags to get
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_GetFlags(int ch, unsigned int *fl);
/**
* @brief Clear channel interrupt flags
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_ClearFlags(int ch);
/**
* @brief Start transfer
* @param ch channel handle
* @details Start the DMA channel transfer, assumes that DMA_SetSrcDstCnt() has been called beforehand.
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_Start(int ch);
/**
* @brief Stop DMA transfer, irrespective of status (complete or in-progress)
* @param ch channel handle
* @return #E_BAD_PARAM if an unused or invalid channel handle
* @return #E_NO_ERROR otherwise
*/
int DMA_Stop(int ch);
/**
* @brief Get a pointer to the DMA channel registers
* @param ch channel handle
* @details If direct access to DMA channel registers is required, this
* function can be used on a channel handle returned by DMA_AcquireChannel().
* @return NULL if an unused or invalid channel handle, or a valid pointer otherwise
*/
mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch);
/**
* @brief Interrupt handler function
* @param ch channel handle
* @details Call this function as the ISR for each DMA channel under driver control.
* Interrupt flags for channel ch will be automatically cleared before return.
* @return NULL if an unused or invalid channel handle, or a valid pointer otherwise
*/
void DMA_Handler(int ch);
/**@} end of group dma */
#ifdef __cplusplus
}
#endif
#endif /* _DMA_H_ */

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/**
* @file
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $
* $Revision: 43696 $
*
*************************************************************************** */
#ifndef _FLC_H_
#define _FLC_H_
/* **** Includes **** */
#include "flc_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup flc Flash Controller
* @ingroup periphlibs
* @{
*/
/***** Definitions *****/
/// Bit mask that can be used to find the starting address of a page in flash
#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1)
/// Calculate the address of a page in flash from the page number
#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))
/***** Function Prototypes *****/
/**
* @brief Initializes the flash controller for erase/write operations
* @param sys_cfg Reserved for future use. Use NULL as this parameter's value.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_Init(const sys_cfg_flc_t *sys_cfg);
/**
* @brief Checks if Flash controller is busy.
* @details Reading or executing from flash is not possible if flash is busy
* with an erase or write operation.
* @return If non-zero, flash operation is in progress
*/
int FLC_Busy(void);
/**
* @brief Erases the entire flash array.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_MassErase(void);
/**
* @brief Erases the page of flash at the specified address.
* @param address Any address within the page to erase.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_PageErase(uint32_t address);
/**
* @brief Page erase from start to end address.
* @note All data within the selected pages will be erased.
* @param start Any address within the first page to erase.
* @param end Any address within the last page to erase.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_Erase(uint32_t start, uint32_t end);
/**
* @brief Erase from start to end address. Restoring any flash page contents outside the given range.
* @param start Starting address to erase, inclusive.
* @param end Ending address to erase, exclusive.
* @param buffer Data buffer to restore data in beginning and ending pages.
* @param length Length of given buffer.
*
* @note Buffer should be appropriate size to store all of the data remaining in the
* first and last pages. length should be greater than or equal to
* (start % MXC_FLASH_PAGE_SIZE) and ((MXC_FLASH_PAGE_SIZE - (end % MXC_FLASH_PAGE_SIZE)) % MXC_FLASH_PAGE_SIZE).
*
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int FLC_BufferErase(uint32_t start, uint32_t end, uint8_t *buffer, unsigned length);
/**
* @brief Writes the specified 32-bit value to flash.
* @param address 32-bit aligned address in flash to write.
* @param data value to be written to flash.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_Write32(uint32_t address, uint32_t data);
/**
* @brief Writes the specified 128-bits of data to flash.
* @param address 128-bit aligned address in flash to write.
* @param data pointer to data to be written to flash.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_Write128(uint32_t address, uint32_t *data);
/**
* @brief Writes data to flash.
* @param address Address in flash to start writing from.
* @param length Number of bytes to be written.
* @param buffer Pointer to data to be written to flash.
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_Write(uint32_t address, uint32_t length, uint8_t *buffer);
/**
* @brief Enable flash interrupts
* @param mask Interrupts to enable
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_EnableInt(uint32_t mask);
/**
* @brief Disable flash interrupts
* @param mask Interrupts to disable
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_DisableInt(uint32_t mask);
/**
* @brief Retrieve flash interrupt flags
* @return Mask of active flags.
*/
int FLC_GetFlags(void);
/**
* @brief Clear flash interrupt flags
* @note Provide the bit position to clear, even if the flag is write-0-to-clear
* @param mask Mask of flags to clear
* @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int FLC_ClearFlags(uint32_t mask);
/**
* @brief Unlock info block
*
* @return #E_NO_ERROR If function is successful.
*/
int FLC_UnlockInfoBlock(void);
/**
* @brief Lock info block
*
* @return #E_NO_ERROR If function is successful.
*/
int FLC_LockInfoBlock(void);
/**@} end of group flc */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_H_ */

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/**
* @file gpio.h
* @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _GPIO_H_
#define _GPIO_H_
/* **** Includes **** */
#include "gpio_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup gpio General-Purpose Input/Output (GPIO)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* @defgroup gpio_port_pin Port and Pin Definitions
* @ingroup gpio
* @{
* @defgroup gpio_port Port Definitions
* @ingroup gpio_port_pin
* @{
*/
#define PORT_0 ((uint32_t)(0UL)) /**< Port 0 Define*/
#define PORT_1 ((uint32_t)(1UL)) /**< Port 1 Define*/
#define PORT_2 ((uint32_t)(2UL)) /**< Port 2 Define*/
#define PORT_3 ((uint32_t)(3UL)) /**< Port 3 Define*/
#define PORT_4 ((uint32_t)(4UL)) /**< Port 4 Define*/
/**@} end of gpio_port group*/
/**
* @defgroup gpio_pin Pin Definitions
* @ingroup gpio_port_pin
* @{
*/
#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */
#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */
#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */
#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */
#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */
#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */
#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */
#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */
#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */
#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */
#define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */
#define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */
#define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */
#define PIN_13 ((uint32_t)(1UL << 13)) /**< Pin 13 Define */
#define PIN_14 ((uint32_t)(1UL << 14)) /**< Pin 14 Define */
#define PIN_15 ((uint32_t)(1UL << 15)) /**< Pin 15 Define */
#define PIN_16 ((uint32_t)(1UL << 16)) /**< Pin 16 Define */
#define PIN_17 ((uint32_t)(1UL << 17)) /**< Pin 17 Define */
#define PIN_18 ((uint32_t)(1UL << 18)) /**< Pin 18 Define */
#define PIN_19 ((uint32_t)(1UL << 19)) /**< Pin 19 Define */
#define PIN_20 ((uint32_t)(1UL << 20)) /**< Pin 20 Define */
#define PIN_21 ((uint32_t)(1UL << 21)) /**< Pin 21 Define */
#define PIN_22 ((uint32_t)(1UL << 22)) /**< Pin 22 Define */
#define PIN_23 ((uint32_t)(1UL << 23)) /**< Pin 23 Define */
#define PIN_24 ((uint32_t)(1UL << 24)) /**< Pin 24 Define */
#define PIN_25 ((uint32_t)(1UL << 25)) /**< Pin 25 Define */
#define PIN_26 ((uint32_t)(1UL << 26)) /**< Pin 26 Define */
#define PIN_27 ((uint32_t)(1UL << 27)) /**< Pin 27 Define */
#define PIN_28 ((uint32_t)(1UL << 28)) /**< Pin 28 Define */
#define PIN_29 ((uint32_t)(1UL << 29)) /**< Pin 29 Define */
#define PIN_30 ((uint32_t)(1UL << 30)) /**< Pin 30 Define */
#define PIN_31 ((uint32_t)(1UL << 31)) /**< Pin 31 Define */
/**@} end of gpio_pin group */
/**@} end of gpio_port_pin group */
/**
* Enumeration type for the GPIO Function Type
*/
typedef enum {
GPIO_FUNC_IN, /**< GPIO Input */
GPIO_FUNC_OUT, /**< GPIO Output */
GPIO_FUNC_ALT1, /**< Alternate Function Selection */
GPIO_FUNC_ALT2, /**< Alternate Function Selection */
GPIO_FUNC_ALT3, /**< Alternate Function Selection */
GPIO_FUNC_ALT4, /**< Alternate Function Selection */
} gpio_func_t;
/**
* Enumeration type for the type of GPIO pad on a given pin.
*/
typedef enum {
GPIO_PAD_NONE, /**< No pull-up or pull-down */
GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */
GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */
} gpio_pad_t;
/**
* Structure type for configuring a GPIO port.
*/
typedef struct {
uint32_t port; /**< Index of GPIO port */
uint32_t mask; /**< Pin mask (multiple pins may be set) */
gpio_func_t func; /**< Function type */
gpio_pad_t pad; /**< Pad type */
} gpio_cfg_t;
/**
* Enumeration type for the interrupt modes.
*/
typedef enum {
GPIO_INT_LEVEL = 0, /**< Interrupt is level sensitive */
GPIO_INT_EDGE = 1 /**< Interrupt is edge sensitive */
} gpio_int_mode_t;
/**
* Enumeration type for the interrupt polarity.
*/
typedef enum {
GPIO_INT_FALLING = 0, /**< Interrupt triggers on falling edge */
GPIO_INT_HIGH = GPIO_INT_FALLING, /**< Interrupt triggers when level is high */
GPIO_INT_RISING, /**< Interrupt triggers on rising edge */
GPIO_INT_LOW = GPIO_INT_RISING, /**< Interrupt triggers when level is low */
GPIO_INT_BOTH /**< Interrupt triggers on either edge */
} gpio_int_pol_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize GPIO.
* @return #E_NO_ERROR if everything is successful.
*/
int GPIO_Init(void);
/**
* @brief Configure GPIO pin(s).
* @param cfg Pointer to configuration structure describing the pin.
* @return #E_NO_ERROR if everything is successful.
*/
int GPIO_Config(const gpio_cfg_t *cfg);
/**
* @brief Gets the pin(s) input state.
* @param cfg Pointer to configuration structure describing the pin.
* @return The requested pin state.
*/
uint32_t GPIO_InGet(const gpio_cfg_t *cfg);
/**
* @brief Sets the pin(s) to a high level output.
* @param cfg Pointer to configuration structure describing the pin.
*
*/
void GPIO_OutSet(const gpio_cfg_t *cfg);
/**
* @brief Clears the pin(s) to a low level output.
* @param cfg Pointer to configuration structure describing the pin.
*
*/
void GPIO_OutClr(const gpio_cfg_t *cfg);
/**
* @brief Gets the pin(s) output state.
* @param cfg Pointer to configuration structure describing the pin.
*
* @return The state of the requested pin.
*
*/
uint32_t GPIO_OutGet(const gpio_cfg_t *cfg);
/**
* @brief Write the pin(s) to a desired output level.
* @param cfg Pointer to configuration structure describing the pin.
* @param val Desired output level of the pin(s). This will be masked
* with the configuration mask.
*/
void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val);
/**
* @brief Toggles the the pin(s) output level.
* @param cfg Pointer to configuration structure describing the pin.
*
*/
void GPIO_OutToggle(const gpio_cfg_t *cfg);
/**
* @brief Configure GPIO interrupt(s)
* @param cfg Pointer to configuration structure describing the pin.
* @param mode Requested interrupt mode.
* @param pol Requested interrupt polarity.
* @return #E_NO_ERROR if everything is successful.
*/
int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol);
/**
* @brief Enables the specified GPIO interrupt
* @param cfg Pointer to configuration structure describing the pin.
*
*/
void GPIO_IntEnable(const gpio_cfg_t *cfg);
/**
* @brief Disables the specified GPIO interrupt.
* @param cfg Pointer to configuration structure describing the pin.
*/
void GPIO_IntDisable(const gpio_cfg_t *cfg);
/**
* @brief Gets the interrupt(s) status on a GPIO pin.
* @param cfg Pointer to configuration structure describing the pin
* for which the status is being requested.
* @return The requested interrupt status.
*/
uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg);
/**
* @brief Clears the interrupt(s) status on a GPIO pin.
* @param cfg Pointer to configuration structure describing the pin
* to clear the interrupt state of.
*/
void GPIO_IntClr(const gpio_cfg_t *cfg);
/**
* @brief Type alias for a GPIO callback function with prototype:
* @code
void callback_fn(void *cbdata);
* @endcode
* @param cbdata A void pointer to the data type as registered when
* GPIO_RegisterCallback() was called.
*/
typedef void (*gpio_callback_fn)(void *cbdata);
/**
* @brief Registers a callback for the interrupt on a given port and pin.
* @param cfg Pointer to configuration structure describing the pin
* @param callback A pointer to a function of type \c #gpio_callback_fn.
* @param cbdata The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs.
*
*/
void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata);
/**
* @brief GPIO IRQ Handler. @note If a callback is registered for a given
* interrupt, the callback function will be called.
*
* @param port number of the port that generated the interrupt service routine.
*
*/
void GPIO_Handler(unsigned int port);
/**@} end of group gpio */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_H_ */

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/**
* @file i2c.h
* @brief Inter-integrated circuit (I2C) communications interface driver.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-06-28 09:42:42 -0500 (Fri, 28 Jun 2019) $
* $Revision: 44330 $
*
*************************************************************************** */
#ifndef _I2C_H_
#define _I2C_H_
#include <stdint.h>
#include "i2c_regs.h"
#include "mxc_sys.h"
/**
* @defgroup i2c I2C
* @ingroup periphlibs
* @{
*/
/***** Definitions *****/
/// @brief I2C Speed Modes
typedef enum {
I2C_STD_MODE = 100000, //!< 100KHz Bus Speed
I2C_FAST_MODE = 400000, //!< 400KHz Bus Speed
I2C_FASTPLUS_MODE = 1000000, //!< 1MHz Bus Speed
I2C_HS_MODE = 3400000 //!< 3.4MHz Bus Speed
} i2c_speed_t;
//State for Master
typedef enum {
I2C_STATE_READING = 0,
I2C_STATE_WRITING = 1
} i2c_state_t;
// @brief Enable/Disable TXFIFO Autoflush mode
typedef enum {
I2C_AUTOFLUSH_ENABLE = 0,
I2C_AUTOFLUSH_DISABLE = 1
} i2c_autoflush_disable_t;
// @brief I2C Transaction request.
typedef struct i2c_req i2c_req_t;
struct i2c_req {
uint8_t addr; /**< @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
* Only supports 7-bit addressing. LSb of the given address
* will be used as the read/write bit, the @p addr <b>will
* not be shifted</b>. Used for <em>both master</em> and
* @em slave transactions. @endparblock
*/
const uint8_t *tx_data; ///< Data for mater write/slave read.
uint8_t *rx_data; ///< Data for master read/slave write.
unsigned tx_len; ///< Length of tx data.
unsigned rx_len; ///< Length of rx.
unsigned tx_num; ///< Number of tx bytes sent.
unsigned rx_num; ///< Number of rx bytes sent.
i2c_state_t state; ///< Read or Write.
/**
* @details 0 to send a stop bit at the end of the transaction,
otherwise send a restart. Only used in master trasnactions.
*/
int restart; /**< @parblock Restart or stop bit indicator.
* @arg 0 to send a stop bit at the end of the transaction
* @arg Non-zero to send a restart at end of the transaction
* @note Only used for Master transactions.
* @endparblock
*/
i2c_autoflush_disable_t sw_autoflush_disable; ///< Enable/Disable autoflush.
/**
* @brief Callback for asynchronous request.
* @param i2c_req_t* Pointer to the transaction request.
* @param int Error code.
*/
void (*callback)(i2c_req_t*, int);
};
/***** Function Prototypes *****/
/**
* @brief Initialize and enable I2C.
* @param i2c Pointer to I2C peripheral registers.
* @param i2cspeed desired speed (I2C mode)
* @param sys_cfg System configuration object
* @returns \c #E_NO_ERROR if everything is successful,
* @ref MXC_Error_Codes if an error occurred.
*/
int I2C_Init(mxc_i2c_regs_t * i2c, i2c_speed_t i2cspeed, const sys_cfg_i2c_t* sys_cfg);
/**
* @brief Shutdown I2C module.
* @param i2c Pointer to the I2C registers.
* @returns #E_NO_ERROR I2C shutdown successfully, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int I2C_Shutdown(mxc_i2c_regs_t *i2c);
/**
* @brief Master write data. Will block until transaction is complete.
* @param i2c Pointer to I2C regs.
* @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
* Only supports 7-bit addressing. LSb of the given address
* will be used as the read/write bit, the \p addr <b>will
* not be shifted</b>. Used for <em>both master</em> and
* @em slave transactions. @endparblock
* @param data Data to be written.
* @param len Number of bytes to Write.
* @param restart 0 to send a stop bit at the end of the transaction,
otherwise send a restart.
* @returns Bytes transacted if everything is successful,
* @ref MXC_Error_Codes if an error occurred.
*/
int I2C_MasterWrite(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* data, int len, int restart);
/**
* @brief Master read data. Will block until transaction is complete.
* @param i2c Pointer to I2C regs.
* @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
* Only supports 7-bit addressing. LSb of the given address
* will be used as the read/write bit, the @p addr <b>will
* not be shifted</b>. Used for <em>both master</em> and
* @em slave transactions. @endparblock
* @param data Data to be written.
* @param len Number of bytes to Write.
* @param restart 0 to send a stop bit at the end of the transaction,
otherwise send a restart.
* @returns Bytes transacted if everything is successful, @ref MXC_Error_Codes if an error occurred.
*/
int I2C_MasterRead(mxc_i2c_regs_t *i2c, uint8_t addr, uint8_t* data, int len, int restart);
/**
* @brief Slave read data. Will block until transaction is complete.
* @param i2c Pointer to I2C regs.
* @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1.
* Only supports 7-bit addressing. LSb of the given address
* will be used as the read/write bit, the @p addr <b>will
* not be shifted</b>. Used for <em>both master</em> and
* @em slave transactions. @endparblock
* @param read_data Buffer that the master will read from.
* @param read_len Number of bytes the master can read.
* @param write_data Buffer that the master will write to.
* @param write_len Number of bytes the master can write.
* @param tx_num Number of bytes transmitted by the slave.
* @param rx_num Number of bytes received by the slave.
* @param sw_autoflush_disable TX Autoflush enabled by default.Set this bit to disable autoflush manually.
* @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
*/
int I2C_Slave(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* read_data,
int read_len, uint8_t* write_data, int write_len, int* tx_num,
int* rx_num, i2c_autoflush_disable_t sw_autoflush_disable);
/**
* @brief Master Read and Write Asynchronous.
* @param i2c Pointer to I2C regs.
* @param req Request for an I2C transaction.
* @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
*/
int I2C_MasterAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req);
/**
* @brief Slave Read and Write Asynchronous.
* @param i2c Pointer to I2C regs.
* @param req Request for an I2C transaction.
* @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred.
*/
int I2C_SlaveAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req);
/**
* @brief I2C interrupt handler.
* @details This function should be called by the application from the interrupt
* handler if I2C interrupts are enabled. Alternately, this function
* can be periodically called by the application if I2C interrupts are
* disabled.
* @param i2c Base address of the I2C module.
*/
void I2C_Handler(mxc_i2c_regs_t *i2c);
/**
* @brief Drain all of the data in the RXFIFO.
* @param i2c Pointer to I2C regs.
*/
void I2C_DrainRX(mxc_i2c_regs_t *i2c);
/**
* @brief Drain all of the data in the TXFIFO.
* @param i2c Pointer to I2C regs.
*/
void I2C_DrainTX(mxc_i2c_regs_t *i2c);
/**
* @brief Abort Async request based on the request you want to abort.
* @param req Pointer to I2C Transaction.
*/
int I2C_AbortAsync(i2c_req_t *req);
/**
* @brief Enable and Set Timeout
*
* @param i2c pointer to I2C regs
* @param[in] us micro seconds to delay
*
* @return E_NO_ERROR or E_BAD_PARAM if delay is to long.
*/
int I2C_SetTimeout(mxc_i2c_regs_t *i2c, int us);
/**
* @brief clear and disable timeout
*
* @param i2c pointer to I2C regs
*/
void I2C_ClearTimeout(mxc_i2c_regs_t *i2c);
/**@} end of group i2c */
#endif /* _I2C_H_ */

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/**
* @file i2s.h
* @brief I2S (Inter-Integrated Sound) driver function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
#ifndef _I2S_H_
#define _I2S_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "dma.h"
#include "spimss_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup i2s Inter-Integrated Sound (I2S)
* @ingroup spi
* @{
*/
/* **** Definitions **** */
/** @brief I2S audio directions */
typedef enum {
AUDIO_OUT = 1,
AUDIO_IN = 2,
} i2s_direction_t;
/** @brief I2S Configuration Struct */
typedef struct {
uint8_t left_justify;
uint8_t mono_audio;
i2s_direction_t audio_direction;
unsigned int sample_rate;
unsigned int start_immediately;
void *dma_src_addr;
void *dma_dst_addr;
unsigned int dma_cnt;
unsigned int dma_reload_en;
} i2s_cfg_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize I2S resources
* @param cfg I2S Configuration Struct
* @param dma_ctz_cb Optional function to be called when the DMA completes
a transfer. Set to NULL if unused.
* @param sys_cfg_i2s System configuration object
* @details This initialization is required before using the I2S driver functions.
* @return \c #E_NO_ERROR if successful
*/
int I2S_Init(const i2s_cfg_t *cfg, void (*dma_ctz_cb)(int, int), const sys_cfg_i2s_t* sys_cfg_i2s);
/**
* @brief Release I2S
* @details De-configures the I2S protocol and stops DMA request
* @return \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise
*/
int I2S_Shutdown(void);
/**
* @brief Mute I2S Output
* @details Sets I2S data to zero, continues sending clock and accessing DMA
* @return \c #E_NO_ERROR
*/
int I2S_Mute(void);
/**
* @brief Unmute I2S Output
* @details Restores I2S data
* @return \c #E_NO_ERROR
*/
int I2S_Unmute(void);
/**
* @brief Pause I2S Output
* @details Similar to mute, but stops FIFO and DMA access, clocks continue
* @return \c #E_NO_ERROR
*/
int I2S_Pause(void);
/**
* @brief Unpause I2S Output
* @details Similar to mute, but restarts FIFO and DMA access
* @return \c #E_NO_ERROR
*/
int I2S_Unpause(void);
/**
* @brief Stops I2S Output
* @details Similar to pause, but also halts clock
* @return \c #E_NO_ERROR
*/
int I2S_Stop(void);
/**
* @brief Starts I2S Output
* @details Starts I2S Output, automatically called by configure if requested
* @return \c #E_NO_ERROR
*/
int I2S_Start(void);
/**
* @brief Clears DMA Interrupt Flags
* @details Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb
* @return \c #E_NO_ERROR
*/
int I2S_DMA_ClearFlags(void);
/**
* @brief Set DMA Addr (Source or Dest) and bytes to transfer
* @param src_addr The address to read data from (Audio Out)
* @param dst_addr The address to write data to (Audio In)
* @param count The length of the transfer in bytes
* @details Sets the address to read/write data in memory and the length of
* the transfer. The unused addr parameter is ignored.
* @return \c #E_NO_ERROR
*/
int I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count);
/**
* @brief Sets the DMA reload address and count
* @param src_addr The address to read data from (Audio Out)
* @param dst_addr The address to write data to (Audio In)
* @param count The length of the transfer in bytes
* @details If DMA reload is enabled, when the DMA has transfered $count bytes
* (a CTZ event occurs) the src, dst, and count registers will be
* set to these. The DMA reload flag clears after a reload occurs.
* @return \c #E_NO_ERROR
*/
int I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count);
/**@} end of group i2s */
#ifdef __cplusplus
}
#endif
#endif /* _I2S_H_ */

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/**
* @file icc.h
* @brief Instruction Controller Cache(ICC) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _ICC_H_
#define _ICC_H_
/* **** Includes **** */
#include <stdint.h>
#include "icc_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup icc Internal Cache Controller (ICC)
* @ingroup periphlibs
* @{
*/
/**
* @brief Enumeration type for the Cache ID Register
*/
typedef enum {
ICC_CACHE_ID_RELNUM, // Identifies the RTL release version
ICC_CACHE_ID_PARTNUM, // Specifies the value of C_ID Port Number
ICC_CACHE_ID_CCHID // Specifies the value of Cache ID
} icc_cache_id_t;
/**
* @brief Reads the data from the Cache Id Register.
* @param cid Enumeration type for Cache Id Register.
* @retval Returns the contents of Cache Id Register.
*/
int ICC_ID(icc_cache_id_t cid);
/**
* @brief Enable the instruction cache controller.
*/
void ICC_Enable(void);
/**
* @brief Disable the instruction cache controller.
*/
void ICC_Disable(void);
/**
* @brief Flush the instruction cache controller.
*/
void ICC_Flush(void);
/**@} end of group icc */
#ifdef __cplusplus
}
#endif
#endif /* _ICC_H_ */

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/**
* @file lp.h
* @brief Low power function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $
* $Revision: 38105 $
*
*************************************************************************** */
// Define to prevent redundant inclusion
#ifndef _LP_H_
#define _LP_H_
/***** Includes *****/
#include "gpio.h"
#include "pwrseq_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
typedef enum {
LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */
LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */
LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */
} lp_ovr_t;
/**
* @brief Clears the low power wakeup flags
*/
void LP_ClearWakeStatus(void);
/**
* @brief Enables power to RAM addresses 0x20010000-0x20017FFF.
*/
void LP_EnableSRAM3(void);
/**
* @brief Enables power to RAM addresses 0x20008000-0x2000FFFF.
*/
void LP_EnableSRAM2(void);
/**
* @brief Enables power to RAM addresses 0x20004000-0x20007FFF.
*/
void LP_EnableSRAM1(void);
/**
* @brief Enables power to RAM addresses 0x20000000-0x20003FFF.
*/
void LP_EnableSRAM0(void);
/**
* @brief Disables power to RAM addresses 0x20010000-0x20017FFF. The contents of the RAM are destroyed.
*/
void LP_DisableSRAM3(void);
/**
* @brief Disables power to RAM addresses 0x20008000-0x2000FFFF. The contents of the RAM are destroyed.
*/
void LP_DisableSRAM2(void);
/**
* @brief Disables power to RAM addresses 0x20004000-0x20007FFF. The contents of the RAM are destroyed.
*/
void LP_DisableSRAM1(void);
/**
* @brief Disables power to RAM addresses 0x20000000-0x20003FFF. The contents of the RAM are destroyed.
*/
void LP_DisableSRAM0(void);
/**
* @brief Places the instruction cache in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableICacheLightSleep(void);
/**
* @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableSysRAM3LightSleep(void);
/**
* @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableSysRAM2LightSleep(void);
/**
* @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableSysRAM1LightSleep(void);
/**
* @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained.
*/
void LP_EnableSysRAM0LightSleep(void);
/**
* @brief Places the instruction cache in active mode.
*/
void LP_DisableICacheLightSleep(void);
/**
* @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in active mode.
*/
void LP_DisableSysRAM3LightSleep(void);
/**
* @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in active mode.
*/
void LP_DisableSysRAM2LightSleep(void);
/**
* @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in active mode.
*/
void LP_DisableSysRAM1LightSleep(void);
/**
* @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in active mode.
*/
void LP_DisableSysRAM0LightSleep(void);
/**
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
* Call this function multiple times to enable pins on multiple ports. This function does not configure
* the GPIO pins nor does it setup their interrupt functionality.
* @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored.
*/
void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins);
/**
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
* Call this function multiple times to disable pins on multiple ports.
* @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the
* structure are used. The func and pad fields are ignored.
*/
void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins);
/**
* @brief Enables the RTC alarm to wake up the device from any low power mode.
*/
void LP_EnableRTCAlarmWakeup(void);
/**
* @brief Disables the RTC alarm from waking up the device.
*/
void LP_DisableRTCAlarmWakeup(void);
/**
* @brief Places the device into SLEEP mode. This function returns once any interrupt occurs.
* @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void LP_EnterSleepMode(void);
/**
* @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur.
* @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void LP_EnterDeepSleepMode(void);
/**
* @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC or external interrupt occur.
* @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again
*/
void LP_EnterBackupMode(void);
/**
* @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns.
* Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur.
*/
void LP_EnterShutDownMode(void);
/**
* @brief Set operating voltage and change the clock to match the new voltage.
* @param system reset configuration struct
*/
void LP_SetOperatingVoltage(lp_ovr_t ovr);
/**
* @brief Enables Data Retention to RAM addresses 0x20000000-0x20003FFF.
*/
void LP_EnableSRamRet0(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20000000-0x20003FFF.
*/
void LP_DisableSRamRet0(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20004000-0x20007FFF.
*/
void LP_EnableSRamRet1(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20004000-0x20007FFF.
*/
void LP_DisableSRamRet1(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
*/
void LP_EnableSRamRet2(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20008000-0x2000FFFF.
*/
void LP_DisableSRamRet2(void);
/**
* @brief Enables Data Retention to RAM addresses 0x20010000-0x20017FFF.
*/
void LP_EnableSRamRet3(void);
/**
* @brief Disables Data Retention to RAM addresses 0x20010000-0x20017FFF.
*/
void LP_DisableSRamRet3(void);
/**
* @brief Enables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time.
*/
void LP_EnableBlockDetect(void);
/**
* @brief Disables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time
*/
void LP_DisableBlockDetect(void);
/**
* @brief RAM Retention Regulator Enable for BACKUP Mode
*/
void LP_EnableRamRetReg(void);
/**
* @brief RAM Retention Regulator Disabels for BACKUP Mode
*/
void LP_DisableRamRetReg(void);
/**
* @brief Enables Fast wake up from deepsleep
*/
void LP_EnableFastWk(void);
/**
* @brief Disables Fast wake up from deepsleep
*/
void LP_DisableFastWk(void);
/**
* @brief Turns on band gap during deepsleep and backup mode.
*/
void LP_EnableBandGap(void);
/**
* @brief Turns off band gap during deepsleep and backup mode.
*/
void LP_DisableBandGap(void);
/**
* @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void LP_EnableVCorePORSignal(void);
/**
* @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void LP_DisableVCorePORSignal(void);
/**
* @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void LP_EnableLDO(void);
/**
* @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode
*/
void LP_DisableLDO(void);
/**
* @brief Enables V CORE Supply Voltage Monitor
*/
void LP_EnableVCoreSVM(void);
/**
* @brief Disables V CORE Supply Voltage Monitor
*/
void LP_DisableVCoreSVM(void);
/**
* @brief Enables VDDIO Power-On-Reset Monitor
*/
void LP_EnableVDDIOPorMonitor(void);
/**
* @brief Disables VDDIO Power-On-Reset Monitor
*/
void LP_DisableVDDIOPorMonitor(void);
#ifdef __cplusplus
}
#endif
#endif /* _LP_H_ */

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/**
* @file
* @brief Assertion checks for debugging.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_ASSERT_H_
#define _MXC_ASSERT_H_
/* **** Includes **** */
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup syscfg
* @defgroup mxc_assertions Assertion Checks for Debugging
* @brief Assertion checks for debugging.
* @{
*/
/* **** Definitions **** */
/**
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
///@cond
#ifdef MXC_ASSERT_ENABLE
/**
* Macro that checks the expression for true and generates an assertion.
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
#define MXC_ASSERT(expr) \
if (!(expr)) \
{ \
mxc_assert(#expr, __FILE__, __LINE__); \
}
/**
* Macro that generates an assertion with the message "FAIL".
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__);
#else
#define MXC_ASSERT(expr)
#define MXC_ASSERT_FAIL()
#endif
///@endcond
/* **** Globals **** */
/* **** Function Prototypes **** */
/**
* @brief Assert an error when the given expression fails during debugging.
* @param expr String with the expression that failed the assertion.
* @param file File containing the failed assertion.
* @param line Line number for the failed assertion.
* @note This is defined as a weak function and can be overridden at the
* application layer to print the debugging information.
* @code
* printf("%s, file: %s, line %d\n", expr, file, line);
* @endcode
* @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be
* defined.
*/
void mxc_assert(const char *expr, const char *file, int line);
/**@} end of group MXC_Assertions*/
#ifdef __cplusplus
}
#endif
#endif /* _MXC_ASSERT_H_ */

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/**
* @file mxc_config.h
* @brief Top-level include file for device configuration.
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
******************************************************************************/
#ifndef _MXC_CONFIG_H
#define _MXC_CONFIG_H
#if !defined __GNUC__
#include "RTE_Components.h"
#endif /* not __GNUC__ */
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_pins.h"
#endif /* _CONFIG_H */

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/**
* @file
* @brief Asynchronous delay routines based on the SysTick Timer.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-11-05 09:52:05 -0600 (Mon, 05 Nov 2018) $
* $Revision: 38934 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _DELAY_H_
#define _DELAY_H_
/**
* @defgroup MXC_delay Delay Utility Functions
* @ingroup devicelibs
* @brief Asynchronous delay routines based on the SysTick Timer
* @{
*/
/***** Definitions *****/
/**
* Macro used to specify a microsecond timing parameter in seconds.
* \code
* x = SEC(3) // 3 seconds -> x = 3,000,000
* \endcode
*/
#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL)
/**
* Macro used to specify a microsecond timing parameter in milliseconds.
* \code
* x = MSEC(3) // 3ms -> x = 3,000
* \endcode
*/
#define MXC_DELAY_MSEC(ms) (ms * 1000UL)
/**
* Macro used to specify a microsecond timing parameter.
* \code
* x = USEC(3) // 3us -> x = 3
* \endcode
*/
#define MXC_DELAY_USEC(us) (us)
/***** Function Prototypes *****/
/**
* @brief Blocks and delays for the specified number of microseconds.
* @details Uses the SysTick to create the requested delay. If the SysTick is
* running, the current settings will be used. If the SysTick is not
* running, it will be started.
* @param us microseconds to delay
* @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int mxc_delay(unsigned long us);
/**
* @brief Starts a non-blocking delay for the specified number of
* microseconds.
* @details Uses the SysTick to time the requested delay. If the SysTick is
* running, the current settings will be used. If the SysTick is not
* running, it will be started.
* @note mxc_delay_handler() must be called from the SysTick interrupt service
* routine or at a rate greater than the SysTick overflow rate.
* @param us microseconds to delay
* @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another
* delay request.
*/
int mxc_delay_start(unsigned long us);
/**
* @brief Returns the status of a non-blocking delay request
* @pre Start the asynchronous delay by calling mxc_delay_start().
* @return #E_BUSY until the requested delay time has expired.
*/
int mxc_delay_check(void);
/**
* @brief Stops an asynchronous delay previously started.
* @pre Start the asynchronous delay by calling mxc_delay_start().
*/
void mxc_delay_stop(void);
/**
* @brief Processes the delay interrupt.
* @details This function must be called from the SysTick IRQ or polled at a
* rate greater than the SysTick overflow rate.
*/
void mxc_delay_handler(void);
/**@} end of group MXC_delay */
#endif /* _DELAY_H_ */

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/**
* @file
* @brief List of common error return codes for Maxim Integrated libraries.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_ERRORS_H_
#define _MXC_ERRORS_H_
/**
* @ingroup syscfg
* @defgroup MXC_Error_Codes Error Codes
* @brief A list of common error codes used by the API.
* @note A Negative Error Convention is used to avoid conflict with
* positive, Non-Error, returns.
* @{
*/
/** No Error */
#define E_NO_ERROR 0
/** No Error, success */
#define E_SUCCESS 0
/** Pointer is NULL */
#define E_NULL_PTR -1
/** No such device */
#define E_NO_DEVICE -2
/** Parameter not acceptable */
#define E_BAD_PARAM -3
/** Value not valid or allowed */
#define E_INVALID -4
/** Module not initialized */
#define E_UNINITIALIZED -5
/** Busy now, try again later */
#define E_BUSY -6
/** Operation not allowed in current state */
#define E_BAD_STATE -7
/** Generic error */
#define E_UNKNOWN -8
/** General communications error */
#define E_COMM_ERR -9
/** Operation timed out */
#define E_TIME_OUT -10
/** Expected response did not occur */
#define E_NO_RESPONSE -11
/** Operations resulted in unexpected overflow */
#define E_OVERFLOW -12
/** Operations resulted in unexpected underflow */
#define E_UNDERFLOW -13
/** Data or resource not available at this time */
#define E_NONE_AVAIL -14
/** Event was shutdown */
#define E_SHUTDOWN -15
/** Event was aborted */
#define E_ABORT -16
/** The requested operation is not supported */
#define E_NOT_SUPPORTED -17
/**@} end of MXC_Error_Codes group */
#endif /* _MXC_ERRORS_H_ */

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/**
* @file
* @brief Exclusive access lock utility functions.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_LOCK_H_
#define _MXC_LOCK_H_
/* **** Includes **** */
#include "mxc_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup syscfg
* @defgroup mxc_lock_utilities Exclusive Access Locks
* @brief Lock functions to obtain and release a variable for exclusive
* access. These functions are marked interrupt safe if they are
* interrupt safe.
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
/* **** Function Prototypes **** */
/**
* @brief Attempts to acquire the lock.
* @details This in an interrupt safe function that can be used as a mutex.
* The lock variable must remain in scope until the lock is
* released. Will not block if another thread has already acquired
* the lock.
* @param lock Pointer to variable that is used for the lock.
* @param value Value to be place in the lock. Can not be 0.
*
* @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken.
*/
int mxc_get_lock(uint32_t *lock, uint32_t value);
/**
* @brief Free the given lock.
* @param[in,out] lock Pointer to the variable used for the lock. When the lock
* is free, the value pointed to by @p lock is set to zero.
*/
void mxc_free_lock(uint32_t *lock);
/**@} end of group mxc_lock_utilities */
#ifdef __cplusplus
}
#endif
#endif /* _MXC_LOCK_H_ */

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/**
* @file mxc_pins.h
* @brief This file contains constant pin configurations for the peripherals.
*/
/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
**************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_PINS_H_
#define _MXC_PINS_H_
/* **** Includes **** */
#include "gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
/* **** Global Variables **** */
// Predefined GPIO Configurations
/***** @brief TIMER pins *****/
extern const gpio_cfg_t gpio_cfg_tmr0;
/***** @brief UART pins *****/
extern const gpio_cfg_t gpio_cfg_uart0rtscts;
extern const gpio_cfg_t gpio_cfg_uart0a;
extern const gpio_cfg_t gpio_cfg_uart1rtscts;
extern const gpio_cfg_t gpio_cfg_uart1a;
extern const gpio_cfg_t gpio_cfg_uart1b;
extern const gpio_cfg_t gpio_cfg_uart1c;
extern const gpio_cfg_t gpio_cfg_uart2;
/***** @brief I2C pins *****/
extern const gpio_cfg_t gpio_cfg_i2c0;
extern const gpio_cfg_t gpio_cfg_i2c1;
/***** @brief SPI/I2S pins *****/
extern const gpio_cfg_t gpio_cfg_spi17y; // SPI0A
extern const gpio_cfg_t gpio_cfg_spimss1a; // SPI1A
extern const gpio_cfg_t gpio_cfg_spimss1b; // SPI1B
extern const gpio_cfg_t gpio_cfg_i2s1a; // same port as SPI1A
extern const gpio_cfg_t gpio_cfg_i2s1b; // same port as SPI1B
/***** @brief SWD pins *****/
extern const gpio_cfg_t gpio_cfg_swd;
/***** @brief RTC pins *****/
extern const gpio_cfg_t gpio_cfg_rtc;
#ifdef __cplusplus
}
#endif
#endif /* _MXC_PINS_H_ */

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/**
* @file
* @brief System level header file.
*/
/*******************************************************************************
* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-04-15 09:35:40 -0500 (Mon, 15 Apr 2019) $
* $Revision: 42499 $
*
******************************************************************************/
#ifndef _MXC_SYS_H_
#define _MXC_SYS_H_
#include "mxc_config.h"
#include "uart_regs.h"
#include "i2c_regs.h"
#include "gcr_regs.h"
#include "tmr_regs.h"
#include "icc_regs.h"
#include "spi17y_regs.h"
#include "spimss_regs.h"
#include "gpio.h"
#include "flc_regs.h"
#include "dma.h"
#include "wdt_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __CC_ARM ) /* Suppressing the warning: "enum value is out of range of int" for Keil */
#pragma push
#pragma diag_suppress 66
#endif /* __CC_ARM */
/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */
typedef enum {
SYS_RESET0_DMA = MXC_F_GCR_RSTR0_DMA, /**< Reset DMA */
SYS_RESET0_WDT = MXC_F_GCR_RSTR0_WDT, /**< Reset WDT */
SYS_RESET0_GPIO0 = MXC_F_GCR_RSTR0_GPIO0, /**< Reset GPIO0 */
SYS_RESET0_TIMER0 = MXC_F_GCR_RSTR0_TIMER0, /**< Reset TIMER0 */
SYS_RESET0_TIMER1 = MXC_F_GCR_RSTR0_TIMER1, /**< Reset TIMER1 */
SYS_RESET0_TIMER2 = MXC_F_GCR_RSTR0_TIMER2, /**< Reset TIMER2 */
SYS_RESET0_UART0 = MXC_F_GCR_RSTR0_UART0, /**< Reset UART0 */
SYS_RESET0_UART1 = MXC_F_GCR_RSTR0_UART1, /**< Reset UART1 */
SYS_RESET0_SPI0 = MXC_F_GCR_RSTR0_SPI0, /**< Reset SPI0 */
SYS_RESET0_SPI1 = MXC_F_GCR_RSTR0_SPI1, /**< Reset SPI1 */
SYS_RESET0_I2C0 = MXC_F_GCR_RSTR0_I2C0, /**< Reset I2C0 */
SYS_RESET0_RTC = MXC_F_GCR_RSTR0_RTC, /**< Reset RTC */
SYS_RESET0_SRST = MXC_F_GCR_RSTR0_SRST, /**< Soft reset */
SYS_RESET0_PRST = MXC_F_GCR_RSTR0_PRST, /**< Peripheral reset */
SYS_RESET0_SYSTEM = MXC_F_GCR_RSTR0_SYSTEM, /**< System reset */
} sys_reset0_t;
/** @brief System reset1 enumeration. Used in SYS_PeriphReset1 function */
typedef enum {
SYS_RESET1_I2C1 = MXC_F_GCR_RSTR1_I2C1, /**< Reset I2C1 */
} sys_reset1_t;
/** @brief System clock disable enumeration. Used in SYS_ClockDisable and SYS_ClockEnable functions */
typedef enum {
SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PERCKCN0_GPIO0D, /**< Disable MXC_F_GCR_PERCKCN0_GPIO0D clock */
SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PERCKCN0_DMAD, /**< Disable MXC_F_GCR_PERCKCN0_DMAD clock */
SYS_PERIPH_CLOCK_SPI17Y = MXC_F_GCR_PERCKCN0_SPI0D, /**< Disable MXC_F_GCR_PERCKCN0_SPI0D clock */
SYS_PERIPH_CLOCK_SPIMSS = MXC_F_GCR_PERCKCN0_SPI1D, /**< Disable MXC_F_GCR_PERCKCN0_SPI1D clock */
SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PERCKCN0_UART0D, /**< Disable MXC_F_GCR_PERCKCN0_UART0D clock */
SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PERCKCN0_UART1D, /**< Disable MXC_F_GCR_PERCKCN0_UART1D clock */
SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PERCKCN0_I2C0D, /**< Disable MXC_F_GCR_PERCKCN0_I2C0D clock */
SYS_PERIPH_CLOCK_T0 = MXC_F_GCR_PERCKCN0_T0D, /**< Disable MXC_F_GCR_PERCKCN0_T0D clock */
SYS_PERIPH_CLOCK_T1 = MXC_F_GCR_PERCKCN0_T1D, /**< Disable MXC_F_GCR_PERCKCN0_T1D clock */
SYS_PERIPH_CLOCK_T2 = MXC_F_GCR_PERCKCN0_T2D, /**< Disable MXC_F_GCR_PERCKCN0_T2D clock */
SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PERCKCN0_I2C1D, /**< Disable MXC_F_GCR_PERCKCN0_I2C1D clock */
} sys_periph_clock_t;
/** @brief Clock source */
typedef enum {
SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */
SYS_CLOCK_HFXIN = MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */
SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/
SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */
} sys_system_clock_t;
typedef void* sys_cfg_t;
typedef sys_cfg_t sys_cfg_i2c_t;
typedef sys_cfg_t sys_cfg_flc_t;
typedef sys_cfg_t sys_cfg_wdt_t;
/** @brief Map control */
typedef enum {
MAP_A,
MAP_B,
MAP_C,
} sys_map_t;
/** @brief UART Flow control */
typedef enum {
UART_FLOW_DISABLE,
UART_FLOW_ENABLE,
} sys_uart_flow_t;
/** @brief UART system configuration object */
typedef struct {
sys_map_t map;
sys_uart_flow_t flow_flag;
} sys_cfg_uart_t;
/** @brief SPI17Y system configuration object */
typedef struct {
sys_map_t map;
} sys_cfg_spi17y_t;
/** @brief SPIMSS system configuration object */
typedef struct {
sys_map_t map;
} sys_cfg_spimss_t;
/** @brief I2S system configuration object */
typedef struct {
sys_map_t map;
dma_reqsel_t dma_reqsel_tx;
dma_reqsel_t dma_reqsel_rx;
} sys_cfg_i2s_t;
/** @brief TIMER system configuration object */
typedef struct {
int out_en;
} sys_cfg_tmr_t;
/** @brief Real Time Clock system configuration object */
typedef struct {
mxc_tmr_regs_t* tmr;
} sys_cfg_rtc_t;
/** @brief Pulse Train System Configuration Object */
typedef gpio_cfg_t sys_cfg_pt_t;
#if defined ( __CC_ARM ) /* Restore the warning: "enum is out of int range" for Keil */
#pragma pop
#endif /* __CC_ARM */
/***** Function Prototypes *****/
/**
* @brief Selects the system clock and enables it once ready
* @param clock Enumeration for desired clock.
* @param tmr Optional tmr pointer for timeout. NULL if undesired.
*
* @returns #E_NO_ERROR is clock is succesfully selected
*/
int SYS_Clock_Select(sys_system_clock_t clock, mxc_tmr_regs_t* tmr);
/**
* @brief Enables the selected peripheral clock.
* @param clock Enumeration for desired clock.
*/
void SYS_ClockEnable(sys_periph_clock_t clock);
/**
* @brief Disables the selected peripheral clock.
* @param clock Enumeration for desired clock.
*/
void SYS_ClockDisable(sys_periph_clock_t clock);
/**
* @brief Enables the external 32k oscillator.
* @param sys_cfg system configuration object
*
* @returns #E_NO_ERROR is successful, appropriate error otherwise
*/
int SYS_ClockEnable_X32K(sys_cfg_rtc_t *sys_cfg);
/**
* @brief Disables the external 32k oscillator.
*
* @returns #E_NO_ERROR is successful, appropriate error otherwise
*/
int SYS_ClockDisable_X32K(void);
/**
* @brief System level initialization for UART module.
* @param uart Pointer to UART module registers
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_UART_Init(mxc_uart_regs_t *uart, const sys_cfg_uart_t* sys_cfg);
/**
* @brief System level shutdown for UART module
* @param uart Pointer to UART module registers
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_UART_Shutdown(mxc_uart_regs_t *uart);
/**
* @brief System level initialization for I2C module.
* @param i2c Pointer to I2C module registers
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_I2C_Init(mxc_i2c_regs_t *i2c, const sys_cfg_i2c_t* sys_cfg);
/**
* @brief System level Shutdown for I2C module.
* @param i2c Pointer to I2C module registers
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_I2C_Shutdown(mxc_i2c_regs_t *i2c);
/**
* @brief Init DMA system settings
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_DMA_Init(void);
/**
* @brief Shutdown DMA system specific settings
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_DMA_Shutdown(void);
/**
* @brief Get the frequency of the I2C module source clock
* @param spim Unused, pointer to I2C module registers
*
* @returns frequency in Hz
*/
unsigned SYS_I2C_GetFreq(mxc_i2c_regs_t *i2c);
/**
* @brief Get the frequency of the Timer module source clock.
* @params tmr Unused, pointer to timer module registers
*
* @returns frequency in Hz
*/
unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr);
/**
* @brief Reset the peripherals and/or CPU in the rstr0 register.
* @param Enumeration for what to reset. Can reset multiple items at once.
*/
void SYS_Reset0(sys_reset0_t reset);
/**
* @brief Reset the peripherals and/or CPU in the rstr1 register.
* @param Enumeration for what to reset. Can reset multiple items at once.
*/
void SYS_Reset1(sys_reset1_t reset);
/**
* @brief Clear Cache and Line buffer.
*/
void SYS_Flash_Operation(void);
/**
* @brief Init TMR system settings
* @param tmr Pointer to timer module registers
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t* sys_cfg);
/**
* @brief Init flash system settings
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg);
/**
* @brief Shutdown flash system specific settings
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_FLC_Shutdown(void);
/**
* @brief System level initialization for SPI17Y module.
* @param spi pointer to spi module registers
* @param sys_cfg System configuration object
*
* @returns E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_SPI17Y_Init( mxc_spi17y_regs_t *spi, const sys_cfg_spi17y_t* sys_cfg);
/**
* @brief System level shutdown for SPI17Y module
* @param pointer to spi module registers
*
* @returns E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi);
/**
* @brief System level initialization for SPIMSS module.
* @param spi pointer to spi module registers
* @param sys_cfg System configuration object
*
* @returns E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_SPIMSS_Init(mxc_spimss_regs_t *spi, const sys_cfg_spimss_t* sys_cfg);
/**
* @brief System level shutdown for SPIMSS module
* @param pointer to spi module registers
*
* @returns E_NO_ERROR if everything is successful
*/
int SYS_SPIMSS_Shutdown(mxc_spimss_regs_t *spi);
/**
* @brief Shutdown Timer system specific settings
* @param tmr pointer to timer module registers
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_TMR_Shutdown(mxc_tmr_regs_t *tmr);
/**
* @brief System level initialization for I2S Module
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_I2S_Init(const sys_cfg_i2s_t* sys_cfg);
/**
* @brief System level shutdown of I2S module
*
* @returns #E_NO_ERROR if everything is successful
*/
int SYS_I2S_Shutdown(void);
/**
* @brief Get the frequency of the I2S module source clock
* @param spimss Pointer to I2S module registers
*
* @returns frequency in Hz
*/
int SYS_I2S_GetFreq(mxc_spimss_regs_t *spimss);
/**
* @brief Init system settings for RTC square wave output.
* @param sys_cfg System configuration object
*
* @returns #E_NO_ERROR if successful, appropriate error otherwise
*/
int SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg);
/**
* @brief System Tick Configuration Helper
*
* The function enables selection of the external clock source for
* the System Tick Timer. It initializes the System Timer and its
* interrupt, and starts the System Tick Timer. Counter is in free
* running mode to generate periodic interrupts.
*
* @param ticks Number of ticks between two interrupts.
* @param clk_src Selects between default SystemClock or External Clock.
* - 0 Use external clock source
* @param tmr Optional tmr pointer for timeout. NULL if undesired.
* - 1 SystemClock
*
* @return #E_NO_ERROR Function succeeded, of #E_INVALID if an invalid value is requested
*/
int SYS_SysTick_Config(uint32_t ticks, int clk_src, mxc_tmr_regs_t* tmr);
/**
* @brief Disable System Tick timer
*/
void SYS_SysTick_Disable(void);
/**
* @brief Delay a requested number of SysTick Timer Ticks.
* @param ticks Number of System Ticks to delay.
* @note This delay function is based on the clock used for the SysTick
* timer if the SysTick timer is enabled. If the SysTick timer is
* not enabled, the current SysTick registers are saved and the
* timer will use the SystemClock as the source for the delay. The
* delay is measured in clock ticks and is not based on the SysTick
* interval.
*
* @return #E_NO_ERROR if everything is successful
*/
int SYS_SysTick_Delay(uint32_t ticks);
/**
* @brief Get the frequency of the SysTick Timer
*
* @return frequency in Hz
*/
uint32_t SYS_SysTick_GetFreq(void);
/**
* @brief Delay a requested number of microseconds.
* @param us Number of microseconds to delay.
* @note Calls SYS_SysTick_Delay().
*/
void SYS_SysTick_DelayUs(uint32_t us);
/**
* @brief Init WDT system settings
* @param wdt watchdog registers
* @param sys_cfg System configuration object
*/
int SYS_WDT_Init(mxc_wdt_regs_t* wdt, const sys_cfg_wdt_t* sys_cfg);
#ifdef __cplusplus
}
#endif
#endif /* _MXC_SYS_H_*/

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/**
* @file nvic_table.h
* @brief Interrupt vector table manipulation functions.
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2020-04-20 15:48:35 -0500 (Mon, 20 Apr 2020) $
* $Revision: 53144 $
*
******************************************************************************/
#ifndef _NVIC_TABLE_H
#define _NVIC_TABLE_H
#include "mxc_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup syscfg
* @defgroup nvic NVIC Table
* @brief functions handling the nvic table.
* @{
*/
/**
* @brief Set an IRQ hander callback function. If the IRQ table is in
* flash, this will copy it to RAM and set NVIC to RAM based table.
*
* @param irqn ARM external IRQ number
* @param irq_callback Function to be called at IRQ context
*
*/
void NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void));
/**
* @brief Copy NVIC vector table to RAM and set NVIC to RAM based table.
*
*/
void NVIC_SetRAM(void);
/**
* @brief Get Interrupt Vector
* @details Reads an interrupt vector from interrupt vector table. The
* interrupt number can be positive to specify a device specific
* interrupt, or negative to specify a processor exception.
* @param[in] IRQn Interrupt number.
* @return Address of interrupt handler function
*/
uint32_t NVIC_GetVector(IRQn_Type IRQn);
/**@} end of group nvic */
#ifdef __cplusplus
}
#endif
#endif /* _NVIC_TABLE_H */

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/**
* @file
* @brief Real Time Clock (RTC) functions and prototypes.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
* $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $
* $Revision: 47429 $
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _RTC_H_
#define _RTC_H_
/* **** Includes **** */
#include <stdint.h>
#include "mxc_config.h"
#include "rtc_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup rtc RTC
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
typedef enum {
SQUARE_WAVE_DISABLED, /**< Sq. wave output disabled */
SQUARE_WAVE_ENABLED, /**< Sq. wave output enabled */
} rtc_sqwave_en_t;
typedef enum {
F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, /**< 1Hz (Compensated) */
F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ, /**< 512Hz (Compensated) */
F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, /**< 4Khz */
F_32KHZ = 32, /**< 32Khz */
} rtc_freq_sel_t;
typedef enum {
NOISE_IMMUNE_MODE = MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE,
QUIET_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETMODE,
QUIET_STOP_WARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP,
QUIET_STOP_NOWARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP,
} rtc_osc_mode_t;
/**
*@brief Enables Time-of-Day's Alarm Interrupt
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_EnableTimeofdayInterrupt(mxc_rtc_regs_t *rtc);
/**
*@brief Disable Time-of-Day's Alarm Interrupt
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_DisableTimeofdayInterrupt(mxc_rtc_regs_t *rtc);
/**
*@brief Enables Sub-Second's Alarm Interrupt
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_EnableSubsecondInterrupt(mxc_rtc_regs_t *rtc);
/**
*@brief Disable Sub-Second's Alarm Interrupt
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_DisableSubsecondInterrupt(mxc_rtc_regs_t *rtc);
/**
*@brief Set Time-of-Day alarm value and enable Interrupt
*@param rtc pointer to the rtc register structure
*@param ras 20-bit value 0-0xFFFFF
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras);
/**
*@brief Set Sub-Second alarm value and enable interrupt,
*@brief this is to be called after the init_rtc() function
*@param rtc pointer to the rtc register structure
*@param rssa 32-bit value 0-0xFFFFFFFF
*@return #E_SUCCESS=pass
*@return #E_BAD_STATE=fail
*@return #E_BUSY=Fail
*/
int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa);
/**
*@brief Enable/Start the Real Time Clock
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=Pass
*@return #E_BUSY=Fail
*/
int RTC_EnableRTCE(mxc_rtc_regs_t *rtc);
/**
*@brief Disable/Stop the Real Time Clock
*@param rtc pointer to the rtc register structure
*@return #E_SUCCESS=Pass
*@return #E_BUSY=Fail
*/
int RTC_DisableRTCE(mxc_rtc_regs_t *rtc);
/**
* @brief Initialize the sec and ssec registers and enable RTC
* @param rtc pointer to the rtc register structure
* @param sec set the RTC Sec counter (32-bit)
* @param ssec set the RTC Sub-second counter (8-bit)
* @param sys_cfg The system configuration
* @return #E_SUCCESS=pass
* @return #E_BAD_STATE=fail
*/
int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint8_t ssec, sys_cfg_rtc_t *sys_cfg);
/**
* @brief Allow generation of Square Wave on the SQW pin
* @param rtc pointer to the rtc register structure
* @param sqe Enable/Disable square wave output
* @param ft Frequency output selection
* @param x32kmd 32KHz Oscillator mode
* @param sys_cfg The system configuration
* @return #E_SUCCESS=Pass
* @return #E_BUSY=Fail
*/
int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft,
rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg);
/**
*@brief Set Trim register value
*@param rtc pointer to the rtc register structure
*@param trm set the RTC Trim (8-bit, +/- 127)
*@return #E_SUCCESS=Pass
*@return #E_BUSY=Fail
*/
int RTC_Trim(mxc_rtc_regs_t *rtc, int8_t trm);
/**
*@brief Check if BUSY bit is 0.
*@return #E_SUCCESS=Pass
*@return #E_BUSY=Fail
*/
int RTC_CheckBusy(void);
/**
*@brief Gets Interrupt flags.
*@return Interrupts flags that have not been cleared
*/
int RTC_GetFlags(void);
/**
*@brief Clear Interrupt flag.
*@param flags the flags that need to be cleared
*/
int RTC_ClearFlags(int flags);
/**
*@brief Get SubSecond
*@return Returns subsecond value
*/
int RTC_GetSubSecond(void);
/**
* @brief Get Second
* @return returns Second value
*/
int RTC_GetSecond(void);
/**
* @brief Read seconds, then subseconds, and finally seconds. If RTC ready flag ever gets cleared during this sequence,
the RTC is in the middle of updating the counts and the user should come back later and try again. If the first
read of the seconds register doesn't match the next read, then a subsecond overflow condition has happened and
another attempt to read the counts should be made.
* @param sec variable that will be changed to hold second value
* @param subsec variable that will be changed to hold Subsecond value
* @return #E_NO_ERROR=Pass
* @return #E_BUSY=Fail
*/
int RTC_GetTime(uint32_t* sec, uint32_t* subsec);
/**
*@brief Check if RTC is already running
*/
int RTC_IsEnabled(void);
#ifdef __cplusplus
}
#endif
/**@} end of group rtc */
#endif /* _RTC_H_ */

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/**
* @file spi.h
* @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-11-07 14:48:15 -0600 (Wed, 07 Nov 2018) $
* $Revision: 39010 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _SPI_H_
#define _SPI_H_
/* **** Includes **** */
#include "spi17y_regs.h"
#include "spimss_regs.h"
#include "spimss.h"
#include "spi17y.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spi SPI
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/**
* @brief Enums assigning numbers to SPI
*/
typedef enum {
SPI0A, // SPI17Y (0A)
SPI1A, // SPIMSS (1A)
SPI1B, // SPIMSS (1B)
}spi_type;
/**
* @brief Renaming the SPI address names
*/
#define MXC_SPI0 MXC_SPI17Y // SPI0A
#define MXC_SPI1 MXC_SPIMSS // SPI1A & SPI1B
/**
* @brief Renaming Interrupt SPI Interrupt sources
*/
#define SPI0_IRQn SPI17Y_IRQn // SPI0A
#define SPI1_IRQn SPIMSS_IRQn // SPI1A & SPI1B
/**
* @brief Renaming SPI Width
*/
#define SPI0_WIDTH_1 SPI17Y_WIDTH_1 /**< 1 Data Line. */
#define SPI0_WIDTH_2 SPI17Y_WIDTH_2 /**< 2 Data Lines (x2). */
#define SPI0_WIDTH_4 SPI17Y_WIDTH_4 /**< 4 Data Lines (x4). */
/**
* @brief Renaming SPI Polarity
*/
#define SPI_POL_LOW SPI17Y_POL_LOW /**< Slave Select polarity Low. */
#define SPI_POL_HIGH SPI17Y_POL_HIGH /**< Slave Select polarity High. */
/**
* @brief Structure type representing a SPI Master Transaction request.
*/
typedef struct spi_req spi_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
* @addtogroup spi_async
*/
typedef void (*spi_callback_fn)(void * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
* @addtogroup spi_async
*/
struct spi_req {
uint8_t ssel; /**< Slave select line to use. (Master only) */
uint8_t deass; /**< Non-zero to de-assert slave select after transaction. (Master only)*/
spi17y_sspol_t ssel_pol; /**< Slave select line polarity. */
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
spi17y_width_t width; /**< Number of data lines to use, see #spi17y_width_t. */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
spi_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
/* **** Function Prototypes **** */
/**
* @brief Initialize the spi.
* @param spi_name spi module to initialize.
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_Init(spi_type spi_name, unsigned mode, unsigned freq);
/**
* @brief Asynchronously read/write SPI Master data
*
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_MasterTransAsync(spi_type spi_name, spi_req_t *req);
/**
* @brief Execute a master transaction.
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_MasterTrans(spi_type spi_name, spi_req_t *req);
/**
* @brief Asynchronously read/write SPI Slave data
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_SlaveTransAsync(spi_type spi_name, spi_req_t *req);
/**
* @brief Execute a slave transaction.
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_SlaveTrans(spi_type spi_name, spi_req_t *req);
/**
* @brief Shutdown SPI module.
* @param spi_name SPI instance being used
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPI_Shutdown(spi_type spi_name);
/**
* @brief Aborts an Asynchronous request
* @param spi_name SPI instance being used
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI_AbortAsync(spi_type spi_name, spi_req_t *req);
/**
* @brief Execute SPI transaction based on interrupt handler
* @param spi_name SPI instance being used
*
* @return #E_NO_ERROR if successful,
* @return #E_BAD_PARAM otherwise
*/
int SPI_Handler(spi_type spi_name);
/**
* @brief Enable SPI
* @param spi_name Pointer to spi module.
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPI_Enable(spi_type spi_name);
/**
* @brief Disable SPI
* @param spi_name Pointer to spi module.
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPI_Disable(spi_type spi_name);
/**
* @brief Clear the TX and RX FIFO
* @param spi_name Pointer to spi module.
*
* @return #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPI_Clear_fifo(spi_type spi_name);
//-------------------------------------------------------------------------------------------
/**@} end of group spi */
#ifdef __cplusplus
}
#endif
#endif /* _SPI_H_ */

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/**
* @file spi17y.h
* @brief Serial Peripheral Interface (SPI17Y) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _SPI17Y_H_
#define _SPI17Y_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "spi17y_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spi17y SPI17Y
* @ingroup spi
* @{
*/
/* **** Definitions **** */
/**
* Enumeration type for setting the number data lines to use for communication.
*/
typedef enum {
SPI17Y_WIDTH_1 = 0, /**< 1 Data Line. */
SPI17Y_WIDTH_2 = 1, /**< 2 Data Lines (x2). */
SPI17Y_WIDTH_4 = 2 /**< 4 Data Lines (x4). */
} spi17y_width_t;
/**
* Enumeration type for setting the polarity of ss lines.
*/
typedef enum {
SPI17Y_POL_LOW = 0, /**< Polarity Low. */
SPI17Y_POL_HIGH = 1 /**< Polarity High. */
} spi17y_sspol_t;
/**
* Structure type representing a SPI17Y Master Transaction request.
*/
typedef struct spi17y_req spi17y_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi17y_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
* @addtogroup spi_async
*/
typedef void (*spi17y_callback_fn)(spi17y_req_t * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
* @addtogroup spi_async
*/
struct spi17y_req {
uint8_t ssel; /**< Slave select line to use. (Master only, ignored in slave mode) */
uint8_t deass; /**< Non-zero to de-assert slave select after transaction. (Master only, ignored in slave mode)*/
spi17y_sspol_t ssel_pol; /**< Slave select line polarity. */
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
spi17y_width_t width; /**< Number of data lines to use, see #spi17y_width_t. */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
spi17y_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
/* **** Function Prototypes **** */
/**
* @brief Initialize the spi.
* @param spi Pointer to spi module to initialize.
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
* @param sys_cfg System configuration object
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_Init(mxc_spi17y_regs_t *spi, unsigned int mode, unsigned int freq, const sys_cfg_spi17y_t* sys_cfg);
/**
* @brief Shutdown SPI module.
* @param spi Pointer to SPI regs.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_Shutdown(mxc_spi17y_regs_t *spi);
/**
* @brief Processing function for asynchronous SPI operations.
* This function must be called either from the SPI interrupt
* handler or periodically.
*
* @param spi Pointer to spi module.
*/
void SPI17Y_Handler(mxc_spi17y_regs_t *spi);
/**
* @brief Execute a master transaction.
* This function will block until the transaction is complete.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_MasterTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
/**
* @brief Execute a slave transaction.
* This function will block until the transaction is complete.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_SlaveTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
/**
* @brief Asynchronously read/write SPI Master data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_MasterTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
/**
* @brief Asynchronously read/write SPI Slave data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_SlaveTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req);
/**
* @brief Aborts an Asynchronous request
*
* @param req Pointer to spi request
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPI17Y_AbortAsync(spi17y_req_t *req);
/**
* @brief Enable SPI
* @param spi Pointer to spi module.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
void SPI17Y_Enable(mxc_spi17y_regs_t* spi);
/**
* @brief Disable SPI. Any pending asynchronous transactions will not
* complete and their callbacks will not be executed.
* @param spi Pointer to spi module.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
void SPI17Y_Disable(mxc_spi17y_regs_t* spi);
/**
* @brief Clear the TX and RX FIFO
* @param spi Pointer to spi module.
*
* @return #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
void SPI17Y_Clear_fifo(mxc_spi17y_regs_t* spi);
/**@} end of group spi17y */
#ifdef __cplusplus
}
#endif
#endif /* _SPI17Y_H_ */

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/**
* @file spimss.h
* @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _SPIMSS_H_
#define _SPIMSS_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "mxc_sys.h"
#include "spimss_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup spimss SPIMSS
* @ingroup spi
* @{
*/
/* **** Definitions **** */
/**
* @brief Enumeration type for setting the number data lines to use for communication.
*/
typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED
DUMMY_1, /**< NOT USED */
DUMMY_2, /**< NOT USED */
DUMMY_3, /**< NOT USED */
} spimss_width_t;
/**
* @brief Structure type representing a SPI Master Transaction request.
*/
typedef struct spimss_req spimss_req_t;
/**
* @brief Callback function type used in asynchronous SPI Master communication requests.
* @details The function declaration for the SPI Master callback is:
* @code
* void callback(spi_req_t * req, int error_code);
* @endcode
* | | |
* | -----: | :----------------------------------------- |
* | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. |
* | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. |
* @note Callback will execute in interrupt context
* @addtogroup spi_async
*/
typedef void (*spimss_callback_fn)(spimss_req_t * req, int error_code);
/**
* @brief Structure definition for an SPI Master Transaction request.
* @note When using this structure for an asynchronous operation, the
* structure must remain allocated until the callback is completed.
* @addtogroup spi_async
*/
struct spimss_req {
uint8_t ssel; /**< Not Used*/
uint8_t deass; /**< Not Used*/
const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */
void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/
spimss_width_t width; /**< Not Used */
unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */
unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */
unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */
unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */
spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */
};
/* **** Function Prototypes **** */
/**
* @brief Initialize the spi.
* @param spi Pointer to spi module to initialize.
* @param mode SPI mode for clock phase and polarity.
* @param freq Desired clock frequency.
* @param sys_cfg System configuration object
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_cfg_spimss_t* sys_cfg);
/**
* @brief Shutdown SPI module.
* @param spi Pointer to SPI regs.
*
* @return \c #E_NO_ERROR if successful, appropriate error otherwise
*/
int SPIMSS_Shutdown(mxc_spimss_regs_t *spi);
/**
* @brief Execute a master transaction.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, spimss_req_t *req);
/**
* @brief Execute SPI transaction based on interrupt handler
* @param spi The spi
*
*/
void SPIMSS_Handler(mxc_spimss_regs_t *spi);
/**
* @brief Execute a slave transaction.
* @param spi Pointer to spi module.
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, spimss_req_t *req);
/**
* @brief Asynchronously read/write SPI Master data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req);
/**
* @brief Asynchronously read/write SPI Slave data
*
* @param spi Pointer to spi module
* @param req Pointer to spi request
*
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req);
/**
* @brief Aborts an Asynchronous request
*
* @param req Pointer to spi request
* @return \c #E_NO_ERROR if successful, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int SPIMSS_AbortAsync(spimss_req_t *req);
/**@} end of group spimss */
#ifdef __cplusplus
}
#endif
#endif /* _SPIMSS_H_ */

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/**
* @file tmr.h
* @brief Timer (TMR) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-09-11 14:32:22 -0500 (Wed, 11 Sep 2019) $
* $Revision: 46047 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _TMR_H_
#define _TMR_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "tmr_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup tmr Timer (TMR)
* @ingroup periphlibs
* @{
*/
/**
* @brief Timer prescaler values
*/
typedef enum {
TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV1, /// Divide input clock by 1
TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV2, /// Divide input clock by 2
TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV4, /// Divide input clock by 4
TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV8, /// Divide input clock by 8
TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV16, /// Divide input clock by 16
TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV32, /// Divide input clock by 32
TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV64, /// Divide input clock by 64
TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV128, /// Divide input clock by 128
TMR_PRES_256 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV1, /// Divide input clock by 256
TMR_PRES_512 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV2, /// Divide input clock by 512
TMR_PRES_1024 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV4, /// Divide input clock by 1024
TMR_PRES_2048 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV8, /// Divide input clock by 2048
TMR_PRES_4096 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV16 /// Divide input clock by 4096
} tmr_pres_t;
/**
* @brief Timer modes
*/
typedef enum {
TMR_MODE_ONESHOT = MXC_V_TMR_CN_TMODE_ONESHOT, /// Timer Mode ONESHOT
TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, /// Timer Mode CONTINUOUS
TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, /// Timer Mode COUNTER
TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, /// Timer Mode PWM
TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, /// Timer Mode CAPTURE
TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, /// Timer Mode COMPARE
TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, /// Timer Mode GATED
TMR_MODE_CAPTURE_COMPARE = MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE
} tmr_mode_t;
/**
* @brief Timer units of time enumeration
*/
typedef enum {
TMR_UNIT_NANOSEC = 0, /**< Nanosecond Unit Indicator. */
TMR_UNIT_MICROSEC, /**< Microsecond Unit Indicator. */
TMR_UNIT_MILLISEC, /**< Millisecond Unit Indicator. */
TMR_UNIT_SEC, /**< Second Unit Indicator. */
} tmr_unit_t;
/**
* @brief Timer Configuration
*/
typedef struct {
tmr_mode_t mode; /// Desired timer mode
uint32_t cmp_cnt; /// Compare register value in timer ticks
unsigned pol; /// Polarity (0 or 1)
} tmr_cfg_t;
/**
* @brief Timer PWM Configuration
*/
typedef struct {
unsigned pol; /// PWM polarity (0 or 1)
uint32_t per_cnt; /// PWM period in timer ticks
uint32_t duty_cnt; /// PWM duty in timer ticks
} tmr_pwm_cfg_t;
/* **** Definitions **** */
/* **** Function Prototypes **** */
/**
* @brief Initialize timer module clock.
* @param tmr Pointer to timer module to initialize.
* @param pres Prescaler value.
* @param sys_cfg System configuration object
* @return #E_NO_ERROR if successful, error code otherwise.
*/
int TMR_Init(mxc_tmr_regs_t *tmr, tmr_pres_t pres, const sys_cfg_tmr_t* sys_cfg);
/**
* @brief Shutdown timer module clock.
* @param tmr Pointer to timer module to initialize.
* @return #E_NO_ERROR if successful, error code otherwise.
*/
int TMR_Shutdown(mxc_tmr_regs_t *tmr);
/**
* @brief Enable the timer.
* @param tmr Pointer to timer module to initialize.
*/
void TMR_Enable(mxc_tmr_regs_t* tmr);
/**
* @brief Disable the timer.
* @param tmr Pointer to timer module to initialize.
*/
void TMR_Disable(mxc_tmr_regs_t* tmr);
/**
* @brief Configure the timer.
* @param tmr Pointer to timer module to initialize.
* @param cfg Pointer to timer configuration struct.
* @return #E_NO_ERROR if successful.
*/
int TMR_Config(mxc_tmr_regs_t *tmr, const tmr_cfg_t *cfg);
/**
* @brief Configure the timer for PWM operation.
* @param tmr Pointer to timer module to initialize.
* @param cfg Pointer to timer PWM configuration struct.
* @note Can cause a glitch if the Timer is currently running.
* @return #E_BAD_PARAM if duty_cnt > per_cnt.
*/
int TMR_PWMConfig(mxc_tmr_regs_t *tmr, const tmr_pwm_cfg_t *cfg);
/**
* @brief Set the timer duty cycle.
* @param tmr Pointer to timer module to initialize
* @param duty New duty cycle count
* @note Will block until safe to change the duty count.
* @return #E_BAD_PARAM if duty_cnt > per_cnt.
*/
int TMR_PWMSetDuty(mxc_tmr_regs_t *tmr, uint32_t duty);
/**
* @brief Set the timer period.
* @param tmr Pointer to timer module to initialize.
* @param per New period count.
* @note Will block until safe to change the period count.
* @return #E_BAD_PARAM if duty_cnt > per_cnt.
*/
int TMR_PWMSetPeriod(mxc_tmr_regs_t* tmr, uint32_t per);
/**
* @brief Get the timer compare count.
* @param tmr Pointer to timer module to initialize.
* @return Returns the current compare count.
*/
uint32_t TMR_GetCompare(mxc_tmr_regs_t* tmr);
/**
* @brief Get the timer capture count.
* @param tmr Pointer to timer module to initialize.
* @return Returns the most recent capture count.
*/
uint32_t TMR_GetCapture(mxc_tmr_regs_t* tmr);
/**
* @brief Get the timer count.
* @param tmr Pointer to timer module to initialize.
* @return Returns the current count.
*/
uint32_t TMR_GetCount(mxc_tmr_regs_t* tmr);
/**
* @brief Clear the timer interrupt.
* @param tmr Pointer to timer module to initialize.
*/
void TMR_IntClear(mxc_tmr_regs_t* tmr);
/**
* @brief Get the timer interrupt status.
* @param tmr Pointer to timer module to initialize.
* @return Returns the interrupt status. 1 if interrupt has occurred.
*/
uint32_t TMR_IntStatus(mxc_tmr_regs_t* tmr);
/**
* @brief Set the timer compare count.
* @param tmr Pointer to timer module to initialize.
* @param cmp_cnt New compare count.
* @note This function does not protect against output glitches in PWM mode.
* Use TMR_PWMSetPeriod when in PWM mode.
*/
void TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt);
/**
* @brief Set the timer count.
* @param tmr Pointer to timer module to initialize.
* @param cnt New count.
*/
void TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt);
/**
* @brief Convert real time to timer ticks.
* @param tmr Pointer to timer module to initialize.
* @param time Number of units of time.
* @param units Which units of time you want to convert.
* @param ticks Pointer to store the number of ticks calculated.
* @return #E_NO_ERROR if successful, error code otherwise.
*/
int TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks);
/**
* @brief Convert timer ticks to real time.
* @param tmr Pointer to timer module to initialize.
* @param ticks Number of ticks.
* @param time Pointer to store number of units of time.
* @param units Pointer to store the units that time represents.
* @return #E_NO_ERROR if successful, error code otherwise.
*/
int TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units);
/**@} end of group tmr */
#ifdef __cplusplus
}
#endif
#endif /* _TMR_H_ */

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/**
* @file tmr_utils.h
* @brief Timer utility function declarations
*/
/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $
* $Revision: 38560 $
*
**************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _TMR_UTILS_H
#define _TMR_UTILS_H
/***** Includes *****/
#include "mxc_config.h"
#include "tmr_regs.h"
#include "mxc_sys.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @ingroup tmr
* @defgroup tmr_utils Timer Utility Functions
* @{
*/
/* **** Definitions **** */
/** @def Macro to convert the parameter \p s from seconds to micro-seconds. */
#define SEC(s) (((unsigned long)s) * 1000000UL)
/** @def Macro to convert the parameter \p ms from milli-seconds to micro-seconds. */
#define MSEC(ms) (ms * 1000UL)
/** @def Macro to convert the parameter \p us to micro-seconds. */
#define USEC(us) (us)
/* **** Globals **** */
/* **** Function Prototypes **** */
/**
* @brief Delays for the specified number of microseconds.
* @param tmr Which Timer instance to use
* @param us Number of microseconds to delay.
* @param sys_cfg System configuration object, identical to TMR_Init()
*/
void TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg);
/**
* @brief Start the timeout time for the specified number of microseconds.
* @param tmr Which Timer instance to use
* @param us Number of microseconds in the timeout.
* @param sys_cfg System configuration object, identical to TMR_Init()
*/
void TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg);
/**
* @brief Check if the timeout has occurred.
* @param tmr Which Timer instance to use
* @return #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has.
*/
int TMR_TO_Check(mxc_tmr_regs_t *tmr);
/**
* @brief Stops the timer for the timeout.
* @param tmr Which Timer instance to use
*/
void TMR_TO_Stop(mxc_tmr_regs_t *tmr);
/**
* @brief Clears the timeout flag.
* @param tmr Which Timer instance to use
*/
void TMR_TO_Clear(mxc_tmr_regs_t *tmr);
/**
* @brief Get the number of microseconds elapsed since TMR_TO_Start().
* @param tmr Which Timer instance to use
* @return Number of microseconds since TMR_TO_Start().
*/
unsigned int TMR_TO_Elapsed(mxc_tmr_regs_t *tmr);
/**
* @brief Get the number of microseconds remaining in the timeout.
* @param tmr Which Timer instance to use
* @return Number of microseconds until timeout.
*/
unsigned int TMR_TO_Remaining(mxc_tmr_regs_t *tmr);
/**
* @brief Start the stopwatch.
* @note This function does not handle overflows
* @param tmr Which Timer to use
* @param sys_cfg System configuration object, identical to TMR_Init()
*/
void TMR_SW_Start(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *sys_cfg);
/**
* @brief Stop the stopwatch and return the number of microseconds that
* have elapsed.
* @note This function does not handle overflows
* @param tmr Which Timer instance to use
* @return Number of microseconds since TMR_SW_Start().
*/
unsigned int TMR_SW_Stop(mxc_tmr_regs_t *tmr);
/**@} end of defgroup tmr_utils*/
#ifdef __cplusplus
}
#endif
#endif /* _TMR_UTILS_H */

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/**
* @file
* @brief This files defines the driver API including definitions, data types
* and function prototypes.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $
* $Revision: 47429 $
*
*************************************************************************** */
#ifndef _UART_H_
#define _UART_H_
/***** Includes *****/
#include <stdint.h>
#include "uart_regs.h"
#include "mxc_sys.h"
/***** Definitions *****/
/**
* @brief Alternate clock rate. (7.3728MHz) */
#define UART_ALTERNATE_CLOCK_HZ 7372800
/**
* @defgroup uart UART
* @ingroup periphlibs
* @{
*/
/**
* @brief Parity settings type */
typedef enum {
UART_PARITY_DISABLE = 0, /**< Parity disabled */
UART_PARITY_EVEN_0 = (MXC_F_UART_CTRL_PARITY_EN |
MXC_S_UART_CTRL_PARITY_EVEN |
MXC_F_UART_CTRL_PARMD), /**< Use for even parity 0 */
UART_PARITY_EVEN_1 = (MXC_F_UART_CTRL_PARITY_EN |
MXC_S_UART_CTRL_PARITY_EVEN), /**< Use for even parity 1 */
UART_PARITY_EVEN = UART_PARITY_EVEN_1, /**< Conventional even parity */
UART_PARITY_ODD_0 = (MXC_F_UART_CTRL_PARITY_EN |
MXC_S_UART_CTRL_PARITY_ODD |
MXC_F_UART_CTRL_PARMD), /**< Use for odd parity 0 */
UART_PARITY_ODD_1 = (MXC_F_UART_CTRL_PARITY_EN |
MXC_S_UART_CTRL_PARITY_ODD), /**< Use for odd parity 1 */
UART_PARITY_ODD = UART_PARITY_ODD_1, /**< Conventional odd parity */
UART_PARITY_MARK_0 = (MXC_F_UART_CTRL_PARITY_EN |
MXC_S_UART_CTRL_PARITY_MARK |
MXC_F_UART_CTRL_PARMD), /**< Use for mark parity 0 */
UART_PARITY_MARK_1 = (MXC_F_UART_CTRL_PARITY_EN |
MXC_S_UART_CTRL_PARITY_MARK), /**< Use for mark parity 1 */
UART_PARITY_MARK = UART_PARITY_MARK_1, /**< Conventional mark parity */
UART_PARITY_SPACE_0 = (MXC_F_UART_CTRL_PARITY_EN |
MXC_S_UART_CTRL_PARITY_SPACE |
MXC_F_UART_CTRL_PARMD), /**< Use for space parity 0 */
UART_PARITY_SPACE_1 = (MXC_F_UART_CTRL_PARITY_EN |
MXC_S_UART_CTRL_PARITY_SPACE), /**< Use for space parity 1 */
UART_PARITY_SPACE = UART_PARITY_SPACE_1, /**< Conventional space parity */
} uart_parity_t;
/**
* @brief Message size settings */
typedef enum {
UART_DATA_SIZE_5_BITS = MXC_S_UART_CTRL_CHAR_SIZE_5, /**< Data Size 5 Bits */
UART_DATA_SIZE_6_BITS = MXC_S_UART_CTRL_CHAR_SIZE_6, /**< Data Size 6 Bits */
UART_DATA_SIZE_7_BITS = MXC_S_UART_CTRL_CHAR_SIZE_7, /**< Data Size 7 Bits */
UART_DATA_SIZE_8_BITS = MXC_S_UART_CTRL_CHAR_SIZE_8, /**< Data Size 8 Bits */
} uart_size_t;
/**
* @brief Stop bit settings */
typedef enum {
UART_STOP_1 = 0, /**< UART Stop 1 clock cycle */
UART_STOP_1P5 = MXC_F_UART_CTRL_STOPBITS, /**< UART Stop 1.5 clock cycle */
UART_STOP_2 = MXC_F_UART_CTRL_STOPBITS, /**< UART Stop 2 clock cycle */
} uart_stop_t;
/**
* @brief Flow control */
typedef enum {
UART_FLOW_CTRL_DIS = 0, /**< RTS/CTS flow is disabled */
UART_FLOW_CTRL_EN = MXC_F_UART_CTRL_FLOW_CTRL, /**< RTS/CTS flow is enabled */
} uart_flow_ctrl_t;
/**
* @brief Flow control Polarity */
typedef enum {
UART_FLOW_POL_DIS = 0, /**< RTS/CTS asserted is low */
UART_FLOW_POL_EN = MXC_F_UART_CTRL_FLOW_POL, /**< RTS/CTS asserted is high */
} uart_flow_pol_t;
#if (TARGET != 32660)
/**
* @brief Clock Source Select */
typedef enum {
UART_CLKSEL_SYSTEM = 0, /**< Peripheral clock will be used as the bit rate clock */
UART_CLKSEL_ALTERNATE = MXC_F_UART_CTRL_CLKSEL, /**< Use the device's alternate UART bit rate clock. */
} uart_clksel_t;
#endif
/**
* @brief UART configuration type. */
typedef struct {
uart_parity_t parity; /** Configure parity checking */
uart_size_t size; /** Configure character size */
uart_stop_t stop; /** Configure the number of stop bits to use */
uart_flow_ctrl_t flow; /** Configure hardware flow control */
uart_flow_pol_t pol; /** Configure hardware flow control */
uint32_t baud; /** Configure baud rate */
#if (TARGET != 32660)
uart_clksel_t clksel; /** Configure hardware clock source */
#endif
} uart_cfg_t;
/**
* @brief Non-blocking UART transaction request. */
typedef struct uart_req uart_req_t;
struct uart_req {
uint8_t *data; /** Data buffer for characters */
int len; /** Length of characters in data to send or receive */
int num; /** Number of characters actually sent or received */
/**
* @brief Callback for asynchronous request.
*
* @param uart_req_t* Pointer to the transaction request.
* @param int Error code.
*
*/
void(*callback)(uart_req_t*, int);
};
/***** Functions Prototypes *****/
/**
* @brief Initialize and enable UART module.
* @param uart Pointer to the UART registers.
* @param cfg Pointer to UART configuration.
* @param sys_cfg Pointer to system configuration object
* @returns #E_NO_ERROR UART initialized successfully, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t* sys_cfg);
/**
* @brief Shutdown UART module.
* @param uart Pointer to the UART registers.
* @returns #E_NO_ERROR UART shutdown successfully, @ref MXC_Error_Codes "error" if
* unsuccessful.
*/
int UART_Shutdown(mxc_uart_regs_t *uart);
/**
* @brief UART interrupt handler.
* @details This function should be called by the application from the
* interrupt handler if UART interrupts are enabled. Alternately,
* this function can be periodically called by the application if
* UART interrupts are disabled. It is only necessary to call this
* when using asynchronous functions.
*
* @param uart Pointer to the UART registers.
*/
void UART_Handler(mxc_uart_regs_t *uart);
/**
* @brief Read UART data, <em>blocking</em> until transaction is complete.
*
* @param uart Pointer to the UART registers.
* @param data Pointer to buffer to save the data read.
* @param len Number of bytes to read.
* @param num Pointer to store the number of bytes actually read, pass NULL if not needed.
*
* @return Number of bytes read, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int UART_Read(mxc_uart_regs_t *uart, uint8_t *data, int len, int *num);
/**
* @brief Write UART data. This function blocks until the write transaction
* is complete.
* @param uart Pointer to the UART registers.
* @param data Pointer to buffer for write data.
* @param len Number of bytes to write.
* @note This function will return once data has been put into FIFO, not necessarily
* transmitted.
* @return Number of bytes written if successful, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int UART_Write(mxc_uart_regs_t *uart, const uint8_t *data, int len);
/**
* @brief Asynchronously read UART data.
*
* @param uart Pointer to the UART registers.
* @param req Pointer to request for a UART transaction, see #uart_req.
* @note Request struct must remain allocated until callback function specified in 'req' is called.
*
* @return #E_NO_ERROR Asynchronous read successfully started, @ref MXC_Error_Codes "error" if unsuccessful.
*/
int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req);
/**
* @brief Asynchronously write/transmit UART data.
*
* @param uart Pointer to the UART registers.
* @param req Request for a UART transaction, see #uart_req.
* @note Request struct must remain allocated until callback function specified in 'req' is called.
*
* @return #E_NO_ERROR Asynchronous write successfully started, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req);
/**
* @brief Read a single byte from the UART.
* @note This function will block until a character is available.
*
* @param uart Pointer to the UART registers.
* @return The byte read.
*/
uint8_t UART_ReadByte(mxc_uart_regs_t *uart);
/**
* @brief Write one byte at a time to the UART.
* @note This function will block until the character has been placed in the transmit FIFO.
* It may return before the character is actually transmitted.
*
* @param uart Pointer to the UART registers.
* @param data The byte to write.
*/
void UART_WriteByte(mxc_uart_regs_t *uart, uint8_t data);
/**
* @brief Check to see if the UART is busy.
*
* @param uart Pointer to the UART registers.
*
* @return #E_NO_ERROR if the UART is idle, #E_BUSY if the UART is in use.
*/
int UART_Busy(mxc_uart_regs_t *uart);
/**
* @brief Prepare the UART for entry into a Low-Power mode (DEEPSLEEP/BACKUP).
* @details Checks for any ongoing transactions. Disables interrupts if the
* UART is idle.
*
* @param uart Pointer to the UART registers.
* @return #E_NO_ERROR UART is ready to enter Low-Power modes (DEEPSLEEP/BACKUP).
* @return #E_BUSY UART is active and busy and not ready to enter a
* Low-Power mode (DEEPSLEEP/BACKUP).
*
*/
int UART_PrepForSleep(mxc_uart_regs_t *uart);
/**
* @brief Abort asynchronous request.
*
* @param req Pointer to the request to abort. See #uart_req.
*
* @return #E_NO_ERROR if the asynchronous request aborted successfully started, @ref
* MXC_Error_Codes "error" if unsuccessful.
*/
int UART_AbortAsync(uart_req_t *req);
/**
* @brief Returns the number of bytes still pending transmission in the UART TX FIFO.
*
* @param uart Pointer to the UART registers.
*
* @return Number of unused bytes in the TX FIFO.
*/
unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart);
/**
* @brief Returns the number of bytes available to be read from the RX FIFO.
*
* @param uart Pointer to the UART registers.
*
* @return The number of bytes available to read in the RX FIFO.
*/
unsigned UART_NumReadAvail(mxc_uart_regs_t *uart);
/**
* @brief Clears the specified interrupt flags.
*
* @param uart Pointer to the UART registers.
* @param mask Mask of the UART interrupts to clear, see
* @ref UART_INT_FL Register.
*/
void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask);
/**
* @brief Get the UART interrupt flags.
*
* @param uart Pointer to the UART registers.
*
* @return Mask of active flags.
*/
unsigned UART_GetFlags(mxc_uart_regs_t *uart);
/**
* @brief Enables the UART.
* @note This function does not change the existing UART configuration.
*
* @param uart Pointer to the UART registers.
*/
void UART_Enable(mxc_uart_regs_t *uart);
/**
* @brief Disables the UART.
* @note This function does not change the existing UART configuration.
*
* @param uart Pointer to the UART registers.
*/
void UART_Disable(mxc_uart_regs_t *uart);
/**
* @brief Drains/empties and data in the RX FIFO, discarding any bytes not yet consumed.
*
* @param uart Pointer to the UART registers.
*/
void UART_DrainRX(mxc_uart_regs_t *uart);
/**
* @brief Drains/empties any data in the TX FIFO, discarding any bytes not yet transmitted.
*
* @param uart Pointer to the UART registers.
*/
void UART_DrainTX(mxc_uart_regs_t *uart);
/**@} end of group uart */
#endif /* _UART_H_ */

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/**
* @file wdt.h
* @brief Watchdog timer (WDT) function prototypes and data types.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2020-04-20 15:06:58 -0500 (Mon, 20 Apr 2020) $
* $Revision: 53142 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _WDT_H_
#define _WDT_H_
/* **** Includes **** */
#include <stdint.h>
#include "mxc_config.h"
#include "mxc_sys.h"
#include "wdt_regs.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @defgroup wdt Watchdog Timer (WDT)
* @ingroup periphlibs
* @{
*/
/* **** Definitions **** */
/** @brief Watchdog period enumeration.
Used to configure the period of the watchdog interrupt */
typedef enum {
WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, /**< Period 2^31 */
WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, /**< Period 2^30 */
WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, /**< Period 2^29 */
WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, /**< Period 2^28 */
WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, /**< Period 2^27 */
WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, /**< Period 2^26 */
WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, /**< Period 2^25 */
WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, /**< Period 2^24 */
WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, /**< Period 2^23 */
WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, /**< Period 2^22 */
WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, /**< Period 2^21 */
WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, /**< Period 2^20 */
WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, /**< Period 2^19 */
WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, /**< Period 2^18 */
WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, /**< Period 2^17 */
WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, /**< Period 2^16 */
} wdt_period_t;
/* **** Function Prototypes **** */
/**
* @brief Initialize the Watchdog Timer
* @param wdt Pointer to the watchdog registers
* @param sys_cfg The system configuration object
*/
int WDT_Init(mxc_wdt_regs_t* wdt, sys_cfg_wdt_t sys_cfg);
/**
* @brief Set the period of the watchdog interrupt.
* @param wdt Pointer to watchdog registers.
* @param period Enumeration of the desired watchdog period.
*/
void WDT_SetIntPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period);
/**
* @brief Set the period of the watchdog reset.
* @param wdt Pointer to watchdog registers.
* @param period Enumeration of the desired watchdog period.
*/
void WDT_SetResetPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period);
/**
* @brief Enable the watchdog timer.
* @param wdt Pointer to watchdog registers.
* @param enable 1 to enable the timer, 0 to disable.
*/
void WDT_Enable(mxc_wdt_regs_t* wdt, int enable);
/**
* @brief Enable the watchdog interrupt.
* @param wdt Pointer to watchdog registers.
* @param enable 1 to enable the interrupt, 0 to disable.
*/
void WDT_EnableInt(mxc_wdt_regs_t* wdt, int enable);
/**
* @brief Enable the watchdog reset.
* @param wdt Pointer to watchdog registers.
* @param enable 1 to enable the reset, 0 to disable.
*/
void WDT_EnableReset(mxc_wdt_regs_t* wdt, int enable);
/**
* @brief Reset the watchdog timer.
* @param wdt Pointer to watchdog registers.
*/
void WDT_ResetTimer(mxc_wdt_regs_t* wdt);
/**
* @brief Get the status of the reset flag.
* @param wdt Pointer to watchdog registers.
* @returns 1 if the previous reset was caused by the watchdog, 0 otherwise.
*/
int WDT_GetResetFlag(mxc_wdt_regs_t* wdt);
/**
* @brief Clears the reset flag.
* @param wdt Pointer to watchdog registers.
*/
void WDT_ClearResetFlag(mxc_wdt_regs_t* wdt);
/**
* @brief Get the status of the interrupt flag.
* @param wdt Pointer to watchdog registers.
* @returns 1 if the interrupt is pending, 0 otherwise.
*/
int WDT_GetIntFlag(mxc_wdt_regs_t* wdt);
/**
* @brief Clears the interrupt flag.
* @param wdt Pointer to watchdog registers.
*/
void WDT_ClearIntFlag(mxc_wdt_regs_t* wdt);
/**@} end of group wdt */
#ifdef __cplusplus
}
#endif
#endif /* _WDT_H_ */

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/* *****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-07-01 11:06:19 -0500 (Mon, 01 Jul 2019) $
* $Revision: 44383 $
*
**************************************************************************** */
#include <stddef.h>
#include <stdint.h>
#include "mxc_config.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "dma.h"
/*
* Structure type
*/
typedef struct {
unsigned int valid; /* Flag to invalidate this resource */
unsigned int instance; /* Hardware instance of this DMA controller */
unsigned int id; /* Channel ID, which matches the index into the underlying hardware */
mxc_dma_ch_regs_t *regs; /* Pointer to the registers for this channel */
void (*cb)(int, int); /* Pointer to a callback function type */
} dma_channel_t;
#define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid))
/* DMA driver must be initialized once before use, and may not be initialized again without shutdown, as it is a shared resource */
static unsigned int dma_initialized = 0;
static dma_channel_t dma_resource[MXC_DMA_CHANNELS];
static uint32_t dma_lock;
/* Initialize DMA to known state */
int DMA_Init(void)
{
int i;
if (dma_initialized) {
return E_BAD_STATE;
}
/* Initialize any system-level DMA settings */
SYS_DMA_Init();
/* Initialize mutex */
mxc_free_lock(&dma_lock);
if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY;
}
/* Ensure all channels are disabled at start, clear flags, init handles */
MXC_DMA->cn = 0;
for (i = 0; i < MXC_DMA_CHANNELS; i++) {
dma_resource[i].valid = 0;
dma_resource[i].instance = 0;
dma_resource[i].id = i;
dma_resource[i].regs = (mxc_dma_ch_regs_t *)&MXC_DMA->ch[i];
dma_resource[i].regs->cfg = 0;
dma_resource[i].regs->st = dma_resource[i].regs->st;
dma_resource[i].cb = NULL;
}
dma_initialized++;
mxc_free_lock(&dma_lock);
return E_NO_ERROR;
}
/* Shut down DMA in an orderly manner, informing clients that their requests did not complete */
int DMA_Shutdown(void)
{
int i;
if (!dma_initialized) {
/* Never initialized, so shutdown is not appropriate */
return E_BUSY;
}
if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY;
}
/* Prevent any new resource allocation by this API */
dma_initialized = 0;
/* Disable interrupts, preventing future callbacks */
MXC_DMA->cn = 0;
/* For each channel:
* - invalidate the handles held by clients
* - stop any transfer in progress
*/
for (i = 0; i < MXC_DMA_CHANNELS; i++) {
dma_resource[i].regs->cfg = 0;
if (dma_resource[i].valid) {
dma_resource[i].valid = 0;
if (dma_resource[i].cb != NULL) {
dma_resource[i].cb(i, E_SHUTDOWN);
}
}
}
/* Disable any system-level DMA settings */
SYS_DMA_Shutdown();
mxc_free_lock(&dma_lock);
return E_NO_ERROR;
}
/* Request DMA channel */
/* Once "owned", this channel may be used directly via the DMA_GetCHRegs(ch) pointer, or */
/* configured via the API functions */
int DMA_AcquireChannel(void)
{
int i, channel;
/* Check for initialization */
if (!dma_initialized) {
return E_BAD_STATE;
}
/* If DMA is locked return busy */
if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY;
}
/* Default is no channel available */
channel = E_NONE_AVAIL;
if (dma_initialized) {
for (i = 0; i < MXC_DMA_CHANNELS; i++) {
if (!dma_resource[i].valid) {
/* Found one */
channel = i;
dma_resource[i].valid = 1;
dma_resource[i].regs->cfg = 0;
dma_resource[i].regs->cnt_rld = 0; /* Used by DMA_Start() to conditionally set RLDEN */
break;
}
}
}
mxc_free_lock(&dma_lock);
return channel;
}
/* Release DMA channel */
/* Callbacks will not be called */
int DMA_ReleaseChannel(int ch)
{
if (CHECK_HANDLE(ch)) {
if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) {
return E_BUSY;
}
dma_resource[ch].valid = 0;
dma_resource[ch].regs->cfg = 0;
dma_resource[ch].regs->st = dma_resource[ch].regs->st;
mxc_free_lock(&dma_lock);
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* Channel configuration */
int DMA_ConfigChannel(int ch,
dma_priority_t prio,
dma_reqsel_t reqsel, unsigned int reqwait_en,
dma_timeout_t tosel, dma_prescale_t pssel,
dma_width_t srcwd, unsigned int srcinc_en,
dma_width_t dstwd, unsigned int dstinc_en,
unsigned int burst_size, unsigned int chdis_inten,
unsigned int ctz_inten)
{
if (CHECK_HANDLE(ch) && (burst_size > 0)) {
/* Designed to be safe, not speedy. Should not be called often */
dma_resource[ch].regs->cfg =
((reqwait_en ? MXC_F_DMA_CFG_REQWAIT : 0) |
(srcinc_en ? MXC_F_DMA_CFG_SRCINC : 0) |
(dstinc_en ? MXC_F_DMA_CFG_DSTINC : 0) |
(chdis_inten ? MXC_F_DMA_CFG_CHDIEN : 0) |
(ctz_inten ? MXC_F_DMA_CFG_CTZIEN : 0) |
prio |reqsel | tosel | pssel |
(srcwd << MXC_F_DMA_CFG_SRCWD_POS) |
(dstwd << MXC_F_DMA_CFG_DSTWD_POS) |
(((burst_size - 1) << MXC_F_DMA_CFG_BRST_POS) & MXC_F_DMA_CFG_BRST));
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/*
* DMA request selects for peripherals will override either src_addr or dst_addr.
* In these cases, the overridden address is a don't care and may be 0.
*/
int DMA_SetSrcDstCnt(int ch,
void *src_addr,
void *dst_addr,
unsigned int count)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->src = (unsigned int)src_addr;
dma_resource[ch].regs->dst = (unsigned int)dst_addr;
dma_resource[ch].regs->cnt = count;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* Must set en_reload == 1 to have any effect */
int DMA_SetReload(int ch,
void *src_addr_reload,
void *dst_addr_reload,
unsigned int count_reload)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->src_rld = (unsigned int)src_addr_reload;
dma_resource[ch].regs->dst_rld = (unsigned int)dst_addr_reload;
if (dma_resource[ch].regs->cfg & MXC_F_DMA_CFG_CHEN) {
/* If channel is already running, set RLDEN to enable next reload */
dma_resource[ch].regs->cnt_rld = MXC_F_DMA_CNT_RLD_RLDEN | count_reload;
} else {
/* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */
dma_resource[ch].regs->cnt_rld = count_reload;
}
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int DMA_SetCallback(int ch, void (*callback)(int, int))
{
if (CHECK_HANDLE(ch)) {
/* Callback for interrupt handler, no checking is done, as NULL is valid for (none) */
dma_resource[ch].cb = callback;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* Interrupt enable/disable */
int DMA_EnableInterrupt(int ch)
{
if (CHECK_HANDLE(ch)) {
MXC_DMA->cn |= (1 << ch);
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int DMA_DisableInterrupt(int ch)
{
if (CHECK_HANDLE(ch)) {
MXC_DMA->cn &= ~(1 << ch);
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* Channel interrupt flags */
int DMA_GetFlags(int ch, unsigned int *fl)
{
if (CHECK_HANDLE(ch) && fl) {
*fl = dma_resource[ch].regs->st;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
int DMA_ClearFlags(int ch)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->st = dma_resource[ch].regs->st;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* Start channel */
int DMA_Start(int ch)
{
if (CHECK_HANDLE(ch)) {
DMA_ClearFlags(ch);
if (dma_resource[ch].regs->cnt_rld) {
dma_resource[ch].regs->cfg |= (MXC_F_DMA_CFG_CHEN | MXC_F_DMA_CFG_RLDEN);
} else {
dma_resource[ch].regs->cfg |= MXC_F_DMA_CFG_CHEN;
}
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* Stop channel */
int DMA_Stop(int ch)
{
if (CHECK_HANDLE(ch)) {
dma_resource[ch].regs->cfg &= ~MXC_F_DMA_CFG_CHEN;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* Get pointer to registers, for advanced users */
mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch)
{
if (CHECK_HANDLE(ch)) {
return dma_resource[ch].regs;
} else {
return NULL;
}
}
/* */
void DMA_Handler(int ch)
{
/* Do callback, if enabled */
if (dma_resource[ch].cb != NULL) {
dma_resource[ch].cb(ch, E_NO_ERROR);
}
DMA_ClearFlags(ch);
}

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/**
* @file flc.h
* @brief Flash Controler driver.
* @details This driver can be used to operate on the embedded flash memory.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $
* $Revision: 43696 $
*
*************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_config.h"
#include "mxc_sys.h"
#include "flc.h"
#include "flc_regs.h"
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
// *****************************************************************************
#if defined (__ICCARM__)
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
static int prepare_flc(void)
{
// Set flash clock divider to generate a 1MHz clock from the APB clock
MXC_FLC->clkdiv = SystemCoreClock / 1000000;
/* Check if the flash controller is busy */
if (FLC_Busy()) {
return E_BUSY;
}
/* Clear stale errors */
if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
}
/* Unlock flash */
MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_UNLOCK) | MXC_S_FLC_CN_UNLOCK_UNLOCKED;
return E_NO_ERROR;
}
// *****************************************************************************
#if defined (__ICCARM__)
// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_Init(const sys_cfg_flc_t *sys_cfg)
{
SYS_FLC_Init(sys_cfg);
return E_NO_ERROR;
}
// *****************************************************************************
#if defined (__ICCARM__)
// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM.
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_Busy(void)
{
return (MXC_FLC->cn & (MXC_F_FLC_CN_WR | MXC_F_FLC_CN_ME | MXC_F_FLC_CN_PGE));
}
// *****************************************************************************
#if defined (__ICCARM__)
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_MassErase(void)
{
int err;
if ((err = prepare_flc()) != E_NO_ERROR)
return err;
/* Write mass erase code */
MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) | MXC_S_FLC_CN_ERASE_CODE_ERASEALL;
/* Issue mass erase command */
MXC_FLC->cn |= MXC_F_FLC_CN_ME;
/* Wait until flash operation is complete */
while (FLC_Busy());
/* Lock flash */
MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
/* Check access violations */
if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
return E_BAD_STATE;
}
SYS_Flash_Operation();
return E_NO_ERROR;
}
// *****************************************************************************
#if defined (__ICCARM__)
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_PageErase(uint32_t address)
{
int err;
if ((err = prepare_flc()) != E_NO_ERROR)
return err;
// Align address on page boundary
address = address - (address % MXC_FLASH_PAGE_SIZE);
/* Write page erase code */
MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) | MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE;
/* Issue page erase command */
MXC_FLC->addr = address;
MXC_FLC->cn |= MXC_F_FLC_CN_PGE;
/* Wait until flash operation is complete */
while (FLC_Busy());
/* Lock flash */
MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
/* Check access violations */
if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
return E_BAD_STATE;
}
SYS_Flash_Operation();
return E_NO_ERROR;
}
// *****************************************************************************
#if defined (__ICCARM__)
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_Erase(uint32_t start, uint32_t end)
{
int retval;
uint32_t addr;
// Align start and end on page boundaries
start = start - (start % MXC_FLASH_PAGE_SIZE);
end = end - (end % MXC_FLASH_PAGE_SIZE);
for (addr = start; addr <= end; addr += MXC_FLASH_PAGE_SIZE) {
retval = FLC_PageErase(addr);
if (retval != E_NO_ERROR) {
return retval;
}
}
return E_NO_ERROR;
}
// *****************************************************************************
#if defined (__ICCARM__)
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_BufferErase(uint32_t start, uint32_t end, uint8_t *buffer, unsigned length)
{
int retval;
uint32_t start_align, start_len, end_align, end_len;
// Align start and end on page boundaries, calculate length of data to buffer
start_align = start - (start % MXC_FLASH_PAGE_SIZE);
start_len = (start % MXC_FLASH_PAGE_SIZE);
end_align = end - (end % MXC_FLASH_PAGE_SIZE);
end_len = ((MXC_FLASH_PAGE_SIZE - (end % MXC_FLASH_PAGE_SIZE)) % MXC_FLASH_PAGE_SIZE);
// Make sure the length of buffer is sufficient
if ((length < start_len) || (length < end_len)) {
return E_BAD_PARAM;
}
// Start and end address are in the same page
if (start_align == end_align) {
if (length < (start_len + end_len)) {
return E_BAD_PARAM;
}
// Buffer first page data and last page data, erase and write
memcpy(buffer, (void*)start_align, start_len);
memcpy(&buffer[start_len], (void*)end, end_len);
retval = FLC_PageErase(start_align);
if (retval != E_NO_ERROR) {
return retval;
}
retval = FLC_Write(start_align, start_len, buffer);
if (retval != E_NO_ERROR) {
return retval;
}
retval = FLC_Write(end, end_len, &buffer[start_len]);
if (retval != E_NO_ERROR) {
return retval;
}
return E_NO_ERROR;
}
// Buffer, erase, and write the data in the first page
memcpy(buffer, (void*)start_align, start_len);
retval = FLC_PageErase(start_align);
if (retval != E_NO_ERROR) {
return retval;
}
retval = FLC_Write(start_align, start_len, buffer);
if (retval != E_NO_ERROR) {
return retval;
}
// Buffer, erase, and write the data in the last page
memcpy(buffer, (void*)end, end_len);
retval = FLC_PageErase(end_align);
if (retval != E_NO_ERROR) {
return retval;
}
retval = FLC_Write(end, end_len, buffer);
if (retval != E_NO_ERROR) {
return retval;
}
// Erase the remaining pages
if (start_align != end_align) {
return FLC_Erase((start_align + MXC_FLASH_PAGE_SIZE), (end_align - MXC_FLASH_PAGE_SIZE));
}
return E_NO_ERROR;
}
// *****************************************************************************
#if defined (__ICCARM__)
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_Write32(uint32_t address, uint32_t data)
{
int err;
// Address checked if it is byte addressable
if (address & 0x3) {
return E_BAD_PARAM;
}
if ((err = prepare_flc()) != E_NO_ERROR)
return err;
// write in 32-bit units
MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST;
// write the data
MXC_FLC->addr = address;
MXC_FLC->data[0] = data;
MXC_FLC->cn |= MXC_F_FLC_CN_WR;
/* Wait until flash operation is complete */
while (FLC_Busy()) {}
/* Lock flash */
MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
/* Check access violations */
if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
return E_BAD_STATE;
}
SYS_Flash_Operation();
return E_NO_ERROR;
}
// *****************************************************************************
#if defined (__ICCARM__)
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_Write128(uint32_t address, uint32_t *data)
{
int err;
// Address checked if it is word addressable
if (address & 0xF) {
return E_BAD_PARAM;
}
if ((err = prepare_flc()) != E_NO_ERROR)
return err;
// write 128-bits
MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
// write the data
MXC_FLC->addr = address;
memcpy((void*)&MXC_FLC->data[0], data, 16);
MXC_FLC->cn |= MXC_F_FLC_CN_WR;
/* Wait until flash operation is complete */
while (FLC_Busy());
/* Lock flash */
MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
/* Check access violations */
if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
return E_BAD_STATE;
}
SYS_Flash_Operation();
return E_NO_ERROR;
}
// *****************************************************************************
#if defined (__ICCARM__)
#pragma section=".flashprog"
#endif
#if defined ( __GNUC__ )
__attribute__ ((section(".flashprog")))
#endif
int FLC_Write(uint32_t address, uint32_t length, uint8_t *buffer)
{
int err;
uint32_t bytes_written;
uint8_t current_data[4];
if ((err = prepare_flc()) != E_NO_ERROR)
return err;
// write in 32-bit units until we are 128-bit aligned
MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST;
MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
// Align the address and read/write if we have to
if (address & 0x3) {
// Figure out how many bytes we have to write to round up the address
bytes_written = 4 - (address & 0x3);
// Save the data currently in the flash
memcpy(current_data, (void*)(address & (~0x3)), 4);
// Modify current_data to insert the data from buffer
memcpy(&current_data[4-bytes_written], buffer, bytes_written);
// Write the modified data
MXC_FLC->addr = address - (address % 4);
memcpy((void*)&MXC_FLC->data[0], &current_data, 4);
MXC_FLC->cn |= MXC_F_FLC_CN_WR;
/* Wait until flash operation is complete */
while (FLC_Busy());
address += bytes_written;
length -= bytes_written;
buffer += bytes_written;
}
while ( (length >= 4) && ((address & 0xF) != 0) ) {
MXC_FLC->addr = address;
memcpy((void*)&MXC_FLC->data[0], buffer, 4);
MXC_FLC->cn |= MXC_F_FLC_CN_WR;
/* Wait until flash operation is complete */
while (FLC_Busy());
address += 4;
length -= 4;
buffer += 4;
}
if (length >= 16) {
// write in 128-bit bursts while we can
MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
while (length >= 16) {
MXC_FLC->addr = address;
memcpy((void*)&MXC_FLC->data[0], buffer, 16);
MXC_FLC->cn |= MXC_F_FLC_CN_WR;
/* Wait until flash operation is complete */
while (FLC_Busy());
address += 16;
length -= 16;
buffer += 16;
}
// Return to 32-bit writes.
MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
}
while (length >= 4) {
MXC_FLC->addr = address;
memcpy((void*)&MXC_FLC->data[0], buffer, 4);
MXC_FLC->cn |= MXC_F_FLC_CN_WR;
/* Wait until flash operation is complete */
while (FLC_Busy());
address += 4;
length -= 4;
buffer += 4;
}
if (length > 0) {
// Save the data currently in the flash
memcpy(current_data, (void*)(address), 4);
// Modify current_data to insert the data from buffer
memcpy(current_data, buffer, length);
MXC_FLC->addr = address;
memcpy((void*)&MXC_FLC->data[0], current_data, 4);
MXC_FLC->cn |= MXC_F_FLC_CN_WR;
/* Wait until flash operation is complete */
while (FLC_Busy());
}
/* Lock flash */
MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
/* Check access violations */
if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
return E_BAD_STATE;
}
SYS_Flash_Operation();
return E_NO_ERROR;
}
int FLC_EnableInt(uint32_t mask)
{
uint32_t tmp;
mask &= (MXC_F_FLC_INTR_DONEIE | MXC_F_FLC_INTR_AFIE);
if (!mask) {
/* No bits set? Wasn't something we can enable. */
return E_BAD_PARAM;
}
/* Careful with access_fail bit, as it is W0C */
tmp = MXC_FLC->intr | MXC_F_FLC_INTR_AF;
/* Don't lose done flag */
tmp &= ~(MXC_F_FLC_INTR_DONE);
/* Apply enables and write back */
MXC_FLC->intr = (tmp | mask);
return E_NO_ERROR;
}
int FLC_DisableInt(uint32_t mask)
{
uint32_t tmp;
mask &= (MXC_F_FLC_INTR_DONEIE | MXC_F_FLC_INTR_AFIE);
if (!mask) {
/* No bits set? Wasn't something we can disable. */
return E_BAD_PARAM;
}
/* Careful with access_fail bit, as it is W0C */
tmp = MXC_FLC->intr | MXC_F_FLC_INTR_AF;
/* Don't lose done flag */
tmp &= ~(MXC_F_FLC_INTR_DONE);
/* Apply disables and write back */
MXC_FLC->intr = (tmp & ~mask);
return E_NO_ERROR;
}
int FLC_GetFlags(void)
{
return (MXC_FLC->intr & (MXC_F_FLC_INTR_DONE | MXC_F_FLC_INTR_AF));
}
int FLC_ClearFlags(uint32_t mask)
{
mask &= (MXC_F_FLC_INTR_DONE | MXC_F_FLC_INTR_AF);
if (!mask) {
/* No bits set? Wasn't something we can clear. */
return E_BAD_PARAM;
}
// Both bits are write zero clear
MXC_FLC->intr ^= mask;
return E_NO_ERROR;
}
int FLC_UnlockInfoBlock()
{
MXC_FLC->acntl = 0x3a7f5ca3;
MXC_FLC->acntl = 0xa1e34f20;
MXC_FLC->acntl = 0x9608b2c1;
return E_NO_ERROR;
}
int FLC_LockInfoBlock()
{
MXC_FLC->acntl = 0xDEADBEEF;
return E_NO_ERROR;
}

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/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_config.h"
#include "mxc_assert.h"
#include "gpio.h"
#include <stddef.h>
/* **** Definitions **** */
/* **** Globals **** */
static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *);
static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT];
/* **** Functions **** */
int GPIO_Init(void)
{
int i;
int j;
// Initialize call back arrays
for(i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) {
for(j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) {
callback[i][j] = NULL;
}
}
return E_NO_ERROR;
}
/* ************************************************************************** */
/*
* GPIO_EN2 | GPIO_EN1 | GPIO_EN | Function
* --------------|---------------------|---------------------|----------------------
* 0 | 0 | 0 | Alternative 1
* 0 | 1 | 0 | Alternative 2
* 1 | 0 | 0 | Alternative 3
* 1 | 1 | 0 | Alternative 4
* 0 | 0 | 1 | GPIO (default)
*/
int GPIO_Config(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
// Set the GPIO type
switch (cfg->func) {
case GPIO_FUNC_IN:
gpio->out_en_clr = cfg->mask;
gpio->en_set = cfg->mask;
gpio->en1_clr = cfg->mask;
gpio->en2_clr = cfg->mask;
break;
case GPIO_FUNC_OUT:
gpio->out_en_set = cfg->mask;
gpio->en_set = cfg->mask;
gpio->en1_clr = cfg->mask;
gpio->en2_clr = cfg->mask;
break;
case GPIO_FUNC_ALT1:
gpio->en_clr = cfg->mask;
gpio->en1_clr = cfg->mask;
gpio->en2_clr = cfg->mask;
break;
case GPIO_FUNC_ALT2:
gpio->en_clr = cfg->mask;
gpio->en1_set = cfg->mask;
gpio->en2_clr = cfg->mask;
break;
case GPIO_FUNC_ALT3:
#if TARGET==32660
gpio->en_set = cfg->mask;
gpio->en1_set = cfg->mask;
#else
gpio->en_clr = cfg->mask;
gpio->en1_clr = cfg->mask;
gpio->en2_set = cfg->mask;
#endif
break;
case GPIO_FUNC_ALT4:
gpio->en_clr = cfg->mask;
gpio->en1_set = cfg->mask;
gpio->en2_set = cfg->mask;
break;
default:
return E_BAD_PARAM;
}
// Configure the pad
switch (cfg->pad) {
case GPIO_PAD_NONE:
gpio->pad_cfg1 &= ~cfg->mask;
gpio->pad_cfg2 &= ~cfg->mask;
#if TARGET==32660
gpio->ps &= ~cfg->mask;
#endif
break;
case GPIO_PAD_PULL_UP:
gpio->pad_cfg1 |= cfg->mask;
gpio->pad_cfg2 &= ~cfg->mask;
#if TARGET==32660
gpio->ps |= cfg->mask;
#endif
break;
case GPIO_PAD_PULL_DOWN:
gpio->pad_cfg1 &= ~cfg->mask;
gpio->pad_cfg2 |= cfg->mask;
#if TARGET==32660
gpio->ps &= ~cfg->mask;
#endif
break;
default:
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
uint32_t GPIO_InGet(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
return (gpio->in & cfg->mask);
}
/* ************************************************************************** */
void GPIO_OutSet(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
gpio->out_set = cfg->mask;
}
/* ************************************************************************** */
void GPIO_OutClr(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
gpio->out_clr = cfg->mask;
}
/* ************************************************************************** */
uint32_t GPIO_OutGet(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
return (gpio->out & cfg->mask);
}
/* ************************************************************************** */
void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
gpio->out = (gpio->out & ~cfg->mask) | (val & cfg->mask);
}
/* ************************************************************************** */
void GPIO_OutToggle(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
gpio->out ^= cfg->mask;
}
/* ************************************************************************** */
int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
switch (mode) {
case GPIO_INT_LEVEL:
gpio->int_mod &= ~cfg->mask;
break;
case GPIO_INT_EDGE:
gpio->int_mod |= cfg->mask;
break;
default:
return E_BAD_PARAM;
}
switch (pol) {
case GPIO_INT_FALLING: /* GPIO_INT_HIGH */
gpio->int_pol &= ~cfg->mask;
gpio->int_dual_edge &= ~cfg->mask;
break;
case GPIO_INT_RISING: /* GPIO_INT_LOW */
gpio->int_pol |= cfg->mask;
gpio->int_dual_edge &= ~cfg->mask;
break;
case GPIO_INT_BOTH:
gpio->int_dual_edge |= cfg->mask;
break;
default:
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
void GPIO_IntEnable(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
gpio->int_en_set = cfg->mask;
}
/* ************************************************************************** */
void GPIO_IntDisable(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
gpio->int_en_clr = cfg->mask;
}
/* ************************************************************************** */
uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
return (gpio->int_stat & cfg->mask);
}
/* ************************************************************************** */
void GPIO_IntClr(const gpio_cfg_t *cfg)
{
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port);
gpio->int_clr = cfg->mask;
}
/* ************************************************************************** */
void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn func, void *cbdata)
{
uint32_t mask;
unsigned int pin;
mask = cfg->mask;
pin = 0;
while (mask) {
if (mask & 1) {
callback[cfg->port][pin] = func;
cbparam[cfg->port][pin] = cbdata;
}
pin++;
mask >>= 1;
}
}
/* ************************************************************************** */
void GPIO_Handler(unsigned int port)
{
uint32_t stat;
unsigned int pin;
MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES);
mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port);
stat = gpio->int_stat;
gpio->int_clr = stat;
pin = 0;
while (stat) {
if (stat & 1) {
if(callback[port][pin]) {
callback[port][pin](cbparam[port][pin]);
}
}
pin++;
stat >>= 1;
}
}

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216
Project/SDK/Driver/Source/i2s.c
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/**
* @file i2s.c
* @brief Inter-Integrated Sound (I2S) driver implementation.
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
#include <stddef.h>
#include <stdint.h>
#include "mxc_config.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "dma.h"
#include "i2s.h"
#define I2S_CHANNELS 2
#define I2S_WIDTH 16
int dma_channel = -1;
int I2S_Init(const i2s_cfg_t *cfg, void (*dma_ctz_cb)(int, int), const sys_cfg_i2s_t* sys_cfg_i2s)
{
unsigned int i2s_clk, baud;
uint16_t clocks;
uint8_t ctz_en;
int err;
SYS_I2S_Init(sys_cfg_i2s);
/* Setup SPI_MSS as master, mode 0, 16 bit transfers as I2S Requires */
MXC_SPIMSS->ctrl = MXC_F_SPIMSS_CTRL_MMEN;
MXC_SPIMSS->mod = MXC_V_SPIMSS_MOD_NUMBITS_BITS16 | MXC_F_SPIMSS_MOD_SSIO;
MXC_SPIMSS->dma = MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8;
/* Setup I2S register from i2s_cfg_t */
MXC_SPIMSS->i2s_ctrl = cfg->left_justify << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS |
cfg->mono_audio << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS;
/* Determine divisor for baud rate generator */
baud = cfg->sample_rate*I2S_CHANNELS*I2S_WIDTH;
i2s_clk = SYS_I2S_GetFreq(MXC_SPIMSS);
if (i2s_clk/4 < baud) {
return E_BAD_PARAM;
}
clocks = i2s_clk / (2*baud);
MXC_SPIMSS->brg = clocks;
/* Prepare SPIMSS DMA register for DMA setup */
if (dma_ctz_cb == NULL) {
ctz_en = 0;
} else {
ctz_en = 1;
}
/* Initialize DMA */
if (cfg->audio_direction % 2) {
MXC_SPIMSS->dma |= MXC_F_SPIMSS_DMA_TX_DMA_EN | MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR;
if ((err = DMA_Init()) != E_NO_ERROR) {
if (err != E_BAD_STATE) {
return err;
}
}
if ((err = DMA_AcquireChannel()) < 0) {
return err;
}
dma_channel = err;
DMA_ConfigChannel(dma_channel, DMA_PRIO_MEDHIGH,
sys_cfg_i2s->dma_reqsel_tx, 1, DMA_TIMEOUT_512_CLK,
DMA_PRESCALE_DIV64K, DMA_WIDTH_HALFWORD, 1,
DMA_WIDTH_HALFWORD, 0, 16, 0, ctz_en);
if (ctz_en) {
DMA_SetCallback(dma_channel, dma_ctz_cb);
DMA_EnableInterrupt(dma_channel);
}
}
if (cfg->audio_direction / 2) {
MXC_SPIMSS->dma = MXC_F_SPIMSS_DMA_RX_DMA_EN | MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR;
if ((err = DMA_Init()) != E_NO_ERROR) {
if (err != E_BAD_STATE) { //DMA already initialized
return err;
}
}
if ((err = DMA_AcquireChannel()) < 0) {
return err;
}
dma_channel = err;
DMA_ConfigChannel(dma_channel, DMA_PRIO_MEDHIGH,
sys_cfg_i2s->dma_reqsel_rx, 1, DMA_TIMEOUT_512_CLK,
DMA_PRESCALE_DIV64K, DMA_WIDTH_HALFWORD, 0,
DMA_WIDTH_HALFWORD, 1, 8, 0, ctz_en);
if (ctz_en) {
DMA_SetCallback(dma_channel, dma_ctz_cb);
DMA_EnableInterrupt(dma_channel);
}
}
I2S_DMA_SetAddrCnt(cfg->dma_src_addr, cfg->dma_dst_addr, cfg->dma_cnt);
if (cfg->dma_reload_en) {
I2S_DMA_SetReload(cfg->dma_src_addr, cfg->dma_dst_addr, cfg->dma_cnt);
}
if (cfg->start_immediately) {
return I2S_Start();
}
return E_NO_ERROR;
}
int I2S_Shutdown(void)
{
MXC_SPIMSS->ctrl = 0;
MXC_SPIMSS->i2s_ctrl = 0;
MXC_SPIMSS->brg = 0;
MXC_SPIMSS->mod = 0;
MXC_SPIMSS->dma = 0;
SYS_I2S_Shutdown();
return DMA_ReleaseChannel(dma_channel);
}
int I2S_Mute(void)
{
MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE;
return E_NO_ERROR;
}
int I2S_Unmute(void)
{
MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE;
return E_NO_ERROR;
}
int I2S_Pause(void)
{
MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE;
return E_NO_ERROR;
}
int I2S_Unpause(void)
{
MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE;
return E_NO_ERROR;
}
int I2S_Stop(void)
{
MXC_SPIMSS->ctrl &= ~MXC_F_SPIMSS_CTRL_SPIEN;
MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_EN;
return DMA_Stop(dma_channel);
}
int I2S_Start(void)
{
MXC_SPIMSS->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN;
MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_EN;
return DMA_Start(dma_channel);
}
int I2S_DMA_ClearFlags(void)
{
return DMA_ClearFlags(dma_channel);
}
int I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count)
{
return DMA_SetSrcDstCnt(dma_channel, src_addr, dst_addr, count);
}
int I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count)
{
return DMA_SetReload(dma_channel, src_addr, dst_addr, count);
}

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/* *****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
**************************************************************************** */
/* **** Includes **** */
#include <stdint.h>
#include <stdio.h>
#include "mxc_config.h"
#include "mxc_errors.h"
#include "icc_regs.h"
#include "icc.h"
static int ICC_Ready(void)
{
return (MXC_ICC->cache_ctrl & MXC_F_ICC_CACHE_CTRL_CACHE_RDY);
}
int ICC_ID(icc_cache_id_t cid)
{
switch (cid) {
case ICC_CACHE_ID_RELNUM:
return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_RELNUM) >> MXC_F_ICC_CACHE_ID_RELNUM_POS);
case ICC_CACHE_ID_PARTNUM:
return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_PARTNUM) >> MXC_F_ICC_CACHE_ID_PARTNUM_POS);
case ICC_CACHE_ID_CCHID:
return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_CCHID) >> MXC_F_ICC_CACHE_ID_CCHID_POS);
default:
return E_BAD_PARAM;
}
}
void ICC_Enable(void)
{
// Invalidate cache and wait until ready
MXC_ICC->invalidate = 1;
while (!(ICC_Ready()));
// Enable Cache
MXC_ICC->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
}
void ICC_Disable(void)
{
// Disable Cache
MXC_ICC->cache_ctrl &= ~MXC_F_ICC_CACHE_CTRL_CACHE_EN;
}
void ICC_Flush(void)
{
ICC_Disable();
ICC_Enable();
}

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/**
* @file lp.c
* @brief Low power functions
*/
/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $
* $Revision: 47429 $
*
*************************************************************************** */
/***** Includes *****/
#include "lp.h"
#include "pwrseq_regs.h"
#include "mxc_errors.h"
#include "gcr_regs.h"
#include "mxc_config.h"
#include "mxc_sys.h"
#include "flc.h"
#include "tmr_utils.h"
/***** Functions *****/
void LP_ClearWakeStatus(void)
{
MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF;
/* These flags are slow to clear, so block until they do */
while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en));
}
void LP_EnableSRAM3(void)
{
MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF;
}
void LP_DisableSRAM3(void)
{
MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF;
}
void LP_EnableSRAM2(void)
{
MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF;
}
void LP_DisableSRAM2(void)
{
MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF;
}
void LP_EnableSRAM1(void)
{
MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF;
}
void LP_DisableSRAM1(void)
{
MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF;
}
void LP_EnableSRAM0(void)
{
MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF;
}
void LP_DisableSRAM0(void)
{
MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF;
}
void LP_EnableICacheLightSleep(void)
{
MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_ICACHELS);
}
void LP_DisableICacheLightSleep(void)
{
MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_ICACHELS);
}
void LP_EnableSysRAM3LightSleep(void)
{
MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM3LS);
}
void LP_DisableSysRAM3LightSleep(void)
{
MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM3LS);
}
void LP_EnableSysRAM2LightSleep(void)
{
MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM2LS);
}
void LP_DisableSysRAM2LightSleep(void)
{
MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM2LS);
}
void LP_EnableSysRAM1LightSleep(void)
{
MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM1LS);
}
void LP_DisableSysRAM1LightSleep(void)
{
MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM1LS);
}
void LP_EnableSysRAM0LightSleep(void)
{
MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM0LS);
}
void LP_DisableSysRAM0LightSleep(void)
{
MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM0LS);
}
void LP_EnableRTCAlarmWakeup(void)
{
MXC_GCR->pm |= MXC_F_GCR_PM_RTCWKEN;
}
void LP_DisableRTCAlarmWakeup(void)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWKEN;
}
void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins)
{
MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWKEN;
switch(wu_pins->port)
{
case 0: MXC_PWRSEQ->lpwk_en |= wu_pins->mask; break;
}
}
void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins)
{
switch(wu_pins->port)
{
case 0: MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; break;
}
if(MXC_PWRSEQ->lpwk_en == 0)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWKEN;
}
}
void LP_EnterSleepMode(void)
{
// Clear SLEEPDEEP bit
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
// Go into Sleep mode and wait for an interrupt to wake the processor
__WFI();
}
void LP_EnterDeepSleepMode(void)
{
// Set SLEEPDEEP bit
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
// Auto-powerdown 96 MHz oscillator when in deep sleep
MXC_GCR->pm |= MXC_F_GCR_PM_HIRCPD;
// Go into Deepsleep mode and wait for an interrupt to wake the processor
__WFI();
}
void LP_EnterBackupMode(void)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP;
while(1);
}
void LP_EnterShutdownMode(void)
{
MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE;
MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN;
while(1);
}
void LP_SetOperatingVoltage(lp_ovr_t ovr)
{
uint32_t div;
//Set flash wait state for any clock so its not to low after clock changes.
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS);
//set the OVR bits
MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR);
MXC_PWRSEQ->lp_ctrl |= ovr;
//Set LVE bit
if(ovr == LP_OVR_0_9){
MXC_FLC->cn |= MXC_F_FLC_CN_LVE;
}
else{
MXC_FLC->cn &= ~(MXC_F_FLC_CN_LVE);
}
// Update SystemCoreClock variable
SystemCoreClockUpdate();
// Get the clock divider
div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
//Set Flash Wait States
if(ovr == LP_OVR_0_9){
if(div == 0){
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
} else{
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
}
} else if( ovr == LP_OVR_1_0){
if(div == 0){
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
} else{
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
}
} else {
if(div == 0){
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS);
} else if(div == 1){
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
} else{
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
}
}
}
void LP_EnableSRamRet0(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
}
void LP_DisableSRamRet0(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0;
}
void LP_EnableSRamRet1(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
}
void LP_DisableSRamRet1(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1;
}
void LP_EnableSRamRet2(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
}
void LP_DisableSRamRet2(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2;
}
void LP_EnableSRamRet3(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
}
void LP_DisableSRamRet3(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3;
}
void LP_EnableBlockDetect(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
}
void LP_DisableBlockDetect(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS;
}
void LP_EnableRamRetReg(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
}
void LP_DisableRamRetReg(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN;
}
void LP_EnableFastWk(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
}
void LP_DisableFastWk(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN;
}
void LP_EnableBandGap(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
}
void LP_DisableBandGap(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF;
}
void LP_EnableVCorePORSignal(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
}
void LP_DisableVCorePORSignal(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS;
}
void LP_EnableLDO(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
}
void LP_DisableLDO(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS;
}
void LP_EnableVCoreSVM(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
}
void LP_DisableVCoreSVM(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS;
}
void LP_EnableVDDIOPorMonitoF(void){
MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
}
void LP_DisableVDDIOPorMonitor(void){
MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS;
}

50
Project/SDK/Driver/Source/mxc_assert.c
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/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
*
*************************************************************************** */
/* **** Includes **** */
#include "mxc_config.h"
/* **** Definitions **** */
/* **** Globals *****/
/* **** Functions **** */
/* ************************************************************************** */
__weak void mxc_assert(const char *expr, const char *file, int line)
{
while (1) {}
}

179
Project/SDK/Driver/Source/mxc_delay.c
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/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Id: mxc_delay.c 36202 2018-07-16 21:06:02Z michael.bayern $
*
*************************************************************************** */
/* **** Includes **** */
#include <stdint.h>
#include "mxc_config.h"
#include "mxc_delay.h"
/* **** File Scope Variables **** */
static uint32_t ctrl_save;
static volatile uint64_t compare_value = 0;
static volatile uint64_t curr_value;
static volatile uint32_t reload;
static void mxc_delay_init(unsigned long us);
extern void SysTick_Handler(void);
/* ************************************************************************** */
__weak void SysTick_Handler(void)
{
mxc_delay_handler();
}
/* ************************************************************************** */
void mxc_delay_handler(void)
{
// Check and clear overflow flag
if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) {
// Is a delay in progress?
if(compare_value != 0) {
curr_value += reload;
if(curr_value >= compare_value) {
mxc_delay_stop();
}
}
}
}
/* ************************************************************************** */
static void mxc_delay_init(unsigned long us)
{
uint32_t starttick, ticks;
// Record the current tick value and clear the overflow flag
starttick = SysTick->VAL;
// Save the state of control register (and clear the overflow flag)
ctrl_save = SysTick->CTRL & ~SysTick_CTRL_COUNTFLAG_Msk;
// If the SysTick is not running, configure and start it
if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
SysTick->LOAD = SysTick_LOAD_RELOAD_Msk;
SysTick->VAL = SysTick_VAL_CURRENT_Msk;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk;
starttick = SysTick_VAL_CURRENT_Msk;
reload = SysTick_LOAD_RELOAD_Msk + 1;
} else {
reload = SysTick->LOAD + 1; // get the current reload value
}
// Calculate the total number of ticks to delay
ticks = (uint32_t)(((uint64_t)us * (uint64_t)SystemCoreClock) / 1000000);
compare_value = ticks + (reload - starttick);
curr_value = 0;
if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
}
/* ************************************************************************** */
int mxc_delay_start(unsigned long us)
{
// Check if timeout currently ongoing
if (compare_value != 0) {
return E_BUSY;
}
// Check if there is nothing to do
if (us == 0) {
return E_NO_ERROR;
}
// Calculate the necessary delay and start the timer
mxc_delay_init(us);
// Enable SysTick interrupt if necessary
if (compare_value != 0) {
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int mxc_delay_check(void)
{
// Check if timeout currently ongoing
if (compare_value == 0) {
return E_NO_ERROR;
}
if((curr_value + (reload - SysTick->VAL)) >= compare_value) {
mxc_delay_stop();
return E_NO_ERROR;
}
return E_BUSY;
}
/* ************************************************************************** */
void mxc_delay_stop(void)
{
SysTick->CTRL = ctrl_save;
compare_value = 0;
}
/* ************************************************************************** */
int mxc_delay(unsigned long us)
{
// Check if timeout currently ongoing
if (compare_value != 0) {
return E_BUSY;
}
// Check if there is nothing to do
if (us == 0) {
return E_NO_ERROR;
}
// Calculate the necessary delay and start the timer
mxc_delay_init(us);
// Wait until the total number of ticks exceeds the compare value.
while ((curr_value + (reload - SysTick->VAL)) < compare_value) {
// If SysTick interrupts are enabled, COUNTFLAG will never be set here and
// curr_value will be incremented in the ISR. If SysTick interrupts are
// disabled, curr_value is incremented here.
if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) {
curr_value += reload;
}
}
mxc_delay_stop();
return E_NO_ERROR;
}

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Project/SDK/Driver/Source/mxc_lock.c
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/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
*************************************************************************** */
/* Define to prevent redundant inclusion */
#ifndef _MXC_LOCK_H_
#define _MXC_LOCK_H_
/* **** Includes **** */
#include "mxc_config.h"
#include "mxc_lock.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined ( __ICCARM__ )
#define MXC_LOCK_CAST unsigned int volatile *
#else
#define MXC_LOCK_CAST volatile unsigned long *
#endif
/* ************************************************************************** */
int mxc_get_lock(uint32_t *lock, uint32_t value)
{
do {
// Return if the lock is taken by a different thread
if(__LDREXW((MXC_LOCK_CAST)lock) != 0) {
return E_BUSY;
}
// Attempt to take the lock
} while(__STREXW(value, (MXC_LOCK_CAST)lock) != 0);
// Do not start any other memory access until memory barrier is complete
__DMB();
return E_NO_ERROR;
}
/* ************************************************************************** */
void mxc_free_lock(uint32_t *lock)
{
// Ensure memory operations complete before releasing lock
__DMB();
*lock = 0;
}
#ifdef __cplusplus
}
#endif
#endif /* _MXC_LOCK_H_ */

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Project/SDK/Driver/Source/mxc_pins.c
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/**
* @file mxc_pins.c
* @brief This file contains constant pin configurations for the peripherals.
*/
/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
**************************************************************************** */
/* **** Includes **** */
#include "gpio.h"
#include "mxc_config.h"
/**
* @ingroup MXC_pins
* @{
*/
/* **** TIMER pins **** */
const gpio_cfg_t gpio_cfg_tmr0 = { PORT_0, PIN_3, GPIO_FUNC_ALT3, GPIO_PAD_NONE };
/* **** UART pins **** */
const gpio_cfg_t gpio_cfg_uart0rtscts = { PORT_0, (PIN_6 | PIN_7), GPIO_FUNC_ALT2, GPIO_PAD_NONE };
const gpio_cfg_t gpio_cfg_uart0a = { PORT_0, (PIN_4 | PIN_5), GPIO_FUNC_ALT2, GPIO_PAD_NONE };
const gpio_cfg_t gpio_cfg_uart1rtscts = { PORT_0, (PIN_12 | PIN_13), GPIO_FUNC_ALT2, GPIO_PAD_NONE };
const gpio_cfg_t gpio_cfg_uart1a = { PORT_0, (PIN_10 | PIN_11), GPIO_FUNC_ALT2, GPIO_PAD_NONE };
const gpio_cfg_t gpio_cfg_uart1b = { PORT_0, (PIN_0 | PIN_1), GPIO_FUNC_ALT3, GPIO_PAD_NONE };
const gpio_cfg_t gpio_cfg_uart1c = { PORT_0, (PIN_6 | PIN_7), GPIO_FUNC_ALT3, GPIO_PAD_NONE };
/* **** I2C pins **** */
const gpio_cfg_t gpio_cfg_i2c0 = { PORT_0, (PIN_8 | PIN_9), GPIO_FUNC_ALT1, GPIO_PAD_PULL_UP };
const gpio_cfg_t gpio_cfg_i2c1 = { PORT_0, (PIN_2 | PIN_3), GPIO_FUNC_ALT1, GPIO_PAD_PULL_UP };
/* **** SPI/I2S pins **** */
const gpio_cfg_t gpio_cfg_spi17y = { PORT_0, (PIN_4 | PIN_5 | PIN_6 | PIN_7), GPIO_FUNC_ALT1, GPIO_PAD_NONE }; // SPI0A
const gpio_cfg_t gpio_cfg_spimss1a = { PORT_0, (PIN_10 | PIN_11 | PIN_12 | PIN_13) , GPIO_FUNC_ALT1, GPIO_PAD_NONE }; // SPI1A
const gpio_cfg_t gpio_cfg_spimss1b = { PORT_0, (PIN_0 | PIN_1 | PIN_2 | PIN_3 ) , GPIO_FUNC_ALT2, GPIO_PAD_NONE }; // SPI1B
const gpio_cfg_t gpio_cfg_i2s1a = { PORT_0, (PIN_10 | PIN_11 | PIN_12 | PIN_13) , GPIO_FUNC_ALT1, GPIO_PAD_NONE }; // same port as SPI1A
const gpio_cfg_t gpio_cfg_i2s1b = { PORT_0, (PIN_0 | PIN_1 | PIN_2 | PIN_3 ) , GPIO_FUNC_ALT2, GPIO_PAD_NONE }; // same port as SPI1B
/* **** SWD pins **** */
const gpio_cfg_t gpio_cfg_swd = { PORT_0, (PIN_0 | PIN_1 | PIN_2 | PIN_3 ) , GPIO_FUNC_ALT1, GPIO_PAD_NONE };
/* **** RTC pins **** */
const gpio_cfg_t gpio_cfg_rtc = { PORT_0, PIN_2, GPIO_FUNC_ALT3, GPIO_PAD_NONE };
/**@} end of ingroup MXC_pins*/

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Project/SDK/Driver/Source/mxc_sys.c
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/**
* @file mxc_sys.c
* @brief System level setup help
*/
/*******************************************************************************
* Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2020-01-17 08:38:51 -0600 (Fri, 17 Jan 2020) $
* $Revision: 50772 $
*
******************************************************************************/
#include <stddef.h>
#include "mxc_config.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "gpio.h"
#include "mxc_pins.h"
#include "gcr_regs.h"
#include "tmr_regs.h"
#include "pwrseq_regs.h"
#include "spi17y_regs.h"
#include "spimss_regs.h"
#include "mxc_delay.h"
#include "rtc.h"
/**
* @ingroup MXC_sys
* @{
*/
/***** Definitions *****/
#define SYS_CLOCK_TIMEOUT MXC_DELAY_MSEC(1)
#define SYS_RTC_CLK 32768UL
/***** Functions ******/
static int SYS_Clock_Timeout(uint32_t ready)
{
// Start timeout, wait for ready
mxc_delay_start(SYS_CLOCK_TIMEOUT);
do {
if (MXC_GCR->clkcn & ready) {
mxc_delay_stop();
return E_NO_ERROR;
}
} while (mxc_delay_check() == E_BUSY);
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_Clock_Select(sys_system_clock_t clock, mxc_tmr_regs_t* tmr)
{
uint32_t current_clock,ovr, div;
// Save the current system clock
current_clock = MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL;
// Set FWS higher than what the minimum for the fastest clock is
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS);
switch(clock) {
case SYS_CLOCK_NANORING:
// Set NANORING clock as System Clock
MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_NANORING);
break;
case SYS_CLOCK_HFXIN:
// Enable 32k Oscillator
MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN;
// Check if 32k clock is ready
if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_X32K_RDY) != E_NO_ERROR) {
return E_TIME_OUT;
}
MXC_RTC->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers
// Set 32k clock as System Clock
MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HFXIN);
break;
case SYS_CLOCK_HFXIN_DIGITAL:
// Enable 32k Oscillator
MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN;
// Check if 32k clock is ready
if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_X32K_RDY) != E_NO_ERROR) {
return E_TIME_OUT;
}
MXC_RTC->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers
MXC_RTC->oscctrl |= MXC_F_RTC_OSCCTRL_BYPASS; // To allow square wave driven on 32KIN
// Set 32k clock as System Clock
MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HFXIN);
break;
case SYS_CLOCK_HIRC:
// Enable 96MHz Clock
MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_HIRC_EN;
// Check if 96MHz clock is ready
if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_HIRC_RDY) != E_NO_ERROR) {
return E_TIME_OUT;
}
// Set 96MHz clock as System Clock
MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HIRC);
break;
default:
return E_BAD_PARAM;
}
// Wait for system clock to be ready
if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_CKRDY) != E_NO_ERROR) {
// Restore the old system clock if timeout
MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, current_clock);
return E_TIME_OUT;
}
// Disable other clocks
switch(clock) {
case SYS_CLOCK_NANORING:
MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN);
break;
case SYS_CLOCK_HFXIN:
MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN);
break;
case SYS_CLOCK_HFXIN_DIGITAL:
MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN);
break;
case SYS_CLOCK_HIRC:
//Don't disable 32KHz clock
break;
}
// Update the system core clock
SystemCoreClockUpdate();
// Get the clock divider
div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
//get ovr setting
ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR);
//Set flash wait settings
if(ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V){
if(div == 0){
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
} else{
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
}
} else if( ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V){
if(div == 0){
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
} else{
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
}
} else {
if(div == 0){
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS);
} else if(div == 1){
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS);
} else{
MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS);
}
}
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_ClockEnable_X32K(sys_cfg_rtc_t *sys_cfg)
{
// Enable 32k Oscillator
MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN;
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_ClockDisable_X32K()
{
// Disable 32k Oscillator
MXC_GCR->clkcn &= (~MXC_F_GCR_CLKCN_X32K_EN);
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_UART_Init(mxc_uart_regs_t *uart, const sys_cfg_uart_t* sys_cfg)
{
// Configure GPIO for UART
if (uart == MXC_UART0) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_UART0);
if(sys_cfg->map == MAP_A){
GPIO_Config(&gpio_cfg_uart0a);
}
else{
return E_BAD_PARAM;
}
if(sys_cfg->flow_flag == UART_FLOW_ENABLE){
GPIO_Config(&gpio_cfg_uart0rtscts);
}
}
if (uart == MXC_UART1) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_UART1);
if(sys_cfg->map == MAP_A){
GPIO_Config(&gpio_cfg_uart1a);
}
else if(sys_cfg->map == MAP_B){
GPIO_Config(&gpio_cfg_uart1b);
}
else if(sys_cfg->map == MAP_C){
GPIO_Config(&gpio_cfg_uart1c);
}
else{
return E_BAD_PARAM;
}
if(sys_cfg->flow_flag == UART_FLOW_ENABLE){
GPIO_Config(&gpio_cfg_uart1rtscts);
}
}
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_UART_Shutdown(mxc_uart_regs_t *uart)
{
if (uart == MXC_UART0) {
SYS_ClockDisable(SYS_PERIPH_CLOCK_UART0);
}
else if (uart == MXC_UART1) {
SYS_ClockDisable(SYS_PERIPH_CLOCK_UART1);
}
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_I2C_Init(mxc_i2c_regs_t *i2c, const sys_cfg_i2c_t* sys_cfg)
{
// Configure GPIO for I2C
if (i2c == MXC_I2C0) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_I2C0);
GPIO_Config(&gpio_cfg_i2c0);
} else if (i2c == MXC_I2C1) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_I2C1);
GPIO_Config(&gpio_cfg_i2c1);
} else {
return E_NO_DEVICE;
}
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_I2C_Shutdown(mxc_i2c_regs_t *i2c)
{
if (i2c == MXC_I2C0) {
gpio_cfg_t cfg = { gpio_cfg_i2c0.port, gpio_cfg_i2c0.mask, GPIO_FUNC_IN, GPIO_PAD_NONE };
SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C0);
GPIO_Config(&cfg);
} else if (i2c == MXC_I2C1) {
gpio_cfg_t cfg = { gpio_cfg_i2c1.port, gpio_cfg_i2c1.mask, GPIO_FUNC_IN, GPIO_PAD_NONE };
SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C1);
GPIO_Config(&cfg);
} else {
return E_NO_DEVICE;
}
// Clear registers
i2c->ctrl = 0;
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_DMA_Init(void)
{
SYS_ClockEnable(SYS_PERIPH_CLOCK_DMA);
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_DMA_Shutdown(void)
{
SYS_ClockDisable(SYS_PERIPH_CLOCK_DMA);
return E_NO_ERROR;
}
/* ************************************************************************ */
unsigned SYS_I2C_GetFreq(mxc_i2c_regs_t *i2c)
{
return PeripheralClock;
}
/* ************************************************************************ */
unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr)
{
return PeripheralClock;
}
/* ************************************************************************ */
void SYS_Reset0(sys_reset0_t reset)
{
MXC_GCR->rstr0 = reset;
while(MXC_GCR->rstr0 != 0x0) {}
}
/* ************************************************************************ */
void SYS_Reset1(sys_reset1_t reset)
{
MXC_GCR->rstr1 = reset;
while(MXC_GCR->rstr0 != 0x0) {}
}
/* ************************************************************************ */
void SYS_ClockDisable(sys_periph_clock_t clock)
{
/* The sys_periph_clock_t enum uses bit 27 (an unused bit in both perkcn registers)
to determine which of the two perckcn registers to write to. */
if (clock & (1<<27)) {
clock &= ~(1<<27);
MXC_GCR->perckcn1 |= clock;
} else {
MXC_GCR->perckcn0 |= clock;
}
}
/* ************************************************************************ */
void SYS_ClockEnable(sys_periph_clock_t clock)
{
/* The sys_periph_clock_t enum uses bit 27 (an unused bit in both perkcn registers)
to determine which of the two perckcn registers to write to. */
if (clock & (1<<27)) {
clock &= ~(1<<27);
MXC_GCR->perckcn1 &= ~(clock);
} else {
MXC_GCR->perckcn0 &= ~(clock);
}
}
/* ************************************************************************ */
#if defined (__ICCARM__)
#pragma optimize=none /* Turn off optimizations for next function */
#elif defined ( __CC_ARM )
/* Keil MDK - Turn off optimizations after saving current state */
#pragma push /* Save current optimization level */
#pragma O0 /* Optimization level 0 */
#elif ( __GNUC__ )
/* GCC - Turn off optimizations after saving current state */
#pragma GCC push_options /* Save current optimization level */
#pragma GCC optimize ("O0") /* Set optimization level to none for this function */
#endif
void SYS_Flash_Operation(void)
{
volatile uint32_t *line_addr;
volatile uint32_t __attribute__ ((unused)) line;
// Clear the cache
MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
// Clear the line fill buffer
line_addr = (uint32_t*)(MXC_FLASH_MEM_BASE);
line = *line_addr;
line_addr = (uint32_t*)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE);
line = *line_addr;
}
/* Set optimizations to the previous level. For IAR, the optimize none applies
only to the next function. Keil MDK and GNUC need state restored. */
#if defined ( __CC_ARM )
#pragma pop /* Restore Kiel MDK optimizations to saved level */
#elif defined ( __GNUC__ )
#pragma GCC pop_options /* Restore GCC optimization level */
#endif
/* ************************************************************************ */
int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t* sys_cfg)
{
if(sys_cfg) {
if(sys_cfg->out_en) {
if (tmr == MXC_TMR0) {
GPIO_Config(&gpio_cfg_tmr0);
}
}
}
if (tmr == MXC_TMR0) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_T0);
}
else if (tmr == MXC_TMR1) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_T1);
}
else if (tmr == MXC_TMR2) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_T2);
}
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg)
{
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_FLC_Shutdown(void)
{
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_SPI17Y_Init(mxc_spi17y_regs_t *spi, const sys_cfg_spi17y_t* sys_cfg)
{
// Configure GPIO for spi17y
if (spi == MXC_SPI17Y) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_SPI17Y);
if(sys_cfg->map == MAP_A){
GPIO_Config(&gpio_cfg_spi17y);
MXC_GPIO0->ds |= 0x0003BF0;
}else{
return E_BAD_PARAM;
}
} else {
return E_NO_DEVICE;
}
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi)
{
if (spi == MXC_SPI17Y) {
SYS_ClockDisable(SYS_PERIPH_CLOCK_SPI17Y);
}
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_SPIMSS_Init(mxc_spimss_regs_t *spi, const sys_cfg_spimss_t* sys_cfg)
{
// Configure GPIO for spimss
if (spi == MXC_SPIMSS) {
SYS_ClockEnable(SYS_PERIPH_CLOCK_SPIMSS);
if(sys_cfg->map == MAP_A){
GPIO_Config(&gpio_cfg_spimss1a); // SPI1A chosen
}else if(sys_cfg->map == MAP_B){
GPIO_Config(&gpio_cfg_spimss1b); // SPI1B chosen
}else{
return E_BAD_PARAM;
}
} else {
return E_NO_DEVICE;
}
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
{
if(spi == MXC_SPIMSS) {
SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS);
}
return E_NO_ERROR;
}
int SYS_TMR_Shutdown(mxc_tmr_regs_t *tmr)
{
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_I2S_Init(const sys_cfg_i2s_t* sys_cfg)
{
if(sys_cfg->map == MAP_A) {
GPIO_Config(&gpio_cfg_i2s1a);
}
else if(sys_cfg->map == MAP_B) {
GPIO_Config(&gpio_cfg_i2s1b);
}
else {
return E_BAD_PARAM;
}
SYS_ClockEnable(SYS_PERIPH_CLOCK_SPIMSS);
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_I2S_Shutdown(void)
{
SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS);
return E_NO_ERROR;
}
/* ************************************************************************ */
int SYS_I2S_GetFreq(mxc_spimss_regs_t *spimss)
{
return PeripheralClock;
}
/* ************************************************************************ */
int SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg)
{
GPIO_Config(&gpio_cfg_rtc);
return E_NO_ERROR;
}
/* ************************************************************************ */
uint32_t SYS_SysTick_GetFreq(void)
{
// Determine is using internal (SystemCoreClock) or external (32768) clock
if ( (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) || !(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
return SystemCoreClock;
} else {
return SYS_RTC_CLK;
}
}
/* ************************************************************************ */
int SYS_SysTick_Config(uint32_t ticks, int clk_src, mxc_tmr_regs_t* tmr)
{
if(ticks == 0)
return E_BAD_PARAM;
// If SystemClock, call default CMSIS config and return
if (clk_src) {
return SysTick_Config(ticks);
} else { /* External clock source requested
enable RTC clock in run mode*/
RTC_Init(MXC_RTC, 0, 0, NULL);
RTC_EnableRTCE(MXC_RTC);
// Disable SysTick Timer
SysTick->CTRL = 0;
// Check reload value for valid
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) {
// Reload value impossible
return E_BAD_PARAM;
}
// set reload register
SysTick->LOAD = ticks - 1;
// set Priority for Systick Interrupt
NVIC_SetPriority(SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
// Load the SysTick Counter Value
SysTick->VAL = 0;
// Enable SysTick IRQ and SysTick Timer leaving clock source as external
SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
// Function successful
return E_NO_ERROR;
}
}
/* ************************************************************************ */
void SYS_SysTick_Disable(void)
{
SysTick->CTRL = 0;
}
/* ************************************************************************ */
int SYS_SysTick_Delay(uint32_t ticks)
{
uint32_t cur_ticks, num_full, num_remain, previous_ticks, num_subtract, i;
uint32_t reload, value, ctrl; // save/restore variables
if(ticks == 0)
return E_BAD_PARAM;
// If SysTick is not enabled we can take it for our delay
if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) {
// Save current state in case it's disabled but already configured, restore at return.
reload = SysTick->LOAD;
value = SysTick->VAL;
ctrl = SysTick->CTRL;
// get the number of ticks less than max RELOAD.
num_remain = ticks % SysTick_LOAD_RELOAD_Msk;
/* if ticks is < Max SysTick Reload num_full will be 0, otherwise it will
give us the number of max SysTicks cycles required */
num_full = (ticks - 1) / SysTick_LOAD_RELOAD_Msk;
// Do the required full systick countdowns
if (num_full) {
// load the max count value into systick
SysTick->LOAD = SysTick_LOAD_RELOAD_Msk;
// load the starting value
SysTick->VAL = 0;
// enable SysTick counter with SystemClock source internal, immediately forces LOAD register into VAL register
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
// CountFlag will get set when VAL reaches zero
for (i = num_full; i > 0; i--) {
do {
cur_ticks = SysTick->CTRL;
} while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk));
}
// Disable systick
SysTick->CTRL = 0;
}
// Now handle the remainder of ticks
if (num_remain) {
SysTick->LOAD = num_remain;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
// wait for countflag to get set
do {
cur_ticks = SysTick->CTRL;
} while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk));
// Disable systick
SysTick->CTRL = 0;
}
// restore original state of SysTick and return
SysTick->LOAD = reload;
SysTick->VAL = value;
SysTick->CTRL = ctrl;
return E_NO_ERROR;
} else { /* SysTick is enabled
When SysTick is enabled count flag can not be used
and the reload can not be changed.
Do not read the CTRL register -> clears count flag */
// Get the reload value for wrap/reload case
reload = SysTick->LOAD;
// Read the starting systick value
previous_ticks = SysTick->VAL;
do {
// get current SysTick value
cur_ticks = SysTick->VAL;
// Check for wrap/reload of timer countval
if (cur_ticks > previous_ticks) {
// subtract count to 0 (previous_ticks) and wrap (reload value - cur_ticks)
num_subtract = (previous_ticks + (reload - cur_ticks));
} else { /* standard case (no wrap)
subtract off the number of ticks since last pass */
num_subtract = (previous_ticks - cur_ticks);
}
// check to see if we are done.
if (num_subtract >= ticks)
return E_NO_ERROR;
else
ticks -= num_subtract;
// cur_ticks becomes previous_ticks for next timer read.
previous_ticks = cur_ticks;
} while (ticks > 0);
// Should not ever be reached
return E_NO_ERROR;
}
}
/* ************************************************************************ */
void SYS_SysTick_DelayUs(uint32_t us)
{
SYS_SysTick_Delay((uint32_t)(((uint64_t)SYS_SysTick_GetFreq() * us) / 1000000));
}
/* ************************************************************************ */
int SYS_WDT_Init(mxc_wdt_regs_t* wdt, const sys_cfg_wdt_t* sys_cfg)
{
return E_NO_ERROR;
}
/**@} end of ingroup MXC_sys*/

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Project/SDK/Driver/Source/nvic_table.c
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/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $
* $Revision: 43696 $
*
**************************************************************************** */
#include "mxc_config.h"
#include <string.h>
#include "nvic_table.h"
#if !defined (NVIC_USER_IRQ_OFFSET)
#define NVIC_USER_IRQ_OFFSET 16 /**! Offset for device specific IRQs */
#endif
/* RAM vector_table needs to be aligned with the size of the vector table */
#if defined ( __ICCARM__ )
#pragma data_alignment = 512
#else
__attribute__((aligned(512)))
#endif
static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
void NVIC_SetRAM(void)
{
#if defined (__ICCARM__)
extern void (* const __isr_vector[])(void);
#else
/* should be defined in starup_<device>.S */
extern uint32_t __isr_vector[97];
#endif
memcpy(&ramVectorTable, &__isr_vector, sizeof(ramVectorTable));
SCB->VTOR = (uint32_t)&ramVectorTable;
}
void NVIC_SetVector(IRQn_Type irqn, void(*irq_handler)(void))
{
int index = irqn + 16; /* offset for externals */
/* If not copied, do copy */
if (SCB->VTOR != (uint32_t)&ramVectorTable) {
NVIC_SetRAM();
}
ramVectorTable[index] = irq_handler;
NVIC_EnableIRQ(irqn);
}
uint32_t NVIC_GetVector(IRQn_Type irqn)
{
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)irqn + NVIC_USER_IRQ_OFFSET];
}

419
Project/SDK/Driver/Source/rtc.c
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/* ****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
**************************************************************************** */
#include "mxc_config.h"
#include "rtc_regs.h"
#include "rtc.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "gpio_regs.h"
#include "mxc_errors.h"
#if TARGET == 32650
#include "pwrseq_regs.h"
#endif
#define RTC_CTRL_RESET_DEFAULT (0x0000UL)
#define RTC_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_CTRL_BUSY)
#define RTC_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_CTRL_RTCE)
#define BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit
// *****************************************************************************
int RTC_EnableTimeofdayInterrupt(mxc_rtc_regs_t *rtc)
{
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_ADE; // Enable Time-of-day Interrupt
return E_SUCCESS;
}
// *****************************************************************************
int RTC_DisableTimeofdayInterrupt(mxc_rtc_regs_t *rtc)
{
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_CTRL_ADE; // Disable Time-of-day Interrupt
if (RTC_CheckBusy()) {
return E_BUSY;
}
return E_SUCCESS;
}
// *****************************************************************************
int RTC_EnableSubsecondInterrupt(mxc_rtc_regs_t *rtc)
{
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_ASE; // Enable Sub-Second Interrupt
return E_SUCCESS;
}
// *****************************************************************************
int RTC_DisableSubsecondInterrupt(mxc_rtc_regs_t *rtc)
{
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_CTRL_ASE; // Alarm Sub-Second Interrupt disabled
if (RTC_CheckBusy()) {
return E_BUSY;
}
return E_SUCCESS;
}
// *****************************************************************************
int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras)
{
// ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0);
if(RTC_DisableTimeofdayInterrupt(rtc) == E_BUSY) {
return E_BUSY;
}
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ras = (ras << MXC_F_RTC_RAS_RAS_POS) & MXC_F_RTC_RAS_RAS;
if(RTC_EnableTimeofdayInterrupt(rtc) == E_BUSY) {
return E_BUSY;
}
return E_SUCCESS;
}
// *****************************************************************************
int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa)
{
// ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0);
if(RTC_DisableSubsecondInterrupt(rtc) == E_BUSY) {
return E_BUSY;
}
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->rssa = (rssa << MXC_F_RTC_RSSA_RSSA_POS) & MXC_F_RTC_RSSA_RSSA;
if(RTC_EnableSubsecondInterrupt(rtc) == E_BUSY) {
return E_BUSY;
}
return E_SUCCESS;
}
// *****************************************************************************
int RTC_EnableRTCE(mxc_rtc_regs_t *rtc)
{
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers
if (RTC_CheckBusy()) {
return E_BUSY;
}
// Can only write if WE=1 and BUSY=0
rtc->ctrl |= MXC_F_RTC_CTRL_RTCE; // setting RTCE = 1
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Prevent Writing...
return E_SUCCESS;
}
// *****************************************************************************
int RTC_DisableRTCE(mxc_rtc_regs_t *rtc)
{
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers
if (RTC_CheckBusy()) {
return E_BUSY;
}
// Can only write if WE=1 and BUSY=0
rtc->ctrl &= ~MXC_F_RTC_CTRL_RTCE; // setting RTCE = 0
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Prevent Writing...
return E_SUCCESS;
}
// *****************************************************************************
int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint8_t ssec, sys_cfg_rtc_t *sys_cfg)
{
#if((TARGET == 32650) || (TARGET == 32660))
SYS_ClockEnable_X32K(sys_cfg);
#else
SYS_RTCClockEnable(sys_cfg);
#endif
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl = MXC_F_RTC_CTRL_WE; // Allow Writes
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl = RTC_CTRL_RESET_DEFAULT; // Start with a Clean Register
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_WE; // Set Write Enable, allow writing to reg.
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ssec = ssec;
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->sec = sec;
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Prevent Writing...
return E_SUCCESS;
}
// *****************************************************************************
int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft,
rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg)
{
SYS_RTC_SqwavInit(sys_cfg); // Set the Output pins for the squarewave.
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers
if (RTC_CheckBusy()) {
return E_BUSY;
}
if (sqe == SQUARE_WAVE_ENABLED) {
if (ft == F_32KHZ){ // if 32KHz output is selected...
rtc->oscctrl |= MXC_F_RTC_OSCCTRL_OUT32K; // Enable 32KHz wave
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_SQE; // Enable output on the pin
} else { // if 1Hz, 512Hz, 4KHz output is selected
rtc->oscctrl &= ~MXC_F_RTC_OSCCTRL_OUT32K; // Must make sure that the 32KHz is disabled
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~(MXC_F_RTC_CTRL_FT | MXC_F_RTC_CTRL_X32KMD);
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= (MXC_F_RTC_CTRL_SQE | ft | x32kmd); // Enable Sq. wave,
}
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_RTCE; // Enable Real Time Clock
} else { // Turn off the square wave output on the pin
rtc->oscctrl &= ~MXC_F_RTC_OSCCTRL_OUT32K; // Must make sure that the 32KHz is disabled
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_CTRL_SQE; // No sq. wave output
}
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Disable Writing to register
return E_SUCCESS;
}
// *****************************************************************************
int RTC_Trim(mxc_rtc_regs_t *rtc, int8_t trim)
{
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl |= MXC_F_RTC_CTRL_WE;
if (RTC_CheckBusy()) {
return E_BUSY;
}
MXC_SETFIELD(rtc->trim, MXC_F_RTC_TRIM_TRIM, trim << MXC_F_RTC_TRIM_TRIM_POS);
if (RTC_CheckBusy()) {
return E_BUSY;
}
rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Disable Writing to register
return E_SUCCESS;
}
// *****************************************************************************
int RTC_CheckBusy(void)
{
// Time-out transfer if it takes > BUSY_TIMEOUT microseconds
mxc_delay_start(MXC_DELAY_USEC(BUSY_TIMEOUT));
while (RTC_IS_BUSY) {
if (mxc_delay_check() != E_BUSY){
return E_BUSY;
}
}
mxc_delay_stop();
return E_SUCCESS;
}
// *****************************************************************************
int RTC_GetFlags(void)
{
return MXC_RTC->ctrl & (MXC_F_RTC_CTRL_ALDF | MXC_F_RTC_CTRL_ALSF | MXC_F_RTC_CTRL_RDY);
}
// *****************************************************************************
int RTC_ClearFlags(int flags)
{
if (RTC_CheckBusy()) {
return E_BUSY;
}
MXC_RTC->ctrl &= ~(flags & (MXC_F_RTC_CTRL_ALDF | MXC_F_RTC_CTRL_ALSF | MXC_F_RTC_CTRL_RDY));
return E_SUCCESS;
}
// *****************************************************************************
int RTC_GetSubSecond(void)
{
#if TARGET == 32650
int ssec;
if(ChipRevision > 0xA1){
ssec = ((MXC_PWRSEQ->lpcn >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF);
}else{
ssec = MXC_RTC->ssec;
}
return ssec;
#else
return MXC_RTC->ssec;
#endif
}
// *****************************************************************************
int RTC_GetSecond(void)
{
return MXC_RTC->sec;
}
// *****************************************************************************
int RTC_GetTime(uint32_t* sec, uint32_t* subsec)
{
uint32_t temp_sec;
do {
// Check if an update is about to happen.
if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {
return E_BUSY;
}
// Read the seconds count.
temp_sec = RTC_GetSecond();
// Check if an update is about to happen.
if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {
return E_BUSY;
}
// Read the sub-seconds count.
*subsec = RTC_GetSubSecond();
// Check if an update is about to happen.
if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {
return E_BUSY;
}
// Read the seconds count.
*sec = RTC_GetSecond();
// Repeat until a steady state is reached.
} while (temp_sec != *sec);
return E_NO_ERROR;
}
// *****************************************************************************
int RTC_IsEnabled(void)
{
return RTC_IS_ENABLED;
}

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/**
* @file spi.c
* @brief This file contains the function implementations for the
* Serial Peripheral Interface (SPIMSS) peripheral module.
*/
/* *****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $
* $Revision: 38560 $
*
**************************************************************************** */
/* **** Includes **** */
#include "spi.h"
#include "mxc_sys.h"
#include "spimss.h"
#include "spi17y.h"
/**
* @ingroup spi
* @{
*/
/***** Definitions *****/
/***** Functions *****/
/* ************************************************************************ */
int SPI_Init(spi_type spi_name, unsigned mode, unsigned freq)
{
sys_cfg_spimss_t spimss_cfg;
sys_cfg_spi17y_t spi17y_cfg;
int error = E_NO_ERROR;
if (spi_name == SPI0A) {
spi17y_cfg.map = MAP_A;
error = SPI17Y_Init(MXC_SPI17Y, mode, freq, &spi17y_cfg);
} else if(spi_name == SPI1A) {
spimss_cfg.map = MAP_A;
error = SPIMSS_Init(MXC_SPIMSS, mode, freq, &spimss_cfg);
} else if(spi_name == SPI1B) {
spimss_cfg.map = MAP_B;
error = SPIMSS_Init(MXC_SPIMSS, mode, freq, &spimss_cfg);
} else {
return E_BAD_PARAM;
}
return error;
}
/* ************************************************************************ */
int SPI_MasterTransAsync(spi_type spi_name, spi_req_t *req)
{
int error = E_NO_ERROR;
if (spi_name == SPI0A) {
error = SPI17Y_MasterTransAsync(MXC_SPI17Y, (spi17y_req_t *) req);
} else if((spi_name == SPI1A) || (spi_name == SPI1B)) {
error = SPIMSS_MasterTransAsync(MXC_SPIMSS, (spimss_req_t *) req);
} else {
return E_BAD_PARAM;
}
return error;
}
/* ************************************************************************ */
int SPI_MasterTrans(spi_type spi_name, spi_req_t *req)
{
int error = E_NO_ERROR;
if (spi_name == SPI0A) {
error = SPI17Y_MasterTrans(MXC_SPI17Y, (spi17y_req_t *) req);
} else if((spi_name == SPI1A) || (spi_name == SPI1B)) {
error = SPIMSS_MasterTrans(MXC_SPIMSS, (spimss_req_t *) req);
} else {
return E_BAD_PARAM;
}
return error;
}
/* ************************************************************************ */
int SPI_SlaveTrans(spi_type spi_name, spi_req_t *req)
{
int error = E_NO_ERROR;
if (spi_name == SPI0A) {
error = SPI17Y_SlaveTrans(MXC_SPI17Y, (spi17y_req_t *) req);
} else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
error = SPIMSS_SlaveTrans(MXC_SPIMSS, (spimss_req_t *) req);
} else {
return E_BAD_PARAM;
}
return error;
}
/* ************************************************************************ */
int SPI_SlaveTransAsync(spi_type spi_name, spi_req_t *req)
{
int error = E_NO_ERROR;
if (spi_name == SPI0A) {
error = SPI17Y_SlaveTransAsync(MXC_SPI17Y, (spi17y_req_t *) req);
} else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
error = SPIMSS_SlaveTransAsync(MXC_SPIMSS, (spimss_req_t *) req);
} else {
return E_BAD_PARAM;
}
return error;
}
/* ************************************************************************ */
int SPI_Shutdown(spi_type spi_name)
{
int error = E_NO_ERROR;
if (spi_name == SPI0A) {
error = SPI17Y_Shutdown(MXC_SPI17Y);
} else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
error = SPIMSS_Shutdown(MXC_SPIMSS);
} else {
return E_BAD_PARAM;
}
return error;
}
/* ************************************************************************ */
int SPI_AbortAsync(spi_type spi_name, spi_req_t *req)
{
int error = E_NO_ERROR;
if (spi_name == SPI0A) {
error = SPI17Y_AbortAsync((spi17y_req_t *) req);
} else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
error = SPIMSS_AbortAsync((spimss_req_t *) req);
} else {
return E_BAD_PARAM;
}
return error;
}
/* ************************************************************************ */
int SPI_Handler(spi_type spi_name)
{
if (spi_name == SPI0A) {
SPI17Y_Handler(MXC_SPI17Y);
} else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
SPIMSS_Handler(MXC_SPIMSS);
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
// *****************************************************************************
int SPI_Enable(spi_type spi_name)
{
if (spi_name == SPI0A) {
SPI17Y_Enable(MXC_SPI17Y);
} else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
return E_NOT_SUPPORTED;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
// *****************************************************************************
int SPI_Disable(spi_type spi_name)
{
if (spi_name == SPI0A) {
SPI17Y_Disable(MXC_SPI17Y);
} else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
return E_NOT_SUPPORTED;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
// *****************************************************************************
int SPI_Clear_fifo(spi_type spi_name)
{
if (spi_name == SPI0A) {
SPI17Y_Clear_fifo(MXC_SPI17Y);
} else if ((spi_name == SPI1A) || (spi_name == SPI1B)) {
return E_NOT_SUPPORTED;
} else {
return E_BAD_PARAM;
}
return E_NO_ERROR;
}
/**@} end of group spi */

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/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-06-25 10:15:10 -0500 (Tue, 25 Jun 2019) $
* $Revision: 44277 $
*
**************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include "mxc_config.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "tmr_utils.h"
#include "mxc_lock.h"
#include "spi17y.h"
/* **** Definitions **** */
/* **** Globals **** */
typedef struct {
spi17y_req_t *req;
int started;
unsigned last_size;
unsigned deass;
} spi17y_req_state_t;
static spi17y_req_state_t states[MXC_SPI17Y_INSTANCES];
/* **** Functions **** */
static int SPI17Y_TransSetup(mxc_spi17y_regs_t *spi, spi17y_req_t *req, int master);
static int SPI17Y_MasterTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
static int SPI17Y_TransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
static int SPI17Y_SlaveTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async);
/* ************************************************************************** */
int SPI17Y_Init(mxc_spi17y_regs_t *spi, unsigned int mode, unsigned int freq,
const sys_cfg_spi17y_t* sys_cfg)
{
uint32_t freq_div;
int spi_num, error, hi_clk, lo_clk, scale;
spi_num = MXC_SPI17Y_GET_IDX(spi);
MXC_ASSERT(spi_num >= 0);
if (mode > 3) {
return E_BAD_PARAM;
}
if ((error = SYS_SPI17Y_Init(spi, sys_cfg)) != E_NO_ERROR) {
return error;
}
states[spi_num].req = NULL;
states[spi_num].last_size = 0;
states[spi_num].deass = 1;
// Enable SPI17Y
spi->ctrl0 = (MXC_F_SPI17Y_CTRL0_EN);
spi->ss_time = ((0x1 << MXC_F_SPI17Y_SS_TIME_PRE_POS) |
(0x1 << MXC_F_SPI17Y_SS_TIME_POST_POS) |
(0x1 << MXC_F_SPI17Y_SS_TIME_INACT_POS));
// Check if frequency is too high
if (freq > PeripheralClock) {
return E_BAD_PARAM;
}
// Set the clock high and low
freq_div = PeripheralClock/ (freq);
hi_clk = freq_div/2;
lo_clk = freq_div/2;
scale = 0;
if (freq_div %2) {
hi_clk +=1;
}
while (hi_clk > 16 && scale < 9) {
hi_clk /= 2;
lo_clk /=2;
scale ++;
}
spi->clk_cfg = ((lo_clk << MXC_F_SPI17Y_CLK_CFG_LO_POS) |
(hi_clk << MXC_F_SPI17Y_CLK_CFG_HI_POS));
MXC_SETFIELD(spi->clk_cfg, MXC_F_SPI17Y_CLK_CFG_SCALE, (scale << MXC_F_SPI17Y_CLK_CFG_SCALE_POS));
// Set the mode
spi->ctrl2 = (mode << MXC_F_SPI17Y_CTRL2_CPHA_POS);
// Clear the interrupts
spi->int_fl = spi->int_fl;
return E_NO_ERROR;
}
/* ************************************************************************* */
int SPI17Y_Shutdown(mxc_spi17y_regs_t *spi)
{
int spi_num, err;
spi17y_req_t *temp_req;
// Disable and clear interrupts
spi->int_en = 0;
spi->int_fl = spi->int_fl;
// Disable SPI17Y and FIFOS
spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
spi->dma &= ~(MXC_F_SPI17Y_DMA_TX_FIFO_EN | MXC_F_SPI17Y_DMA_RX_FIFO_EN);
// Call all of the pending callbacks for this SPI17Y
spi_num = MXC_SPI17Y_GET_IDX(spi);
if (states[spi_num].req != NULL) {
// Save the request
temp_req = states[spi_num].req;
// Unlock this SPI17Y
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (temp_req->callback != NULL) {
temp_req->callback(temp_req, E_SHUTDOWN);
}
}
// Clear registers
spi->ctrl0 = 0;
spi->ctrl1 = 0;
spi->ctrl2 = 0;
spi->ss_time = 0;
// Clear system level configurations
if ((err = SYS_SPI17Y_Shutdown(spi)) != E_NO_ERROR) {
return err;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPI17Y_TransSetup(mxc_spi17y_regs_t *spi, spi17y_req_t *req, int master)
{
int spi_num;
if ((req->tx_data == NULL) && (req->rx_data == NULL)) {
return E_BAD_PARAM;
}
if ((req->width > SPI17Y_WIDTH_1) && (req->tx_data != NULL) && (req->rx_data != NULL)) {
return E_BAD_PARAM;
}
// HW has problem with these two character sizes
if (req->bits == 1 || req->bits == 9) {
return E_BAD_PARAM;
}
spi_num = MXC_SPI17Y_GET_IDX(spi);
MXC_ASSERT(spi_num >= 0);
MXC_ASSERT(req->ssel < MXC_SPI17Y_SS_INSTANCES);
req->tx_num = 0;
req->rx_num = 0;
if (req->len == 0) {
return E_NO_ERROR;
}
states[spi_num].req = req;
states[spi_num].started = 0;
// HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive).
if (states[spi_num].deass == 1) {
spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
}
if (master) {
// Enable master mode
spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_MASTER;
// Setup the slave select
MXC_SETFIELD(spi->ctrl0, MXC_F_SPI17Y_CTRL0_SS, ((0x1 << req->ssel) << MXC_F_SPI17Y_CTRL0_SS_POS));
spi->ctrl2 |= ((req->ssel_pol << req->ssel)<<MXC_F_SPI17Y_CTRL2_SS_POL_POS);
} else {
// Enable slave mode
spi->ctrl0 &= ~MXC_F_SPI17Y_CTRL0_MASTER;
// Setup the slave select
spi->ctrl2 |= ((req->ssel_pol << 0)<<MXC_F_SPI17Y_CTRL2_SS_POL_POS);
}
if ((req->bits != states[spi_num].last_size)) {
// Setup the character size
// Master should only change character size at the end of a transaction. No restrictions on when slave can change.
if (!master || (!(spi->stat & MXC_F_SPI17Y_STAT_BUSY) && (states[spi_num].deass == 1)) || !(spi->ctrl0 & MXC_F_SPI17Y_CTRL0_EN)) {
//disable spi to change transfer size
spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
// set bit size
states[spi_num].last_size = req->bits;
if (req->bits <16) {
MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_NUMBITS, req->bits << MXC_F_SPI17Y_CTRL2_NUMBITS_POS);
} else {
MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_NUMBITS, 0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS);
}
} else {
// cant change transfer size while spi is busy
return E_BAD_STATE;
}
}
// Setup the data width
if (req->width == SPI17Y_WIDTH_4) {
MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD);
} else if (req->width == SPI17Y_WIDTH_2) {
MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL);
} else {
MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO);
}
// Setup the number of characters to transact
if (req->len > (MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR >> MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) {
return E_BAD_PARAM;
}
if (req->rx_data != NULL) {
// The TX_NUM field is used for both RX and TX length when in 4-wire mode.
if(req->width == SPI17Y_WIDTH_1) {
MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR,
req->len << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS);
} else {
MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR,
req->len << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS);
}
spi->dma |= MXC_F_SPI17Y_DMA_RX_FIFO_EN;
} else {
spi->ctrl1 &= ~(MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR);
spi->dma &= ~(MXC_F_SPI17Y_DMA_RX_FIFO_EN);
}
// Must use TXFIFO and NUM in full duplex
if (req->width == SPI17Y_WIDTH_1
&& !((spi->ctrl2 & MXC_F_SPI17Y_CTRL2_THREE_WIRE)>> MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) {
if (req->tx_data == NULL) {
// Must have something to send, so we'll use the rx_data buffer initialized to 0.
memset(req->rx_data, 0, (req->bits > 8 ? req->len << 1 : req->len));
req->tx_data = req->rx_data;
req->tx_num = 0;
}
}
if(req->tx_data != NULL) {
MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR,
req->len << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS);
spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_EN;
} else {
spi->dma &= ~(MXC_F_SPI17Y_DMA_TX_FIFO_EN);
}
spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR | MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR;
spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
states[spi_num].deass = req->deass;
// Clear master done flag
spi->int_fl = MXC_F_SPI17Y_INT_FL_M_DONE;
return E_NO_ERROR;
}
/* ************************************************************************** */
void SPI17Y_Handler(mxc_spi17y_regs_t *spi)
{
int spi_num, rx_avail;
uint32_t flags;
// Clear the interrupt flags
spi->int_en = 0;
flags = spi->int_fl;
spi->int_fl = flags;
spi_num = MXC_SPI17Y_GET_IDX(spi);
// Figure out if this SPI17Y has an active request
if ((states[spi_num].req != NULL) && (flags)) {
if ((spi->ctrl0 & MXC_F_SPI17Y_CTRL0_MASTER)>> MXC_F_SPI17Y_CTRL0_MASTER_POS) {
do {
SPI17Y_MasterTransHandler(spi, states[spi_num].req, 1);
rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
} while ((states[spi_num].req->rx_data != NULL) && (rx_avail > (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL)
>>MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
} else {
do {
SPI17Y_SlaveTransHandler(spi, states[spi_num].req, 1);
rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
} while ((states[spi_num].req->rx_data != NULL) && (rx_avail > (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL)
>>MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
}
}
}
/* ************************************************************************** */
int SPI17Y_MasterTrans(mxc_spi17y_regs_t *spi,spi17y_req_t *req)
{
int error;
if ((error =SPI17Y_TransSetup(spi, req, 1)) != E_NO_ERROR) {
return error;
}
req->callback = NULL;
while (SPI17Y_MasterTransHandler(spi,req,0)==0) {
}
while (!(spi->int_fl & MXC_F_SPI17Y_INT_FL_M_DONE)) {
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPI17Y_SlaveTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
{
int error;
if ((error =SPI17Y_TransSetup(spi, req,0)) != E_NO_ERROR) {
return error;
}
req->callback = NULL;
while (SPI17Y_SlaveTransHandler(spi,req,0)==0) {
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPI17Y_MasterTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
{
int error;
if ((error =SPI17Y_TransSetup(spi, req, 1))!= E_NO_ERROR) {
return error;
}
SPI17Y_MasterTransHandler(spi,req, 1);
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPI17Y_SlaveTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req)
{
int error;
if ((error =SPI17Y_TransSetup(spi, req, 0)) != E_NO_ERROR) {
return error;
}
SPI17Y_SlaveTransHandler(spi,req, 1);
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPI17Y_MasterTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req,uint8_t async)
{
int retval;
int spi_num;
spi_num = MXC_SPI17Y_GET_IDX(spi);
// Leave slave select asserted at the end of the transaction
if (!req->deass) {
spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_SS_CTRL;
}
retval = SPI17Y_TransHandler(spi,req, async);
if (!states[spi_num].started) {
spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_START;
states[spi_num].started = 1;
}
// Deassert slave select at the end of the transaction
if (req->deass) {
spi->ctrl0 &= ~MXC_F_SPI17Y_CTRL0_SS_CTRL;
}
return retval;
}
/* ************************************************************************** */
int SPI17Y_SlaveTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async)
{
return SPI17Y_TransHandler(spi,req, async);
}
/* ************************************************************************** */
// Returns non-zero if transactions is complete, or 0 if not.
int SPI17Y_TransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async)
{
unsigned tx_avail, rx_avail;
int remain, spi_num;
uint32_t int_en =0;
uint32_t length =0;
spi_num = MXC_SPI17Y_GET_IDX(spi);
// Read/write 2x number of bytes if larger character size
if (req->bits > 8) {
length = req->len*2;
} else {
length = req->len;
}
if (req->tx_data != NULL) {
// Need to know when all bytes are transmitted, so the callback can be triggered.
int_en |= MXC_F_SPI17Y_INT_EN_TX_EMPTY;
// Calculate how many bytes we can write to the FIFO
tx_avail = MXC_SPI17Y_FIFO_DEPTH - ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) >>
MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS);
if ((length - req->tx_num) < tx_avail) {
tx_avail = (length - req->tx_num);
}
if (req->bits > 8) {
tx_avail &= ~(unsigned)0x1;
}
// Write the FIFO
while (tx_avail) {
if (tx_avail > 3) {
memcpy((void*)&spi->data32,&((uint8_t*)req->tx_data)[req->tx_num], 4);
tx_avail -= 4;
req->tx_num += 4;
} else if (tx_avail > 1) {
memcpy((void*)&spi->data16[0],&((uint8_t*)req->tx_data)[req->tx_num], 2);
tx_avail -= 2;
req->tx_num += 2;
} else if (req->bits<=8) {
spi->data8[0] = ((uint8_t*)req->tx_data)[req->tx_num++];
tx_avail -= 1;
}
}
}
remain = length - req->tx_num;
// Set the TX interrupts
if (remain) {
if (remain > MXC_SPI17Y_FIFO_DEPTH) {
// Set the TX FIFO almost empty interrupt if we have to refill
spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL) |
((MXC_SPI17Y_FIFO_DEPTH) << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS));
} else {
spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL) |
((remain) << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS));
}
int_en |= MXC_F_SPI17Y_INT_EN_TX_THRESH;
}
// Break out if we've transmitted all the bytes and not receiving
if ((req->rx_data == NULL) && (req->tx_num == length) && ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) == 0)) {
spi->int_en = 0;
int_en = 0;
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
return 1;
}
// Read the RX FIFO
if (req->rx_data != NULL) {
// Wait for there to be data in the RX FIFO
rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS;
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
if (req->bits <= 8 || rx_avail >= 2) {
// Read from the FIFO
while (rx_avail) {
if (rx_avail > 3) {
memcpy(&((uint8_t*)req->rx_data)[req->rx_num], (void*)&spi->data32, 4);
rx_avail -= 4;
req->rx_num += 4;
} else if (rx_avail > 1) {
memcpy(&((uint8_t*)req->rx_data)[req->rx_num], (void*)&spi->data16[0], 2);
rx_avail -= 2;
req->rx_num += 2;
} else {
((uint8_t*)req->rx_data)[req->rx_num++] = spi->data8[0];
rx_avail -= 1;
}
// Don't read less than 2 bytes if we are using greater than 8 bit characters
if (rx_avail == 1 && req->bits > 8) {
break;
}
}
}
remain = length - req->rx_num;
if (remain) {
if (remain > MXC_SPI17Y_FIFO_DEPTH) {
spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) |
((2) << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
} else {
spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) |
((remain-1) << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS));
}
int_en |= MXC_F_SPI17Y_INT_EN_RX_THRESH;
}
// Break out if we've received all the bytes and we're not transmitting
if ((req->tx_data == NULL) && (req->rx_num == length)) {
spi->int_en = 0;
int_en = 0;
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
return 1;
}
}
// Break out once we've transmitted and received all of the data
if ((req->rx_num == length) && (req->tx_num == length) && ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) == 0)) {
spi->int_en = 0;
int_en = 0;
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
return 1;
}
if(async){
spi->int_en = int_en;
}
return 0;
}
/* ************************************************************************* */
int SPI17Y_AbortAsync(spi17y_req_t *req)
{
int spi_num;
mxc_spi17y_regs_t *spi;
// Check the input parameters
if (req == NULL) {
return E_BAD_PARAM;
}
// Find the request, set to NULL
for (spi_num = 0; spi_num < MXC_SPI17Y_INSTANCES; spi_num++) {
if (req == states[spi_num].req) {
spi = MXC_SPI17Y_GET_SPI17Y(spi_num);
// Disable interrupts, clear the flags
spi->int_en = 0;
spi->int_fl = spi->int_fl;
// Reset the SPI17Y to cancel the on ongoing transaction
spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
// Unlock this SPI17Y
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_ABORT);
}
return E_NO_ERROR;
}
}
return E_BAD_PARAM;
}
// *****************************************************************************
void SPI17Y_Enable(mxc_spi17y_regs_t* spi)
{
spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN);
}
// *****************************************************************************
void SPI17Y_Disable(mxc_spi17y_regs_t* spi)
{
spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN);
}
// *****************************************************************************
void SPI17Y_Clear_fifo(mxc_spi17y_regs_t* spi)
{
spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR | MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR;
}

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Project/SDK/Driver/Source/spimss.c
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/**
* @file spimss.c
* @brief This file contains the function implementations for the
* Serial Peripheral Interface (SPIMSS) peripheral module.
*/
/* *****************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-05-06 14:44:04 -0500 (Mon, 06 May 2019) $
* $Revision: 43157 $
*
**************************************************************************** */
/* **** Includes **** */
#include <string.h>
#include <stdio.h>
#include <stdint.h>
#include "mxc_config.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "spimss.h"
#include "mxc_lock.h"
/**
* @ingroup spimss
* @{
*/
/* **** Definitions **** */
/* **** Globals **** */
typedef struct {
spimss_req_t *req;
} spimss_req_state_t;
static spimss_req_state_t states[MXC_SPIMSS_INSTANCES];
/* **** Functions **** */
static int SPIMSS_TransSetup(mxc_spimss_regs_t *spi, spimss_req_t *req, int master);
static uint32_t SPIMSS_MasterTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
static uint32_t SPIMSS_TransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
static uint32_t SPIMSS_SlaveTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req);
/* ************************************************************************** */
int SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_cfg_spimss_t* sys_cfg)
{
int spi_num, error;
unsigned int spimss_clk;
unsigned int pol, pha; // Polarity and phase of the clock (SPI mode)
spi_num = MXC_SPIMSS_GET_IDX(spi);
MXC_ASSERT(spi_num >= 0);
if (mode > 3) {
return E_BAD_PARAM;
}
if ((error = SYS_SPIMSS_Init(spi, sys_cfg)) != E_NO_ERROR) {
return error;
}
states[spi_num].req = NULL;
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Keep the SPI Disabled (This is the SPI Start)
// Check if frequency is too high
if (freq > PeripheralClock) {
return E_BAD_PARAM;
}
// Set the bit rate
spimss_clk = PeripheralClock;
spi->brg = (spimss_clk / freq) >> 1;
// Set the mode
pol = mode >> 1; // Get the polarity out of the mode input value
pha = mode & 1; // Get the phase out of the mode input value
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_CTRL_CLKPOL_POS); // polarity
spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_CTRL_PHASE_POS); // phase
spi->status &= ~(MXC_F_SPIMSS_STATUS_IRQ);
return E_NO_ERROR;
}
/* ************************************************************************* */
int SPIMSS_Shutdown(mxc_spimss_regs_t *spi)
{
int spi_num, err;
spimss_req_t *temp_req;
// Disable and turn off the SPI transaction.
spi->ctrl = 0; // Interrupts, SPI transaction all turned off
spi->status = 0;
spi->mod = 0;
// Reset FIFO counters
spi->dma &= ~(MXC_F_SPIMSS_DMA_RX_FIFO_CNT|MXC_F_SPIMSS_DMA_TX_FIFO_CNT);
// Call all of the pending callbacks for this SPI
spi_num = MXC_SPIMSS_GET_IDX(spi);
if (states[spi_num].req != NULL) {
// Save the request
temp_req = states[spi_num].req;
// Unlock this SPI
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (temp_req->callback != NULL) {
temp_req->callback(temp_req, E_SHUTDOWN);
}
}
spi->status = 0;
// Clear system level configurations
if ((err = SYS_SPIMSS_Shutdown(spi)) != E_NO_ERROR) {
return err;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPIMSS_TransSetup(mxc_spimss_regs_t *spi, spimss_req_t *req, int master)
{
int spi_num;
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Make sure the Initiation
// of SPI Start is disabled.
spi->mod |= MXC_F_SPIMSS_MOD_TX_LJ; // Making sure data is left
// justified.
if ((req->tx_data == NULL) && (req->rx_data == NULL)) {
return -1;
}
spi_num = MXC_SPIMSS_GET_IDX(spi);
MXC_ASSERT(spi_num >= 0);
if (req->len == 0) {
return 0;
}
req->tx_num = 0;
req->rx_num = 0;
if (mxc_get_lock((uint32_t*)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) {
return E_BUSY;
}
if (master) { // Enable master mode
spi->ctrl |= MXC_F_SPIMSS_CTRL_MMEN; // SPI configured as master.
spi->mod |= MXC_F_SPIMSS_CTRL_MMEN; // SSEL pin is an output.
} else { // Enable slave mode
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_MMEN); // SPI configured as slave.
spi->mod &= ~(MXC_F_SPIMSS_CTRL_MMEN); // SSEL pin is an input.
}
// Setup the character size
if (req->bits <16) {
MXC_SETFIELD(spi->mod, MXC_F_SPIMSS_MOD_NUMBITS , req->bits << MXC_F_SPIMSS_MOD_NUMBITS_POS);
} else {
MXC_SETFIELD(spi->mod, MXC_F_SPIMSS_MOD_NUMBITS , 0 << MXC_F_SPIMSS_MOD_NUMBITS_POS);
}
// Setup the slave select
spi->mod |= MXC_F_SPIMSS_MOD_SSV; // Assert a high on Slave Select,
// to get the line ready for active low later
// Clear the TX and RX FIFO
spi->dma |= (MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR | MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR);
return E_NO_ERROR;
}
/* ************************************************************************** */
void SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ
{
int spi_num;
uint32_t flags;
unsigned int int_enable;
flags = spi->status;
spi->status = flags;
spi->status|= 0x80; // clear interrupt
spi_num = MXC_SPIMSS_GET_IDX(spi);
int_enable = 0;
if (states[spi_num].req != NULL) {
if ((spi->ctrl & MXC_F_SPIMSS_CTRL_MMEN) >> MXC_F_SPIMSS_CTRL_MMEN_POS) {
int_enable = SPIMSS_MasterTransHandler(spi, states[spi_num].req);
} else {
int_enable = SPIMSS_SlaveTransHandler(spi, states[spi_num].req);
}
}
if (int_enable==1) {
spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE );
}
}
/* ************************************************************************** */
int SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, spimss_req_t *req)
{
int error;
if ((error = SPIMSS_TransSetup(spi, req, 1)) != E_NO_ERROR) {
return error;
}
req->callback = NULL;
spi->mod &= ~(MXC_F_SPIMSS_MOD_SSV); // This will assert the Slave Select.
spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI
while (SPIMSS_MasterTransHandler(spi,req)!=0) {
}
spi->mod |= MXC_F_SPIMSS_MOD_SSV;
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Last of the SPIMSS value has been transmitted...
// stop the transmission...
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, spimss_req_t *req)
{
int error;
if ((error = SPIMSS_TransSetup(spi, req,0)) != E_NO_ERROR) {
return error;
}
while (SPIMSS_SlaveTransHandler(spi,req)!=0) {
spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI
while ((spi->status & MXC_F_SPIMSS_STATUS_TXST) == MXC_F_SPIMSS_STATUS_TXST) {}
}
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Last of the SPIMSS value has been transmitted...
// stop the transmission...
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req)
{
int error;
uint8_t int_enable;
if ((error = SPIMSS_TransSetup(spi, req, 1) )!= E_NO_ERROR) {
return error;
}
int_enable = SPIMSS_MasterTransHandler(spi,req);
spi->mod ^= MXC_F_SPIMSS_MOD_SSV; // This will assert the Slave Select.
spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI
if (int_enable==1) {
spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
}
return E_NO_ERROR;
}
/* ************************************************************************** */
int SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req)
{
int error;
uint8_t int_enable;
if ((error = SPIMSS_TransSetup(spi, req, 0)) != E_NO_ERROR) {
return error;
}
int_enable = SPIMSS_SlaveTransHandler(spi,req);
spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI
if (int_enable==1) { // Trigger a SPI Interrupt
spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE );
}
return E_NO_ERROR;
}
/* ************************************************************************** */
uint32_t SPIMSS_MasterTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
{
unsigned start_set = 0;
uint32_t retval;
if (!start_set) {
start_set = 1;
retval = SPIMSS_TransHandler(spi,req);
}
return retval;
}
/* ************************************************************************** */
uint32_t SPIMSS_SlaveTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
{
return SPIMSS_TransHandler(spi,req);
}
/* ************************************************************************** */
uint32_t SPIMSS_TransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req)
{
unsigned tx_avail, rx_avail;
int remain, spi_num;
uint32_t int_en =0;
uint32_t length =req->len;
spi_num = MXC_SPIMSS_GET_IDX(spi);
// Read the RX FIFO
if (req->rx_data != NULL) {
// Wait for there to be data in the RX FIFO
rx_avail = ((spi->dma & MXC_F_SPIMSS_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS);
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
// Read from the FIFO
while (rx_avail) {
// Don't read less than 2 bytes if we are using greater than 8 bit characters
if (req->bits>8) {
((uint16_t*)req->rx_data)[req->rx_num++] = spi->data16;
rx_avail -= 1;
} else {
((uint8_t*)req->rx_data)[req->rx_num++] = spi->data8[0];
rx_avail -= 1;
}
rx_avail = ((spi->dma & MXC_F_SPIMSS_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS);
if ((length - req->rx_num) < rx_avail) {
rx_avail = (length - req->rx_num);
}
}
remain = length - req->rx_num;
if (remain) {
if (remain > MXC_SPIMSS_FIFO_DEPTH) {
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS));
} else {
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS));
}
int_en = 1;
}
// Break out if we've received all the bytes and we're not transmitting
if ((req->tx_data == NULL) && (req->rx_num == length)) {
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
int_en = 0;
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
}
}
// Note:- spi->dma shows the FIFO TX count and FIFO RX count in
// Words, while the calculation below is in bytes.
if (req->tx_data != NULL) {
if (req->tx_num < length) {
// Calculate how many bytes we can write to the FIFO (tx_avail holds that value)
tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)); // in bytes
if ((length - req->tx_num) < tx_avail) {
tx_avail = (length - req->tx_num); // This is for the last spin
}
if (req->bits > 8) {
tx_avail &= ~(unsigned)0x1;
}
// Write the FIFO
while (tx_avail) {
if (req->bits >8) {
spi->data16 = ((uint16_t*)req->tx_data)[req->tx_num++];
tx_avail -= 1;
} else {
spi->data8[0] = ((uint8_t*)req->tx_data)[req->tx_num++];
tx_avail -=1;
}
}
}
remain = length - req->tx_num;
// If there are values remaining to be transmitted, this portion will get
// executed and int_en set, to indicate that this must spin and come back again...
if (remain) {
if (remain > MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum,
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS));
} else { // only one more tx round will be done... Transfer whatever remains,
spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS));
}
int_en = 1; // This will act as a trigger for the next round...
}
// Break out if we've transmitted all the bytes and not receiving
if ((req->rx_data == NULL) && (req->tx_num == length)) {
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
int_en = 0;
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
}
}
// Break out once we've transmitted and received all of the data
if ((req->rx_num == length) && (req->tx_num == length)) {
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
int_en = 0;
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
}
return int_en;
}
/* ************************************************************************* */
int SPIMSS_AbortAsync(spimss_req_t *req)
{
int spi_num;
mxc_spimss_regs_t *spi;
// Check the input parameters
if (req == NULL) {
return E_BAD_PARAM;
}
// Find the request, set to NULL
for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) {
if (req == states[spi_num].req) {
spi = MXC_SPIMSS_GET_SPI(spi_num);
// Disable interrupts, clear the flags
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR);
// Disable and turn off the SPI transaction.
spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN);
// Unlock this SPI
mxc_free_lock((uint32_t*)&states[spi_num].req);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_ABORT);
}
return E_NO_ERROR;
}
}
return E_BAD_PARAM;
}
/**@} end of group spimss */

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/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2019-09-11 14:32:22 -0500 (Wed, 11 Sep 2019) $
* $Revision: 46047 $
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_config.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "tmr.h"
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
/* ************************************************************************** */
int TMR_Init(mxc_tmr_regs_t *tmr, tmr_pres_t pres, const sys_cfg_tmr_t* sys_cfg)
{
MXC_ASSERT(tmr);
int err;
// System settigns
if((err=SYS_TMR_Init(tmr, sys_cfg)) !=E_NO_ERROR)
{
return err;
}
// Disable timer and clear settings
tmr->cn = 0;
// Clear interrupt flag
tmr->intr = MXC_F_TMR_INTR_IRQ_CLR;
// Set the prescaler
tmr->cn = pres;
return err;
}
int TMR_Shutdown(mxc_tmr_regs_t *tmr)
{
MXC_ASSERT(tmr);
int err;
// System settigns
if((err=SYS_TMR_Shutdown(tmr)) !=E_NO_ERROR)
{
return err;
}
// Disable timer and clear settings
tmr->cn = 0;
return err;
}
/* ************************************************************************** */
void TMR_Enable(mxc_tmr_regs_t* tmr)
{
MXC_ASSERT(tmr);
tmr->cn |= MXC_F_TMR_CN_TEN;
}
/* ************************************************************************** */
void TMR_Disable(mxc_tmr_regs_t* tmr)
{
MXC_ASSERT(tmr);
tmr->cn &= ~(MXC_F_TMR_CN_TEN);
}
/* ************************************************************************** */
int TMR_Config(mxc_tmr_regs_t *tmr, const tmr_cfg_t *cfg)
{
MXC_ASSERT(tmr);
// Configure the timer
tmr->cn = (tmr->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) |
((cfg->mode << MXC_F_TMR_CN_TMODE_POS) & MXC_F_TMR_CN_TMODE) |
((cfg->pol << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL);
tmr->cnt = 0x1;
tmr->cmp = cfg->cmp_cnt;
return E_NO_ERROR;
}
/* ************************************************************************** */
int TMR_PWMConfig(mxc_tmr_regs_t *tmr, const tmr_pwm_cfg_t *cfg)
{
if (cfg->duty_cnt > cfg->per_cnt) {
return E_BAD_PARAM;
}
// Configure the timer
tmr->cn = (tmr->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) |
MXC_S_TMR_CN_TMODE_PWM | ((cfg->pol << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL);
tmr->cnt = 0x1;
tmr->cmp = cfg->per_cnt;
tmr->pwm = cfg->duty_cnt;
return E_NO_ERROR;
}
/* ************************************************************************** */
int TMR_PWMSetDuty(mxc_tmr_regs_t *tmr, uint32_t duty)
{
uint32_t cnt;
// Make sure the new Duty count is less than the period count
if (duty > tmr->cmp) {
return E_BAD_PARAM;
}
cnt = tmr->cnt; // make sure order of volatile access is known.
// Avoid glitching the output
if (duty >= tmr->pwm) {
// Wait for the count to be in the range of 1 to tmr->pwm
while (cnt > tmr->pwm) {
cnt = tmr->cnt; // update the volatile access variable
}
} else {
// Wait for the count to pass tmr->pwm
while (cnt < tmr->pwm) {
cnt = tmr->cnt; // update the volatile access variable
}
}
tmr->pwm = duty;
return E_NO_ERROR;
}
/* ************************************************************************** */
int TMR_PWMSetPeriod(mxc_tmr_regs_t *tmr, uint32_t per)
{
// Make sure the new Duty count is less than the period count
if (tmr->pwm > per) {
return E_BAD_PARAM;
}
// Wait for the count to be less than the new dut_cnt
while (tmr->cnt >= per) {}
tmr->cmp = per;
return E_NO_ERROR;
}
/* ************************************************************************** */
uint32_t TMR_GetCompare(mxc_tmr_regs_t* tmr)
{
return tmr->cmp;
}
/* ************************************************************************** */
uint32_t TMR_GetCapture(mxc_tmr_regs_t* tmr)
{
return tmr->pwm;
}
/* ************************************************************************* */
uint32_t TMR_GetCount(mxc_tmr_regs_t* tmr)
{
return tmr->cnt;
}
/* ************************************************************************* */
void TMR_IntClear(mxc_tmr_regs_t* tmr)
{
tmr->intr = MXC_F_TMR_INTR_IRQ_CLR;
}
/* ************************************************************************* */
uint32_t TMR_IntStatus(mxc_tmr_regs_t* tmr)
{
return tmr->intr;
}
/* ************************************************************************* */
void TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt)
{
tmr->cmp = cmp_cnt;
}
/* ************************************************************************* */
void TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt)
{
tmr->cnt = cnt;
}
/* ************************************************************************* */
int TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks)
{
uint32_t unit_div0, unit_div1;
uint32_t timerClock;
uint32_t prescale;
uint64_t temp_ticks;
timerClock = SYS_TMR_GetFreq(tmr);
prescale = ((tmr->cn & MXC_F_TMR_CN_PRES) >> MXC_F_TMR_CN_PRES_POS)
| (((tmr->cn & MXC_F_TMR_CN_PRES3) >> (MXC_F_TMR_CN_PRES3_POS))<<3);
switch (units) {
case TMR_UNIT_NANOSEC:
unit_div0 = 1000000;
unit_div1 = 1000;
break;
case TMR_UNIT_MICROSEC:
unit_div0 = 1000;
unit_div1 = 1000;
break;
case TMR_UNIT_MILLISEC:
unit_div0 = 1;
unit_div1 = 1000;
break;
case TMR_UNIT_SEC:
unit_div0 = 1;
unit_div1 = 1;
break;
default:
return E_BAD_PARAM;
}
temp_ticks = (uint64_t)time * (timerClock / unit_div0) / (unit_div1 * (1 << (prescale & 0xF)));
//make sure ticks is within a 32 bit value
if (!(temp_ticks & 0xffffffff00000000) && (temp_ticks & 0xffffffff)) {
*ticks = temp_ticks;
return E_NO_ERROR;
}
return E_INVALID;
}
/* ************************************************************************* */
int TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units)
{
uint64_t temp_time = 0;
uint32_t timerClock = SYS_TMR_GetFreq(tmr);
uint32_t prescale = ((tmr->cn & MXC_F_TMR_CN_PRES) >> MXC_F_TMR_CN_PRES_POS)
| (((tmr->cn & MXC_F_TMR_CN_PRES3) >> (MXC_F_TMR_CN_PRES3_POS))<<3);
temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000);
if (!(temp_time & 0xffffffff00000000)) {
*time = temp_time;
*units = TMR_UNIT_NANOSEC;
return E_NO_ERROR;
}
temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000);
if (!(temp_time & 0xffffffff00000000)) {
*time = temp_time;
*units = TMR_UNIT_MICROSEC;
return E_NO_ERROR;
}
temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / timerClock;
if (!(temp_time & 0xffffffff00000000)) {
*time = temp_time;
*units = TMR_UNIT_MILLISEC;
return E_NO_ERROR;
}
temp_time = (uint64_t)ticks * (1 << (prescale & 0xF)) / timerClock;
if (!(temp_time & 0xffffffff00000000)) {
*time = temp_time;
*units = TMR_UNIT_SEC;
return E_NO_ERROR;
}
return E_INVALID;
}

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/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $
* $Revision: 38560 $
*
**************************************************************************** */
/* **** Includes **** */
#include <stddef.h>
#include "mxc_assert.h"
#include "tmr.h"
#include "tmr_utils.h"
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
/* ************************************************************************** */
void TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg)
{
// Return immediately if delay is 0
if (!us) {
return;
}
TMR_TO_Start(tmr, us, sys_cfg);
while (TMR_TO_Check(tmr) != E_TIME_OUT) {}
}
/* ************************************************************************** */
void TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg)
{
uint64_t ticks;
int clk_shift = 0;
ticks = (uint64_t)us * (uint64_t)PeripheralClock / (uint64_t)1000000;
while (ticks > 0xFFFFFFFFUL) {
ticks >>= 1;
++clk_shift;
}
tmr_pres_t prescale = (tmr_pres_t)(clk_shift << MXC_F_TMR_CN_PRES_POS);
TMR_Init(tmr, prescale, sys_cfg);
// Initialize the timer in one-shot mode
tmr_cfg_t cfg;
cfg.mode = TMR_MODE_ONESHOT;
cfg.cmp_cnt = ticks;
cfg.pol = 0;
TMR_Disable(tmr);
TMR_Config(tmr, &cfg);
TMR_IntClear(tmr);
TMR_Enable(tmr);
}
/* ************************************************************************** */
int TMR_TO_Check(mxc_tmr_regs_t *tmr)
{
if (TMR_IntStatus(tmr)) {
return E_TIME_OUT;
}
return E_NO_ERROR;
}
/* ************************************************************************** */
void TMR_TO_Stop(mxc_tmr_regs_t *tmr)
{
TMR_Disable(tmr);
TMR_SetCount(tmr, 0x0);
}
/* ************************************************************************** */
void TMR_TO_Clear(mxc_tmr_regs_t *tmr)
{
TMR_IntClear(tmr);
TMR_SetCount(tmr, 0x0);
}
/* ************************************************************************** */
unsigned int TMR_TO_Elapsed(mxc_tmr_regs_t *tmr)
{
uint32_t elapsed;
tmr_unit_t units;
TMR_GetTime(tmr, TMR_GetCount(tmr), &elapsed, &units);
switch (units) {
case TMR_UNIT_NANOSEC:
default:
return (elapsed / 1000);
case TMR_UNIT_MICROSEC:
return (elapsed);
case TMR_UNIT_MILLISEC:
return (elapsed * 1000);
case TMR_UNIT_SEC:
return (elapsed * 1000000);
}
}
/* ************************************************************************** */
unsigned int TMR_TO_Remaining(mxc_tmr_regs_t *tmr)
{
uint32_t remaining_ticks, remaining_time;
tmr_unit_t units;
remaining_ticks = TMR_GetCompare(tmr) - TMR_GetCount(tmr);
TMR_GetTime(tmr, remaining_ticks, &remaining_time, &units);
switch (units) {
case TMR_UNIT_NANOSEC:
default:
return (remaining_time / 1000);
case TMR_UNIT_MICROSEC:
return (remaining_time);
case TMR_UNIT_MILLISEC:
return (remaining_time * 1000);
case TMR_UNIT_SEC:
return (remaining_time * 1000000);
}
}
/* ************************************************************************** */
void TMR_SW_Start(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *sys_cfg)
{
TMR_TO_Start(tmr, 0xFFFFFFFF, sys_cfg);
}
/* ************************************************************************** */
unsigned int TMR_SW_Stop(mxc_tmr_regs_t *tmr)
{
unsigned int elapsed = TMR_TO_Elapsed(tmr);
TMR_TO_Stop(tmr);
return elapsed;
}

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/* ****************************************************************************
* Copyright (C) 2014-2018 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2020-09-08 13:28:39 -0500 (Tue, 08 Sep 2020) $
* $Revision: 55611 $
*
*************************************************************************** */
/* **** Includes **** */
#include <stdint.h>
#include <string.h>
#include "mxc_config.h"
#include "mxc_assert.h"
#include "uart_regs.h"
#include "uart.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
/* **** Definitions **** */
#define UART_ER_IF (MXC_F_UART_INT_FL_RX_FRAME_ERROR | \
MXC_F_UART_INT_FL_RX_PARITY_ERROR | \
MXC_F_UART_INT_FL_RX_OVERRUN)
#define UART_ER_IE (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \
MXC_F_UART_INT_EN_RX_PARITY_ERROR | \
MXC_F_UART_INT_EN_RX_OVERRUN )
#define UART_RX_IF (MXC_F_UART_INT_FL_RX_FIFO_THRESH)
#define UART_RX_IE (MXC_F_UART_INT_EN_RX_FIFO_THRESH)
#define UART_TX_IF (MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \
MXC_F_UART_INT_FL_TX_FIFO_THRESH)
#define UART_TX_IE (MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \
MXC_F_UART_INT_EN_TX_FIFO_THRESH)
#if (TARGET == 32660) || (TARGET == 32665)
#define MAX_FACTOR 3
#else
#define MAX_FACTOR 7
#endif
/* **** File Scope Data **** */
// Saves the state of the non-blocking read requests.
static uart_req_t *rx_states[MXC_UART_INSTANCES];
// Saves the state of the non-blocking write requests.
static uart_req_t *tx_states[MXC_UART_INSTANCES];
/* **** Functions **** */
static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num);
static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
uint32_t flags);
static uint32_t uart_error_check(mxc_uart_regs_t *uart);
static void uart_error_clear(mxc_uart_regs_t *uart);
/* ************************************************************************* */
uint32_t uart_error_check(mxc_uart_regs_t *uart)
{
return (uart->int_fl & UART_ER_IF);
}
/* ************************************************************************* */
void uart_error_clear(mxc_uart_regs_t *uart)
{
UART_ClearFlags(uart,UART_ER_IF);
}
/* ************************************************************************* */
int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t* sys_cfg)
{
int err;
int uart_num;
uint32_t baud0 = 0, baud1 = 0,div;
int32_t factor = -1;
// Get the state array index
uart_num = MXC_UART_GET_IDX(uart);
if (uart_num == -1) {
return E_BAD_PARAM;
}
if ((err = SYS_UART_Init(uart, sys_cfg)) != E_NO_ERROR) {
return err;
}
// Initialize state pointers
rx_states[uart_num] = NULL;
tx_states[uart_num] = NULL;
// Drain FIFOs, enable UART, and set configuration
uart->ctrl = (MXC_F_UART_CTRL_ENABLE | cfg->parity | cfg->size | cfg->stop | cfg->flow | cfg->pol);
// Set the baud rate
// Calculate divisor
#if (TARGET != 32660)
uart->ctrl |= cfg->clksel;
if (cfg->clksel == UART_CLKSEL_ALTERNATE) {
div = UART_ALTERNATE_CLOCK_HZ / ((cfg->baud));
} else {
div = PeripheralClock / ((cfg->baud));
}
#else
div = PeripheralClock / ((cfg->baud));
#endif
// Search for integer and fractional baud rate registers based on divisor
do {
factor += 1;
baud0 = div >> (7-factor); // divide by 128,64,32,16 to extract integer part
baud1 = ((div << factor) - (baud0 << 7)); //subtract factor corrected div - integer parts
} while ((baud0 == 0) && (factor < MAX_FACTOR));
uart->baud0 = ((factor << MXC_F_UART_BAUD0_FACTOR_POS) | baud0);
#if (TARGET == 32660) || (TARGET == 32665) || (TARGET == 32650)
/* Erratum:
* Hardware bug causes exact baud rates to generate framing error. Slightly mis-adjust timing
* to help avoid this bug.
*/
if (baud1 > 3) {
uart->baud1 = baud1 - 3;
} else {
uart->baud1 = baud1 + 3;
}
#else
uart->baud1 = baud1;
#endif
// Clear pending requests
rx_states[uart_num] = NULL;
tx_states[uart_num] = NULL;
return E_NO_ERROR;
}
/* ************************************************************************* */
int UART_Shutdown(mxc_uart_regs_t *uart)
{
int uart_num;
uart_req_t *temp_req;
// Get the state array index
uart_num = MXC_UART_GET_IDX(uart);
if (uart_num < 0) {
return E_BAD_PARAM;
}
// Disable interrupts
uart->int_en = 0;
// Flush RX and TX FIFOS
uart->ctrl |= (MXC_F_UART_CTRL_TX_FLUSH | MXC_F_UART_CTRL_RX_FLUSH);
// Call all of the pending callbacks for this UART
if(rx_states[uart_num] != NULL) {
// Save the request
temp_req = rx_states[uart_num];
// Unlock this UART to read
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
// Callback if not NULL
if (temp_req->callback != NULL) {
temp_req->callback(temp_req, E_SHUTDOWN);
}
}
if (tx_states[uart_num] != NULL) {
// Save the request
temp_req = tx_states[uart_num];
// Unlock this UART to write
mxc_free_lock((uint32_t*)&tx_states[uart_num]);
// Callback if not NULL
if (temp_req->callback != NULL) {
temp_req->callback(temp_req, E_SHUTDOWN);
}
}
// Wait for not busy
while (uart->status & (MXC_F_UART_STATUS_TX_BUSY | MXC_F_UART_STATUS_RX_BUSY)) {
}
// Shutdown the UART
uart->ctrl = 0;
// Shutdown any system level setup
SYS_UART_Shutdown(uart);
// Clear pending requests
rx_states[uart_num] = NULL;
tx_states[uart_num] = NULL;
return E_NO_ERROR;
}
/* ************************************************************************* */
void UART_Handler(mxc_uart_regs_t *uart)
{
int uart_num; // Holds the current index of rx_states or tx_states
uint32_t intst;
// Get the state array index
uart_num = MXC_UART_GET_IDX(uart);
if (uart_num == -1) {
return;
}
// Read and clear interrupts
intst = uart->int_fl;
uart->int_fl = intst;
// Read interrupt
if (intst & (UART_RX_IF | UART_ER_IF)) {
UART_ReadHandler(uart, rx_states[uart_num], uart_num, intst);
}
// Write Interrupt
if (intst & (UART_TX_IF | UART_ER_IF)) {
UART_WriteHandler(uart, tx_states[uart_num], uart_num);
}
}
/* ************************************************************************* */
static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num)
{
int remain, avail;
req = tx_states[uart_num];
if (req == NULL) {
// Nothing to do
uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; // disable interrupt
return;
}
// Refill the TX FIFO
avail = UART_NumWriteAvail(uart);
remain = req->len - req->num;
while (avail && remain) {
uart->fifo = req->data[req->num++];
remain--;
avail--;
}
// See if we've sent all of the characters
if (req->len == req->num) {
// Disable interrupts
uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY;
// Deinit state before callback in case another is requested
tx_states[uart_num] = NULL;
mxc_free_lock((uint32_t*)&tx_states[uart_num]);
// Callback when we've written all the characters
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
}
// Enable the interrupts
uart->int_en |= UART_TX_IE | UART_ER_IE;
}
/* ************************************************************************* */
static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num,
uint32_t flags)
{
int remain, avail;
if (req == NULL) {
// Nothing to do
uart->int_en &= ~(UART_RX_IE | UART_ER_IE); // disable interrupts
return;
}
// Save the data in the FIFO while we still need data
avail = UART_NumReadAvail(uart);
remain = req->len - req->num;
while (avail && remain) {
req->data[req->num++] = uart->fifo;
remain--;
avail--;
}
// Check for errors
if (flags & MXC_F_UART_INT_FL_RX_OVERRUN) {
// Unlock this UART to read
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
if (req->callback != NULL) {
req->callback(req, E_OVERFLOW);
}
return;
}
if (flags & (MXC_F_UART_INT_FL_RX_FRAME_ERROR |
MXC_F_UART_INT_FL_RX_PARITY_ERROR)) {
// Unlock this UART to read
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
if (req->callback != NULL) {
req->callback(req, E_COMM_ERR);
}
return;
}
// Check to see if we've received all of the characters.
if (req->num == req->len) {
// Disable interrupts
uart->int_en &= ~(UART_RX_IE | UART_ER_IE);
// Deinit state before callback in case another is requested
rx_states[uart_num] = NULL;
// Call the callback function
if (req->callback != NULL) {
req->callback(req, E_NO_ERROR);
}
return;
} else if (req->num > (req->len - MXC_UART_FIFO_DEPTH)) {
// Set RX threshold less than FIFO_DEPTH characters if needed
uart->thresh_ctrl = ((req->len - req->num)<<
MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS);
} else {
uart->thresh_ctrl = MXC_UART_FIFO_DEPTH<<
MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS;
}
}
/* ************************************************************************* */
int UART_Read(mxc_uart_regs_t *uart, uint8_t *data, int len, int *num)
{
int uart_num; // Holds the current index of rx_states
int char_read = 0; // Holds the number of characters successfully read
int error_code =0; // Holds the error to return while reading
// Get the state array index
uart_num = MXC_UART_GET_IDX(uart);
if (uart_num < 0) {
return E_BAD_PARAM;
}
// Check to make sure baud rate has been set
if (uart->baud0 == 0) {
return E_UNINITIALIZED;
}
// Check data pointer
if (data == NULL) {
return E_BAD_PARAM;
}
// Check if there is already a request in progress
if (rx_states[uart_num] != NULL) {
return E_BUSY;
}
// Lock this UART from reading
while (mxc_get_lock((uint32_t*)&rx_states[uart_num], 1) != E_NO_ERROR) {
}
// Get bytes FIFO
while (char_read < len) {
// Wait for RXFIFO to not be empty
while (uart->status & MXC_F_UART_STATUS_RX_EMPTY) {
// Check for error
if (uart_error_check(uart) != E_NO_ERROR) {
if (uart->int_fl & MXC_F_UART_INT_FL_RX_OVERRUN) {
error_code = E_OVERFLOW;
} else {
error_code = E_COMM_ERR;
}
uart_error_clear(uart);
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
return error_code;
}
}
data[char_read] = uart->fifo;
char_read++;
}
if (num != NULL) {
*num = char_read;
}
// Unlock this UART to read
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
return char_read;
}
/* ************************************************************************* */
uint8_t UART_ReadByte(mxc_uart_regs_t *uart)
{
while (uart->status & MXC_F_UART_STATUS_RX_EMPTY) {}
return uart->fifo;
}
/* ************************************************************************* */
int UART_Write(mxc_uart_regs_t *uart, const uint8_t *data, int len)
{
int uart_num; // Holds the current index of tx_states
int char_written = 0; // Holds the number of characters successfully written
// Get the state array index
uart_num = MXC_UART_GET_IDX(uart);
if (uart_num < 0) {
return E_BAD_PARAM;
}
// Check to make sure baud rate has been set
if (uart->baud0 == 0) {
return E_UNINITIALIZED;
}
// Check data pointer
if (data == NULL) {
return E_BAD_PARAM;
}
// Check if there is already a request in progress
if (tx_states[uart_num] != NULL) {
return E_BUSY;
}
// Lock this UART from writing
while (mxc_get_lock((uint32_t*)&tx_states[uart_num], 1) != E_NO_ERROR) {
}
// Clear errors
uart_error_clear(uart);
// Put bytes into FIFO
while (char_written < len) {
UART_WriteByte(uart,data[char_written]);
char_written++;
}
// Unlock this UART to write
mxc_free_lock((uint32_t*)&tx_states[uart_num]);
return char_written;
}
/* ************************************************************************* */
void UART_WriteByte(mxc_uart_regs_t *uart, uint8_t data)
{
// Wait for TXFIFO if full
while (uart->status & MXC_F_UART_STATUS_TX_FULL) {
}
// Put data into fifo
uart->fifo = data;
}
/* ************************************************************************* */
int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req)
{
int uart_num; // Holds the current index of tx_states
uint32_t flags; // Holds the Interrupt flags
// Check data pointer
if (req == NULL) {
return E_BAD_PARAM;
}
// Get the state array index
uart_num = MXC_UART_GET_IDX(uart);
if (uart_num < 0) {
return E_BAD_PARAM;
}
if (req->data == NULL) {
return E_NULL_PTR;
}
// Check to make sure baud rate has been set
if (uart->baud0 == 0) {
return E_UNINITIALIZED;
}
// Check if there is already a request in progress
if (rx_states[uart_num] != NULL) {
return E_BUSY;
}
if (!(req->len > 0)) {
return E_NO_ERROR;
}
// Attempt to register this write request
if (mxc_get_lock((uint32_t*)&rx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
return E_BUSY;
}
// Clear the data counter
req->num = 0;
// Clear Interrupt Flags
flags = uart->int_fl;
uart->int_fl = flags;
UART_ReadHandler(uart,req,uart_num,flags);
// Enable the interrupts
uart->int_en |= UART_RX_IE | UART_ER_IE;
return E_NO_ERROR;
}
/* ************************************************************************* */
int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req)
{
int uart_num; // Holds the current index of tx_states
// Check data pointer
if (req == NULL) {
return E_BAD_PARAM;
}
// Get the state array index
uart_num = MXC_UART_GET_IDX(uart);
if (uart_num < 0) {
return E_BAD_PARAM;
}
if (req->data == NULL) {
return E_NULL_PTR;
}
// Check to make sure baud rate has been set
if (uart->baud0 == 0) {
return E_UNINITIALIZED;
}
// Check if there is already a request in progress
if (tx_states[uart_num] != NULL) {
return E_BUSY;
}
if (!(req->len > 0)) {
return E_NO_ERROR;
}
// Attempt to register this write request
if (mxc_get_lock((uint32_t*)&tx_states[uart_num], (uint32_t)req) != E_NO_ERROR) {
return E_BUSY;
}
// Clear the data counter
req->num = 0;
UART_WriteHandler(uart, req, uart_num);
return E_NO_ERROR;
}
/* ************************************************************************* */
int UART_Busy(mxc_uart_regs_t *uart)
{
int uart_num = MXC_UART_GET_IDX(uart); // Holds the current index of tx_states
MXC_ASSERT(uart_num >= 0);
if ((uart->status & MXC_F_UART_STATUS_TX_BUSY) || (uart->status & MXC_F_UART_STATUS_RX_BUSY)) {
return E_BUSY;
}
// Check to see if there are any ongoing transactions and the UART has room in its FIFO
if ((tx_states[uart_num] == NULL) &&
!(uart->status & MXC_F_UART_STATUS_TX_FULL)) {
return E_NO_ERROR;
}
return E_BUSY;
}
/* ************************************************************************* */
int UART_PrepForSleep(mxc_uart_regs_t *uart)
{
if (UART_Busy(uart) != E_NO_ERROR) {
return E_BUSY;
}
// Leave read interrupts enabled, if already enabled
uart->int_en &= (UART_RX_IE | UART_ER_IE);
return E_NO_ERROR;
}
/* ************************************************************************* */
int UART_AbortAsync(uart_req_t *req)
{
int uart_num;
// Figure out if this was a read or write request, find the request, set to NULL
for (uart_num = 0; uart_num < MXC_UART_INSTANCES; uart_num++) {
if (req == rx_states[uart_num]) {
// Disable read interrupts, clear flags.
MXC_UART_GET_UART(uart_num)->int_en &= ~(UART_RX_IE | UART_ER_IE);
MXC_UART_GET_UART(uart_num)->int_fl = (UART_RX_IF | UART_ER_IF);
// Unlock this UART to read
mxc_free_lock((uint32_t*)&rx_states[uart_num]);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_ABORT);
}
return E_NO_ERROR;
}
if (req == tx_states[uart_num]) {
// Disable write interrupts, clear flags.
MXC_UART_GET_UART(uart_num)->int_en &= ~(UART_TX_IE | UART_ER_IE);
MXC_UART_GET_UART(uart_num)->int_fl = (UART_TX_IF | UART_ER_IF);
// Unlock this UART to write
mxc_free_lock((uint32_t*)&tx_states[uart_num]);
// Callback if not NULL
if (req->callback != NULL) {
req->callback(req, E_ABORT);
}
return E_NO_ERROR;
}
}
return E_BAD_PARAM;
}
/* ************************************************************************* */
unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart)
{
return MXC_UART_FIFO_DEPTH - ((uart->status & MXC_F_UART_STATUS_TX_FIFO_CNT) >>
MXC_F_UART_STATUS_TX_FIFO_CNT_POS);
}
/* ************************************************************************* */
unsigned UART_NumReadAvail(mxc_uart_regs_t *uart)
{
return ((uart->status & MXC_F_UART_STATUS_RX_FIFO_CNT) >>
MXC_F_UART_STATUS_RX_FIFO_CNT_POS);
}
/* ************************************************************************* */
unsigned UART_GetFlags(mxc_uart_regs_t *uart)
{
return (uart->int_fl);
}
/* ************************************************************************* */
void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask)
{
uart->int_fl = mask;
}
/* ************************************************************************* */
void UART_Enable(mxc_uart_regs_t *uart)
{
uart->ctrl |= MXC_F_UART_CTRL_ENABLE;
}
/* ************************************************************************* */
void UART_Disable(mxc_uart_regs_t *uart)
{
uart->ctrl &= ~MXC_F_UART_CTRL_ENABLE;
}
/* ************************************************************************* */
void UART_DrainRX(mxc_uart_regs_t *uart)
{
uart->ctrl |= MXC_F_UART_CTRL_RX_FLUSH;
}
/* ************************************************************************* */
void UART_DrainTX(mxc_uart_regs_t *uart)
{
uart->ctrl |= MXC_F_UART_CTRL_TX_FLUSH;
}

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Project/SDK/Driver/Source/wdt.c
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/* *****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
**************************************************************************** */
/* **** Includes **** */
#include "mxc_config.h"
#include "mxc_errors.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
#include "wdt.h"
/* **** Definitions **** */
/* **** Globals **** */
/* **** Functions **** */
/* ************************************************************************** */
int WDT_Init(mxc_wdt_regs_t* wdt, sys_cfg_wdt_t sys_cfg)
{
SYS_WDT_Init(wdt, sys_cfg);
return E_NO_ERROR;
}
/* ************************************************************************** */
void WDT_SetIntPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period)
{
MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_CTRL_INT_PERIOD, period);
}
/* ************************************************************************** */
void WDT_SetResetPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period)
{
MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_CTRL_RST_PERIOD, (period << (MXC_F_WDT_CTRL_RST_PERIOD_POS - MXC_F_WDT_CTRL_INT_PERIOD_POS)));
}
/* ************************************************************************** */
void WDT_Enable(mxc_wdt_regs_t* wdt, int enable)
{
if (enable) {
wdt->ctrl |= MXC_F_WDT_CTRL_WDT_EN;
} else {
wdt->ctrl &= ~(MXC_F_WDT_CTRL_WDT_EN);
}
}
/* ************************************************************************** */
void WDT_EnableInt(mxc_wdt_regs_t* wdt, int enable)
{
if (enable) {
wdt->ctrl |= MXC_F_WDT_CTRL_INT_EN;
} else {
wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_EN);
}
}
/* ************************************************************************** */
void WDT_EnableReset(mxc_wdt_regs_t* wdt, int enable)
{
if (enable) {
wdt->ctrl |= MXC_F_WDT_CTRL_RST_EN;
} else {
wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_EN);
}
}
/* ************************************************************************** */
void WDT_ResetTimer(mxc_wdt_regs_t* wdt)
{
wdt->rst = 0x00A5;
wdt->rst = 0x005A;
}
/* ************************************************************************** */
int WDT_GetResetFlag(mxc_wdt_regs_t* wdt)
{
return !!(wdt->ctrl & MXC_F_WDT_CTRL_RST_FLAG);
}
/* ************************************************************************** */
void WDT_ClearResetFlag(mxc_wdt_regs_t* wdt)
{
wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_FLAG);
}
/* ************************************************************************** */
int WDT_GetIntFlag(mxc_wdt_regs_t* wdt)
{
return !!(wdt->ctrl & MXC_F_WDT_CTRL_INT_FLAG);
}
/* ************************************************************************** */
void WDT_ClearIntFlag(mxc_wdt_regs_t* wdt)
{
wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_FLAG);
}

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373
Project/SDK/Startup/startup_max32660.s
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
;
; Permission is hereby granted, free of charge, to any person obtaining a
; copy of this software and associated documentation files (the "Software"),
; to deal in the Software without restriction, including without limitation
; the rights to use, copy, modify, merge, publish, distribute, sublicense,
; and/or sell copies of the Software, and to permit persons to whom the
; Software is furnished to do so, subject to the following conditions:
;
; The above copyright notice and this permission notice shall be included
; in all copies or substantial portions of the Software.
;
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
; OTHER DEALINGS IN THE SOFTWARE.
;
; Except as contained in this notice, the name of Maxim Integrated
; Products, Inc. shall not be used except as stated in the Maxim Integrated
; Products, Inc. Branding Policy.
;
; The mere transfer of this software does not imply any licenses
; of trade secrets, proprietary technology, copyrights, patents,
; trademarks, maskwork rights, or any other form of intellectual
; property whatsoever. Maxim Integrated Products, Inc. retains all
; ownership rights.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; To map FreeRTOS function names to their CMSIS equivalents add following lines to FreeRTOSConfig.h
; #define vPortSVCHandler SVC_Handler
; #define xPortPendSVHandler PendSV_Handler
; #define xPortSysTickHandler SysTick_Handler
; *------- <<< Use Configuration Wizard in Context Menu to Modify Stack Size and Heap Size. >>> ----
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp ; Name used with Keil Configuration Wizard and Keil MicroLib
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
EXPORT __isr_vector
IMPORT SysTick_Handler
__isr_vector DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; Device-specific Interrupts
DCD PF_IRQHandler ; 0x10 0x0040 16: Power Fail
DCD WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0
DCD RSV00_IRQHandler ; 0x12 0x0048 18: RSV00
DCD RTC_IRQHandler ; 0x13 0x004C 19: RTC
DCD RSV01_IRQHandler ; 0x14 0x0050 20: RSV1
DCD TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0
DCD TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1
DCD TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2
DCD RSV02_IRQHandler ; 0x18 0x0060 24: RSV02
DCD RSV03_IRQHandler ; 0x19 0x0064 25: RSV03
DCD RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04
DCD RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05
DCD RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06
DCD I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0
DCD UART0_IRQHandler ; 0x1E 0x0078 30: UART 0
DCD UART1_IRQHandler ; 0x1F 0x007C 31: UART 1
DCD SPI0_IRQHandler ; 0x20 0x0080 32: SPIY17
DCD SPI1_IRQHandler ; 0x21 0x0084 33: SPIMSS
DCD RSV07_IRQHandler ; 0x22 0x0088 34: RSV07
DCD RSV08_IRQHandler ; 0x23 0x008C 35: RSV08
DCD RSV09_IRQHandler ; 0x24 0x0090 36: RSV09
DCD RSV10_IRQHandler ; 0x25 0x0094 37: RSV10
DCD RSV11_IRQHandler ; 0x26 0x0098 38: RSV11
DCD FLC_IRQHandler ; 0x27 0x009C 39: FLC
DCD GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0
DCD RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12
DCD RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13
DCD RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14
DCD DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0
DCD DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1
DCD DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2
DCD DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3
DCD RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15
DCD RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16
DCD RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17
DCD RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18
DCD I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1
DCD RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19
DCD RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20
DCD RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21
DCD RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22
DCD RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23
DCD RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24
DCD RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25
DCD RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26
DCD RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27
DCD RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28
DCD RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29
DCD RSV30_IRQHandler ; 0x40 0x0100 64: RSV30
DCD RSV31_IRQHandler ; 0x41 0x0104 65: RSV31
DCD RSV32_IRQHandler ; 0x42 0x0108 66: RSV32
DCD RSV33_IRQHandler ; 0x43 0x010C 67: RSV33
DCD RSV34_IRQHandler ; 0x44 0x0110 68: RSV34
DCD RSV35_IRQHandler ; 0x45 0x0114 69: RSV35
DCD GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup
__isr_vector_end
__isr_vector_size EQU __isr_vector_end - __isr_vector
__Vectors EQU __isr_vector
__Vectors_End EQU __isr_vector_end
__Vectors_Size EQU __isr_vector_size
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT PreInit
;IMPORT SystemInit
IMPORT __main
LDR R0, =PreInit ; Call to PreInit (prior to RAM initialization)
BLX R0
LDR R0, =__main ; SystemInit() is called from post scatter memory initialization in function $Sub$$__main_after_scatterload - system_max32660.c
BX R0
__SPIN
WFI
BL __SPIN
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
Default_Handler\
PROC
; MAX32660 Device-specific Interrupts
EXPORT PF_IRQHandler [WEAK] ; 0x10 0x0040 16: Power Fail
EXPORT WDT0_IRQHandler [WEAK] ; 0x11 0x0044 17: Watchdog 0
EXPORT RSV00_IRQHandler [WEAK] ; 0x12 0x0048 18: RSV00
EXPORT RTC_IRQHandler [WEAK] ; 0x13 0x004C 19: RTC
EXPORT RSV01_IRQHandler [WEAK] ; 0x14 0x0050 20: RSV01
EXPORT TMR0_IRQHandler [WEAK] ; 0x15 0x0054 21: Timer 0
EXPORT TMR1_IRQHandler [WEAK] ; 0x16 0x0058 22: Timer 1
EXPORT TMR2_IRQHandler [WEAK] ; 0x17 0x005C 23: Timer 2
EXPORT RSV02_IRQHandler [WEAK] ; 0x18 0x0060 24: RSV02
EXPORT RSV03_IRQHandler [WEAK] ; 0x19 0x0064 25: RSV03
EXPORT RSV04_IRQHandler [WEAK] ; 0x1A 0x0068 26: RSV04
EXPORT RSV05_IRQHandler [WEAK] ; 0x1B 0x006C 27: RSV05
EXPORT RSV06_IRQHandler [WEAK] ; 0x1C 0x0070 28: RSV06
EXPORT I2C0_IRQHandler [WEAK] ; 0x1D 0x0074 29: I2C0
EXPORT UART0_IRQHandler [WEAK] ; 0x1E 0x0078 30: UART 0
EXPORT UART1_IRQHandler [WEAK] ; 0x1F 0x007C 31: UART 1
EXPORT SPI0_IRQHandler [WEAK] ; 0x20 0x0080 32: SPIY17
EXPORT SPI1_IRQHandler [WEAK] ; 0x21 0x0084 33: SPIMSS
EXPORT RSV07_IRQHandler [WEAK] ; 0x22 0x0088 34: RSV07
EXPORT RSV08_IRQHandler [WEAK] ; 0x23 0x008C 35: RSV08
EXPORT RSV09_IRQHandler [WEAK] ; 0x24 0x0090 36: RSV09
EXPORT RSV10_IRQHandler [WEAK] ; 0x25 0x0094 37: RSV10
EXPORT RSV11_IRQHandler [WEAK] ; 0x26 0x0098 38: RSV11
EXPORT FLC_IRQHandler [WEAK] ; 0x27 0x009C 39: FLC
EXPORT GPIO0_IRQHandler [WEAK] ; 0x28 0x00A0 40: GPIO0
EXPORT RSV12_IRQHandler [WEAK] ; 0x29 0x00A4 41: RSV12
EXPORT RSV13_IRQHandler [WEAK] ; 0x2A 0x00A8 42: RSV13
EXPORT RSV14_IRQHandler [WEAK] ; 0x2B 0x00AC 43: RSV14
EXPORT DMA0_IRQHandler [WEAK] ; 0x2C 0x00B0 44: DMA0
EXPORT DMA1_IRQHandler [WEAK] ; 0x2D 0x00B4 45: DMA1
EXPORT DMA2_IRQHandler [WEAK] ; 0x2E 0x00B8 46: DMA2
EXPORT DMA3_IRQHandler [WEAK] ; 0x2F 0x00BC 47: DMA3
EXPORT RSV15_IRQHandler [WEAK] ; 0x30 0x00C0 48: RSV15
EXPORT RSV16_IRQHandler [WEAK] ; 0x31 0x00C4 49: RSV16
EXPORT RSV17_IRQHandler [WEAK] ; 0x32 0x00C8 50: RSV17
EXPORT RSV18_IRQHandler [WEAK] ; 0x33 0x00CC 51: RSV18
EXPORT I2C1_IRQHandler [WEAK] ; 0x34 0x00D0 52: I2C1
EXPORT RSV19_IRQHandler [WEAK] ; 0x35 0x00D4 53: RSV19
EXPORT RSV20_IRQHandler [WEAK] ; 0x36 0x00D8 54: RSV20
EXPORT RSV21_IRQHandler [WEAK] ; 0x37 0x00DC 55: RSV21
EXPORT RSV22_IRQHandler [WEAK] ; 0x38 0x00E0 56: RSV22
EXPORT RSV23_IRQHandler [WEAK] ; 0x39 0x00E4 57: RSV23
EXPORT RSV24_IRQHandler [WEAK] ; 0x3A 0x00E8 58: RSV24
EXPORT RSV25_IRQHandler [WEAK] ; 0x3B 0x00EC 59: RSV25
EXPORT RSV26_IRQHandler [WEAK] ; 0x3C 0x00F0 60: RSV26
EXPORT RSV27_IRQHandler [WEAK] ; 0x3D 0x00F4 61: RSV27
EXPORT RSV28_IRQHandler [WEAK] ; 0x3E 0x00F8 62: RSV28
EXPORT RSV29_IRQHandler [WEAK] ; 0x3F 0x00FC 63: RSV29
EXPORT RSV30_IRQHandler [WEAK] ; 0x40 0x0100 64: RSV30
EXPORT RSV31_IRQHandler [WEAK] ; 0x41 0x0104 65: RSV31
EXPORT RSV32_IRQHandler [WEAK] ; 0x42 0x0108 66: RSV32
EXPORT RSV33_IRQHandler [WEAK] ; 0x43 0x010C 67: RSV33
EXPORT RSV34_IRQHandler [WEAK] ; 0x44 0x0110 68: RSV34
EXPORT RSV35_IRQHandler [WEAK] ; 0x45 0x0114 69: RSV35
EXPORT GPIOWAKE_IRQHandler [WEAK] ; 0x46 0x0118 70: GPIO Wakeup
;*******************************************************************************
; Default handler implementations
;*******************************************************************************
PF_IRQHandler ; 0x10 0x0040 16: Power Fail
WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0
RSV00_IRQHandler ; 0x12 0x0048 18: RSV00
RTC_IRQHandler ; 0x13 0x004C 19: RTC
RSV01_IRQHandler ; 0x14 0x0050 20: RSV01
TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0
TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1
TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2
RSV02_IRQHandler ; 0x18 0x0060 24: RSV02
RSV03_IRQHandler ; 0x19 0x0064 25: RSV03
RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04
RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05
RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06
I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0
UART0_IRQHandler ; 0x1E 0x0078 30: UART 0
UART1_IRQHandler ; 0x1F 0x007C 31: UART 1
SPI0_IRQHandler ; 0x20 0x0080 32: SPI0
SPI1_IRQHandler ; 0x21 0x0084 33: SPI1
RSV07_IRQHandler ; 0x22 0x0088 34: RSV07
RSV08_IRQHandler ; 0x23 0x008C 35: RSV08
RSV09_IRQHandler ; 0x24 0x0090 36: RSV09
RSV10_IRQHandler ; 0x25 0x0094 37: RSV10
RSV11_IRQHandler ; 0x26 0x0098 38: RSV11
FLC_IRQHandler ; 0x27 0x009C 39: FLC
GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0
RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12
RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13
RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14
DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0
DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1
DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2
DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3
RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15
RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16
RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17
RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18
I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1
RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19
RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20
RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21
RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22
RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23
RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24
RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25
RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26
RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27
RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28
RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29
RSV30_IRQHandler ; 0x40 0x0100 64: RSV30
RSV31_IRQHandler ; 0x41 0x0104 65: RSV31
RSV32_IRQHandler ; 0x42 0x0108 66: RSV32
RSV33_IRQHandler ; 0x43 0x010C 67: RSV33
RSV34_IRQHandler ; 0x44 0x0110 68: RSV34
RSV35_IRQHandler ; 0x45 0x0114 69: RSV35
GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap\
PROC
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
;;;;;;;;;;;;;;;;;;;;;;;;;
;; End of file.
;;;;;;;;;;;;;;;;;;;;;;;;;
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