From e562e43699f36f1dec0c8c341d20f054f01b659a Mon Sep 17 00:00:00 2001 From: imbis Date: Fri, 24 May 2024 11:37:41 +0900 Subject: [PATCH] Init Commit --- .gitignore | 1 + Project/Application/board_config.h | 38 + Project/Application/define.h | 38 + Project/Application/interrput_handler.c | 4 + Project/Application/interrput_handler.h | 8 + Project/Application/main.c | 27 + Project/Application/main.h | 8 + Project/Application/struct.h | 8 + Project/Application/system_func.c | 30 + Project/Application/system_func.h | 16 + .../Compiler/AKM_Temperature_Demo.uvguix.befs | 1905 ++ Project/Compiler/AKM_Temperature_Demo.uvoptx | 540 + Project/Compiler/AKM_Temperature_Demo.uvprojx | 557 + .../Listings/AKM_Temperature_Demo.map | 1108 + .../Compiler/Listings/startup_max32660.lst | 1638 ++ Project/SDK/Debuggint_Info/max32660.SFR | Bin 0 -> 336380 bytes Project/SDK/Debuggint_Info/max32660.sfd | 19991 ++++++++++++++++ Project/SDK/Debuggint_Info/max32660.svd | 8701 +++++++ .../SDK/Device/Include/arm_common_tables.h | 100 + .../SDK/Device/Include/arm_const_structs.h | 85 + Project/SDK/Device/Include/arm_math.h | 7306 ++++++ Project/SDK/Device/Include/bbfc_regs.h | 127 + Project/SDK/Device/Include/bbsir_regs.h | 111 + Project/SDK/Device/Include/core_cm3.h | 1627 ++ Project/SDK/Device/Include/core_cm4.h | 1772 ++ Project/SDK/Device/Include/core_cm4_simd.h | 671 + Project/SDK/Device/Include/core_cmFunc.h | 633 + Project/SDK/Device/Include/core_cmInstr.h | 688 + Project/SDK/Device/Include/dma_regs.h | 470 + Project/SDK/Device/Include/flc_regs.h | 264 + Project/SDK/Device/Include/gcr_regs.h | 769 + Project/SDK/Device/Include/gpio_regs.h | 663 + Project/SDK/Device/Include/i2c_regs.h | 843 + Project/SDK/Device/Include/icc_regs.h | 167 + Project/SDK/Device/Include/max32660.h | 403 + Project/SDK/Device/Include/mxc_device.h | 72 + Project/SDK/Device/Include/pwrseq_regs.h | 273 + Project/SDK/Device/Include/rtc_regs.h | 297 + Project/SDK/Device/Include/sir_regs.h | 255 + Project/SDK/Device/Include/smon_regs.h | 628 + Project/SDK/Device/Include/spi17y_regs.h | 664 + Project/SDK/Device/Include/spimss_regs.h | 496 + Project/SDK/Device/Include/system_max32660.h | 93 + Project/SDK/Device/Include/tmr_regs.h | 233 + Project/SDK/Device/Include/uart_regs.h | 450 + Project/SDK/Device/Include/wdt_regs.h | 236 + Project/SDK/Device/system_max32660.c | 167 + Project/SDK/Driver/Include/dma.h | 317 + Project/SDK/Driver/Include/flc.h | 200 + Project/SDK/Driver/Include/gpio.h | 295 + Project/SDK/Driver/Include/i2c.h | 250 + Project/SDK/Driver/Include/i2s.h | 179 + Project/SDK/Driver/Include/icc.h | 97 + Project/SDK/Driver/Include/lp.h | 341 + Project/SDK/Driver/Include/mxc_assert.h | 113 + Project/SDK/Driver/Include/mxc_config.h | 53 + Project/SDK/Driver/Include/mxc_delay.h | 124 + Project/SDK/Driver/Include/mxc_errors.h | 94 + Project/SDK/Driver/Include/mxc_lock.h | 94 + Project/SDK/Driver/Include/mxc_pins.h | 91 + Project/SDK/Driver/Include/mxc_sys.h | 450 + Project/SDK/Driver/Include/nvic_table.h | 89 + Project/SDK/Driver/Include/rtc.h | 242 + Project/SDK/Driver/Include/spi.h | 259 + Project/SDK/Driver/Include/spi17y.h | 242 + Project/SDK/Driver/Include/spimss.h | 197 + Project/SDK/Driver/Include/tmr.h | 265 + Project/SDK/Driver/Include/tmr_utils.h | 146 + Project/SDK/Driver/Include/uart.h | 364 + Project/SDK/Driver/Include/wdt.h | 166 + Project/SDK/Driver/Source/dma.c | 374 + Project/SDK/Driver/Source/flc.c | 579 + Project/SDK/Driver/Source/gpio.c | 312 + Project/SDK/Driver/Source/i2c.c | 1068 + Project/SDK/Driver/Source/i2s.c | 216 + Project/SDK/Driver/Source/icc.c | 84 + Project/SDK/Driver/Source/lp.c | 371 + Project/SDK/Driver/Source/mxc_assert.c | 50 + Project/SDK/Driver/Source/mxc_delay.c | 179 + Project/SDK/Driver/Source/mxc_lock.c | 85 + Project/SDK/Driver/Source/mxc_pins.c | 79 + Project/SDK/Driver/Source/mxc_sys.c | 721 + Project/SDK/Driver/Source/nvic_table.c | 84 + Project/SDK/Driver/Source/rtc.c | 419 + Project/SDK/Driver/Source/spi.c | 254 + Project/SDK/Driver/Source/spi17y.c | 641 + Project/SDK/Driver/Source/spimss.c | 514 + Project/SDK/Driver/Source/tmr.c | 307 + Project/SDK/Driver/Source/tmr_utils.c | 168 + Project/SDK/Driver/Source/uart.c | 718 + Project/SDK/Driver/Source/wdt.c | 129 + Project/SDK/FlashLoader/MAX32660.FLM | Bin 0 -> 13696 bytes Project/SDK/Startup/startup_max32660.s | 373 + 93 files changed, 67574 insertions(+) create mode 100644 .gitignore create mode 100644 Project/Application/board_config.h create mode 100644 Project/Application/define.h create mode 100644 Project/Application/interrput_handler.c create mode 100644 Project/Application/interrput_handler.h create mode 100644 Project/Application/main.c create mode 100644 Project/Application/main.h create mode 100644 Project/Application/struct.h create mode 100644 Project/Application/system_func.c create mode 100644 Project/Application/system_func.h create mode 100644 Project/Compiler/AKM_Temperature_Demo.uvguix.befs create mode 100644 Project/Compiler/AKM_Temperature_Demo.uvoptx create mode 100644 Project/Compiler/AKM_Temperature_Demo.uvprojx create mode 100644 Project/Compiler/Listings/AKM_Temperature_Demo.map create mode 100644 Project/Compiler/Listings/startup_max32660.lst create mode 100644 Project/SDK/Debuggint_Info/max32660.SFR create mode 100644 Project/SDK/Debuggint_Info/max32660.sfd create mode 100644 Project/SDK/Debuggint_Info/max32660.svd create mode 100644 Project/SDK/Device/Include/arm_common_tables.h create mode 100644 Project/SDK/Device/Include/arm_const_structs.h create mode 100644 Project/SDK/Device/Include/arm_math.h create mode 100644 Project/SDK/Device/Include/bbfc_regs.h create mode 100644 Project/SDK/Device/Include/bbsir_regs.h create mode 100644 Project/SDK/Device/Include/core_cm3.h create mode 100644 Project/SDK/Device/Include/core_cm4.h create mode 100644 Project/SDK/Device/Include/core_cm4_simd.h create mode 100644 Project/SDK/Device/Include/core_cmFunc.h create mode 100644 Project/SDK/Device/Include/core_cmInstr.h create mode 100644 Project/SDK/Device/Include/dma_regs.h create mode 100644 Project/SDK/Device/Include/flc_regs.h create mode 100644 Project/SDK/Device/Include/gcr_regs.h create mode 100644 Project/SDK/Device/Include/gpio_regs.h create mode 100644 Project/SDK/Device/Include/i2c_regs.h create mode 100644 Project/SDK/Device/Include/icc_regs.h create mode 100644 Project/SDK/Device/Include/max32660.h create mode 100644 Project/SDK/Device/Include/mxc_device.h create mode 100644 Project/SDK/Device/Include/pwrseq_regs.h create mode 100644 Project/SDK/Device/Include/rtc_regs.h create mode 100644 Project/SDK/Device/Include/sir_regs.h create mode 100644 Project/SDK/Device/Include/smon_regs.h create mode 100644 Project/SDK/Device/Include/spi17y_regs.h create mode 100644 Project/SDK/Device/Include/spimss_regs.h create mode 100644 Project/SDK/Device/Include/system_max32660.h create mode 100644 Project/SDK/Device/Include/tmr_regs.h create mode 100644 Project/SDK/Device/Include/uart_regs.h create mode 100644 Project/SDK/Device/Include/wdt_regs.h create mode 100644 Project/SDK/Device/system_max32660.c create mode 100644 Project/SDK/Driver/Include/dma.h create mode 100644 Project/SDK/Driver/Include/flc.h create mode 100644 Project/SDK/Driver/Include/gpio.h create mode 100644 Project/SDK/Driver/Include/i2c.h create mode 100644 Project/SDK/Driver/Include/i2s.h create mode 100644 Project/SDK/Driver/Include/icc.h create mode 100644 Project/SDK/Driver/Include/lp.h create mode 100644 Project/SDK/Driver/Include/mxc_assert.h create mode 100644 Project/SDK/Driver/Include/mxc_config.h create mode 100644 Project/SDK/Driver/Include/mxc_delay.h create mode 100644 Project/SDK/Driver/Include/mxc_errors.h create mode 100644 Project/SDK/Driver/Include/mxc_lock.h create mode 100644 Project/SDK/Driver/Include/mxc_pins.h create mode 100644 Project/SDK/Driver/Include/mxc_sys.h create mode 100644 Project/SDK/Driver/Include/nvic_table.h create mode 100644 Project/SDK/Driver/Include/rtc.h create mode 100644 Project/SDK/Driver/Include/spi.h create mode 100644 Project/SDK/Driver/Include/spi17y.h create mode 100644 Project/SDK/Driver/Include/spimss.h create mode 100644 Project/SDK/Driver/Include/tmr.h create mode 100644 Project/SDK/Driver/Include/tmr_utils.h create mode 100644 Project/SDK/Driver/Include/uart.h create mode 100644 Project/SDK/Driver/Include/wdt.h create mode 100644 Project/SDK/Driver/Source/dma.c create mode 100644 Project/SDK/Driver/Source/flc.c create mode 100644 Project/SDK/Driver/Source/gpio.c create mode 100644 Project/SDK/Driver/Source/i2c.c create mode 100644 Project/SDK/Driver/Source/i2s.c create mode 100644 Project/SDK/Driver/Source/icc.c create mode 100644 Project/SDK/Driver/Source/lp.c create mode 100644 Project/SDK/Driver/Source/mxc_assert.c create mode 100644 Project/SDK/Driver/Source/mxc_delay.c create mode 100644 Project/SDK/Driver/Source/mxc_lock.c create mode 100644 Project/SDK/Driver/Source/mxc_pins.c create mode 100644 Project/SDK/Driver/Source/mxc_sys.c create mode 100644 Project/SDK/Driver/Source/nvic_table.c create mode 100644 Project/SDK/Driver/Source/rtc.c create mode 100644 Project/SDK/Driver/Source/spi.c create mode 100644 Project/SDK/Driver/Source/spi17y.c create mode 100644 Project/SDK/Driver/Source/spimss.c create mode 100644 Project/SDK/Driver/Source/tmr.c create mode 100644 Project/SDK/Driver/Source/tmr_utils.c create mode 100644 Project/SDK/Driver/Source/uart.c create mode 100644 Project/SDK/Driver/Source/wdt.c create mode 100644 Project/SDK/FlashLoader/MAX32660.FLM create mode 100644 Project/SDK/Startup/startup_max32660.s diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..8410fd4 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +Project/Compiler/Objects diff --git a/Project/Application/board_config.h b/Project/Application/board_config.h new file mode 100644 index 0000000..fcf9a52 --- /dev/null +++ b/Project/Application/board_config.h @@ -0,0 +1,38 @@ +/** \file board_config.h */ +#if !defined(BOARD_CONFIG_H__F1656892_AD9D_4187_8FC7_917D59CAB6DB__INCLUDED_) +#define BOARD_CONFIG_H__F1656892_AD9D_4187_8FC7_917D59CAB6DB__INCLUDED_ + + +#include +#include +#include +#include +#include +#include +#include + + + +#include "max32660.h" +#include "mxc_errors.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "i2c.h" +#include "gpio.h" +#include "tmr.h" +#include "lp.h" +#include "flc.h" +#include "uart.h" +#include "icc.h" +#include "wdt.h" + + + +#include "define.h" + + + + + + +#endif diff --git a/Project/Application/define.h b/Project/Application/define.h new file mode 100644 index 0000000..7693dcb --- /dev/null +++ b/Project/Application/define.h @@ -0,0 +1,38 @@ +/** \file define.h */ +#if !defined(DEFINE_H__CB0AACBA_D47E_488E_8E4E_28E3D3453B8C__INCLUDED_) +#define DEFINE_H__CB0AACBA_D47E_488E_8E4E_28E3D3453B8C__INCLUDED_ + + + +#define LOW 0 +#define HIGH 1 + +#define SUCCESS 0 +#define FAIL !SUCCESS + +#define STOP 0 +#define START !START + +#define DISABLE 0 +#define ENABLE !DISABLE + + +#define SETBIT(ADDRESS,BIT) (ADDRESS |= (1< + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 3 + + ..\Application\main.c + 0 + 1 + 8 + 1 + + 0 + + + ..\Application\board_config.h + 16 + 1 + 22 + 1 + + 0 + + + ..\Application\struct.h + 0 + 1 + 6 + 1 + + 0 + + + ..\Application\system_func.c + 32 + 1 + 13 + 1 + + 0 + + + + + diff --git a/Project/Compiler/AKM_Temperature_Demo.uvoptx b/Project/Compiler/AKM_Temperature_Demo.uvoptx new file mode 100644 index 0000000..1930b64 --- /dev/null +++ b/Project/Compiler/AKM_Temperature_Demo.uvoptx @@ -0,0 +1,540 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Demo Board + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00000000 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0MAX32660.FLM -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MAX32660 -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 1000000 + + + + + + Application + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\Application\board_config.h + board_config.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\Application\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\Application\interrput_handler.c + interrput_handler.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\Application\system_func.c + system_func.c + 0 + 0 + + + + + Device + 1 + 0 + 0 + 0 + + 2 + 5 + 1 + 0 + 0 + 0 + ..\SDK\Device\system_max32660.c + system_max32660.c + 0 + 0 + + + + + Startup + 1 + 0 + 0 + 0 + + 3 + 6 + 2 + 0 + 0 + 0 + ..\SDK\Startup\startup_max32660.s + startup_max32660.s + 0 + 0 + + + + + Driver + 0 + 0 + 0 + 0 + + 4 + 7 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\dma.c + dma.c + 0 + 0 + + + 4 + 8 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\flc.c + flc.c + 0 + 0 + + + 4 + 9 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\gpio.c + gpio.c + 0 + 0 + + + 4 + 10 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\i2c.c + i2c.c + 0 + 0 + + + 4 + 11 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\i2s.c + i2s.c + 0 + 0 + + + 4 + 12 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\icc.c + icc.c + 0 + 0 + + + 4 + 13 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\lp.c + lp.c + 0 + 0 + + + 4 + 14 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\mxc_assert.c + mxc_assert.c + 0 + 0 + + + 4 + 15 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\mxc_delay.c + mxc_delay.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\mxc_lock.c + mxc_lock.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\mxc_pins.c + mxc_pins.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\mxc_sys.c + mxc_sys.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\nvic_table.c + nvic_table.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\rtc.c + rtc.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\spi.c + spi.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\spi17y.c + spi17y.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\spimss.c + spimss.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\tmr.c + tmr.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\tmr_utils.c + tmr_utils.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\uart.c + uart.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\SDK\Driver\Source\wdt.c + wdt.c + 0 + 0 + + + + diff --git a/Project/Compiler/AKM_Temperature_Demo.uvprojx b/Project/Compiler/AKM_Temperature_Demo.uvprojx new file mode 100644 index 0000000..d047761 --- /dev/null +++ b/Project/Compiler/AKM_Temperature_Demo.uvprojx @@ -0,0 +1,557 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo Board + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + MAX32660 + Maxim + Maxim.MAX32660.1.4.0 + http://www.mxim.net/microcontroller/pack/ + IRAM(0x20000000,0x00018000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MAX32660 -FS00 -FL040000 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)) + 0 + $$Device:MAX32660$Libraries\Device\Maxim\MAX32660\Include\max32660.h + + + + + + + + + + $$Device:MAX32660$SVD\MAX32660\max32660.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + AKM_Temperature_Demo + 1 + 0 + 1 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + TARGET=32660,TARGET_REV=0x4131 + + ..\SDK\Device;..\SDK\Device\Include;..\SDK\Driver\Include;..\SDK\Driver\Source;..\SDK\FlashLoader;..\SDK\Startup;..\Application;..\Application\common;..\Application\left;..\Application\right;..\Lib\Beflex;..\Lib\H3System;..\Application\sensor\accelometer\bma400;..\Application\sensor\bodytemp;..\Application\sensor\ppg;..\Application\eeprom;..\Application\sensor\proximity;..\Application\sensor\sar + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Application + + + board_config.h + 5 + ..\Application\board_config.h + + + main.c + 1 + ..\Application\main.c + + + interrput_handler.c + 1 + ..\Application\interrput_handler.c + + + system_func.c + 1 + ..\Application\system_func.c + + + + + Device + + + system_max32660.c + 1 + ..\SDK\Device\system_max32660.c + + + + + Startup + + + startup_max32660.s + 2 + ..\SDK\Startup\startup_max32660.s + + + + + Driver + + + dma.c + 1 + ..\SDK\Driver\Source\dma.c + + + flc.c + 1 + ..\SDK\Driver\Source\flc.c + + + gpio.c + 1 + ..\SDK\Driver\Source\gpio.c + + + i2c.c + 1 + ..\SDK\Driver\Source\i2c.c + + + i2s.c + 1 + ..\SDK\Driver\Source\i2s.c + + + icc.c + 1 + ..\SDK\Driver\Source\icc.c + + + lp.c + 1 + ..\SDK\Driver\Source\lp.c + + + mxc_assert.c + 1 + ..\SDK\Driver\Source\mxc_assert.c + + + mxc_delay.c + 1 + ..\SDK\Driver\Source\mxc_delay.c + + + mxc_lock.c + 1 + ..\SDK\Driver\Source\mxc_lock.c + + + mxc_pins.c + 1 + ..\SDK\Driver\Source\mxc_pins.c + + + mxc_sys.c + 1 + ..\SDK\Driver\Source\mxc_sys.c + + + nvic_table.c + 1 + ..\SDK\Driver\Source\nvic_table.c + + + rtc.c + 1 + ..\SDK\Driver\Source\rtc.c + + + spi.c + 1 + ..\SDK\Driver\Source\spi.c + + + spi17y.c + 1 + ..\SDK\Driver\Source\spi17y.c + + + spimss.c + 1 + ..\SDK\Driver\Source\spimss.c + + + tmr.c + 1 + ..\SDK\Driver\Source\tmr.c + + + tmr_utils.c + 1 + ..\SDK\Driver\Source\tmr_utils.c + + + uart.c + 1 + ..\SDK\Driver\Source\uart.c + + + wdt.c + 1 + ..\SDK\Driver\Source\wdt.c + + + + + + + + + + + + + + + + + AKM_Temperature_Demo + 1 + + + + + diff --git a/Project/Compiler/Listings/AKM_Temperature_Demo.map b/Project/Compiler/Listings/AKM_Temperature_Demo.map new file mode 100644 index 0000000..31e9d09 --- /dev/null +++ b/Project/Compiler/Listings/AKM_Temperature_Demo.map @@ -0,0 +1,1108 @@ +Component: ARM Compiler 5.06 update 7 (build 960) Tool: armlink [4d3601] + +============================================================================== + +Section Cross References + + main.o(i.main) refers to system_func.o(i.SystemCoreClockSet) for SystemCoreClockSet + main.o(i.main) refers to icc.o(i.ICC_Enable) for ICC_Enable + system_func.o(i.SystemCoreClockSet) refers to lp.o(i.LP_SetOperatingVoltage) for LP_SetOperatingVoltage + system_func.o(i.SystemCoreClockSet) refers to system_func.o(.data) for usTickCountDiv + system_max32660.o(i.$Sub$$__main_after_scatterload) refers to system_max32660.o(i.SystemInit) for SystemInit + system_max32660.o(i.$Sub$$__main_after_scatterload) refers to entry5.o(.ARM.Collect$$$$00000004) for $Super$$__main_after_scatterload + system_max32660.o(i.SystemCoreClockUpdate) refers to system_max32660.o(.data) for SystemCoreClock + system_max32660.o(i.SystemInit) refers to mxc_sys.o(i.SYS_Clock_Select) for SYS_Clock_Select + system_max32660.o(i.SystemInit) refers to mxc_sys.o(i.SYS_ClockDisable) for SYS_ClockDisable + system_max32660.o(i.SystemInit) refers to system_max32660.o(i.Board_Init) for Board_Init + system_max32660.o(i.SystemInit) refers to startup_max32660.o(RESET) for __isr_vector + startup_max32660.o(RESET) refers to startup_max32660.o(STACK) for __initial_sp + startup_max32660.o(RESET) refers to startup_max32660.o(.text) for Reset_Handler + startup_max32660.o(RESET) refers to mxc_delay.o(i.SysTick_Handler) for SysTick_Handler + startup_max32660.o(.text) refers to system_max32660.o(i.PreInit) for PreInit + startup_max32660.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main + dma.o(i.DMA_AcquireChannel) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + dma.o(i.DMA_AcquireChannel) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + dma.o(i.DMA_AcquireChannel) refers to dma.o(.data) for dma_initialized + dma.o(i.DMA_AcquireChannel) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_ClearFlags) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_ConfigChannel) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_DisableInterrupt) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_EnableInterrupt) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_GetCHRegs) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_GetFlags) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_Handler) refers to dma.o(i.DMA_ClearFlags) for DMA_ClearFlags + dma.o(i.DMA_Handler) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_Init) refers to mxc_sys.o(i.SYS_DMA_Init) for SYS_DMA_Init + dma.o(i.DMA_Init) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + dma.o(i.DMA_Init) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + dma.o(i.DMA_Init) refers to dma.o(.data) for dma_initialized + dma.o(i.DMA_Init) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_ReleaseChannel) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + dma.o(i.DMA_ReleaseChannel) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + dma.o(i.DMA_ReleaseChannel) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_ReleaseChannel) refers to dma.o(.data) for dma_lock + dma.o(i.DMA_SetCallback) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_SetReload) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_SetSrcDstCnt) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_Shutdown) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + dma.o(i.DMA_Shutdown) refers to mxc_sys.o(i.SYS_DMA_Shutdown) for SYS_DMA_Shutdown + dma.o(i.DMA_Shutdown) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + dma.o(i.DMA_Shutdown) refers to dma.o(.data) for dma_initialized + dma.o(i.DMA_Shutdown) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_Start) refers to dma.o(i.DMA_ClearFlags) for DMA_ClearFlags + dma.o(i.DMA_Start) refers to dma.o(.bss) for dma_resource + dma.o(i.DMA_Stop) refers to dma.o(.bss) for dma_resource + flc.o(.flashprog) refers to mxc_sys.o(i.SYS_FLC_Init) for SYS_FLC_Init + flc.o(.flashprog) refers to mxc_sys.o(i.SYS_Flash_Operation) for SYS_Flash_Operation + flc.o(.flashprog) refers to memcpya.o(.text) for __aeabi_memcpy + flc.o(.flashprog) refers to system_max32660.o(.data) for SystemCoreClock + gpio.o(i.GPIO_Handler) refers to gpio.o(.bss) for callback + gpio.o(i.GPIO_Init) refers to gpio.o(.bss) for callback + gpio.o(i.GPIO_RegisterCallback) refers to gpio.o(.bss) for callback + i2c.o(i.I2C_AbortAsync) refers to i2c.o(i.I2C_Recover) for I2C_Recover + i2c.o(i.I2C_AbortAsync) refers to i2c.o(i.I2C_FreeCallback) for I2C_FreeCallback + i2c.o(i.I2C_AbortAsync) refers to i2c.o(.bss) for states + i2c.o(i.I2C_FreeCallback) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + i2c.o(i.I2C_FreeCallback) refers to i2c.o(.bss) for states + i2c.o(i.I2C_Handler) refers to i2c.o(i.I2C_MasterHandler) for I2C_MasterHandler + i2c.o(i.I2C_Handler) refers to i2c.o(i.I2C_SlaveHandler) for I2C_SlaveHandler + i2c.o(i.I2C_Init) refers to mxc_sys.o(i.SYS_I2C_Init) for SYS_I2C_Init + i2c.o(i.I2C_Init) refers to mxc_delay.o(i.mxc_delay) for mxc_delay + i2c.o(i.I2C_Init) refers to i2c.o(i.I2C_Setspeed) for I2C_Setspeed + i2c.o(i.I2C_Init) refers to i2c.o(.bss) for states + i2c.o(i.I2C_MasterAsync) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + i2c.o(i.I2C_MasterAsync) refers to i2c.o(i.I2C_MasterHandler) for I2C_MasterHandler + i2c.o(i.I2C_MasterAsync) refers to i2c.o(.bss) for states + i2c.o(i.I2C_MasterHandler) refers to i2c.o(i.I2C_Recover) for I2C_Recover + i2c.o(i.I2C_MasterHandler) refers to i2c.o(i.I2C_FreeCallback) for I2C_FreeCallback + i2c.o(i.I2C_MasterHandler) refers to i2c.o(.bss) for states + i2c.o(i.I2C_SetTimeout) refers to system_max32660.o(.data) for SystemCoreClock + i2c.o(i.I2C_Setspeed) refers to mxc_sys.o(i.SYS_I2C_GetFreq) for SYS_I2C_GetFreq + i2c.o(i.I2C_Shutdown) refers to i2c.o(i.I2C_Recover) for I2C_Recover + i2c.o(i.I2C_Shutdown) refers to i2c.o(i.I2C_FreeCallback) for I2C_FreeCallback + i2c.o(i.I2C_Shutdown) refers to mxc_sys.o(i.SYS_I2C_Shutdown) for SYS_I2C_Shutdown + i2c.o(i.I2C_Shutdown) refers to i2c.o(.bss) for states + i2c.o(i.I2C_Slave) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + i2c.o(i.I2C_Slave) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + i2c.o(i.I2C_Slave) refers to i2c.o(.bss) for states + i2c.o(i.I2C_SlaveAsync) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + i2c.o(i.I2C_SlaveAsync) refers to i2c.o(.bss) for states + i2c.o(i.I2C_SlaveHandler) refers to i2c.o(i.I2C_Recover) for I2C_Recover + i2c.o(i.I2C_SlaveHandler) refers to i2c.o(i.I2C_FreeCallback) for I2C_FreeCallback + i2c.o(i.I2C_SlaveHandler) refers to i2c.o(.bss) for states + i2s.o(i.I2S_DMA_ClearFlags) refers to dma.o(i.DMA_ClearFlags) for DMA_ClearFlags + i2s.o(i.I2S_DMA_ClearFlags) refers to i2s.o(.data) for dma_channel + i2s.o(i.I2S_DMA_SetAddrCnt) refers to dma.o(i.DMA_SetSrcDstCnt) for DMA_SetSrcDstCnt + i2s.o(i.I2S_DMA_SetAddrCnt) refers to i2s.o(.data) for dma_channel + i2s.o(i.I2S_DMA_SetReload) refers to dma.o(i.DMA_SetReload) for DMA_SetReload + i2s.o(i.I2S_DMA_SetReload) refers to i2s.o(.data) for dma_channel + i2s.o(i.I2S_Init) refers to mxc_sys.o(i.SYS_I2S_Init) for SYS_I2S_Init + i2s.o(i.I2S_Init) refers to mxc_sys.o(i.SYS_I2S_GetFreq) for SYS_I2S_GetFreq + i2s.o(i.I2S_Init) refers to dma.o(i.DMA_Init) for DMA_Init + i2s.o(i.I2S_Init) refers to dma.o(i.DMA_AcquireChannel) for DMA_AcquireChannel + i2s.o(i.I2S_Init) refers to dma.o(i.DMA_ConfigChannel) for DMA_ConfigChannel + i2s.o(i.I2S_Init) refers to dma.o(i.DMA_SetCallback) for DMA_SetCallback + i2s.o(i.I2S_Init) refers to dma.o(i.DMA_EnableInterrupt) for DMA_EnableInterrupt + i2s.o(i.I2S_Init) refers to i2s.o(i.I2S_DMA_SetAddrCnt) for I2S_DMA_SetAddrCnt + i2s.o(i.I2S_Init) refers to i2s.o(i.I2S_DMA_SetReload) for I2S_DMA_SetReload + i2s.o(i.I2S_Init) refers to i2s.o(i.I2S_Start) for I2S_Start + i2s.o(i.I2S_Init) refers to i2s.o(.data) for dma_channel + i2s.o(i.I2S_Shutdown) refers to mxc_sys.o(i.SYS_I2S_Shutdown) for SYS_I2S_Shutdown + i2s.o(i.I2S_Shutdown) refers to dma.o(i.DMA_ReleaseChannel) for DMA_ReleaseChannel + i2s.o(i.I2S_Shutdown) refers to i2s.o(.data) for dma_channel + i2s.o(i.I2S_Start) refers to dma.o(i.DMA_Start) for DMA_Start + i2s.o(i.I2S_Start) refers to i2s.o(.data) for dma_channel + i2s.o(i.I2S_Stop) refers to dma.o(i.DMA_Stop) for DMA_Stop + i2s.o(i.I2S_Stop) refers to i2s.o(.data) for dma_channel + icc.o(i.ICC_Enable) refers to icc.o(i.ICC_Ready) for ICC_Ready + icc.o(i.ICC_Flush) refers to icc.o(i.ICC_Disable) for ICC_Disable + icc.o(i.ICC_Flush) refers to icc.o(i.ICC_Enable) for ICC_Enable + lp.o(i.LP_SetOperatingVoltage) refers to system_max32660.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate + mxc_delay.o(i.SysTick_Handler) refers to mxc_delay.o(i.mxc_delay_handler) for mxc_delay_handler + mxc_delay.o(i.mxc_delay) refers to mxc_delay.o(i.mxc_delay_init) for mxc_delay_init + mxc_delay.o(i.mxc_delay) refers to mxc_delay.o(i.mxc_delay_stop) for mxc_delay_stop + mxc_delay.o(i.mxc_delay) refers to mxc_delay.o(.data) for compare_value + mxc_delay.o(i.mxc_delay_check) refers to mxc_delay.o(i.mxc_delay_stop) for mxc_delay_stop + mxc_delay.o(i.mxc_delay_check) refers to mxc_delay.o(.data) for compare_value + mxc_delay.o(i.mxc_delay_handler) refers to mxc_delay.o(i.mxc_delay_stop) for mxc_delay_stop + mxc_delay.o(i.mxc_delay_handler) refers to mxc_delay.o(.data) for compare_value + mxc_delay.o(i.mxc_delay_init) refers to uldiv.o(.text) for __aeabi_uldivmod + mxc_delay.o(i.mxc_delay_init) refers to mxc_delay.o(.data) for ctrl_save + mxc_delay.o(i.mxc_delay_init) refers to system_max32660.o(.data) for SystemCoreClock + mxc_delay.o(i.mxc_delay_start) refers to mxc_delay.o(i.mxc_delay_init) for mxc_delay_init + mxc_delay.o(i.mxc_delay_start) refers to mxc_delay.o(.data) for compare_value + mxc_delay.o(i.mxc_delay_stop) refers to mxc_delay.o(.data) for ctrl_save + mxc_sys.o(i.SYS_Clock_Select) refers to mxc_sys.o(i.SYS_Clock_Timeout) for SYS_Clock_Timeout + mxc_sys.o(i.SYS_Clock_Select) refers to system_max32660.o(i.SystemCoreClockUpdate) for SystemCoreClockUpdate + mxc_sys.o(i.SYS_Clock_Timeout) refers to mxc_delay.o(i.mxc_delay_start) for mxc_delay_start + mxc_sys.o(i.SYS_Clock_Timeout) refers to mxc_delay.o(i.mxc_delay_stop) for mxc_delay_stop + mxc_sys.o(i.SYS_Clock_Timeout) refers to mxc_delay.o(i.mxc_delay_check) for mxc_delay_check + mxc_sys.o(i.SYS_DMA_Init) refers to mxc_sys.o(i.SYS_ClockEnable) for SYS_ClockEnable + mxc_sys.o(i.SYS_DMA_Shutdown) refers to mxc_sys.o(i.SYS_ClockDisable) for SYS_ClockDisable + mxc_sys.o(i.SYS_I2C_GetFreq) refers to system_max32660.o(.data) for SystemCoreClock + mxc_sys.o(i.SYS_I2C_Init) refers to mxc_sys.o(i.SYS_ClockEnable) for SYS_ClockEnable + mxc_sys.o(i.SYS_I2C_Init) refers to gpio.o(i.GPIO_Config) for GPIO_Config + mxc_sys.o(i.SYS_I2C_Init) refers to mxc_pins.o(.constdata) for gpio_cfg_i2c0 + mxc_sys.o(i.SYS_I2C_Shutdown) refers to mxc_sys.o(i.SYS_ClockDisable) for SYS_ClockDisable + mxc_sys.o(i.SYS_I2C_Shutdown) refers to gpio.o(i.GPIO_Config) for GPIO_Config + mxc_sys.o(i.SYS_I2C_Shutdown) refers to mxc_pins.o(.constdata) for gpio_cfg_i2c0 + mxc_sys.o(i.SYS_I2S_GetFreq) refers to system_max32660.o(.data) for SystemCoreClock + mxc_sys.o(i.SYS_I2S_Init) refers to gpio.o(i.GPIO_Config) for GPIO_Config + mxc_sys.o(i.SYS_I2S_Init) refers to mxc_sys.o(i.SYS_ClockEnable) for SYS_ClockEnable + mxc_sys.o(i.SYS_I2S_Init) refers to mxc_pins.o(.constdata) for gpio_cfg_i2s1a + mxc_sys.o(i.SYS_I2S_Shutdown) refers to mxc_sys.o(i.SYS_ClockDisable) for SYS_ClockDisable + mxc_sys.o(i.SYS_RTC_SqwavInit) refers to gpio.o(i.GPIO_Config) for GPIO_Config + mxc_sys.o(i.SYS_RTC_SqwavInit) refers to mxc_pins.o(.constdata) for gpio_cfg_rtc + mxc_sys.o(i.SYS_SPI17Y_Init) refers to mxc_sys.o(i.SYS_ClockEnable) for SYS_ClockEnable + mxc_sys.o(i.SYS_SPI17Y_Init) refers to gpio.o(i.GPIO_Config) for GPIO_Config + mxc_sys.o(i.SYS_SPI17Y_Init) refers to mxc_pins.o(.constdata) for gpio_cfg_spi17y + mxc_sys.o(i.SYS_SPI17Y_Shutdown) refers to mxc_sys.o(i.SYS_ClockDisable) for SYS_ClockDisable + mxc_sys.o(i.SYS_SPIMSS_Init) refers to mxc_sys.o(i.SYS_ClockEnable) for SYS_ClockEnable + mxc_sys.o(i.SYS_SPIMSS_Init) refers to gpio.o(i.GPIO_Config) for GPIO_Config + mxc_sys.o(i.SYS_SPIMSS_Init) refers to mxc_pins.o(.constdata) for gpio_cfg_spimss1a + mxc_sys.o(i.SYS_SPIMSS_Shutdown) refers to mxc_sys.o(i.SYS_ClockDisable) for SYS_ClockDisable + mxc_sys.o(i.SYS_SysTick_Config) refers to mxc_sys.o(i.NVIC_SetPriority) for NVIC_SetPriority + mxc_sys.o(i.SYS_SysTick_Config) refers to rtc.o(i.RTC_Init) for RTC_Init + mxc_sys.o(i.SYS_SysTick_Config) refers to rtc.o(i.RTC_EnableRTCE) for RTC_EnableRTCE + mxc_sys.o(i.SYS_SysTick_DelayUs) refers to mxc_sys.o(i.SYS_SysTick_GetFreq) for SYS_SysTick_GetFreq + mxc_sys.o(i.SYS_SysTick_DelayUs) refers to uldiv.o(.text) for __aeabi_uldivmod + mxc_sys.o(i.SYS_SysTick_DelayUs) refers to mxc_sys.o(i.SYS_SysTick_Delay) for SYS_SysTick_Delay + mxc_sys.o(i.SYS_SysTick_GetFreq) refers to system_max32660.o(.data) for SystemCoreClock + mxc_sys.o(i.SYS_TMR_GetFreq) refers to system_max32660.o(.data) for SystemCoreClock + mxc_sys.o(i.SYS_TMR_Init) refers to gpio.o(i.GPIO_Config) for GPIO_Config + mxc_sys.o(i.SYS_TMR_Init) refers to mxc_sys.o(i.SYS_ClockEnable) for SYS_ClockEnable + mxc_sys.o(i.SYS_TMR_Init) refers to mxc_pins.o(.constdata) for gpio_cfg_tmr0 + mxc_sys.o(i.SYS_UART_Init) refers to mxc_sys.o(i.SYS_ClockEnable) for SYS_ClockEnable + mxc_sys.o(i.SYS_UART_Init) refers to gpio.o(i.GPIO_Config) for GPIO_Config + mxc_sys.o(i.SYS_UART_Init) refers to mxc_pins.o(.constdata) for gpio_cfg_uart0a + mxc_sys.o(i.SYS_UART_Shutdown) refers to mxc_sys.o(i.SYS_ClockDisable) for SYS_ClockDisable + nvic_table.o(i.NVIC_SetRAM) refers to memcpya.o(.text) for __aeabi_memcpy4 + nvic_table.o(i.NVIC_SetRAM) refers to startup_max32660.o(RESET) for __isr_vector + nvic_table.o(i.NVIC_SetRAM) refers to nvic_table.o(.bss) for ramVectorTable + nvic_table.o(i.NVIC_SetVector) refers to nvic_table.o(i.NVIC_SetRAM) for NVIC_SetRAM + nvic_table.o(i.NVIC_SetVector) refers to nvic_table.o(.bss) for ramVectorTable + rtc.o(i.RTC_CheckBusy) refers to mxc_delay.o(i.mxc_delay_start) for mxc_delay_start + rtc.o(i.RTC_CheckBusy) refers to mxc_delay.o(i.mxc_delay_check) for mxc_delay_check + rtc.o(i.RTC_CheckBusy) refers to mxc_delay.o(i.mxc_delay_stop) for mxc_delay_stop + rtc.o(i.RTC_ClearFlags) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_DisableRTCE) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_DisableSubsecondInterrupt) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_DisableTimeofdayInterrupt) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_EnableRTCE) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_EnableSubsecondInterrupt) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_EnableTimeofdayInterrupt) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_GetTime) refers to rtc.o(i.RTC_GetSecond) for RTC_GetSecond + rtc.o(i.RTC_GetTime) refers to rtc.o(i.RTC_GetSubSecond) for RTC_GetSubSecond + rtc.o(i.RTC_Init) refers to mxc_sys.o(i.SYS_ClockEnable_X32K) for SYS_ClockEnable_X32K + rtc.o(i.RTC_Init) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_SetSubsecondAlarm) refers to rtc.o(i.RTC_DisableSubsecondInterrupt) for RTC_DisableSubsecondInterrupt + rtc.o(i.RTC_SetSubsecondAlarm) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_SetSubsecondAlarm) refers to rtc.o(i.RTC_EnableSubsecondInterrupt) for RTC_EnableSubsecondInterrupt + rtc.o(i.RTC_SetTimeofdayAlarm) refers to rtc.o(i.RTC_DisableTimeofdayInterrupt) for RTC_DisableTimeofdayInterrupt + rtc.o(i.RTC_SetTimeofdayAlarm) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_SetTimeofdayAlarm) refers to rtc.o(i.RTC_EnableTimeofdayInterrupt) for RTC_EnableTimeofdayInterrupt + rtc.o(i.RTC_SquareWave) refers to mxc_sys.o(i.SYS_RTC_SqwavInit) for SYS_RTC_SqwavInit + rtc.o(i.RTC_SquareWave) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + rtc.o(i.RTC_Trim) refers to rtc.o(i.RTC_CheckBusy) for RTC_CheckBusy + spi.o(i.SPI_AbortAsync) refers to spi17y.o(i.SPI17Y_AbortAsync) for SPI17Y_AbortAsync + spi.o(i.SPI_AbortAsync) refers to spimss.o(i.SPIMSS_AbortAsync) for SPIMSS_AbortAsync + spi.o(i.SPI_Clear_fifo) refers to spi17y.o(i.SPI17Y_Clear_fifo) for SPI17Y_Clear_fifo + spi.o(i.SPI_Disable) refers to spi17y.o(i.SPI17Y_Disable) for SPI17Y_Disable + spi.o(i.SPI_Enable) refers to spi17y.o(i.SPI17Y_Enable) for SPI17Y_Enable + spi.o(i.SPI_Handler) refers to spi17y.o(i.SPI17Y_Handler) for SPI17Y_Handler + spi.o(i.SPI_Handler) refers to spimss.o(i.SPIMSS_Handler) for SPIMSS_Handler + spi.o(i.SPI_Init) refers to spi17y.o(i.SPI17Y_Init) for SPI17Y_Init + spi.o(i.SPI_Init) refers to spimss.o(i.SPIMSS_Init) for SPIMSS_Init + spi.o(i.SPI_MasterTrans) refers to spi17y.o(i.SPI17Y_MasterTrans) for SPI17Y_MasterTrans + spi.o(i.SPI_MasterTrans) refers to spimss.o(i.SPIMSS_MasterTrans) for SPIMSS_MasterTrans + spi.o(i.SPI_MasterTransAsync) refers to spi17y.o(i.SPI17Y_MasterTransAsync) for SPI17Y_MasterTransAsync + spi.o(i.SPI_MasterTransAsync) refers to spimss.o(i.SPIMSS_MasterTransAsync) for SPIMSS_MasterTransAsync + spi.o(i.SPI_Shutdown) refers to spi17y.o(i.SPI17Y_Shutdown) for SPI17Y_Shutdown + spi.o(i.SPI_Shutdown) refers to spimss.o(i.SPIMSS_Shutdown) for SPIMSS_Shutdown + spi.o(i.SPI_SlaveTrans) refers to spi17y.o(i.SPI17Y_SlaveTrans) for SPI17Y_SlaveTrans + spi.o(i.SPI_SlaveTrans) refers to spimss.o(i.SPIMSS_SlaveTrans) for SPIMSS_SlaveTrans + spi.o(i.SPI_SlaveTransAsync) refers to spi17y.o(i.SPI17Y_SlaveTransAsync) for SPI17Y_SlaveTransAsync + spi.o(i.SPI_SlaveTransAsync) refers to spimss.o(i.SPIMSS_SlaveTransAsync) for SPIMSS_SlaveTransAsync + spi17y.o(i.SPI17Y_AbortAsync) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + spi17y.o(i.SPI17Y_AbortAsync) refers to spi17y.o(.bss) for states + spi17y.o(i.SPI17Y_Handler) refers to spi17y.o(i.SPI17Y_MasterTransHandler) for SPI17Y_MasterTransHandler + spi17y.o(i.SPI17Y_Handler) refers to spi17y.o(i.SPI17Y_SlaveTransHandler) for SPI17Y_SlaveTransHandler + spi17y.o(i.SPI17Y_Handler) refers to spi17y.o(.bss) for states + spi17y.o(i.SPI17Y_Init) refers to mxc_sys.o(i.SYS_SPI17Y_Init) for SYS_SPI17Y_Init + spi17y.o(i.SPI17Y_Init) refers to spi17y.o(.bss) for states + spi17y.o(i.SPI17Y_Init) refers to system_max32660.o(.data) for SystemCoreClock + spi17y.o(i.SPI17Y_MasterTrans) refers to spi17y.o(i.SPI17Y_TransSetup) for SPI17Y_TransSetup + spi17y.o(i.SPI17Y_MasterTrans) refers to spi17y.o(i.SPI17Y_MasterTransHandler) for SPI17Y_MasterTransHandler + spi17y.o(i.SPI17Y_MasterTransAsync) refers to spi17y.o(i.SPI17Y_TransSetup) for SPI17Y_TransSetup + spi17y.o(i.SPI17Y_MasterTransAsync) refers to spi17y.o(i.SPI17Y_MasterTransHandler) for SPI17Y_MasterTransHandler + spi17y.o(i.SPI17Y_MasterTransHandler) refers to spi17y.o(i.SPI17Y_TransHandler) for SPI17Y_TransHandler + spi17y.o(i.SPI17Y_MasterTransHandler) refers to spi17y.o(.bss) for states + spi17y.o(i.SPI17Y_Shutdown) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + spi17y.o(i.SPI17Y_Shutdown) refers to mxc_sys.o(i.SYS_SPI17Y_Shutdown) for SYS_SPI17Y_Shutdown + spi17y.o(i.SPI17Y_Shutdown) refers to spi17y.o(.bss) for states + spi17y.o(i.SPI17Y_SlaveTrans) refers to spi17y.o(i.SPI17Y_TransSetup) for SPI17Y_TransSetup + spi17y.o(i.SPI17Y_SlaveTrans) refers to spi17y.o(i.SPI17Y_SlaveTransHandler) for SPI17Y_SlaveTransHandler + spi17y.o(i.SPI17Y_SlaveTransAsync) refers to spi17y.o(i.SPI17Y_TransSetup) for SPI17Y_TransSetup + spi17y.o(i.SPI17Y_SlaveTransAsync) refers to spi17y.o(i.SPI17Y_SlaveTransHandler) for SPI17Y_SlaveTransHandler + spi17y.o(i.SPI17Y_SlaveTransHandler) refers to spi17y.o(i.SPI17Y_TransHandler) for SPI17Y_TransHandler + spi17y.o(i.SPI17Y_TransHandler) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + spi17y.o(i.SPI17Y_TransHandler) refers to spi17y.o(.bss) for states + spi17y.o(i.SPI17Y_TransSetup) refers to memseta.o(.text) for __aeabi_memclr + spi17y.o(i.SPI17Y_TransSetup) refers to spi17y.o(.bss) for states + spimss.o(i.SPIMSS_AbortAsync) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + spimss.o(i.SPIMSS_AbortAsync) refers to spimss.o(.data) for states + spimss.o(i.SPIMSS_Handler) refers to spimss.o(i.SPIMSS_MasterTransHandler) for SPIMSS_MasterTransHandler + spimss.o(i.SPIMSS_Handler) refers to spimss.o(i.SPIMSS_SlaveTransHandler) for SPIMSS_SlaveTransHandler + spimss.o(i.SPIMSS_Handler) refers to spimss.o(.data) for states + spimss.o(i.SPIMSS_Init) refers to mxc_sys.o(i.SYS_SPIMSS_Init) for SYS_SPIMSS_Init + spimss.o(i.SPIMSS_Init) refers to spimss.o(.data) for states + spimss.o(i.SPIMSS_Init) refers to system_max32660.o(.data) for SystemCoreClock + spimss.o(i.SPIMSS_MasterTrans) refers to spimss.o(i.SPIMSS_TransSetup) for SPIMSS_TransSetup + spimss.o(i.SPIMSS_MasterTrans) refers to spimss.o(i.SPIMSS_MasterTransHandler) for SPIMSS_MasterTransHandler + spimss.o(i.SPIMSS_MasterTransAsync) refers to spimss.o(i.SPIMSS_TransSetup) for SPIMSS_TransSetup + spimss.o(i.SPIMSS_MasterTransAsync) refers to spimss.o(i.SPIMSS_MasterTransHandler) for SPIMSS_MasterTransHandler + spimss.o(i.SPIMSS_MasterTransHandler) refers to spimss.o(i.SPIMSS_TransHandler) for SPIMSS_TransHandler + spimss.o(i.SPIMSS_Shutdown) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + spimss.o(i.SPIMSS_Shutdown) refers to mxc_sys.o(i.SYS_SPIMSS_Shutdown) for SYS_SPIMSS_Shutdown + spimss.o(i.SPIMSS_Shutdown) refers to spimss.o(.data) for states + spimss.o(i.SPIMSS_SlaveTrans) refers to spimss.o(i.SPIMSS_TransSetup) for SPIMSS_TransSetup + spimss.o(i.SPIMSS_SlaveTrans) refers to spimss.o(i.SPIMSS_SlaveTransHandler) for SPIMSS_SlaveTransHandler + spimss.o(i.SPIMSS_SlaveTransAsync) refers to spimss.o(i.SPIMSS_TransSetup) for SPIMSS_TransSetup + spimss.o(i.SPIMSS_SlaveTransAsync) refers to spimss.o(i.SPIMSS_SlaveTransHandler) for SPIMSS_SlaveTransHandler + spimss.o(i.SPIMSS_SlaveTransHandler) refers to spimss.o(i.SPIMSS_TransHandler) for SPIMSS_TransHandler + spimss.o(i.SPIMSS_TransHandler) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + spimss.o(i.SPIMSS_TransHandler) refers to spimss.o(.data) for states + spimss.o(i.SPIMSS_TransSetup) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + spimss.o(i.SPIMSS_TransSetup) refers to spimss.o(.data) for states + tmr.o(i.TMR_GetTicks) refers to mxc_sys.o(i.SYS_TMR_GetFreq) for SYS_TMR_GetFreq + tmr.o(i.TMR_GetTicks) refers to uldiv.o(.text) for __aeabi_uldivmod + tmr.o(i.TMR_GetTime) refers to mxc_sys.o(i.SYS_TMR_GetFreq) for SYS_TMR_GetFreq + tmr.o(i.TMR_GetTime) refers to uldiv.o(.text) for __aeabi_uldivmod + tmr.o(i.TMR_Init) refers to mxc_sys.o(i.SYS_TMR_Init) for SYS_TMR_Init + tmr.o(i.TMR_Shutdown) refers to mxc_sys.o(i.SYS_TMR_Shutdown) for SYS_TMR_Shutdown + tmr_utils.o(i.TMR_Delay) refers to tmr_utils.o(i.TMR_TO_Start) for TMR_TO_Start + tmr_utils.o(i.TMR_Delay) refers to tmr_utils.o(i.TMR_TO_Check) for TMR_TO_Check + tmr_utils.o(i.TMR_SW_Start) refers to tmr_utils.o(i.TMR_TO_Start) for TMR_TO_Start + tmr_utils.o(i.TMR_SW_Stop) refers to tmr_utils.o(i.TMR_TO_Elapsed) for TMR_TO_Elapsed + tmr_utils.o(i.TMR_SW_Stop) refers to tmr_utils.o(i.TMR_TO_Stop) for TMR_TO_Stop + tmr_utils.o(i.TMR_TO_Check) refers to tmr.o(i.TMR_IntStatus) for TMR_IntStatus + tmr_utils.o(i.TMR_TO_Clear) refers to tmr.o(i.TMR_IntClear) for TMR_IntClear + tmr_utils.o(i.TMR_TO_Clear) refers to tmr.o(i.TMR_SetCount) for TMR_SetCount + tmr_utils.o(i.TMR_TO_Elapsed) refers to tmr.o(i.TMR_GetCount) for TMR_GetCount + tmr_utils.o(i.TMR_TO_Elapsed) refers to tmr.o(i.TMR_GetTime) for TMR_GetTime + tmr_utils.o(i.TMR_TO_Remaining) refers to tmr.o(i.TMR_GetCompare) for TMR_GetCompare + tmr_utils.o(i.TMR_TO_Remaining) refers to tmr.o(i.TMR_GetCount) for TMR_GetCount + tmr_utils.o(i.TMR_TO_Remaining) refers to tmr.o(i.TMR_GetTime) for TMR_GetTime + tmr_utils.o(i.TMR_TO_Start) refers to uldiv.o(.text) for __aeabi_uldivmod + tmr_utils.o(i.TMR_TO_Start) refers to tmr.o(i.TMR_Init) for TMR_Init + tmr_utils.o(i.TMR_TO_Start) refers to tmr.o(i.TMR_Disable) for TMR_Disable + tmr_utils.o(i.TMR_TO_Start) refers to tmr.o(i.TMR_Config) for TMR_Config + tmr_utils.o(i.TMR_TO_Start) refers to tmr.o(i.TMR_IntClear) for TMR_IntClear + tmr_utils.o(i.TMR_TO_Start) refers to tmr.o(i.TMR_Enable) for TMR_Enable + tmr_utils.o(i.TMR_TO_Start) refers to system_max32660.o(.data) for SystemCoreClock + tmr_utils.o(i.TMR_TO_Stop) refers to tmr.o(i.TMR_Disable) for TMR_Disable + tmr_utils.o(i.TMR_TO_Stop) refers to tmr.o(i.TMR_SetCount) for TMR_SetCount + uart.o(i.UART_AbortAsync) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + uart.o(i.UART_AbortAsync) refers to uart.o(.data) for rx_states + uart.o(i.UART_Busy) refers to uart.o(.data) for tx_states + uart.o(i.UART_Handler) refers to uart.o(i.UART_ReadHandler) for UART_ReadHandler + uart.o(i.UART_Handler) refers to uart.o(i.UART_WriteHandler) for UART_WriteHandler + uart.o(i.UART_Handler) refers to uart.o(.data) for rx_states + uart.o(i.UART_Init) refers to mxc_sys.o(i.SYS_UART_Init) for SYS_UART_Init + uart.o(i.UART_Init) refers to uart.o(.data) for rx_states + uart.o(i.UART_Init) refers to system_max32660.o(.data) for SystemCoreClock + uart.o(i.UART_PrepForSleep) refers to uart.o(i.UART_Busy) for UART_Busy + uart.o(i.UART_Read) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + uart.o(i.UART_Read) refers to uart.o(i.uart_error_check) for uart_error_check + uart.o(i.UART_Read) refers to uart.o(i.uart_error_clear) for uart_error_clear + uart.o(i.UART_Read) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + uart.o(i.UART_Read) refers to uart.o(.data) for rx_states + uart.o(i.UART_ReadAsync) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + uart.o(i.UART_ReadAsync) refers to uart.o(i.UART_ReadHandler) for UART_ReadHandler + uart.o(i.UART_ReadAsync) refers to uart.o(.data) for rx_states + uart.o(i.UART_ReadHandler) refers to uart.o(i.UART_NumReadAvail) for UART_NumReadAvail + uart.o(i.UART_ReadHandler) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + uart.o(i.UART_ReadHandler) refers to uart.o(.data) for rx_states + uart.o(i.UART_Shutdown) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + uart.o(i.UART_Shutdown) refers to mxc_sys.o(i.SYS_UART_Shutdown) for SYS_UART_Shutdown + uart.o(i.UART_Shutdown) refers to uart.o(.data) for rx_states + uart.o(i.UART_Write) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + uart.o(i.UART_Write) refers to uart.o(i.uart_error_clear) for uart_error_clear + uart.o(i.UART_Write) refers to uart.o(i.UART_WriteByte) for UART_WriteByte + uart.o(i.UART_Write) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + uart.o(i.UART_Write) refers to uart.o(.data) for tx_states + uart.o(i.UART_WriteAsync) refers to mxc_lock.o(i.mxc_get_lock) for mxc_get_lock + uart.o(i.UART_WriteAsync) refers to uart.o(i.UART_WriteHandler) for UART_WriteHandler + uart.o(i.UART_WriteAsync) refers to uart.o(.data) for tx_states + uart.o(i.UART_WriteHandler) refers to uart.o(i.UART_NumWriteAvail) for UART_NumWriteAvail + uart.o(i.UART_WriteHandler) refers to mxc_lock.o(i.mxc_free_lock) for mxc_free_lock + uart.o(i.UART_WriteHandler) refers to uart.o(.data) for tx_states + uart.o(i.uart_error_clear) refers to uart.o(i.UART_ClearFlags) for UART_ClearFlags + wdt.o(i.WDT_Init) refers to mxc_sys.o(i.SYS_WDT_Init) for SYS_WDT_Init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000F) for __rt_final_cpp + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$00000011) for __rt_final_exit + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry12b.o(.ARM.Collect$$$$0000000E) for __rt_lib_shutdown_fini + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload + entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk + entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload + uldiv.o(.text) refers to llushr.o(.text) for __aeabi_llsr + uldiv.o(.text) refers to llshl.o(.text) for __aeabi_llsl + entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000 + entry2.o(.ARM.Collect$$$$00002712) refers to startup_max32660.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to startup_max32660.o(STACK) for __initial_sp + entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main + entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main + entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main + init.o(.text) refers to system_max32660.o(i.$Sub$$__main_after_scatterload) for __main_after_scatterload + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.rev16_text), (4 bytes). + Removing main.o(.revsh_text), (4 bytes). + Removing interrput_handler.o(.rev16_text), (4 bytes). + Removing interrput_handler.o(.revsh_text), (4 bytes). + Removing system_func.o(.rev16_text), (4 bytes). + Removing system_func.o(.revsh_text), (4 bytes). + Removing system_max32660.o(.rev16_text), (4 bytes). + Removing system_max32660.o(.revsh_text), (4 bytes). + Removing startup_max32660.o(HEAP), (4096 bytes). + Removing dma.o(.rev16_text), (4 bytes). + Removing dma.o(.revsh_text), (4 bytes). + Removing dma.o(i.DMA_AcquireChannel), (128 bytes). + Removing dma.o(i.DMA_ClearFlags), (64 bytes). + Removing dma.o(i.DMA_ConfigChannel), (216 bytes). + Removing dma.o(i.DMA_DisableInterrupt), (56 bytes). + Removing dma.o(i.DMA_EnableInterrupt), (56 bytes). + Removing dma.o(i.DMA_GetCHRegs), (44 bytes). + Removing dma.o(i.DMA_GetFlags), (56 bytes). + Removing dma.o(i.DMA_Handler), (48 bytes). + Removing dma.o(i.DMA_Init), (200 bytes). + Removing dma.o(i.DMA_ReleaseChannel), (116 bytes). + Removing dma.o(i.DMA_SetCallback), (48 bytes). + Removing dma.o(i.DMA_SetReload), (116 bytes). + Removing dma.o(i.DMA_SetSrcDstCnt), (76 bytes). + Removing dma.o(i.DMA_Shutdown), (152 bytes). + Removing dma.o(i.DMA_Start), (128 bytes). + Removing dma.o(i.DMA_Stop), (68 bytes). + Removing dma.o(.bss), (80 bytes). + Removing dma.o(.data), (8 bytes). + Removing flc.o(.rev16_text), (4 bytes). + Removing flc.o(.revsh_text), (4 bytes). + Removing flc.o(.flashprog), (1256 bytes). + Removing flc.o(i.FLC_ClearFlags), (32 bytes). + Removing flc.o(i.FLC_DisableInt), (44 bytes). + Removing flc.o(i.FLC_EnableInt), (44 bytes). + Removing flc.o(i.FLC_GetFlags), (16 bytes). + Removing flc.o(i.FLC_LockInfoBlock), (20 bytes). + Removing flc.o(i.FLC_UnlockInfoBlock), (36 bytes). + Removing gpio.o(.rev16_text), (4 bytes). + Removing gpio.o(.revsh_text), (4 bytes). + Removing gpio.o(i.GPIO_Config), (248 bytes). + Removing gpio.o(i.GPIO_Handler), (100 bytes). + Removing gpio.o(i.GPIO_InGet), (28 bytes). + Removing gpio.o(i.GPIO_Init), (48 bytes). + Removing gpio.o(i.GPIO_IntClr), (24 bytes). + Removing gpio.o(i.GPIO_IntConfig), (128 bytes). + Removing gpio.o(i.GPIO_IntDisable), (24 bytes). + Removing gpio.o(i.GPIO_IntEnable), (24 bytes). + Removing gpio.o(i.GPIO_IntStatus), (28 bytes). + Removing gpio.o(i.GPIO_OutClr), (24 bytes). + Removing gpio.o(i.GPIO_OutGet), (28 bytes). + Removing gpio.o(i.GPIO_OutPut), (32 bytes). + Removing gpio.o(i.GPIO_OutSet), (24 bytes). + Removing gpio.o(i.GPIO_OutToggle), (28 bytes). + Removing gpio.o(i.GPIO_RegisterCallback), (68 bytes). + Removing gpio.o(.bss), (112 bytes). + Removing i2c.o(.rev16_text), (4 bytes). + Removing i2c.o(.revsh_text), (4 bytes). + Removing i2c.o(i.I2C_AbortAsync), (80 bytes). + Removing i2c.o(i.I2C_ClearTimeout), (6 bytes). + Removing i2c.o(i.I2C_DrainRX), (10 bytes). + Removing i2c.o(i.I2C_DrainTX), (10 bytes). + Removing i2c.o(i.I2C_FreeCallback), (40 bytes). + Removing i2c.o(i.I2C_Handler), (40 bytes). + Removing i2c.o(i.I2C_Init), (384 bytes). + Removing i2c.o(i.I2C_MasterAsync), (172 bytes). + Removing i2c.o(i.I2C_MasterHandler), (540 bytes). + Removing i2c.o(i.I2C_MasterRead), (228 bytes). + Removing i2c.o(i.I2C_MasterWrite), (242 bytes). + Removing i2c.o(i.I2C_Recover), (24 bytes). + Removing i2c.o(i.I2C_SetTimeout), (48 bytes). + Removing i2c.o(i.I2C_Setspeed), (248 bytes). + Removing i2c.o(i.I2C_Shutdown), (120 bytes). + Removing i2c.o(i.I2C_Slave), (628 bytes). + Removing i2c.o(i.I2C_SlaveAsync), (120 bytes). + Removing i2c.o(i.I2C_SlaveHandler), (540 bytes). + Removing i2c.o(.bss), (16 bytes). + Removing i2s.o(.rev16_text), (4 bytes). + Removing i2s.o(.revsh_text), (4 bytes). + Removing i2s.o(i.I2S_DMA_ClearFlags), (16 bytes). + Removing i2s.o(i.I2S_DMA_SetAddrCnt), (28 bytes). + Removing i2s.o(i.I2S_DMA_SetReload), (28 bytes). + Removing i2s.o(i.I2S_Init), (392 bytes). + Removing i2s.o(i.I2S_Mute), (20 bytes). + Removing i2s.o(i.I2S_Pause), (20 bytes). + Removing i2s.o(i.I2S_Shutdown), (40 bytes). + Removing i2s.o(i.I2S_Start), (44 bytes). + Removing i2s.o(i.I2S_Stop), (44 bytes). + Removing i2s.o(i.I2S_Unmute), (20 bytes). + Removing i2s.o(i.I2S_Unpause), (20 bytes). + Removing i2s.o(.data), (4 bytes). + Removing icc.o(.rev16_text), (4 bytes). + Removing icc.o(.revsh_text), (4 bytes). + Removing icc.o(i.ICC_Disable), (24 bytes). + Removing icc.o(i.ICC_Flush), (12 bytes). + Removing icc.o(i.ICC_ID), (56 bytes). + Removing lp.o(.rev16_text), (4 bytes). + Removing lp.o(.revsh_text), (4 bytes). + Removing lp.o(i.LP_ClearWakeStatus), (32 bytes). + Removing lp.o(i.LP_DisableBandGap), (20 bytes). + Removing lp.o(i.LP_DisableBlockDetect), (20 bytes). + Removing lp.o(i.LP_DisableFastWk), (20 bytes). + Removing lp.o(i.LP_DisableGPIOWakeup), (48 bytes). + Removing lp.o(i.LP_DisableICacheLightSleep), (18 bytes). + Removing lp.o(i.LP_DisableLDO), (20 bytes). + Removing lp.o(i.LP_DisableRTCAlarmWakeup), (18 bytes). + Removing lp.o(i.LP_DisableRamRetReg), (20 bytes). + Removing lp.o(i.LP_DisableSRAM0), (20 bytes). + Removing lp.o(i.LP_DisableSRAM1), (20 bytes). + Removing lp.o(i.LP_DisableSRAM2), (20 bytes). + Removing lp.o(i.LP_DisableSRAM3), (20 bytes). + Removing lp.o(i.LP_DisableSRamRet0), (20 bytes). + Removing lp.o(i.LP_DisableSRamRet1), (20 bytes). + Removing lp.o(i.LP_DisableSRamRet2), (20 bytes). + Removing lp.o(i.LP_DisableSRamRet3), (20 bytes). + Removing lp.o(i.LP_DisableSysRAM0LightSleep), (18 bytes). + Removing lp.o(i.LP_DisableSysRAM1LightSleep), (18 bytes). + Removing lp.o(i.LP_DisableSysRAM2LightSleep), (18 bytes). + Removing lp.o(i.LP_DisableSysRAM3LightSleep), (18 bytes). + Removing lp.o(i.LP_DisableVCorePORSignal), (20 bytes). + Removing lp.o(i.LP_DisableVCoreSVM), (20 bytes). + Removing lp.o(i.LP_DisableVDDIOPorMonitor), (20 bytes). + Removing lp.o(i.LP_EnableBandGap), (20 bytes). + Removing lp.o(i.LP_EnableBlockDetect), (20 bytes). + Removing lp.o(i.LP_EnableFastWk), (20 bytes). + Removing lp.o(i.LP_EnableGPIOWakeup), (44 bytes). + Removing lp.o(i.LP_EnableICacheLightSleep), (18 bytes). + Removing lp.o(i.LP_EnableLDO), (20 bytes). + Removing lp.o(i.LP_EnableRTCAlarmWakeup), (18 bytes). + Removing lp.o(i.LP_EnableRamRetReg), (20 bytes). + Removing lp.o(i.LP_EnableSRAM0), (20 bytes). + Removing lp.o(i.LP_EnableSRAM1), (20 bytes). + Removing lp.o(i.LP_EnableSRAM2), (20 bytes). + Removing lp.o(i.LP_EnableSRAM3), (20 bytes). + Removing lp.o(i.LP_EnableSRamRet0), (20 bytes). + Removing lp.o(i.LP_EnableSRamRet1), (20 bytes). + Removing lp.o(i.LP_EnableSRamRet2), (20 bytes). + Removing lp.o(i.LP_EnableSRamRet3), (20 bytes). + Removing lp.o(i.LP_EnableSysRAM0LightSleep), (18 bytes). + Removing lp.o(i.LP_EnableSysRAM1LightSleep), (18 bytes). + Removing lp.o(i.LP_EnableSysRAM2LightSleep), (18 bytes). + Removing lp.o(i.LP_EnableSysRAM3LightSleep), (18 bytes). + Removing lp.o(i.LP_EnableVCorePORSignal), (20 bytes). + Removing lp.o(i.LP_EnableVCoreSVM), (20 bytes). + Removing lp.o(i.LP_EnableVDDIOPorMonitoF), (20 bytes). + Removing lp.o(i.LP_EnterBackupMode), (30 bytes). + Removing lp.o(i.LP_EnterDeepSleepMode), (32 bytes). + Removing lp.o(i.LP_EnterShutdownMode), (30 bytes). + Removing lp.o(i.LP_EnterSleepMode), (20 bytes). + Removing mxc_assert.o(.rev16_text), (4 bytes). + Removing mxc_assert.o(.revsh_text), (4 bytes). + Removing mxc_assert.o(i.mxc_assert), (4 bytes). + Removing mxc_delay.o(.rev16_text), (4 bytes). + Removing mxc_delay.o(.revsh_text), (4 bytes). + Removing mxc_delay.o(i.mxc_delay), (128 bytes). + Removing mxc_lock.o(.rev16_text), (4 bytes). + Removing mxc_lock.o(.revsh_text), (4 bytes). + Removing mxc_lock.o(i.mxc_free_lock), (10 bytes). + Removing mxc_lock.o(i.mxc_get_lock), (32 bytes). + Removing mxc_pins.o(.rev16_text), (4 bytes). + Removing mxc_pins.o(.revsh_text), (4 bytes). + Removing mxc_pins.o(.constdata), (192 bytes). + Removing mxc_sys.o(.rev16_text), (4 bytes). + Removing mxc_sys.o(.revsh_text), (4 bytes). + Removing mxc_sys.o(i.NVIC_SetPriority), (40 bytes). + Removing mxc_sys.o(i.SYS_ClockDisable_X32K), (20 bytes). + Removing mxc_sys.o(i.SYS_ClockEnable), (42 bytes). + Removing mxc_sys.o(i.SYS_ClockEnable_X32K), (22 bytes). + Removing mxc_sys.o(i.SYS_DMA_Init), (12 bytes). + Removing mxc_sys.o(i.SYS_DMA_Shutdown), (12 bytes). + Removing mxc_sys.o(i.SYS_FLC_Init), (6 bytes). + Removing mxc_sys.o(i.SYS_FLC_Shutdown), (4 bytes). + Removing mxc_sys.o(i.SYS_Flash_Operation), (56 bytes). + Removing mxc_sys.o(i.SYS_I2C_GetFreq), (16 bytes). + Removing mxc_sys.o(i.SYS_I2C_Init), (76 bytes). + Removing mxc_sys.o(i.SYS_I2C_Shutdown), (116 bytes). + Removing mxc_sys.o(i.SYS_I2S_GetFreq), (16 bytes). + Removing mxc_sys.o(i.SYS_I2S_Init), (56 bytes). + Removing mxc_sys.o(i.SYS_I2S_Shutdown), (12 bytes). + Removing mxc_sys.o(i.SYS_RTC_SqwavInit), (20 bytes). + Removing mxc_sys.o(i.SYS_Reset0), (20 bytes). + Removing mxc_sys.o(i.SYS_Reset1), (20 bytes). + Removing mxc_sys.o(i.SYS_SPI17Y_Init), (76 bytes). + Removing mxc_sys.o(i.SYS_SPI17Y_Shutdown), (24 bytes). + Removing mxc_sys.o(i.SYS_SPIMSS_Init), (72 bytes). + Removing mxc_sys.o(i.SYS_SPIMSS_Shutdown), (24 bytes). + Removing mxc_sys.o(i.SYS_SysTick_Config), (148 bytes). + Removing mxc_sys.o(i.SYS_SysTick_Delay), (248 bytes). + Removing mxc_sys.o(i.SYS_SysTick_DelayUs), (40 bytes). + Removing mxc_sys.o(i.SYS_SysTick_Disable), (10 bytes). + Removing mxc_sys.o(i.SYS_SysTick_GetFreq), (40 bytes). + Removing mxc_sys.o(i.SYS_TMR_GetFreq), (16 bytes). + Removing mxc_sys.o(i.SYS_TMR_Init), (92 bytes). + Removing mxc_sys.o(i.SYS_TMR_Shutdown), (6 bytes). + Removing mxc_sys.o(i.SYS_UART_Init), (156 bytes). + Removing mxc_sys.o(i.SYS_UART_Shutdown), (44 bytes). + Removing mxc_sys.o(i.SYS_WDT_Init), (6 bytes). + Removing nvic_table.o(.rev16_text), (4 bytes). + Removing nvic_table.o(.revsh_text), (4 bytes). + Removing nvic_table.o(i.NVIC_GetVector), (20 bytes). + Removing nvic_table.o(i.NVIC_SetRAM), (36 bytes). + Removing nvic_table.o(i.NVIC_SetVector), (64 bytes). + Removing nvic_table.o(.bss), (284 bytes). + Removing rtc.o(.rev16_text), (4 bytes). + Removing rtc.o(.revsh_text), (4 bytes). + Removing rtc.o(i.RTC_CheckBusy), (52 bytes). + Removing rtc.o(i.RTC_ClearFlags), (40 bytes). + Removing rtc.o(i.RTC_DisableRTCE), (68 bytes). + Removing rtc.o(i.RTC_DisableSubsecondInterrupt), (40 bytes). + Removing rtc.o(i.RTC_DisableTimeofdayInterrupt), (40 bytes). + Removing rtc.o(i.RTC_EnableRTCE), (68 bytes). + Removing rtc.o(i.RTC_EnableSubsecondInterrupt), (28 bytes). + Removing rtc.o(i.RTC_EnableTimeofdayInterrupt), (28 bytes). + Removing rtc.o(i.RTC_GetFlags), (16 bytes). + Removing rtc.o(i.RTC_GetSecond), (12 bytes). + Removing rtc.o(i.RTC_GetSubSecond), (12 bytes). + Removing rtc.o(i.RTC_GetTime), (88 bytes). + Removing rtc.o(i.RTC_Init), (126 bytes). + Removing rtc.o(i.RTC_IsEnabled), (16 bytes). + Removing rtc.o(i.RTC_SetSubsecondAlarm), (56 bytes). + Removing rtc.o(i.RTC_SetTimeofdayAlarm), (60 bytes). + Removing rtc.o(i.RTC_SquareWave), (218 bytes). + Removing rtc.o(i.RTC_Trim), (70 bytes). + Removing spi.o(.rev16_text), (4 bytes). + Removing spi.o(.revsh_text), (4 bytes). + Removing spi.o(i.SPI_AbortAsync), (48 bytes). + Removing spi.o(i.SPI_Clear_fifo), (44 bytes). + Removing spi.o(i.SPI_Disable), (44 bytes). + Removing spi.o(i.SPI_Enable), (44 bytes). + Removing spi.o(i.SPI_Handler), (48 bytes). + Removing spi.o(i.SPI_Init), (104 bytes). + Removing spi.o(i.SPI_MasterTrans), (60 bytes). + Removing spi.o(i.SPI_MasterTransAsync), (60 bytes). + Removing spi.o(i.SPI_Shutdown), (56 bytes). + Removing spi.o(i.SPI_SlaveTrans), (60 bytes). + Removing spi.o(i.SPI_SlaveTransAsync), (60 bytes). + Removing spi17y.o(.rev16_text), (4 bytes). + Removing spi17y.o(.revsh_text), (4 bytes). + Removing spi17y.o(i.SPI17Y_AbortAsync), (112 bytes). + Removing spi17y.o(i.SPI17Y_Clear_fifo), (10 bytes). + Removing spi17y.o(i.SPI17Y_Disable), (10 bytes). + Removing spi17y.o(i.SPI17Y_Enable), (10 bytes). + Removing spi17y.o(i.SPI17Y_Handler), (156 bytes). + Removing spi17y.o(i.SPI17Y_Init), (212 bytes). + Removing spi17y.o(i.SPI17Y_MasterTrans), (60 bytes). + Removing spi17y.o(i.SPI17Y_MasterTransAsync), (38 bytes). + Removing spi17y.o(i.SPI17Y_MasterTransHandler), (104 bytes). + Removing spi17y.o(i.SPI17Y_Shutdown), (128 bytes). + Removing spi17y.o(i.SPI17Y_SlaveTrans), (48 bytes). + Removing spi17y.o(i.SPI17Y_SlaveTransAsync), (38 bytes). + Removing spi17y.o(i.SPI17Y_SlaveTransHandler), (20 bytes). + Removing spi17y.o(i.SPI17Y_TransHandler), (556 bytes). + Removing spi17y.o(i.SPI17Y_TransSetup), (524 bytes). + Removing spi17y.o(.bss), (64 bytes). + Removing spimss.o(.rev16_text), (4 bytes). + Removing spimss.o(.revsh_text), (4 bytes). + Removing spimss.o(i.SPIMSS_AbortAsync), (100 bytes). + Removing spimss.o(i.SPIMSS_Handler), (108 bytes). + Removing spimss.o(i.SPIMSS_Init), (160 bytes). + Removing spimss.o(i.SPIMSS_MasterTrans), (78 bytes). + Removing spimss.o(i.SPIMSS_MasterTransAsync), (70 bytes). + Removing spimss.o(i.SPIMSS_MasterTransHandler), (30 bytes). + Removing spimss.o(i.SPIMSS_Shutdown), (108 bytes). + Removing spimss.o(i.SPIMSS_SlaveTrans), (70 bytes). + Removing spimss.o(i.SPIMSS_SlaveTransAsync), (62 bytes). + Removing spimss.o(i.SPIMSS_SlaveTransHandler), (16 bytes). + Removing spimss.o(i.SPIMSS_TransHandler), (452 bytes). + Removing spimss.o(i.SPIMSS_TransSetup), (184 bytes). + Removing spimss.o(.data), (4 bytes). + Removing tmr.o(.rev16_text), (4 bytes). + Removing tmr.o(.revsh_text), (4 bytes). + Removing tmr.o(i.TMR_Config), (42 bytes). + Removing tmr.o(i.TMR_Disable), (10 bytes). + Removing tmr.o(i.TMR_Enable), (10 bytes). + Removing tmr.o(i.TMR_GetCapture), (6 bytes). + Removing tmr.o(i.TMR_GetCompare), (6 bytes). + Removing tmr.o(i.TMR_GetCount), (6 bytes). + Removing tmr.o(i.TMR_GetTicks), (196 bytes). + Removing tmr.o(i.TMR_GetTime), (380 bytes). + Removing tmr.o(i.TMR_Init), (42 bytes). + Removing tmr.o(i.TMR_IntClear), (6 bytes). + Removing tmr.o(i.TMR_IntStatus), (6 bytes). + Removing tmr.o(i.TMR_PWMConfig), (54 bytes). + Removing tmr.o(i.TMR_PWMSetDuty), (50 bytes). + Removing tmr.o(i.TMR_PWMSetPeriod), (28 bytes). + Removing tmr.o(i.TMR_SetCompare), (4 bytes). + Removing tmr.o(i.TMR_SetCount), (4 bytes). + Removing tmr.o(i.TMR_Shutdown), (26 bytes). + Removing tmr_utils.o(.rev16_text), (4 bytes). + Removing tmr_utils.o(.revsh_text), (4 bytes). + Removing tmr_utils.o(i.TMR_Delay), (40 bytes). + Removing tmr_utils.o(i.TMR_SW_Start), (20 bytes). + Removing tmr_utils.o(i.TMR_SW_Stop), (22 bytes). + Removing tmr_utils.o(i.TMR_TO_Check), (22 bytes). + Removing tmr_utils.o(i.TMR_TO_Clear), (20 bytes). + Removing tmr_utils.o(i.TMR_TO_Elapsed), (84 bytes). + Removing tmr_utils.o(i.TMR_TO_Remaining), (92 bytes). + Removing tmr_utils.o(i.TMR_TO_Start), (132 bytes). + Removing tmr_utils.o(i.TMR_TO_Stop), (20 bytes). + Removing uart.o(.rev16_text), (4 bytes). + Removing uart.o(.revsh_text), (4 bytes). + Removing uart.o(i.UART_AbortAsync), (232 bytes). + Removing uart.o(i.UART_Busy), (88 bytes). + Removing uart.o(i.UART_ClearFlags), (4 bytes). + Removing uart.o(i.UART_Disable), (10 bytes). + Removing uart.o(i.UART_DrainRX), (10 bytes). + Removing uart.o(i.UART_DrainTX), (10 bytes). + Removing uart.o(i.UART_Enable), (10 bytes). + Removing uart.o(i.UART_GetFlags), (6 bytes). + Removing uart.o(i.UART_Handler), (104 bytes). + Removing uart.o(i.UART_Init), (220 bytes). + Removing uart.o(i.UART_NumReadAvail), (10 bytes). + Removing uart.o(i.UART_NumWriteAvail), (14 bytes). + Removing uart.o(i.UART_PrepForSleep), (30 bytes). + Removing uart.o(i.UART_Read), (212 bytes). + Removing uart.o(i.UART_ReadAsync), (164 bytes). + Removing uart.o(i.UART_ReadByte), (20 bytes). + Removing uart.o(i.UART_ReadHandler), (208 bytes). + Removing uart.o(i.UART_Shutdown), (184 bytes). + Removing uart.o(i.UART_Write), (148 bytes). + Removing uart.o(i.UART_WriteAsync), (144 bytes). + Removing uart.o(i.UART_WriteByte), (16 bytes). + Removing uart.o(i.UART_WriteHandler), (136 bytes). + Removing uart.o(i.uart_error_check), (10 bytes). + Removing uart.o(i.uart_error_clear), (14 bytes). + Removing uart.o(.data), (16 bytes). + Removing wdt.o(.rev16_text), (4 bytes). + Removing wdt.o(.revsh_text), (4 bytes). + Removing wdt.o(i.WDT_ClearIntFlag), (10 bytes). + Removing wdt.o(i.WDT_ClearResetFlag), (10 bytes). + Removing wdt.o(i.WDT_Enable), (22 bytes). + Removing wdt.o(i.WDT_EnableInt), (22 bytes). + Removing wdt.o(i.WDT_EnableReset), (22 bytes). + Removing wdt.o(i.WDT_GetIntFlag), (10 bytes). + Removing wdt.o(i.WDT_GetResetFlag), (8 bytes). + Removing wdt.o(i.WDT_Init), (18 bytes). + Removing wdt.o(i.WDT_ResetTimer), (10 bytes). + Removing wdt.o(i.WDT_SetIntPeriod), (10 bytes). + Removing wdt.o(i.WDT_SetResetPeriod), (10 bytes). + +339 unused section(s) (total 24764 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + RESET 0x00000000 Section 284 startup_max32660.o(RESET) + ../clib/microlib/division.c 0x00000000 Number 0 uldiv.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry12b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE + ../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llshl.o ABSOLUTE + ../clib/microlib/longlong.c 0x00000000 Number 0 llushr.o ABSOLUTE + ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpyb.o ABSOLUTE + ../clib/microlib/string/memcpy.c 0x00000000 Number 0 memcpya.o ABSOLUTE + ../clib/microlib/string/memset.c 0x00000000 Number 0 memseta.o ABSOLUTE + ..\Application\interrput_handler.c 0x00000000 Number 0 interrput_handler.o ABSOLUTE + ..\Application\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\Application\system_func.c 0x00000000 Number 0 system_func.o ABSOLUTE + ..\SDK\Device\system_max32660.c 0x00000000 Number 0 system_max32660.o ABSOLUTE + ..\SDK\Driver\Source\dma.c 0x00000000 Number 0 dma.o ABSOLUTE + ..\SDK\Driver\Source\flc.c 0x00000000 Number 0 flc.o ABSOLUTE + ..\SDK\Driver\Source\gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + ..\SDK\Driver\Source\i2c.c 0x00000000 Number 0 i2c.o ABSOLUTE + ..\SDK\Driver\Source\i2s.c 0x00000000 Number 0 i2s.o ABSOLUTE + ..\SDK\Driver\Source\icc.c 0x00000000 Number 0 icc.o ABSOLUTE + ..\SDK\Driver\Source\lp.c 0x00000000 Number 0 lp.o ABSOLUTE + ..\SDK\Driver\Source\mxc_assert.c 0x00000000 Number 0 mxc_assert.o ABSOLUTE + ..\SDK\Driver\Source\mxc_delay.c 0x00000000 Number 0 mxc_delay.o ABSOLUTE + ..\SDK\Driver\Source\mxc_lock.c 0x00000000 Number 0 mxc_lock.o ABSOLUTE + ..\SDK\Driver\Source\mxc_pins.c 0x00000000 Number 0 mxc_pins.o ABSOLUTE + ..\SDK\Driver\Source\mxc_sys.c 0x00000000 Number 0 mxc_sys.o ABSOLUTE + ..\SDK\Driver\Source\nvic_table.c 0x00000000 Number 0 nvic_table.o ABSOLUTE + ..\SDK\Driver\Source\rtc.c 0x00000000 Number 0 rtc.o ABSOLUTE + ..\SDK\Driver\Source\spi.c 0x00000000 Number 0 spi.o ABSOLUTE + ..\SDK\Driver\Source\spi17y.c 0x00000000 Number 0 spi17y.o ABSOLUTE + ..\SDK\Driver\Source\spimss.c 0x00000000 Number 0 spimss.o ABSOLUTE + ..\SDK\Driver\Source\tmr.c 0x00000000 Number 0 tmr.o ABSOLUTE + ..\SDK\Driver\Source\tmr_utils.c 0x00000000 Number 0 tmr_utils.o ABSOLUTE + ..\SDK\Driver\Source\uart.c 0x00000000 Number 0 uart.o ABSOLUTE + ..\SDK\Driver\Source\wdt.c 0x00000000 Number 0 wdt.o ABSOLUTE + ..\SDK\Startup\startup_max32660.s 0x00000000 Number 0 startup_max32660.o ABSOLUTE + ..\\Application\\interrput_handler.c 0x00000000 Number 0 interrput_handler.o ABSOLUTE + ..\\Application\\main.c 0x00000000 Number 0 main.o ABSOLUTE + ..\\Application\\system_func.c 0x00000000 Number 0 system_func.o ABSOLUTE + ..\\SDK\\Device\\system_max32660.c 0x00000000 Number 0 system_max32660.o ABSOLUTE + ..\\SDK\\Driver\\Source\\dma.c 0x00000000 Number 0 dma.o ABSOLUTE + ..\\SDK\\Driver\\Source\\flc.c 0x00000000 Number 0 flc.o ABSOLUTE + ..\\SDK\\Driver\\Source\\gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + ..\\SDK\\Driver\\Source\\i2c.c 0x00000000 Number 0 i2c.o ABSOLUTE + ..\\SDK\\Driver\\Source\\i2s.c 0x00000000 Number 0 i2s.o ABSOLUTE + ..\\SDK\\Driver\\Source\\icc.c 0x00000000 Number 0 icc.o ABSOLUTE + ..\\SDK\\Driver\\Source\\lp.c 0x00000000 Number 0 lp.o ABSOLUTE + ..\\SDK\\Driver\\Source\\mxc_assert.c 0x00000000 Number 0 mxc_assert.o ABSOLUTE + ..\\SDK\\Driver\\Source\\mxc_delay.c 0x00000000 Number 0 mxc_delay.o ABSOLUTE + ..\\SDK\\Driver\\Source\\mxc_lock.c 0x00000000 Number 0 mxc_lock.o ABSOLUTE + ..\\SDK\\Driver\\Source\\mxc_pins.c 0x00000000 Number 0 mxc_pins.o ABSOLUTE + ..\\SDK\\Driver\\Source\\mxc_sys.c 0x00000000 Number 0 mxc_sys.o ABSOLUTE + ..\\SDK\\Driver\\Source\\nvic_table.c 0x00000000 Number 0 nvic_table.o ABSOLUTE + ..\\SDK\\Driver\\Source\\rtc.c 0x00000000 Number 0 rtc.o ABSOLUTE + ..\\SDK\\Driver\\Source\\spi.c 0x00000000 Number 0 spi.o ABSOLUTE + ..\\SDK\\Driver\\Source\\spi17y.c 0x00000000 Number 0 spi17y.o ABSOLUTE + ..\\SDK\\Driver\\Source\\spimss.c 0x00000000 Number 0 spimss.o ABSOLUTE + ..\\SDK\\Driver\\Source\\tmr.c 0x00000000 Number 0 tmr.o ABSOLUTE + ..\\SDK\\Driver\\Source\\tmr_utils.c 0x00000000 Number 0 tmr_utils.o ABSOLUTE + ..\\SDK\\Driver\\Source\\uart.c 0x00000000 Number 0 uart.o ABSOLUTE + ..\\SDK\\Driver\\Source\\wdt.c 0x00000000 Number 0 wdt.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE + init.s 0x00000000 Number 0 init.o ABSOLUTE + .ARM.Collect$$$$00000000 0x0000011c Section 0 entry.o(.ARM.Collect$$$$00000000) + .ARM.Collect$$$$00000001 0x0000011c Section 4 entry2.o(.ARM.Collect$$$$00000001) + .ARM.Collect$$$$00000004 0x00000120 Section 4 entry5.o(.ARM.Collect$$$$00000004) + .ARM.Collect$$$$00000008 0x00000124 Section 0 entry7b.o(.ARM.Collect$$$$00000008) + .ARM.Collect$$$$0000000A 0x00000124 Section 0 entry8b.o(.ARM.Collect$$$$0000000A) + .ARM.Collect$$$$0000000B 0x00000124 Section 8 entry9a.o(.ARM.Collect$$$$0000000B) + .ARM.Collect$$$$0000000E 0x0000012c Section 4 entry12b.o(.ARM.Collect$$$$0000000E) + .ARM.Collect$$$$0000000F 0x00000130 Section 0 entry10a.o(.ARM.Collect$$$$0000000F) + .ARM.Collect$$$$00000011 0x00000130 Section 0 entry11a.o(.ARM.Collect$$$$00000011) + .ARM.Collect$$$$00002712 0x00000130 Section 4 entry2.o(.ARM.Collect$$$$00002712) + __lit__00000000 0x00000130 Data 4 entry2.o(.ARM.Collect$$$$00002712) + .text 0x00000134 Section 40 startup_max32660.o(.text) + $v0 0x00000134 Number 0 startup_max32660.o(.text) + .text 0x0000015c Section 0 uldiv.o(.text) + .text 0x000001c0 Section 36 init.o(.text) + .text 0x000001e4 Section 0 llshl.o(.text) + .text 0x00000202 Section 0 llushr.o(.text) + i.$Sub$$__main_after_scatterload 0x00000222 Section 0 system_max32660.o(i.$Sub$$__main_after_scatterload) + i.Board_Init 0x0000022e Section 0 system_max32660.o(i.Board_Init) + i.ICC_Enable 0x00000234 Section 0 icc.o(i.ICC_Enable) + i.ICC_Ready 0x00000264 Section 0 icc.o(i.ICC_Ready) + ICC_Ready 0x00000265 Thumb Code 10 icc.o(i.ICC_Ready) + i.LP_SetOperatingVoltage 0x00000274 Section 0 lp.o(i.LP_SetOperatingVoltage) + i.PreInit 0x00000364 Section 0 system_max32660.o(i.PreInit) + i.SYS_ClockDisable 0x00000368 Section 0 mxc_sys.o(i.SYS_ClockDisable) + i.SYS_Clock_Select 0x00000394 Section 0 mxc_sys.o(i.SYS_Clock_Select) + i.SYS_Clock_Timeout 0x000005c8 Section 0 mxc_sys.o(i.SYS_Clock_Timeout) + SYS_Clock_Timeout 0x000005c9 Thumb Code 46 mxc_sys.o(i.SYS_Clock_Timeout) + i.SysTick_Handler 0x000005f6 Section 0 mxc_delay.o(i.SysTick_Handler) + i.SystemCoreClockSet 0x00000600 Section 0 system_func.o(i.SystemCoreClockSet) + i.SystemCoreClockUpdate 0x00000650 Section 0 system_max32660.o(i.SystemCoreClockUpdate) + i.SystemInit 0x000006b4 Section 0 system_max32660.o(i.SystemInit) + i.__scatterload_copy 0x00000748 Section 14 handlers.o(i.__scatterload_copy) + i.__scatterload_null 0x00000756 Section 2 handlers.o(i.__scatterload_null) + i.__scatterload_zeroinit 0x00000758 Section 14 handlers.o(i.__scatterload_zeroinit) + i.main 0x00000766 Section 0 main.o(i.main) + i.mxc_delay_check 0x00000778 Section 0 mxc_delay.o(i.mxc_delay_check) + i.mxc_delay_handler 0x000007cc Section 0 mxc_delay.o(i.mxc_delay_handler) + i.mxc_delay_init 0x00000824 Section 0 mxc_delay.o(i.mxc_delay_init) + mxc_delay_init 0x00000825 Thumb Code 154 mxc_delay.o(i.mxc_delay_init) + i.mxc_delay_start 0x000008d8 Section 0 mxc_delay.o(i.mxc_delay_start) + i.mxc_delay_stop 0x00000924 Section 0 mxc_delay.o(i.mxc_delay_stop) + .data 0x20000000 Section 1 system_func.o(.data) + usTickCountDiv 0x20000000 Data 1 system_func.o(.data) + .data 0x20000004 Section 4 system_max32660.o(.data) + .data 0x20000008 Section 28 mxc_delay.o(.data) + ctrl_save 0x20000008 Data 4 mxc_delay.o(.data) + compare_value 0x20000010 Data 8 mxc_delay.o(.data) + curr_value 0x20000018 Data 8 mxc_delay.o(.data) + reload 0x20000020 Data 4 mxc_delay.o(.data) + STACK 0x20000028 Section 8192 startup_max32660.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$E$P$D$K$B$S$7EM$VFPi3$EXTD16$VFPS$VFMA$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + __Vectors 0x00000000 Data 0 startup_max32660.o(RESET) + __isr_vector 0x00000000 Data 4 startup_max32660.o(RESET) + __arm_fini_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __decompress - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _microlib_exit - Undefined Weak Reference + __Vectors_End 0x0000011c Data 0 startup_max32660.o(RESET) + __Vectors_Size 0x0000011c Number 0 startup_max32660.o ABSOLUTE + __main 0x0000011d Thumb Code 0 entry.o(.ARM.Collect$$$$00000000) + _main_stk 0x0000011d Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001) + _main_scatterload 0x00000121 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + $Super$$__main_after_scatterload 0x00000125 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004) + _main_clock 0x00000125 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008) + _main_cpp_init 0x00000125 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A) + _main_init 0x00000125 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B) + __rt_lib_shutdown_fini 0x0000012d Thumb Code 0 entry12b.o(.ARM.Collect$$$$0000000E) + __rt_final_cpp 0x00000131 Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000F) + __rt_final_exit 0x00000131 Thumb Code 0 entry11a.o(.ARM.Collect$$$$00000011) + Reset_Handler 0x00000135 Thumb Code 14 startup_max32660.o(.text) + NMI_Handler 0x00000143 Thumb Code 2 startup_max32660.o(.text) + HardFault_Handler 0x00000145 Thumb Code 2 startup_max32660.o(.text) + MemManage_Handler 0x00000147 Thumb Code 2 startup_max32660.o(.text) + BusFault_Handler 0x00000149 Thumb Code 2 startup_max32660.o(.text) + UsageFault_Handler 0x0000014b Thumb Code 2 startup_max32660.o(.text) + SVC_Handler 0x0000014d Thumb Code 2 startup_max32660.o(.text) + DebugMon_Handler 0x0000014f Thumb Code 2 startup_max32660.o(.text) + PendSV_Handler 0x00000151 Thumb Code 2 startup_max32660.o(.text) + DMA0_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + DMA1_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + DMA2_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + DMA3_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + FLC_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + GPIO0_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + GPIOWAKE_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + I2C0_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + I2C1_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + PF_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV00_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV01_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV02_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV03_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV04_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV05_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV06_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV07_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV08_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV09_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV10_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV11_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV12_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV13_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV14_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV15_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV16_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV17_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV18_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV19_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV20_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV21_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV22_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV23_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV24_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV25_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV26_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV27_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV28_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV29_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV30_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV31_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV32_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV33_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV34_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RSV35_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + RTC_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + SPI0_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + SPI1_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + TMR0_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + TMR1_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + TMR2_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + UART0_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + UART1_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + WDT0_IRQHandler 0x00000153 Thumb Code 0 startup_max32660.o(.text) + __aeabi_uldivmod 0x0000015d Thumb Code 98 uldiv.o(.text) + __scatterload 0x000001c1 Thumb Code 28 init.o(.text) + __scatterload_rt2 0x000001c1 Thumb Code 0 init.o(.text) + __aeabi_llsl 0x000001e5 Thumb Code 30 llshl.o(.text) + _ll_shift_l 0x000001e5 Thumb Code 0 llshl.o(.text) + __aeabi_llsr 0x00000203 Thumb Code 32 llushr.o(.text) + _ll_ushift_r 0x00000203 Thumb Code 0 llushr.o(.text) + __main_after_scatterload 0x00000223 Thumb Code 12 system_max32660.o(i.$Sub$$__main_after_scatterload) + Board_Init 0x0000022f Thumb Code 4 system_max32660.o(i.Board_Init) + ICC_Enable 0x00000235 Thumb Code 34 icc.o(i.ICC_Enable) + LP_SetOperatingVoltage 0x00000275 Thumb Code 232 lp.o(i.LP_SetOperatingVoltage) + PreInit 0x00000365 Thumb Code 4 system_max32660.o(i.PreInit) + SYS_ClockDisable 0x00000369 Thumb Code 42 mxc_sys.o(i.SYS_ClockDisable) + SYS_Clock_Select 0x00000395 Thumb Code 556 mxc_sys.o(i.SYS_Clock_Select) + SysTick_Handler 0x000005f7 Thumb Code 8 mxc_delay.o(i.SysTick_Handler) + SystemCoreClockSet 0x00000601 Thumb Code 76 system_func.o(i.SystemCoreClockSet) + SystemCoreClockUpdate 0x00000651 Thumb Code 80 system_max32660.o(i.SystemCoreClockUpdate) + SystemInit 0x000006b5 Thumb Code 132 system_max32660.o(i.SystemInit) + __scatterload_copy 0x00000749 Thumb Code 14 handlers.o(i.__scatterload_copy) + __scatterload_null 0x00000757 Thumb Code 2 handlers.o(i.__scatterload_null) + __scatterload_zeroinit 0x00000759 Thumb Code 14 handlers.o(i.__scatterload_zeroinit) + main 0x00000767 Thumb Code 16 main.o(i.main) + mxc_delay_check 0x00000779 Thumb Code 72 mxc_delay.o(i.mxc_delay_check) + mxc_delay_handler 0x000007cd Thumb Code 76 mxc_delay.o(i.mxc_delay_handler) + mxc_delay_start 0x000008d9 Thumb Code 72 mxc_delay.o(i.mxc_delay_start) + mxc_delay_stop 0x00000925 Thumb Code 20 mxc_delay.o(i.mxc_delay_stop) + Region$$Table$$Base 0x00000940 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x00000960 Number 0 anon$$obj.o(Region$$Table) + SystemCoreClock 0x20000004 Data 4 system_max32660.o(.data) + __initial_sp 0x20002028 Data 0 startup_max32660.o(STACK) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x0000011d + + Load Region LR_IROM1 (Base: 0x00000000, Size: 0x00000984, Max: 0x00040000, ABSOLUTE) + + Execution Region ER_IROM1 (Exec base: 0x00000000, Load base: 0x00000000, Size: 0x00000960, Max: 0x00040000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x00000000 0x00000000 0x0000011c Data RO 280 RESET startup_max32660.o + 0x0000011c 0x0000011c 0x00000000 Code RO 2395 * .ARM.Collect$$$$00000000 mc_w.l(entry.o) + 0x0000011c 0x0000011c 0x00000004 Code RO 2407 .ARM.Collect$$$$00000001 mc_w.l(entry2.o) + 0x00000120 0x00000120 0x00000004 Code RO 2396 .ARM.Collect$$$$00000004 mc_w.l(entry5.o) + 0x00000124 0x00000124 0x00000000 Code RO 2411 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o) + 0x00000124 0x00000124 0x00000000 Code RO 2413 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o) + 0x00000124 0x00000124 0x00000008 Code RO 2414 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o) + 0x0000012c 0x0000012c 0x00000004 Code RO 2421 .ARM.Collect$$$$0000000E mc_w.l(entry12b.o) + 0x00000130 0x00000130 0x00000000 Code RO 2416 .ARM.Collect$$$$0000000F mc_w.l(entry10a.o) + 0x00000130 0x00000130 0x00000000 Code RO 2418 .ARM.Collect$$$$00000011 mc_w.l(entry11a.o) + 0x00000130 0x00000130 0x00000004 Code RO 2408 .ARM.Collect$$$$00002712 mc_w.l(entry2.o) + 0x00000134 0x00000134 0x00000028 Code RO 281 .text startup_max32660.o + 0x0000015c 0x0000015c 0x00000062 Code RO 2399 .text mc_w.l(uldiv.o) + 0x000001be 0x000001be 0x00000002 PAD + 0x000001c0 0x000001c0 0x00000024 Code RO 2422 .text mc_w.l(init.o) + 0x000001e4 0x000001e4 0x0000001e Code RO 2424 .text mc_w.l(llshl.o) + 0x00000202 0x00000202 0x00000020 Code RO 2426 .text mc_w.l(llushr.o) + 0x00000222 0x00000222 0x0000000c Code RO 213 i.$Sub$$__main_after_scatterload system_max32660.o + 0x0000022e 0x0000022e 0x00000004 Code RO 214 i.Board_Init system_max32660.o + 0x00000232 0x00000232 0x00000002 PAD + 0x00000234 0x00000234 0x00000030 Code RO 781 i.ICC_Enable icc.o + 0x00000264 0x00000264 0x00000010 Code RO 784 i.ICC_Ready icc.o + 0x00000274 0x00000274 0x000000f0 Code RO 878 i.LP_SetOperatingVoltage lp.o + 0x00000364 0x00000364 0x00000004 Code RO 215 i.PreInit system_max32660.o + 0x00000368 0x00000368 0x0000002a Code RO 1284 i.SYS_ClockDisable mxc_sys.o + 0x00000392 0x00000392 0x00000002 PAD + 0x00000394 0x00000394 0x00000234 Code RO 1288 i.SYS_Clock_Select mxc_sys.o + 0x000005c8 0x000005c8 0x0000002e Code RO 1289 i.SYS_Clock_Timeout mxc_sys.o + 0x000005f6 0x000005f6 0x00000008 Code RO 1179 i.SysTick_Handler mxc_delay.o + 0x000005fe 0x000005fe 0x00000002 PAD + 0x00000600 0x00000600 0x00000050 Code RO 187 i.SystemCoreClockSet system_func.o + 0x00000650 0x00000650 0x00000064 Code RO 216 i.SystemCoreClockUpdate system_max32660.o + 0x000006b4 0x000006b4 0x00000094 Code RO 217 i.SystemInit system_max32660.o + 0x00000748 0x00000748 0x0000000e Code RO 2430 i.__scatterload_copy mc_w.l(handlers.o) + 0x00000756 0x00000756 0x00000002 Code RO 2431 i.__scatterload_null mc_w.l(handlers.o) + 0x00000758 0x00000758 0x0000000e Code RO 2432 i.__scatterload_zeroinit mc_w.l(handlers.o) + 0x00000766 0x00000766 0x00000010 Code RO 3 i.main main.o + 0x00000776 0x00000776 0x00000002 PAD + 0x00000778 0x00000778 0x00000054 Code RO 1181 i.mxc_delay_check mxc_delay.o + 0x000007cc 0x000007cc 0x00000058 Code RO 1182 i.mxc_delay_handler mxc_delay.o + 0x00000824 0x00000824 0x000000b4 Code RO 1183 i.mxc_delay_init mxc_delay.o + 0x000008d8 0x000008d8 0x0000004c Code RO 1184 i.mxc_delay_start mxc_delay.o + 0x00000924 0x00000924 0x0000001c Code RO 1185 i.mxc_delay_stop mxc_delay.o + 0x00000940 0x00000940 0x00000020 Data RO 2428 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x00000960, Size: 0x00002028, Max: 0x00018000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x00000960 0x00000001 Data RW 188 .data system_func.o + 0x20000001 0x00000961 0x00000003 PAD + 0x20000004 0x00000964 0x00000004 Data RW 218 .data system_max32660.o + 0x20000008 0x00000968 0x0000001c Data RW 1186 .data mxc_delay.o + 0x20000024 0x00000984 0x00000004 PAD + 0x20000028 - 0x00002000 Zero RW 278 STACK startup_max32660.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 64 20 0 0 0 961 icc.o + 240 8 0 0 0 689 lp.o + 16 0 0 0 0 115095 main.o + 464 62 0 28 0 4263 mxc_delay.o + 652 8 0 0 0 6998 mxc_sys.o + 40 8 284 0 8192 812 startup_max32660.o + 80 4 0 1 0 1241 system_func.o + 268 36 0 4 0 2987 system_max32660.o + + ---------------------------------------------------------------------- + 1832 146 316 36 8196 133046 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 8 0 0 3 4 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 0 0 0 0 0 0 entry.o + 0 0 0 0 0 0 entry10a.o + 0 0 0 0 0 0 entry11a.o + 4 0 0 0 0 0 entry12b.o + 8 4 0 0 0 0 entry2.o + 4 0 0 0 0 0 entry5.o + 0 0 0 0 0 0 entry7b.o + 0 0 0 0 0 0 entry8b.o + 8 4 0 0 0 0 entry9a.o + 30 0 0 0 0 0 handlers.o + 36 8 0 0 0 68 init.o + 30 0 0 0 0 68 llshl.o + 32 0 0 0 0 68 llushr.o + 98 0 0 0 0 92 uldiv.o + + ---------------------------------------------------------------------- + 252 16 0 0 0 296 Library Totals + 2 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 250 16 0 0 0 296 mc_w.l + + ---------------------------------------------------------------------- + 252 16 0 0 0 296 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 2084 162 316 36 8196 131894 Grand Totals + 2084 162 316 36 8196 131894 ELF Image Totals + 2084 162 316 36 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 2400 ( 2.34kB) + Total RW Size (RW Data + ZI Data) 8232 ( 8.04kB) + Total ROM Size (Code + RO Data + RW Data) 2436 ( 2.38kB) + +============================================================================== + diff --git a/Project/Compiler/Listings/startup_max32660.lst b/Project/Compiler/Listings/startup_max32660.lst new file mode 100644 index 0000000..0db8572 --- /dev/null +++ b/Project/Compiler/Listings/startup_max32660.lst @@ -0,0 +1,1638 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ;;;;;;;;;;;;;;;;;;;;;;;; + 2 00000000 ; Copyright (C) 2016 Maxim Integrated Products, Inc., Al + l Rights Reserved. + 3 00000000 ; + 4 00000000 ; Permission is hereby granted, free of charge, to any p + erson obtaining a + 5 00000000 ; copy of this software and associated documentation fil + es (the "Software"), + 6 00000000 ; to deal in the Software without restriction, including + without limitation + 7 00000000 ; the rights to use, copy, modify, merge, publish, distr + ibute, sublicense, + 8 00000000 ; and/or sell copies of the Software, and to permit pers + ons to whom the + 9 00000000 ; Software is furnished to do so, subject to the followi + ng conditions: + 10 00000000 ; + 11 00000000 ; The above copyright notice and this permission notice + shall be included + 12 00000000 ; in all copies or substantial portions of the Software. + + 13 00000000 ; + 14 00000000 ; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF + ANY KIND, EXPRESS + 15 00000000 ; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIE + S OF + 16 00000000 ; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + NONINFRINGEMENT. + 17 00000000 ; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY C + LAIM, DAMAGES + 18 00000000 ; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, + 19 00000000 ; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWAR + E OR THE USE OR + 20 00000000 ; OTHER DEALINGS IN THE SOFTWARE. + 21 00000000 ; + 22 00000000 ; Except as contained in this notice, the name of Maxim + Integrated + 23 00000000 ; Products, Inc. shall not be used except as stated in t + he Maxim Integrated + 24 00000000 ; Products, Inc. Branding Policy. + 25 00000000 ; + 26 00000000 ; The mere transfer of this software does not imply any + licenses + 27 00000000 ; of trade secrets, proprietary technology, copyrights, + patents, + 28 00000000 ; trademarks, maskwork rights, or any other form of inte + llectual + 29 00000000 ; property whatsoever. Maxim Integrated Products, Inc. r + etains all + 30 00000000 ; ownership rights. + 31 00000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ;;;;;;;;;;;;;;;;;;;;;;; + 32 00000000 + 33 00000000 ; To map FreeRTOS function names to their CMSIS equivale + nts add following lines to FreeRTOSConfig.h + 34 00000000 ; #define vPortSVCHandler SVC_Handler + 35 00000000 ; #define xPortPendSVHandler PendSV_Handler + + + +ARM Macro Assembler Page 2 + + + 36 00000000 ; #define xPortSysTickHandler SysTick_Handler + 37 00000000 ; *------- <<< Use Configuration Wizard in Context Menu + to Modify Stack Size and Heap Size. >>> ---- + 38 00000000 + 39 00000000 ; Stack Configuration + 40 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 41 00000000 ; + 42 00000000 + 43 00000000 00002000 + Stack_Size + EQU 0x00002000 + 44 00000000 + 45 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 46 00000000 Stack_Mem + SPACE Stack_Size + 47 00002000 __initial_sp ; Name used with Ke + il Configuration Wi + zard and Keil Micro + Lib + 48 00002000 + 49 00002000 ; Heap Configuration + 50 00002000 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 51 00002000 ; + 52 00002000 + 53 00002000 00001000 + Heap_Size + EQU 0x00001000 + 54 00002000 + 55 00002000 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 56 00000000 __heap_base + 57 00000000 Heap_Mem + SPACE Heap_Size + 58 00001000 __heap_limit + 59 00001000 + 60 00001000 PRESERVE8 + 61 00001000 THUMB + 62 00001000 + 63 00001000 + 64 00001000 ; Vector Table Mapped to Address 0 at Reset + 65 00001000 + 66 00001000 AREA RESET, DATA, READONLY + 67 00000000 EXPORT __Vectors + 68 00000000 EXPORT __Vectors_End + 69 00000000 EXPORT __Vectors_Size + 70 00000000 EXPORT __isr_vector + 71 00000000 IMPORT SysTick_Handler + 72 00000000 + 73 00000000 00000000 + __isr_vector + DCD __initial_sp ; Top of Stack + 74 00000004 00000000 DCD Reset_Handler ; Reset Handler + 75 00000008 00000000 DCD NMI_Handler ; NMI Handler + 76 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 77 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + + + +ARM Macro Assembler Page 3 + + + 78 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 79 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 80 0000001C 00000000 DCD 0 ; Reserved + 81 00000020 00000000 DCD 0 ; Reserved + 82 00000024 00000000 DCD 0 ; Reserved + 83 00000028 00000000 DCD 0 ; Reserved + 84 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 85 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 86 00000034 00000000 DCD 0 ; Reserved + 87 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 88 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 89 00000040 + 90 00000040 ; Device-specific Interrupts + 91 00000040 00000000 DCD PF_IRQHandler ; 0x10 0x0040 1 + 6: Power Fail + 92 00000044 00000000 DCD WDT0_IRQHandler ; 0x11 0x0044 + 17: Watchdog 0 + 93 00000048 00000000 DCD RSV00_IRQHandler ; 0x12 0x0048 + 18: RSV00 + 94 0000004C 00000000 DCD RTC_IRQHandler ; 0x13 0x004C + 19: RTC + 95 00000050 00000000 DCD RSV01_IRQHandler ; 0x14 0x0050 + 20: RSV1 + 96 00000054 00000000 DCD TMR0_IRQHandler ; 0x15 0x0054 + 21: Timer 0 + 97 00000058 00000000 DCD TMR1_IRQHandler ; 0x16 0x0058 + 22: Timer 1 + 98 0000005C 00000000 DCD TMR2_IRQHandler ; 0x17 0x005C + 23: Timer 2 + 99 00000060 00000000 DCD RSV02_IRQHandler ; 0x18 0x0060 + 24: RSV02 + 100 00000064 00000000 DCD RSV03_IRQHandler ; 0x19 0x0064 + 25: RSV03 + 101 00000068 00000000 DCD RSV04_IRQHandler ; 0x1A 0x0068 + 26: RSV04 + 102 0000006C 00000000 DCD RSV05_IRQHandler ; 0x1B 0x006C + 27: RSV05 + 103 00000070 00000000 DCD RSV06_IRQHandler ; 0x1C 0x0070 + 28: RSV06 + 104 00000074 00000000 DCD I2C0_IRQHandler ; 0x1D 0x0074 + 29: I2C0 + 105 00000078 00000000 DCD UART0_IRQHandler ; 0x1E 0x0078 + 30: UART 0 + 106 0000007C 00000000 DCD UART1_IRQHandler ; 0x1F 0x007C + 31: UART 1 + 107 00000080 00000000 DCD SPI0_IRQHandler ; 0x20 0x0080 + 32: SPIY17 + 108 00000084 00000000 DCD SPI1_IRQHandler ; 0x21 0x0084 + 33: SPIMSS + 109 00000088 00000000 DCD RSV07_IRQHandler ; 0x22 0x0088 + 34: RSV07 + 110 0000008C 00000000 DCD RSV08_IRQHandler ; 0x23 0x008C + 35: RSV08 + + + +ARM Macro Assembler Page 4 + + + 111 00000090 00000000 DCD RSV09_IRQHandler ; 0x24 0x0090 + 36: RSV09 + 112 00000094 00000000 DCD RSV10_IRQHandler ; 0x25 0x0094 + 37: RSV10 + 113 00000098 00000000 DCD RSV11_IRQHandler ; 0x26 0x0098 + 38: RSV11 + 114 0000009C 00000000 DCD FLC_IRQHandler ; 0x27 0x009C + 39: FLC + 115 000000A0 00000000 DCD GPIO0_IRQHandler ; 0x28 0x00A0 + 40: GPIO0 + 116 000000A4 00000000 DCD RSV12_IRQHandler ; 0x29 0x00A4 + 41: RSV12 + 117 000000A8 00000000 DCD RSV13_IRQHandler ; 0x2A 0x00A8 + 42: RSV13 + 118 000000AC 00000000 DCD RSV14_IRQHandler ; 0x2B 0x00AC + 43: RSV14 + 119 000000B0 00000000 DCD DMA0_IRQHandler ; 0x2C 0x00B0 + 44: DMA0 + 120 000000B4 00000000 DCD DMA1_IRQHandler ; 0x2D 0x00B4 + 45: DMA1 + 121 000000B8 00000000 DCD DMA2_IRQHandler ; 0x2E 0x00B8 + 46: DMA2 + 122 000000BC 00000000 DCD DMA3_IRQHandler ; 0x2F 0x00BC + 47: DMA3 + 123 000000C0 00000000 DCD RSV15_IRQHandler ; 0x30 0x00C0 + 48: RSV15 + 124 000000C4 00000000 DCD RSV16_IRQHandler ; 0x31 0x00C4 + 49: RSV16 + 125 000000C8 00000000 DCD RSV17_IRQHandler ; 0x32 0x00C8 + 50: RSV17 + 126 000000CC 00000000 DCD RSV18_IRQHandler ; 0x33 0x00CC + 51: RSV18 + 127 000000D0 00000000 DCD I2C1_IRQHandler ; 0x34 0x00D0 + 52: I2C1 + 128 000000D4 00000000 DCD RSV19_IRQHandler ; 0x35 0x00D4 + 53: RSV19 + 129 000000D8 00000000 DCD RSV20_IRQHandler ; 0x36 0x00D8 + 54: RSV20 + 130 000000DC 00000000 DCD RSV21_IRQHandler ; 0x37 0x00DC + 55: RSV21 + 131 000000E0 00000000 DCD RSV22_IRQHandler ; 0x38 0x00E0 + 56: RSV22 + 132 000000E4 00000000 DCD RSV23_IRQHandler ; 0x39 0x00E4 + 57: RSV23 + 133 000000E8 00000000 DCD RSV24_IRQHandler ; 0x3A 0x00E8 + 58: RSV24 + 134 000000EC 00000000 DCD RSV25_IRQHandler ; 0x3B 0x00EC + 59: RSV25 + 135 000000F0 00000000 DCD RSV26_IRQHandler ; 0x3C 0x00F0 + 60: RSV26 + 136 000000F4 00000000 DCD RSV27_IRQHandler ; 0x3D 0x00F4 + 61: RSV27 + 137 000000F8 00000000 DCD RSV28_IRQHandler ; 0x3E 0x00F8 + 62: RSV28 + 138 000000FC 00000000 DCD RSV29_IRQHandler ; 0x3F 0x00FC + 63: RSV29 + 139 00000100 00000000 DCD RSV30_IRQHandler ; 0x40 0x0100 + 64: RSV30 + 140 00000104 00000000 DCD RSV31_IRQHandler ; 0x41 0x0104 + + + +ARM Macro Assembler Page 5 + + + 65: RSV31 + 141 00000108 00000000 DCD RSV32_IRQHandler ; 0x42 0x0108 + 66: RSV32 + 142 0000010C 00000000 DCD RSV33_IRQHandler ; 0x43 0x010C + 67: RSV33 + 143 00000110 00000000 DCD RSV34_IRQHandler ; 0x44 0x0110 + 68: RSV34 + 144 00000114 00000000 DCD RSV35_IRQHandler ; 0x45 0x0114 + 69: RSV35 + 145 00000118 00000000 DCD GPIOWAKE_IRQHandler ; 0x46 0x0 + 118 70: GPIO Wakeu + p + 146 0000011C __isr_vector_end + 147 0000011C + 148 0000011C 0000011C + __isr_vector_size + EQU __isr_vector_end - __isr_vector + 149 0000011C 00000000 + __Vectors + EQU __isr_vector + 150 0000011C 0000011C + __Vectors_End + EQU __isr_vector_end + 151 0000011C 0000011C + __Vectors_Size + EQU __isr_vector_size + 152 0000011C + 153 0000011C AREA |.text|, CODE, READONLY + 154 00000000 + 155 00000000 Reset_Handler + PROC + 156 00000000 EXPORT Reset_Handler + [WEAK] + 157 00000000 IMPORT PreInit + 158 00000000 ;IMPORT SystemInit + 159 00000000 IMPORT __main + 160 00000000 4807 LDR R0, =PreInit ; Call to PreInit + (prior to RAM initi + alization) + 161 00000002 4780 BLX R0 + 162 00000004 4807 LDR R0, =__main ; SystemInit() is c + alled from post sca + tter memory initial + ization in function + $Sub$$__main_afte + r_scatterload - sys + tem_max32660.c + 163 00000006 4700 BX R0 + 164 00000008 __SPIN + 165 00000008 BF30 WFI + 166 0000000A F7FF FFFD BL __SPIN + 167 0000000E ENDP + 168 0000000E + 169 0000000E ; Dummy Exception Handlers (infinite loops which can be + modified) + 170 0000000E + 172 0000000E NMI_Handler + PROC + 173 0000000E EXPORT NMI_Handler [WEAK] + + + +ARM Macro Assembler Page 6 + + + 174 0000000E E7FE B . + 175 00000010 ENDP + 176 00000010 + 178 00000010 HardFault_Handler + PROC + 179 00000010 EXPORT HardFault_Handler [WEAK] + 180 00000010 E7FE B . + 181 00000012 ENDP + 182 00000012 + 184 00000012 MemManage_Handler + PROC + 185 00000012 EXPORT MemManage_Handler [WEAK] + 186 00000012 E7FE B . + 187 00000014 ENDP + 188 00000014 + 190 00000014 BusFault_Handler + PROC + 191 00000014 EXPORT BusFault_Handler [WEAK] + 192 00000014 E7FE B . + 193 00000016 ENDP + 194 00000016 + 196 00000016 UsageFault_Handler + PROC + 197 00000016 EXPORT UsageFault_Handler [WEAK] + 198 00000016 E7FE B . + 199 00000018 ENDP + 200 00000018 + 202 00000018 SVC_Handler + PROC + 203 00000018 EXPORT SVC_Handler [WEAK] + 204 00000018 E7FE B . + 205 0000001A ENDP + 206 0000001A + 208 0000001A DebugMon_Handler + PROC + 209 0000001A EXPORT DebugMon_Handler [WEAK] + 210 0000001A E7FE B . + 211 0000001C ENDP + 212 0000001C + 214 0000001C PendSV_Handler + PROC + 215 0000001C EXPORT PendSV_Handler [WEAK] + 216 0000001C E7FE B . + 217 0000001E ENDP + 219 0000001E Default_Handler + PROC + 220 0000001E ; MAX32660 Device-specific Interrupts + 221 0000001E EXPORT PF_IRQHandler [WEAK] + + ; 0x10 0x0040 16 + : Power Fail + 222 0000001E EXPORT WDT0_IRQHandler [WEAK] + + ; 0x11 0x0044 17 + : Watchdog 0 + 223 0000001E EXPORT RSV00_IRQHandler [WEAK] + + ; 0x12 0x0048 18 + : RSV00 + + + +ARM Macro Assembler Page 7 + + + 224 0000001E EXPORT RTC_IRQHandler [WEAK] + + ; 0x13 0x004C 19 + : RTC + 225 0000001E EXPORT RSV01_IRQHandler [WEAK] + + ; 0x14 0x0050 20 + : RSV01 + 226 0000001E EXPORT TMR0_IRQHandler [WEAK] + + ; 0x15 0x0054 21 + : Timer 0 + 227 0000001E EXPORT TMR1_IRQHandler [WEAK] + + ; 0x16 0x0058 22 + : Timer 1 + 228 0000001E EXPORT TMR2_IRQHandler [WEAK] + + ; 0x17 0x005C 23 + : Timer 2 + 229 0000001E EXPORT RSV02_IRQHandler [WEAK] + + ; 0x18 0x0060 24 + : RSV02 + 230 0000001E EXPORT RSV03_IRQHandler [WEAK] + + ; 0x19 0x0064 25 + : RSV03 + 231 0000001E EXPORT RSV04_IRQHandler [WEAK] + + ; 0x1A 0x0068 26 + : RSV04 + 232 0000001E EXPORT RSV05_IRQHandler [WEAK] + + ; 0x1B 0x006C 27 + : RSV05 + 233 0000001E EXPORT RSV06_IRQHandler [WEAK] + + ; 0x1C 0x0070 28 + : RSV06 + 234 0000001E EXPORT I2C0_IRQHandler [WEAK] + + ; 0x1D 0x0074 29 + : I2C0 + 235 0000001E EXPORT UART0_IRQHandler [WEAK] + + ; 0x1E 0x0078 30 + : UART 0 + 236 0000001E EXPORT UART1_IRQHandler [WEAK] + + ; 0x1F 0x007C 31 + : UART 1 + 237 0000001E EXPORT SPI0_IRQHandler [WEAK] + + ; 0x20 0x0080 32 + : SPIY17 + 238 0000001E EXPORT SPI1_IRQHandler [WEAK] + + ; 0x21 0x0084 33 + + + +ARM Macro Assembler Page 8 + + + : SPIMSS + 239 0000001E EXPORT RSV07_IRQHandler [WEAK] + + ; 0x22 0x0088 34 + : RSV07 + 240 0000001E EXPORT RSV08_IRQHandler [WEAK] + + ; 0x23 0x008C 35 + : RSV08 + 241 0000001E EXPORT RSV09_IRQHandler [WEAK] + + ; 0x24 0x0090 36 + : RSV09 + 242 0000001E EXPORT RSV10_IRQHandler [WEAK] + + ; 0x25 0x0094 37 + : RSV10 + 243 0000001E EXPORT RSV11_IRQHandler [WEAK] + + ; 0x26 0x0098 38 + : RSV11 + 244 0000001E EXPORT FLC_IRQHandler [WEAK] + + ; 0x27 0x009C 39 + : FLC + 245 0000001E EXPORT GPIO0_IRQHandler [WEAK] + + ; 0x28 0x00A0 40 + : GPIO0 + 246 0000001E EXPORT RSV12_IRQHandler [WEAK] + + ; 0x29 0x00A4 41 + : RSV12 + 247 0000001E EXPORT RSV13_IRQHandler [WEAK] + + ; 0x2A 0x00A8 42 + : RSV13 + 248 0000001E EXPORT RSV14_IRQHandler [WEAK] + + ; 0x2B 0x00AC 43 + : RSV14 + 249 0000001E EXPORT DMA0_IRQHandler [WEAK] + + ; 0x2C 0x00B0 44 + : DMA0 + 250 0000001E EXPORT DMA1_IRQHandler [WEAK] + + ; 0x2D 0x00B4 45 + : DMA1 + 251 0000001E EXPORT DMA2_IRQHandler [WEAK] + + ; 0x2E 0x00B8 46 + : DMA2 + 252 0000001E EXPORT DMA3_IRQHandler [WEAK] + + ; 0x2F 0x00BC 47 + : DMA3 + 253 0000001E EXPORT RSV15_IRQHandler [WEAK] + + + + +ARM Macro Assembler Page 9 + + + ; 0x30 0x00C0 48 + : RSV15 + 254 0000001E EXPORT RSV16_IRQHandler [WEAK] + + ; 0x31 0x00C4 49 + : RSV16 + 255 0000001E EXPORT RSV17_IRQHandler [WEAK] + + ; 0x32 0x00C8 50 + : RSV17 + 256 0000001E EXPORT RSV18_IRQHandler [WEAK] + + ; 0x33 0x00CC 51 + : RSV18 + 257 0000001E EXPORT I2C1_IRQHandler [WEAK] + + ; 0x34 0x00D0 52 + : I2C1 + 258 0000001E EXPORT RSV19_IRQHandler [WEAK] + + ; 0x35 0x00D4 53 + : RSV19 + 259 0000001E EXPORT RSV20_IRQHandler [WEAK] + + ; 0x36 0x00D8 54 + : RSV20 + 260 0000001E EXPORT RSV21_IRQHandler [WEAK] + + ; 0x37 0x00DC 55 + : RSV21 + 261 0000001E EXPORT RSV22_IRQHandler [WEAK] + + ; 0x38 0x00E0 56 + : RSV22 + 262 0000001E EXPORT RSV23_IRQHandler [WEAK] + + ; 0x39 0x00E4 57 + : RSV23 + 263 0000001E EXPORT RSV24_IRQHandler [WEAK] + + ; 0x3A 0x00E8 58 + : RSV24 + 264 0000001E EXPORT RSV25_IRQHandler [WEAK] + + ; 0x3B 0x00EC 59 + : RSV25 + 265 0000001E EXPORT RSV26_IRQHandler [WEAK] + + ; 0x3C 0x00F0 60 + : RSV26 + 266 0000001E EXPORT RSV27_IRQHandler [WEAK] + + ; 0x3D 0x00F4 61 + : RSV27 + 267 0000001E EXPORT RSV28_IRQHandler [WEAK] + + ; 0x3E 0x00F8 62 + : RSV28 + 268 0000001E EXPORT RSV29_IRQHandler [WEAK] + + + +ARM Macro Assembler Page 10 + + + + ; 0x3F 0x00FC 63 + : RSV29 + 269 0000001E EXPORT RSV30_IRQHandler [WEAK] + + ; 0x40 0x0100 64 + : RSV30 + 270 0000001E EXPORT RSV31_IRQHandler [WEAK] + + ; 0x41 0x0104 65 + : RSV31 + 271 0000001E EXPORT RSV32_IRQHandler [WEAK] + + ; 0x42 0x0108 66 + : RSV32 + 272 0000001E EXPORT RSV33_IRQHandler [WEAK] + + ; 0x43 0x010C 67 + : RSV33 + 273 0000001E EXPORT RSV34_IRQHandler [WEAK] + + ; 0x44 0x0110 68 + : RSV34 + 274 0000001E EXPORT RSV35_IRQHandler [WEAK] + + ; 0x45 0x0114 69 + : RSV35 + 275 0000001E EXPORT GPIOWAKE_IRQHandler [WEAK] + + ; 0x46 0x0118 70 + : GPIO Wakeup + 276 0000001E + 277 0000001E ;******************************************************* + ************************ + 278 0000001E ; Default handler implementations + 279 0000001E ;******************************************************* + ************************ + 280 0000001E PF_IRQHandler ; 0x10 0x0040 16 + : Power Fail + 281 0000001E WDT0_IRQHandler ; 0x11 0x0044 17 + : Watchdog 0 + 282 0000001E RSV00_IRQHandler ; 0x12 0x0048 18 + : RSV00 + 283 0000001E RTC_IRQHandler ; 0x13 0x004C 19 + : RTC + 284 0000001E RSV01_IRQHandler ; 0x14 0x0050 20 + : RSV01 + 285 0000001E TMR0_IRQHandler ; 0x15 0x0054 21 + : Timer 0 + 286 0000001E TMR1_IRQHandler ; 0x16 0x0058 22 + : Timer 1 + 287 0000001E TMR2_IRQHandler ; 0x17 0x005C 23 + : Timer 2 + 288 0000001E RSV02_IRQHandler ; 0x18 0x0060 24 + : RSV02 + 289 0000001E RSV03_IRQHandler ; 0x19 0x0064 25 + : RSV03 + 290 0000001E RSV04_IRQHandler ; 0x1A 0x0068 26 + : RSV04 + + + +ARM Macro Assembler Page 11 + + + 291 0000001E RSV05_IRQHandler ; 0x1B 0x006C 27 + : RSV05 + 292 0000001E RSV06_IRQHandler ; 0x1C 0x0070 28 + : RSV06 + 293 0000001E I2C0_IRQHandler ; 0x1D 0x0074 29 + : I2C0 + 294 0000001E UART0_IRQHandler ; 0x1E 0x0078 30 + : UART 0 + 295 0000001E UART1_IRQHandler ; 0x1F 0x007C 31 + : UART 1 + 296 0000001E SPI0_IRQHandler ; 0x20 0x0080 32 + : SPI0 + 297 0000001E SPI1_IRQHandler ; 0x21 0x0084 33 + : SPI1 + 298 0000001E RSV07_IRQHandler ; 0x22 0x0088 34 + : RSV07 + 299 0000001E RSV08_IRQHandler ; 0x23 0x008C 35 + : RSV08 + 300 0000001E RSV09_IRQHandler ; 0x24 0x0090 36 + : RSV09 + 301 0000001E RSV10_IRQHandler ; 0x25 0x0094 37 + : RSV10 + 302 0000001E RSV11_IRQHandler ; 0x26 0x0098 38 + : RSV11 + 303 0000001E FLC_IRQHandler ; 0x27 0x009C 39 + : FLC + 304 0000001E GPIO0_IRQHandler ; 0x28 0x00A0 40 + : GPIO0 + 305 0000001E RSV12_IRQHandler ; 0x29 0x00A4 41 + : RSV12 + 306 0000001E RSV13_IRQHandler ; 0x2A 0x00A8 42 + : RSV13 + 307 0000001E RSV14_IRQHandler ; 0x2B 0x00AC 43 + : RSV14 + 308 0000001E DMA0_IRQHandler ; 0x2C 0x00B0 44 + : DMA0 + 309 0000001E DMA1_IRQHandler ; 0x2D 0x00B4 45 + : DMA1 + 310 0000001E DMA2_IRQHandler ; 0x2E 0x00B8 46 + : DMA2 + 311 0000001E DMA3_IRQHandler ; 0x2F 0x00BC 47 + : DMA3 + 312 0000001E RSV15_IRQHandler ; 0x30 0x00C0 48 + : RSV15 + 313 0000001E RSV16_IRQHandler ; 0x31 0x00C4 49 + : RSV16 + 314 0000001E RSV17_IRQHandler ; 0x32 0x00C8 50 + : RSV17 + 315 0000001E RSV18_IRQHandler ; 0x33 0x00CC 51 + : RSV18 + 316 0000001E I2C1_IRQHandler ; 0x34 0x00D0 52 + : I2C1 + 317 0000001E RSV19_IRQHandler ; 0x35 0x00D4 53 + : RSV19 + 318 0000001E RSV20_IRQHandler ; 0x36 0x00D8 54 + : RSV20 + 319 0000001E RSV21_IRQHandler ; 0x37 0x00DC 55 + : RSV21 + 320 0000001E RSV22_IRQHandler ; 0x38 0x00E0 56 + + + +ARM Macro Assembler Page 12 + + + : RSV22 + 321 0000001E RSV23_IRQHandler ; 0x39 0x00E4 57 + : RSV23 + 322 0000001E RSV24_IRQHandler ; 0x3A 0x00E8 58 + : RSV24 + 323 0000001E RSV25_IRQHandler ; 0x3B 0x00EC 59 + : RSV25 + 324 0000001E RSV26_IRQHandler ; 0x3C 0x00F0 60 + : RSV26 + 325 0000001E RSV27_IRQHandler ; 0x3D 0x00F4 61 + : RSV27 + 326 0000001E RSV28_IRQHandler ; 0x3E 0x00F8 62 + : RSV28 + 327 0000001E RSV29_IRQHandler ; 0x3F 0x00FC 63 + : RSV29 + 328 0000001E RSV30_IRQHandler ; 0x40 0x0100 64 + : RSV30 + 329 0000001E RSV31_IRQHandler ; 0x41 0x0104 65 + : RSV31 + 330 0000001E RSV32_IRQHandler ; 0x42 0x0108 66 + : RSV32 + 331 0000001E RSV33_IRQHandler ; 0x43 0x010C 67 + : RSV33 + 332 0000001E RSV34_IRQHandler ; 0x44 0x0110 68 + : RSV34 + 333 0000001E RSV35_IRQHandler ; 0x45 0x0114 69 + : RSV35 + 334 0000001E GPIOWAKE_IRQHandler ; 0x46 0x0118 70 + : GPIO Wakeup + 335 0000001E + 336 0000001E E7FE B . + 337 00000020 ENDP + 338 00000020 + 339 00000020 ALIGN + 340 00000020 + 341 00000020 ;******************************************************* + ************************ + 342 00000020 ; User Stack and Heap initialization + 343 00000020 ;******************************************************* + ************************ + 344 00000020 IF :DEF:__MICROLIB + 345 00000020 + 346 00000020 EXPORT __initial_sp + 347 00000020 EXPORT __heap_base + 348 00000020 EXPORT __heap_limit + 349 00000020 + 350 00000020 ELSE + 367 ENDIF + 368 00000020 + 369 00000020 END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M4.fp.sp --apcs= +interwork --depend=.\objects\startup_max32660.d -o.\objects\startup_max32660.o +-IC:\Users\befs\AppData\Local\Arm\Packs\Maxim\MAX32660\1.4.0\Libraries\Device\M +axim\MAX32660\Include -IC:\Keil_v5\ARM\CMSIS\Include --predefine="__MICROLIB SE +TA 1" --predefine="__UVISION_VERSION SETA 533" --predefine="MAX32660 SETA 1" -- +list=.\listings\startup_max32660.lst ..\SDK\Startup\startup_max32660.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 45 in file ..\SDK\Startup\startup_max32660.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 46 in file ..\SDK\Startup\startup_max32660.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00002000 + +Symbol: __initial_sp + Definitions + At line 47 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 73 in file ..\SDK\Startup\startup_max32660.s + At line 346 in file ..\SDK\Startup\startup_max32660.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 55 in file ..\SDK\Startup\startup_max32660.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 57 in file ..\SDK\Startup\startup_max32660.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 56 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 347 in file ..\SDK\Startup\startup_max32660.s +Comment: __heap_base used once +__heap_limit 00001000 + +Symbol: __heap_limit + Definitions + At line 58 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 348 in file ..\SDK\Startup\startup_max32660.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 66 in file ..\SDK\Startup\startup_max32660.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 149 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 67 in file ..\SDK\Startup\startup_max32660.s +Comment: __Vectors used once +__Vectors_End 0000011C + +Symbol: __Vectors_End + Definitions + At line 150 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 68 in file ..\SDK\Startup\startup_max32660.s +Comment: __Vectors_End used once +__isr_vector 00000000 + +Symbol: __isr_vector + Definitions + At line 73 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 70 in file ..\SDK\Startup\startup_max32660.s + At line 148 in file ..\SDK\Startup\startup_max32660.s + At line 149 in file ..\SDK\Startup\startup_max32660.s + +__isr_vector_end 0000011C + +Symbol: __isr_vector_end + Definitions + At line 146 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 148 in file ..\SDK\Startup\startup_max32660.s + At line 150 in file ..\SDK\Startup\startup_max32660.s + +5 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 153 in file ..\SDK\Startup\startup_max32660.s + Uses + None +Comment: .text unused +BusFault_Handler 00000014 + +Symbol: BusFault_Handler + Definitions + At line 190 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 78 in file ..\SDK\Startup\startup_max32660.s + At line 191 in file ..\SDK\Startup\startup_max32660.s + +DMA0_IRQHandler 0000001E + +Symbol: DMA0_IRQHandler + Definitions + At line 308 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 119 in file ..\SDK\Startup\startup_max32660.s + At line 249 in file ..\SDK\Startup\startup_max32660.s + +DMA1_IRQHandler 0000001E + +Symbol: DMA1_IRQHandler + Definitions + At line 309 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 120 in file ..\SDK\Startup\startup_max32660.s + At line 250 in file ..\SDK\Startup\startup_max32660.s + +DMA2_IRQHandler 0000001E + +Symbol: DMA2_IRQHandler + Definitions + At line 310 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 121 in file ..\SDK\Startup\startup_max32660.s + At line 251 in file ..\SDK\Startup\startup_max32660.s + +DMA3_IRQHandler 0000001E + +Symbol: DMA3_IRQHandler + Definitions + At line 311 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 122 in file ..\SDK\Startup\startup_max32660.s + At line 252 in file ..\SDK\Startup\startup_max32660.s + +DebugMon_Handler 0000001A + +Symbol: DebugMon_Handler + Definitions + At line 208 in file ..\SDK\Startup\startup_max32660.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 85 in file ..\SDK\Startup\startup_max32660.s + At line 209 in file ..\SDK\Startup\startup_max32660.s + +Default_Handler 0000001E + +Symbol: Default_Handler + Definitions + At line 219 in file ..\SDK\Startup\startup_max32660.s + Uses + None +Comment: Default_Handler unused +FLC_IRQHandler 0000001E + +Symbol: FLC_IRQHandler + Definitions + At line 303 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 114 in file ..\SDK\Startup\startup_max32660.s + At line 244 in file ..\SDK\Startup\startup_max32660.s + +GPIO0_IRQHandler 0000001E + +Symbol: GPIO0_IRQHandler + Definitions + At line 304 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 115 in file ..\SDK\Startup\startup_max32660.s + At line 245 in file ..\SDK\Startup\startup_max32660.s + +GPIOWAKE_IRQHandler 0000001E + +Symbol: GPIOWAKE_IRQHandler + Definitions + At line 334 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 145 in file ..\SDK\Startup\startup_max32660.s + At line 275 in file ..\SDK\Startup\startup_max32660.s + +HardFault_Handler 00000010 + +Symbol: HardFault_Handler + Definitions + At line 178 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 76 in file ..\SDK\Startup\startup_max32660.s + At line 179 in file ..\SDK\Startup\startup_max32660.s + +I2C0_IRQHandler 0000001E + +Symbol: I2C0_IRQHandler + Definitions + At line 293 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 104 in file ..\SDK\Startup\startup_max32660.s + At line 234 in file ..\SDK\Startup\startup_max32660.s + +I2C1_IRQHandler 0000001E + +Symbol: I2C1_IRQHandler + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 316 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 127 in file ..\SDK\Startup\startup_max32660.s + At line 257 in file ..\SDK\Startup\startup_max32660.s + +MemManage_Handler 00000012 + +Symbol: MemManage_Handler + Definitions + At line 184 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 77 in file ..\SDK\Startup\startup_max32660.s + At line 185 in file ..\SDK\Startup\startup_max32660.s + +NMI_Handler 0000000E + +Symbol: NMI_Handler + Definitions + At line 172 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 75 in file ..\SDK\Startup\startup_max32660.s + At line 173 in file ..\SDK\Startup\startup_max32660.s + +PF_IRQHandler 0000001E + +Symbol: PF_IRQHandler + Definitions + At line 280 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 91 in file ..\SDK\Startup\startup_max32660.s + At line 221 in file ..\SDK\Startup\startup_max32660.s + +PendSV_Handler 0000001C + +Symbol: PendSV_Handler + Definitions + At line 214 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 87 in file ..\SDK\Startup\startup_max32660.s + At line 215 in file ..\SDK\Startup\startup_max32660.s + +RSV00_IRQHandler 0000001E + +Symbol: RSV00_IRQHandler + Definitions + At line 282 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 93 in file ..\SDK\Startup\startup_max32660.s + At line 223 in file ..\SDK\Startup\startup_max32660.s + +RSV01_IRQHandler 0000001E + +Symbol: RSV01_IRQHandler + Definitions + At line 284 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 95 in file ..\SDK\Startup\startup_max32660.s + At line 225 in file ..\SDK\Startup\startup_max32660.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +RSV02_IRQHandler 0000001E + +Symbol: RSV02_IRQHandler + Definitions + At line 288 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 99 in file ..\SDK\Startup\startup_max32660.s + At line 229 in file ..\SDK\Startup\startup_max32660.s + +RSV03_IRQHandler 0000001E + +Symbol: RSV03_IRQHandler + Definitions + At line 289 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 100 in file ..\SDK\Startup\startup_max32660.s + At line 230 in file ..\SDK\Startup\startup_max32660.s + +RSV04_IRQHandler 0000001E + +Symbol: RSV04_IRQHandler + Definitions + At line 290 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 101 in file ..\SDK\Startup\startup_max32660.s + At line 231 in file ..\SDK\Startup\startup_max32660.s + +RSV05_IRQHandler 0000001E + +Symbol: RSV05_IRQHandler + Definitions + At line 291 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 102 in file ..\SDK\Startup\startup_max32660.s + At line 232 in file ..\SDK\Startup\startup_max32660.s + +RSV06_IRQHandler 0000001E + +Symbol: RSV06_IRQHandler + Definitions + At line 292 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 103 in file ..\SDK\Startup\startup_max32660.s + At line 233 in file ..\SDK\Startup\startup_max32660.s + +RSV07_IRQHandler 0000001E + +Symbol: RSV07_IRQHandler + Definitions + At line 298 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 109 in file ..\SDK\Startup\startup_max32660.s + At line 239 in file ..\SDK\Startup\startup_max32660.s + +RSV08_IRQHandler 0000001E + +Symbol: RSV08_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 299 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 110 in file ..\SDK\Startup\startup_max32660.s + At line 240 in file ..\SDK\Startup\startup_max32660.s + +RSV09_IRQHandler 0000001E + +Symbol: RSV09_IRQHandler + Definitions + At line 300 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 111 in file ..\SDK\Startup\startup_max32660.s + At line 241 in file ..\SDK\Startup\startup_max32660.s + +RSV10_IRQHandler 0000001E + +Symbol: RSV10_IRQHandler + Definitions + At line 301 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 112 in file ..\SDK\Startup\startup_max32660.s + At line 242 in file ..\SDK\Startup\startup_max32660.s + +RSV11_IRQHandler 0000001E + +Symbol: RSV11_IRQHandler + Definitions + At line 302 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 113 in file ..\SDK\Startup\startup_max32660.s + At line 243 in file ..\SDK\Startup\startup_max32660.s + +RSV12_IRQHandler 0000001E + +Symbol: RSV12_IRQHandler + Definitions + At line 305 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 116 in file ..\SDK\Startup\startup_max32660.s + At line 246 in file ..\SDK\Startup\startup_max32660.s + +RSV13_IRQHandler 0000001E + +Symbol: RSV13_IRQHandler + Definitions + At line 306 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 117 in file ..\SDK\Startup\startup_max32660.s + At line 247 in file ..\SDK\Startup\startup_max32660.s + +RSV14_IRQHandler 0000001E + +Symbol: RSV14_IRQHandler + Definitions + At line 307 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 118 in file ..\SDK\Startup\startup_max32660.s + At line 248 in file ..\SDK\Startup\startup_max32660.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +RSV15_IRQHandler 0000001E + +Symbol: RSV15_IRQHandler + Definitions + At line 312 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 123 in file ..\SDK\Startup\startup_max32660.s + At line 253 in file ..\SDK\Startup\startup_max32660.s + +RSV16_IRQHandler 0000001E + +Symbol: RSV16_IRQHandler + Definitions + At line 313 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 124 in file ..\SDK\Startup\startup_max32660.s + At line 254 in file ..\SDK\Startup\startup_max32660.s + +RSV17_IRQHandler 0000001E + +Symbol: RSV17_IRQHandler + Definitions + At line 314 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 125 in file ..\SDK\Startup\startup_max32660.s + At line 255 in file ..\SDK\Startup\startup_max32660.s + +RSV18_IRQHandler 0000001E + +Symbol: RSV18_IRQHandler + Definitions + At line 315 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 126 in file ..\SDK\Startup\startup_max32660.s + At line 256 in file ..\SDK\Startup\startup_max32660.s + +RSV19_IRQHandler 0000001E + +Symbol: RSV19_IRQHandler + Definitions + At line 317 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 128 in file ..\SDK\Startup\startup_max32660.s + At line 258 in file ..\SDK\Startup\startup_max32660.s + +RSV20_IRQHandler 0000001E + +Symbol: RSV20_IRQHandler + Definitions + At line 318 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 129 in file ..\SDK\Startup\startup_max32660.s + At line 259 in file ..\SDK\Startup\startup_max32660.s + +RSV21_IRQHandler 0000001E + +Symbol: RSV21_IRQHandler + Definitions + At line 319 in file ..\SDK\Startup\startup_max32660.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 130 in file ..\SDK\Startup\startup_max32660.s + At line 260 in file ..\SDK\Startup\startup_max32660.s + +RSV22_IRQHandler 0000001E + +Symbol: RSV22_IRQHandler + Definitions + At line 320 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 131 in file ..\SDK\Startup\startup_max32660.s + At line 261 in file ..\SDK\Startup\startup_max32660.s + +RSV23_IRQHandler 0000001E + +Symbol: RSV23_IRQHandler + Definitions + At line 321 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 132 in file ..\SDK\Startup\startup_max32660.s + At line 262 in file ..\SDK\Startup\startup_max32660.s + +RSV24_IRQHandler 0000001E + +Symbol: RSV24_IRQHandler + Definitions + At line 322 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 133 in file ..\SDK\Startup\startup_max32660.s + At line 263 in file ..\SDK\Startup\startup_max32660.s + +RSV25_IRQHandler 0000001E + +Symbol: RSV25_IRQHandler + Definitions + At line 323 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 134 in file ..\SDK\Startup\startup_max32660.s + At line 264 in file ..\SDK\Startup\startup_max32660.s + +RSV26_IRQHandler 0000001E + +Symbol: RSV26_IRQHandler + Definitions + At line 324 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 135 in file ..\SDK\Startup\startup_max32660.s + At line 265 in file ..\SDK\Startup\startup_max32660.s + +RSV27_IRQHandler 0000001E + +Symbol: RSV27_IRQHandler + Definitions + At line 325 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 136 in file ..\SDK\Startup\startup_max32660.s + At line 266 in file ..\SDK\Startup\startup_max32660.s + +RSV28_IRQHandler 0000001E + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: RSV28_IRQHandler + Definitions + At line 326 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 137 in file ..\SDK\Startup\startup_max32660.s + At line 267 in file ..\SDK\Startup\startup_max32660.s + +RSV29_IRQHandler 0000001E + +Symbol: RSV29_IRQHandler + Definitions + At line 327 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 138 in file ..\SDK\Startup\startup_max32660.s + At line 268 in file ..\SDK\Startup\startup_max32660.s + +RSV30_IRQHandler 0000001E + +Symbol: RSV30_IRQHandler + Definitions + At line 328 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 139 in file ..\SDK\Startup\startup_max32660.s + At line 269 in file ..\SDK\Startup\startup_max32660.s + +RSV31_IRQHandler 0000001E + +Symbol: RSV31_IRQHandler + Definitions + At line 329 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 140 in file ..\SDK\Startup\startup_max32660.s + At line 270 in file ..\SDK\Startup\startup_max32660.s + +RSV32_IRQHandler 0000001E + +Symbol: RSV32_IRQHandler + Definitions + At line 330 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 141 in file ..\SDK\Startup\startup_max32660.s + At line 271 in file ..\SDK\Startup\startup_max32660.s + +RSV33_IRQHandler 0000001E + +Symbol: RSV33_IRQHandler + Definitions + At line 331 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 142 in file ..\SDK\Startup\startup_max32660.s + At line 272 in file ..\SDK\Startup\startup_max32660.s + +RSV34_IRQHandler 0000001E + +Symbol: RSV34_IRQHandler + Definitions + At line 332 in file ..\SDK\Startup\startup_max32660.s + Uses + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + At line 143 in file ..\SDK\Startup\startup_max32660.s + At line 273 in file ..\SDK\Startup\startup_max32660.s + +RSV35_IRQHandler 0000001E + +Symbol: RSV35_IRQHandler + Definitions + At line 333 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 144 in file ..\SDK\Startup\startup_max32660.s + At line 274 in file ..\SDK\Startup\startup_max32660.s + +RTC_IRQHandler 0000001E + +Symbol: RTC_IRQHandler + Definitions + At line 283 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 94 in file ..\SDK\Startup\startup_max32660.s + At line 224 in file ..\SDK\Startup\startup_max32660.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 155 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 74 in file ..\SDK\Startup\startup_max32660.s + At line 156 in file ..\SDK\Startup\startup_max32660.s + +SPI0_IRQHandler 0000001E + +Symbol: SPI0_IRQHandler + Definitions + At line 296 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 107 in file ..\SDK\Startup\startup_max32660.s + At line 237 in file ..\SDK\Startup\startup_max32660.s + +SPI1_IRQHandler 0000001E + +Symbol: SPI1_IRQHandler + Definitions + At line 297 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 108 in file ..\SDK\Startup\startup_max32660.s + At line 238 in file ..\SDK\Startup\startup_max32660.s + +SVC_Handler 00000018 + +Symbol: SVC_Handler + Definitions + At line 202 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 84 in file ..\SDK\Startup\startup_max32660.s + At line 203 in file ..\SDK\Startup\startup_max32660.s + +TMR0_IRQHandler 0000001E + + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + +Symbol: TMR0_IRQHandler + Definitions + At line 285 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 96 in file ..\SDK\Startup\startup_max32660.s + At line 226 in file ..\SDK\Startup\startup_max32660.s + +TMR1_IRQHandler 0000001E + +Symbol: TMR1_IRQHandler + Definitions + At line 286 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 97 in file ..\SDK\Startup\startup_max32660.s + At line 227 in file ..\SDK\Startup\startup_max32660.s + +TMR2_IRQHandler 0000001E + +Symbol: TMR2_IRQHandler + Definitions + At line 287 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 98 in file ..\SDK\Startup\startup_max32660.s + At line 228 in file ..\SDK\Startup\startup_max32660.s + +UART0_IRQHandler 0000001E + +Symbol: UART0_IRQHandler + Definitions + At line 294 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 105 in file ..\SDK\Startup\startup_max32660.s + At line 235 in file ..\SDK\Startup\startup_max32660.s + +UART1_IRQHandler 0000001E + +Symbol: UART1_IRQHandler + Definitions + At line 295 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 106 in file ..\SDK\Startup\startup_max32660.s + At line 236 in file ..\SDK\Startup\startup_max32660.s + +UsageFault_Handler 00000016 + +Symbol: UsageFault_Handler + Definitions + At line 196 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 79 in file ..\SDK\Startup\startup_max32660.s + At line 197 in file ..\SDK\Startup\startup_max32660.s + +WDT0_IRQHandler 0000001E + +Symbol: WDT0_IRQHandler + Definitions + At line 281 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 92 in file ..\SDK\Startup\startup_max32660.s + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + + At line 222 in file ..\SDK\Startup\startup_max32660.s + +__SPIN 00000008 + +Symbol: __SPIN + Definitions + At line 164 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 166 in file ..\SDK\Startup\startup_max32660.s +Comment: __SPIN used once +67 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00001000 + +Symbol: Heap_Size + Definitions + At line 53 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 57 in file ..\SDK\Startup\startup_max32660.s +Comment: Heap_Size used once +Stack_Size 00002000 + +Symbol: Stack_Size + Definitions + At line 43 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 46 in file ..\SDK\Startup\startup_max32660.s +Comment: Stack_Size used once +__Vectors_Size 0000011C + +Symbol: __Vectors_Size + Definitions + At line 151 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 69 in file ..\SDK\Startup\startup_max32660.s +Comment: __Vectors_Size used once +__isr_vector_size 0000011C + +Symbol: __isr_vector_size + Definitions + At line 148 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 151 in file ..\SDK\Startup\startup_max32660.s +Comment: __isr_vector_size used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +PreInit 00000000 + +Symbol: PreInit + Definitions + At line 157 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 160 in file ..\SDK\Startup\startup_max32660.s +Comment: PreInit used once +SysTick_Handler 00000000 + +Symbol: SysTick_Handler + Definitions + At line 71 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 88 in file ..\SDK\Startup\startup_max32660.s +Comment: SysTick_Handler used once +__main 00000000 + +Symbol: __main + Definitions + At line 159 in file ..\SDK\Startup\startup_max32660.s + Uses + At line 162 in file ..\SDK\Startup\startup_max32660.s +Comment: __main used once +3 symbols +422 symbols in table diff --git a/Project/SDK/Debuggint_Info/max32660.SFR b/Project/SDK/Debuggint_Info/max32660.SFR new file mode 100644 index 0000000000000000000000000000000000000000..08c303a65875d1f5caae938c0ad3740517514b49 GIT binary patch literal 336380 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zX_S~ZiOkp-ZVK0=F=M0I92P|@krnQ<5~muqak17U7O9-c<_I&dH|afCv18TFUKq1Z zZI~h@k2V@S8PA*aZb~1M+y$RoW+IdGCb>xaAJe0kPBm$rKjgE^bPVj2j*E<@P~wLz zhP`p&n)H>N57MhOoD3BWp@#`ok2Yia>}2p`rn$u=_sabiUIz?TPzmY|W#0M40Hu5` zGx)y-vND!M&d;&)lt7MKIYagTV0Ot|Wzmr#uS%v82Sul!S7D`+i<$ve8S#WN+MTvd z=!**4o=;e%vT8P`X?PKRQ4$SbG$yPyq#kV;c#YFcvaTEH?L{e`f}YlIC|UrX_Mv}n zOd#Q_vka-I#in`ZfS>M=1lWR8m5+6S_FY^{nqt>w1}@a4&sCt(DKGAZd6TY7S02(e z6fzinLDThOG-~(#PK@D1S_$=3!T#> zcJt?`w+7atKC7!T6@4bH$Y~Rk-UzZ?YtpGK4Bpsq5Pg0IDv<=R6IlS0NCNN_0s@#+ z5`Z!leI|_rC{JqvOgfb%H+w`WBmfdg06UQdFo`5UMebV`O)3dMnIfLLpC<`W@dYsH z{4hvQj7xqGTSNQ017S2@LuK5K0X?U3BLwP7X!^xi0zE=D1b$>Tpx@@krsIK{Nmugn zgvO6|8z1*l-7SX}`s%us4JwJEnfch*>FB~fT#4=|`Xanf&}zpLf^V;r-VKM+1Ml(@ hUZ%yrYf);)+)oETpJgenediZF&3XEE94(6v|37cv^H%@> literal 0 HcmV?d00001 diff --git a/Project/SDK/Debuggint_Info/max32660.sfd b/Project/SDK/Debuggint_Info/max32660.sfd new file mode 100644 index 0000000..e4b2d9f --- /dev/null +++ b/Project/SDK/Debuggint_Info/max32660.sfd @@ -0,0 +1,19991 @@ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * @file max32660.sfd + * @brief CMSIS-SVD SFD File + * @version 1.0 + * @date 03. June 2022 + * @note Generated by SVDConv V3.3.39 on Friday, 03.06.2022 16:50:52 + * from File 'max32660.svd', + * last modified on Thursday, 30.09.2021 05:36:38 + */ + + + + +// --------------------------- Register Item Address: BBFC_BBFCR0 ------------------------------- +// SVD Line: 35 + +unsigned int BBFC_BBFCR0 __AT (0x40005800); + + + +// ----------------------------- Field Item: BBFC_BBFCR0_CKPDRV --------------------------------- +// SVD Line: 41 + +// SFDITEM_FIELD__BBFC_BBFCR0_CKPDRV +// CKPDRV +// +// [Bits 3..0] RW (@ 0x40005800) Hyperbus CK Pad Driver Control. +// +// ( (unsigned char)((BBFC_BBFCR0 >> 0) & 0xF), ((BBFC_BBFCR0 = (BBFC_BBFCR0 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Field Item: BBFC_BBFCR0_CKNPDRV -------------------------------- +// SVD Line: 47 + +// SFDITEM_FIELD__BBFC_BBFCR0_CKNPDRV +// CKNPDRV +// +// [Bits 7..4] RW (@ 0x40005800) Hyperbus CKN Pad Driver Control. +// +// ( (unsigned char)((BBFC_BBFCR0 >> 4) & 0xF), ((BBFC_BBFCR0 = (BBFC_BBFCR0 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) )) +// +// +// + + +// ---------------------------- Field Item: BBFC_BBFCR0_RDSDLLEN -------------------------------- +// SVD Line: 53 + +// SFDITEM_FIELD__BBFC_BBFCR0_RDSDLLEN +// RDSDLLEN +// +// [Bit 8] RW (@ 0x40005800) \nHyperbus RDS DLL Power Up Control.\n0 : dis = Disabled.\n1 : en = Enabled. +// +// ( (unsigned int) BBFC_BBFCR0 ) +// RDSDLLEN +// <0=> 0: dis = Disabled. +// <1=> 1: en = Enabled. +// +// +// + + +// ------------------------------- Register RTree: BBFC_BBFCR0 ---------------------------------- +// SVD Line: 35 + +// SFDITEM_REG__BBFC_BBFCR0 +// BBFCR0 +// +// [Bits 31..0] RW (@ 0x40005800) Function Control Register 0. +// ( (unsigned int)((BBFC_BBFCR0 >> 0) & 0xFFFFFFFF), ((BBFC_BBFCR0 = (BBFC_BBFCR0 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) +// SFDITEM_FIELD__BBFC_BBFCR0_CKPDRV +// SFDITEM_FIELD__BBFC_BBFCR0_CKNPDRV +// SFDITEM_FIELD__BBFC_BBFCR0_RDSDLLEN +// +// + + +// ---------------------------------- Peripheral View: BBFC ------------------------------------- +// SVD Line: 25 + +// BBFC +// BBFC +// SFDITEM_REG__BBFC_BBFCR0 +// +// + + +// ---------------------------- Register Item Address: BBSIR_rsv0 ------------------------------- +// SVD Line: 86 + +unsigned int BBSIR_rsv0 __AT (0x40005400); + + + +// -------------------------------- Register Item: BBSIR_rsv0 ----------------------------------- +// SVD Line: 86 + +// SFDITEM_REG__BBSIR_rsv0 +// rsv0 +// [Bits 31..0] RW (@ 0x40005400) RFU +// +// ( (unsigned int)((BBSIR_rsv0 >> 0) & 0xFFFFFFFF), ((BBSIR_rsv0 = (BBSIR_rsv0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register Item Address: BBSIR_BB_SIR2 ------------------------------ +// SVD Line: 91 + +unsigned int BBSIR_BB_SIR2 __AT (0x40005408); + + + +// ------------------------------ Register Item: BBSIR_BB_SIR2 ---------------------------------- +// SVD Line: 91 + +// SFDITEM_REG__BBSIR_BB_SIR2 +// BB_SIR2 +// [Bits 31..0] RO (@ 0x40005408) System Init. Configuration Register 2. +// +// ( (unsigned int)((BBSIR_BB_SIR2 >> 0) & 0xFFFFFFFF), ((BBSIR_BB_SIR2 = (BBSIR_BB_SIR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register Item Address: BBSIR_BB_SIR3 ------------------------------ +// SVD Line: 97 + +unsigned int BBSIR_BB_SIR3 __AT (0x4000540C); + + + +// ------------------------------ Register Item: BBSIR_BB_SIR3 ---------------------------------- +// SVD Line: 97 + +// SFDITEM_REG__BBSIR_BB_SIR3 +// BB_SIR3 +// [Bits 31..0] RO (@ 0x4000540C) System Init. Configuration Register 3. +// +// ( (unsigned int)((BBSIR_BB_SIR3 >> 0) & 0xFFFFFFFF), ((BBSIR_BB_SIR3 = (BBSIR_BB_SIR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// --------------------------------- Peripheral View: BBSIR ------------------------------------- +// SVD Line: 76 + +// BBSIR +// BBSIR +// SFDITEM_REG__BBSIR_rsv0 +// SFDITEM_REG__BBSIR_BB_SIR2 +// SFDITEM_REG__BBSIR_BB_SIR3 +// +// + + +// ------------------------------ Register Item Address: DMA_CN --------------------------------- +// SVD Line: 181 + +unsigned int DMA_CN __AT (0x40028000); + + + +// ------------------------------- Field Item: DMA_CN_CH0_IEN ----------------------------------- +// SVD Line: 186 + +// SFDITEM_FIELD__DMA_CN_CH0_IEN +// CH0_IEN +// +// [Bit 0] RW (@ 0x40028000) \nChannel 0 Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CN ) +// CH0_IEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: DMA_CN_CH1_IEN ----------------------------------- +// SVD Line: 204 + +// SFDITEM_FIELD__DMA_CN_CH1_IEN +// CH1_IEN +// +// [Bit 1] RW (@ 0x40028000) \nChannel 1 Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CN ) +// CH1_IEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: DMA_CN_CH2_IEN ----------------------------------- +// SVD Line: 210 + +// SFDITEM_FIELD__DMA_CN_CH2_IEN +// CH2_IEN +// +// [Bit 2] RW (@ 0x40028000) \nChannel 2 Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CN ) +// CH2_IEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: DMA_CN_CH3_IEN ----------------------------------- +// SVD Line: 216 + +// SFDITEM_FIELD__DMA_CN_CH3_IEN +// CH3_IEN +// +// [Bit 3] RW (@ 0x40028000) \nChannel 3 Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CN ) +// CH3_IEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------------- Register RTree: DMA_CN ------------------------------------- +// SVD Line: 181 + +// SFDITEM_REG__DMA_CN +// CN +// +// [Bits 31..0] RW (@ 0x40028000) DMA Control Register. +// ( (unsigned int)((DMA_CN >> 0) & 0xFFFFFFFF), ((DMA_CN = (DMA_CN & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CN_CH0_IEN +// SFDITEM_FIELD__DMA_CN_CH1_IEN +// SFDITEM_FIELD__DMA_CN_CH2_IEN +// SFDITEM_FIELD__DMA_CN_CH3_IEN +// +// + + +// ----------------------------- Register Item Address: DMA_INTR -------------------------------- +// SVD Line: 224 + +unsigned int DMA_INTR __AT (0x40028004); + + + +// ----------------------------- Field Item: DMA_INTR_CH0_IPEND --------------------------------- +// SVD Line: 230 + +// SFDITEM_FIELD__DMA_INTR_CH0_IPEND +// CH0_IPEND +// +// [Bit 0] RO (@ 0x40028004) \nChannel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) DMA_INTR ) +// CH0_IPEND +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ----------------------------- Field Item: DMA_INTR_CH1_IPEND --------------------------------- +// SVD Line: 249 + +// SFDITEM_FIELD__DMA_INTR_CH1_IPEND +// CH1_IPEND +// +// [Bit 1] RO (@ 0x40028004) \nChannel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) DMA_INTR ) +// CH1_IPEND +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ----------------------------- Field Item: DMA_INTR_CH2_IPEND --------------------------------- +// SVD Line: 254 + +// SFDITEM_FIELD__DMA_INTR_CH2_IPEND +// CH2_IPEND +// +// [Bit 2] RO (@ 0x40028004) \nChannel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) DMA_INTR ) +// CH2_IPEND +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ----------------------------- Field Item: DMA_INTR_CH3_IPEND --------------------------------- +// SVD Line: 259 + +// SFDITEM_FIELD__DMA_INTR_CH3_IPEND +// CH3_IPEND +// +// [Bit 3] RO (@ 0x40028004) \nChannel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) DMA_INTR ) +// CH3_IPEND +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// -------------------------------- Register RTree: DMA_INTR ------------------------------------ +// SVD Line: 224 + +// SFDITEM_REG__DMA_INTR +// INTR +// +// [Bits 31..0] RO (@ 0x40028004) DMA Interrupt Register. +// ( (unsigned int)((DMA_INTR >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__DMA_INTR_CH0_IPEND +// SFDITEM_FIELD__DMA_INTR_CH1_IPEND +// SFDITEM_FIELD__DMA_INTR_CH2_IPEND +// SFDITEM_FIELD__DMA_INTR_CH3_IPEND +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH0_CFG ---------------------------- +// SVD Line: 274 + +unsigned int DMA_CH_CH_CH0_CFG __AT (0x40028200); + + + +// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_CHEN ------------------------------- +// SVD Line: 279 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CHEN +// CHEN +// +// [Bit 0] RW (@ 0x40028200) \nChannel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// CHEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_RLDEN ------------------------------ +// SVD Line: 297 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_RLDEN +// RLDEN +// +// [Bit 1] RW (@ 0x40028200) \nReload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// RLDEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: DMA_CH_CH_CH0_CFG_PRI ------------------------------- +// SVD Line: 315 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_PRI +// PRI +// +// [Bits 3..2] RW (@ 0x40028200) \nDMA Priority.\n0 : high = Highest Priority.\n1 : medHigh = Medium High Priority.\n2 : medLow = Medium Low Priority.\n3 : low = Lowest Priority. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// PRI +// <0=> 0: high = Highest Priority. +// <1=> 1: medHigh = Medium High Priority. +// <2=> 2: medLow = Medium Low Priority. +// <3=> 3: low = Lowest Priority. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_REQSEL ------------------------------ +// SVD Line: 343 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_REQSEL +// REQSEL +// +// [Bits 9..4] RW (@ 0x40028200) \nRequest Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n0 : MEMTOMEM = Memory To Memory\n1 : SPI0RX = SPI0 RX\n2 : SPI1RX = SPI1 RX\n3 : Reserved - do not use\n4 : UART0RX = UART0 RX\n5 : UART1RX = UART1 RX\n6 : Reserved - do not use\n7 : I2C0RX = I2C0 RX\n8 : I2C1RX = I2C1 RX\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : SPI0TX = SPI0 TX\n34 : SPI1TX = SPI1 TX\n35 : Reserved - do not use\n36 : UART0TX = UART0 TX\n37 : UART1TX = UART1 TX\n38 : Reserved - do not use\n39 : I2C0TX = I2C0 TX\n40 : I2C1TX = I2C1 TX\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// REQSEL +// <0=> 0: MEMTOMEM = Memory To Memory +// <1=> 1: SPI0RX = SPI0 RX +// <2=> 2: SPI1RX = SPI1 RX +// <3=> 3: +// <4=> 4: UART0RX = UART0 RX +// <5=> 5: UART1RX = UART1 RX +// <6=> 6: +// <7=> 7: I2C0RX = I2C0 RX +// <8=> 8: I2C1RX = I2C1 RX +// <9=> 9: +// <10=> 10: +// <11=> 11: +// <12=> 12: +// <13=> 13: +// <14=> 14: +// <15=> 15: +// <16=> 16: +// <17=> 17: +// <18=> 18: +// <19=> 19: +// <20=> 20: +// <21=> 21: +// <22=> 22: +// <23=> 23: +// <24=> 24: +// <25=> 25: +// <26=> 26: +// <27=> 27: +// <28=> 28: +// <29=> 29: +// <30=> 30: +// <31=> 31: +// <32=> 32: +// <33=> 33: SPI0TX = SPI0 TX +// <34=> 34: SPI1TX = SPI1 TX +// <35=> 35: +// <36=> 36: UART0TX = UART0 TX +// <37=> 37: UART1TX = UART1 TX +// <38=> 38: +// <39=> 39: I2C0TX = I2C0 TX +// <40=> 40: I2C1TX = I2C1 TX +// <41=> 41: +// <42=> 42: +// <43=> 43: +// <44=> 44: +// <45=> 45: +// <46=> 46: +// <47=> 47: +// <48=> 48: +// <49=> 49: +// <50=> 50: +// <51=> 51: +// <52=> 52: +// <53=> 53: +// <54=> 54: +// <55=> 55: +// <56=> 56: +// <57=> 57: +// <58=> 58: +// <59=> 59: +// <60=> 60: +// <61=> 61: +// <62=> 62: +// <63=> 63: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_REQWAIT ----------------------------- +// SVD Line: 416 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_REQWAIT +// REQWAIT +// +// [Bit 10] RW (@ 0x40028200) \nRequest Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// REQWAIT +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_TOSEL ------------------------------ +// SVD Line: 434 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_TOSEL +// TOSEL +// +// [Bits 13..11] RW (@ 0x40028200) \nTime-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.\n0 : to4 = Timeout of 3 to 4 prescale clocks.\n1 : to8 = Timeout of 7 to 8 prescale clocks.\n2 : to16 = Timeout of 15 to 16 prescale clocks.\n3 : to32 = Timeout of 31 to 32 prescale clocks.\n4 : to64 = Timeout of 63 to 64 prescale clocks.\n5 : to128 = Timeout of 127 to 128 prescale clocks.\n6 : to256 = Timeout of 255 to 256 prescale clocks.\n7 : to512 = Timeout of 511 to 512 prescale clocks. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// TOSEL +// <0=> 0: to4 = Timeout of 3 to 4 prescale clocks. +// <1=> 1: to8 = Timeout of 7 to 8 prescale clocks. +// <2=> 2: to16 = Timeout of 15 to 16 prescale clocks. +// <3=> 3: to32 = Timeout of 31 to 32 prescale clocks. +// <4=> 4: to64 = Timeout of 63 to 64 prescale clocks. +// <5=> 5: to128 = Timeout of 127 to 128 prescale clocks. +// <6=> 6: to256 = Timeout of 255 to 256 prescale clocks. +// <7=> 7: to512 = Timeout of 511 to 512 prescale clocks. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_PSSEL ------------------------------ +// SVD Line: 482 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_PSSEL +// PSSEL +// +// [Bits 15..14] RW (@ 0x40028200) \nPre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n0 : dis = Disable timer.\n1 : div256 = hclk / 256.\n2 : div64k = hclk / 64k.\n3 : div16M = hclk / 16M. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// PSSEL +// <0=> 0: dis = Disable timer. +// <1=> 1: div256 = hclk / 256. +// <2=> 2: div64k = hclk / 64k. +// <3=> 3: div16M = hclk / 16M. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_SRCWD ------------------------------ +// SVD Line: 510 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_SRCWD +// SRCWD +// +// [Bits 17..16] RW (@ 0x40028200) \nSource Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// SRCWD +// <0=> 0: byte = Byte. +// <1=> 1: halfWord = Halfword. +// <2=> 2: word = Word. +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_SRCINC ------------------------------ +// SVD Line: 533 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_SRCINC +// SRCINC +// +// [Bit 18] RW (@ 0x40028200) \nSource Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// SRCINC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_DSTWD ------------------------------ +// SVD Line: 551 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_DSTWD +// DSTWD +// +// [Bits 21..20] RW (@ 0x40028200) \nDestination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// DSTWD +// <0=> 0: byte = Byte. +// <1=> 1: halfWord = Halfword. +// <2=> 2: word = Word. +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_DSTINC ------------------------------ +// SVD Line: 574 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_DSTINC +// DSTINC +// +// [Bit 22] RW (@ 0x40028200) \nDestination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// DSTINC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_CFG_BRST ------------------------------- +// SVD Line: 592 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_BRST +// BRST +// +// [Bits 28..24] RW (@ 0x40028200) Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. +// +// ( (unsigned char)((DMA_CH_CH_CH0_CFG >> 24) & 0x1F), ((DMA_CH_CH_CH0_CFG = (DMA_CH_CH_CH0_CFG & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) )) +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_CHDIEN ------------------------------ +// SVD Line: 598 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CHDIEN +// CHDIEN +// +// [Bit 30] RW (@ 0x40028200) \nChannel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// CHDIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH0_CFG_CTZIEN ------------------------------ +// SVD Line: 616 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CTZIEN +// CTZIEN +// +// [Bit 31] RW (@ 0x40028200) \nCount-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_CFG ) +// CTZIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH0_CFG ------------------------------- +// SVD Line: 274 + +// SFDITEM_REG__DMA_CH_CH_CH0_CFG +// CFG +// +// [Bits 31..0] RW (@ 0x40028200) DMA Channel Configuration Register. +// ( (unsigned int)((DMA_CH_CH_CH0_CFG >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_CFG = (DMA_CH_CH_CH0_CFG & ~(0xDF77FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF77FFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CHEN +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_RLDEN +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_PRI +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_REQSEL +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_REQWAIT +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_TOSEL +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_PSSEL +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_SRCWD +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_SRCINC +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_DSTWD +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_DSTINC +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_BRST +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CHDIEN +// SFDITEM_FIELD__DMA_CH_CH_CH0_CFG_CTZIEN +// +// + + +// ------------------------- Register Item Address: DMA_CH_CH_CH0_ST ---------------------------- +// SVD Line: 636 + +unsigned int DMA_CH_CH_CH0_ST __AT (0x40028204); + + + +// --------------------------- Field Item: DMA_CH_CH_CH0_ST_CH_ST ------------------------------- +// SVD Line: 641 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_CH_ST +// CH_ST +// +// [Bit 0] RO (@ 0x40028204) \nChannel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_ST ) +// CH_ST +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_ST_IPEND ------------------------------- +// SVD Line: 660 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_IPEND +// IPEND +// +// [Bit 1] RO (@ 0x40028204) \nChannel Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) DMA_CH_CH_CH0_ST ) +// IPEND +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_ST_CTZ_ST ------------------------------ +// SVD Line: 679 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_CTZ_ST +// CTZ_ST +// +// [Bit 2] RW (@ 0x40028204) \nCount-to-Zero (CTZ) Status\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH0_ST ) +// CTZ_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_ST_RLD_ST ------------------------------ +// SVD Line: 709 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_RLD_ST +// RLD_ST +// +// [Bit 3] RW (@ 0x40028204) \nReload Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH0_ST ) +// RLD_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH0_ST_BUS_ERR ------------------------------ +// SVD Line: 737 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_BUS_ERR +// BUS_ERR +// +// [Bit 4] RW (@ 0x40028204) \nBus Error. Indicates that an AHB abort was received and the channel has been disabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH0_ST ) +// BUS_ERR +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH0_ST_TO_ST ------------------------------- +// SVD Line: 765 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_TO_ST +// TO_ST +// +// [Bit 6] RW (@ 0x40028204) \nTime-Out Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH0_ST ) +// TO_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH0_ST -------------------------------- +// SVD Line: 636 + +// SFDITEM_REG__DMA_CH_CH_CH0_ST +// ST +// +// [Bits 31..0] RW (@ 0x40028204) DMA Channel Status Register. +// ( (unsigned int)((DMA_CH_CH_CH0_ST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_ST = (DMA_CH_CH_CH0_ST & ~(0x5CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5C) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_CH_ST +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_IPEND +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_CTZ_ST +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_RLD_ST +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_BUS_ERR +// SFDITEM_FIELD__DMA_CH_CH_CH0_ST_TO_ST +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH0_SRC ---------------------------- +// SVD Line: 795 + +unsigned int DMA_CH_CH_CH0_SRC __AT (0x40028208); + + + +// --------------------------- Field Item: DMA_CH_CH_CH0_SRC_ADDR ------------------------------- +// SVD Line: 800 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_SRC_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x40028208) ADDR +// +// ( (unsigned int)((DMA_CH_CH_CH0_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_SRC = (DMA_CH_CH_CH0_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH0_SRC ------------------------------- +// SVD Line: 795 + +// SFDITEM_REG__DMA_CH_CH_CH0_SRC +// SRC +// +// [Bits 31..0] RW (@ 0x40028208) Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. +// ( (unsigned int)((DMA_CH_CH_CH0_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_SRC = (DMA_CH_CH_CH0_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH0_SRC_ADDR +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH0_DST ---------------------------- +// SVD Line: 807 + +unsigned int DMA_CH_CH_CH0_DST __AT (0x4002820C); + + + +// --------------------------- Field Item: DMA_CH_CH_CH0_DST_ADDR ------------------------------- +// SVD Line: 812 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_DST_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x4002820C) ADDR +// +// ( (unsigned int)((DMA_CH_CH_CH0_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_DST = (DMA_CH_CH_CH0_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH0_DST ------------------------------- +// SVD Line: 807 + +// SFDITEM_REG__DMA_CH_CH_CH0_DST +// DST +// +// [Bits 31..0] RW (@ 0x4002820C) Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. +// ( (unsigned int)((DMA_CH_CH_CH0_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_DST = (DMA_CH_CH_CH0_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH0_DST_ADDR +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH0_CNT ---------------------------- +// SVD Line: 819 + +unsigned int DMA_CH_CH_CH0_CNT __AT (0x40028210); + + + +// ---------------------------- Field Item: DMA_CH_CH_CH0_CNT_CNT ------------------------------- +// SVD Line: 824 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_CNT +// CNT +// +// [Bits 23..0] RW (@ 0x40028210) DMA Counter. +// +// ( (unsigned int)((DMA_CH_CH_CH0_CNT >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH0_CNT = (DMA_CH_CH_CH0_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH0_CNT ------------------------------- +// SVD Line: 819 + +// SFDITEM_REG__DMA_CH_CH_CH0_CNT +// CNT +// +// [Bits 31..0] RW (@ 0x40028210) DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. +// ( (unsigned int)((DMA_CH_CH_CH0_CNT >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_CNT = (DMA_CH_CH_CH0_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_CNT +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH0_SRC_RLD -------------------------- +// SVD Line: 832 + +unsigned int DMA_CH_CH_CH0_SRC_RLD __AT (0x40028214); + + + +// ------------------------ Field Item: DMA_CH_CH_CH0_SRC_RLD_SRC_RLD --------------------------- +// SVD Line: 837 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_SRC_RLD_SRC_RLD +// SRC_RLD +// +// [Bits 30..0] RW (@ 0x40028214) Source Address Reload Value. +// +// ( (unsigned int)((DMA_CH_CH_CH0_SRC_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH0_SRC_RLD = (DMA_CH_CH_CH0_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH0_SRC_RLD ----------------------------- +// SVD Line: 832 + +// SFDITEM_REG__DMA_CH_CH_CH0_SRC_RLD +// SRC_RLD +// +// [Bits 31..0] RW (@ 0x40028214) Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. +// ( (unsigned int)((DMA_CH_CH_CH0_SRC_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_SRC_RLD = (DMA_CH_CH_CH0_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH0_SRC_RLD_SRC_RLD +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH0_DST_RLD -------------------------- +// SVD Line: 845 + +unsigned int DMA_CH_CH_CH0_DST_RLD __AT (0x40028218); + + + +// ------------------------ Field Item: DMA_CH_CH_CH0_DST_RLD_DST_RLD --------------------------- +// SVD Line: 850 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_DST_RLD_DST_RLD +// DST_RLD +// +// [Bits 30..0] RW (@ 0x40028218) Destination Address Reload Value. +// +// ( (unsigned int)((DMA_CH_CH_CH0_DST_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH0_DST_RLD = (DMA_CH_CH_CH0_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH0_DST_RLD ----------------------------- +// SVD Line: 845 + +// SFDITEM_REG__DMA_CH_CH_CH0_DST_RLD +// DST_RLD +// +// [Bits 31..0] RW (@ 0x40028218) Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. +// ( (unsigned int)((DMA_CH_CH_CH0_DST_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_DST_RLD = (DMA_CH_CH_CH0_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH0_DST_RLD_DST_RLD +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH0_CNT_RLD -------------------------- +// SVD Line: 858 + +unsigned int DMA_CH_CH_CH0_CNT_RLD __AT (0x4002821C); + + + +// ------------------------ Field Item: DMA_CH_CH_CH0_CNT_RLD_CNT_RLD --------------------------- +// SVD Line: 863 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_RLD_CNT_RLD +// CNT_RLD +// +// [Bits 23..0] RW (@ 0x4002821C) Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. +// +// ( (unsigned int)((DMA_CH_CH_CH0_CNT_RLD >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH0_CNT_RLD = (DMA_CH_CH_CH0_CNT_RLD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------- Field Item: DMA_CH_CH_CH0_CNT_RLD_RLDEN ---------------------------- +// SVD Line: 869 + +// SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_RLD_RLDEN +// RLDEN +// +// [Bit 31] RW (@ 0x4002821C) \nReload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH0_CNT_RLD ) +// RLDEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH0_CNT_RLD ----------------------------- +// SVD Line: 858 + +// SFDITEM_REG__DMA_CH_CH_CH0_CNT_RLD +// CNT_RLD +// +// [Bits 31..0] RW (@ 0x4002821C) DMA Channel Count Reload Register. +// ( (unsigned int)((DMA_CH_CH_CH0_CNT_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH0_CNT_RLD = (DMA_CH_CH_CH0_CNT_RLD & ~(0x80FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80FFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_RLD_CNT_RLD +// SFDITEM_FIELD__DMA_CH_CH_CH0_CNT_RLD_RLDEN +// +// + + +// ------------------------------ Cluster ITree: DMA_CH_CH_CH0 ---------------------------------- +// SVD Line: 266 + +// SFDITEM_CLUST__DMA_CH_CH_CH0 +// [0] +// DMA Channel registers. +// SFDITEM_REG__DMA_CH_CH_CH0_CFG +// SFDITEM_REG__DMA_CH_CH_CH0_ST +// SFDITEM_REG__DMA_CH_CH_CH0_SRC +// SFDITEM_REG__DMA_CH_CH_CH0_DST +// SFDITEM_REG__DMA_CH_CH_CH0_CNT +// SFDITEM_REG__DMA_CH_CH_CH0_SRC_RLD +// SFDITEM_REG__DMA_CH_CH_CH0_DST_RLD +// SFDITEM_REG__DMA_CH_CH_CH0_CNT_RLD +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH1_CFG ---------------------------- +// SVD Line: 274 + +unsigned int DMA_CH_CH_CH1_CFG __AT (0x40028204); + + + +// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_CHEN ------------------------------- +// SVD Line: 279 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CHEN +// CHEN +// +// [Bit 0] RW (@ 0x40028204) \nChannel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// CHEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_RLDEN ------------------------------ +// SVD Line: 297 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_RLDEN +// RLDEN +// +// [Bit 1] RW (@ 0x40028204) \nReload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// RLDEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: DMA_CH_CH_CH1_CFG_PRI ------------------------------- +// SVD Line: 315 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_PRI +// PRI +// +// [Bits 3..2] RW (@ 0x40028204) \nDMA Priority.\n0 : high = Highest Priority.\n1 : medHigh = Medium High Priority.\n2 : medLow = Medium Low Priority.\n3 : low = Lowest Priority. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// PRI +// <0=> 0: high = Highest Priority. +// <1=> 1: medHigh = Medium High Priority. +// <2=> 2: medLow = Medium Low Priority. +// <3=> 3: low = Lowest Priority. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_REQSEL ------------------------------ +// SVD Line: 343 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_REQSEL +// REQSEL +// +// [Bits 9..4] RW (@ 0x40028204) \nRequest Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n0 : MEMTOMEM = Memory To Memory\n1 : SPI0RX = SPI0 RX\n2 : SPI1RX = SPI1 RX\n3 : Reserved - do not use\n4 : UART0RX = UART0 RX\n5 : UART1RX = UART1 RX\n6 : Reserved - do not use\n7 : I2C0RX = I2C0 RX\n8 : I2C1RX = I2C1 RX\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : SPI0TX = SPI0 TX\n34 : SPI1TX = SPI1 TX\n35 : Reserved - do not use\n36 : UART0TX = UART0 TX\n37 : UART1TX = UART1 TX\n38 : Reserved - do not use\n39 : I2C0TX = I2C0 TX\n40 : I2C1TX = I2C1 TX\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// REQSEL +// <0=> 0: MEMTOMEM = Memory To Memory +// <1=> 1: SPI0RX = SPI0 RX +// <2=> 2: SPI1RX = SPI1 RX +// <3=> 3: +// <4=> 4: UART0RX = UART0 RX +// <5=> 5: UART1RX = UART1 RX +// <6=> 6: +// <7=> 7: I2C0RX = I2C0 RX +// <8=> 8: I2C1RX = I2C1 RX +// <9=> 9: +// <10=> 10: +// <11=> 11: +// <12=> 12: +// <13=> 13: +// <14=> 14: +// <15=> 15: +// <16=> 16: +// <17=> 17: +// <18=> 18: +// <19=> 19: +// <20=> 20: +// <21=> 21: +// <22=> 22: +// <23=> 23: +// <24=> 24: +// <25=> 25: +// <26=> 26: +// <27=> 27: +// <28=> 28: +// <29=> 29: +// <30=> 30: +// <31=> 31: +// <32=> 32: +// <33=> 33: SPI0TX = SPI0 TX +// <34=> 34: SPI1TX = SPI1 TX +// <35=> 35: +// <36=> 36: UART0TX = UART0 TX +// <37=> 37: UART1TX = UART1 TX +// <38=> 38: +// <39=> 39: I2C0TX = I2C0 TX +// <40=> 40: I2C1TX = I2C1 TX +// <41=> 41: +// <42=> 42: +// <43=> 43: +// <44=> 44: +// <45=> 45: +// <46=> 46: +// <47=> 47: +// <48=> 48: +// <49=> 49: +// <50=> 50: +// <51=> 51: +// <52=> 52: +// <53=> 53: +// <54=> 54: +// <55=> 55: +// <56=> 56: +// <57=> 57: +// <58=> 58: +// <59=> 59: +// <60=> 60: +// <61=> 61: +// <62=> 62: +// <63=> 63: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_REQWAIT ----------------------------- +// SVD Line: 416 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_REQWAIT +// REQWAIT +// +// [Bit 10] RW (@ 0x40028204) \nRequest Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// REQWAIT +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_TOSEL ------------------------------ +// SVD Line: 434 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_TOSEL +// TOSEL +// +// [Bits 13..11] RW (@ 0x40028204) \nTime-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.\n0 : to4 = Timeout of 3 to 4 prescale clocks.\n1 : to8 = Timeout of 7 to 8 prescale clocks.\n2 : to16 = Timeout of 15 to 16 prescale clocks.\n3 : to32 = Timeout of 31 to 32 prescale clocks.\n4 : to64 = Timeout of 63 to 64 prescale clocks.\n5 : to128 = Timeout of 127 to 128 prescale clocks.\n6 : to256 = Timeout of 255 to 256 prescale clocks.\n7 : to512 = Timeout of 511 to 512 prescale clocks. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// TOSEL +// <0=> 0: to4 = Timeout of 3 to 4 prescale clocks. +// <1=> 1: to8 = Timeout of 7 to 8 prescale clocks. +// <2=> 2: to16 = Timeout of 15 to 16 prescale clocks. +// <3=> 3: to32 = Timeout of 31 to 32 prescale clocks. +// <4=> 4: to64 = Timeout of 63 to 64 prescale clocks. +// <5=> 5: to128 = Timeout of 127 to 128 prescale clocks. +// <6=> 6: to256 = Timeout of 255 to 256 prescale clocks. +// <7=> 7: to512 = Timeout of 511 to 512 prescale clocks. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_PSSEL ------------------------------ +// SVD Line: 482 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_PSSEL +// PSSEL +// +// [Bits 15..14] RW (@ 0x40028204) \nPre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n0 : dis = Disable timer.\n1 : div256 = hclk / 256.\n2 : div64k = hclk / 64k.\n3 : div16M = hclk / 16M. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// PSSEL +// <0=> 0: dis = Disable timer. +// <1=> 1: div256 = hclk / 256. +// <2=> 2: div64k = hclk / 64k. +// <3=> 3: div16M = hclk / 16M. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_SRCWD ------------------------------ +// SVD Line: 510 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_SRCWD +// SRCWD +// +// [Bits 17..16] RW (@ 0x40028204) \nSource Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// SRCWD +// <0=> 0: byte = Byte. +// <1=> 1: halfWord = Halfword. +// <2=> 2: word = Word. +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_SRCINC ------------------------------ +// SVD Line: 533 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_SRCINC +// SRCINC +// +// [Bit 18] RW (@ 0x40028204) \nSource Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// SRCINC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_DSTWD ------------------------------ +// SVD Line: 551 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_DSTWD +// DSTWD +// +// [Bits 21..20] RW (@ 0x40028204) \nDestination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// DSTWD +// <0=> 0: byte = Byte. +// <1=> 1: halfWord = Halfword. +// <2=> 2: word = Word. +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_DSTINC ------------------------------ +// SVD Line: 574 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_DSTINC +// DSTINC +// +// [Bit 22] RW (@ 0x40028204) \nDestination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// DSTINC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_CFG_BRST ------------------------------- +// SVD Line: 592 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_BRST +// BRST +// +// [Bits 28..24] RW (@ 0x40028204) Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. +// +// ( (unsigned char)((DMA_CH_CH_CH1_CFG >> 24) & 0x1F), ((DMA_CH_CH_CH1_CFG = (DMA_CH_CH_CH1_CFG & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) )) +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_CHDIEN ------------------------------ +// SVD Line: 598 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CHDIEN +// CHDIEN +// +// [Bit 30] RW (@ 0x40028204) \nChannel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// CHDIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH1_CFG_CTZIEN ------------------------------ +// SVD Line: 616 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CTZIEN +// CTZIEN +// +// [Bit 31] RW (@ 0x40028204) \nCount-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_CFG ) +// CTZIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH1_CFG ------------------------------- +// SVD Line: 274 + +// SFDITEM_REG__DMA_CH_CH_CH1_CFG +// CFG +// +// [Bits 31..0] RW (@ 0x40028204) DMA Channel Configuration Register. +// ( (unsigned int)((DMA_CH_CH_CH1_CFG >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_CFG = (DMA_CH_CH_CH1_CFG & ~(0xDF77FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF77FFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CHEN +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_RLDEN +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_PRI +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_REQSEL +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_REQWAIT +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_TOSEL +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_PSSEL +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_SRCWD +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_SRCINC +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_DSTWD +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_DSTINC +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_BRST +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CHDIEN +// SFDITEM_FIELD__DMA_CH_CH_CH1_CFG_CTZIEN +// +// + + +// ------------------------- Register Item Address: DMA_CH_CH_CH1_ST ---------------------------- +// SVD Line: 636 + +unsigned int DMA_CH_CH_CH1_ST __AT (0x40028208); + + + +// --------------------------- Field Item: DMA_CH_CH_CH1_ST_CH_ST ------------------------------- +// SVD Line: 641 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_CH_ST +// CH_ST +// +// [Bit 0] RO (@ 0x40028208) \nChannel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_ST ) +// CH_ST +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_ST_IPEND ------------------------------- +// SVD Line: 660 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_IPEND +// IPEND +// +// [Bit 1] RO (@ 0x40028208) \nChannel Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) DMA_CH_CH_CH1_ST ) +// IPEND +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_ST_CTZ_ST ------------------------------ +// SVD Line: 679 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_CTZ_ST +// CTZ_ST +// +// [Bit 2] RW (@ 0x40028208) \nCount-to-Zero (CTZ) Status\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH1_ST ) +// CTZ_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_ST_RLD_ST ------------------------------ +// SVD Line: 709 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_RLD_ST +// RLD_ST +// +// [Bit 3] RW (@ 0x40028208) \nReload Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH1_ST ) +// RLD_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH1_ST_BUS_ERR ------------------------------ +// SVD Line: 737 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_BUS_ERR +// BUS_ERR +// +// [Bit 4] RW (@ 0x40028208) \nBus Error. Indicates that an AHB abort was received and the channel has been disabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH1_ST ) +// BUS_ERR +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH1_ST_TO_ST ------------------------------- +// SVD Line: 765 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_TO_ST +// TO_ST +// +// [Bit 6] RW (@ 0x40028208) \nTime-Out Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH1_ST ) +// TO_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH1_ST -------------------------------- +// SVD Line: 636 + +// SFDITEM_REG__DMA_CH_CH_CH1_ST +// ST +// +// [Bits 31..0] RW (@ 0x40028208) DMA Channel Status Register. +// ( (unsigned int)((DMA_CH_CH_CH1_ST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_ST = (DMA_CH_CH_CH1_ST & ~(0x5CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5C) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_CH_ST +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_IPEND +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_CTZ_ST +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_RLD_ST +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_BUS_ERR +// SFDITEM_FIELD__DMA_CH_CH_CH1_ST_TO_ST +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH1_SRC ---------------------------- +// SVD Line: 795 + +unsigned int DMA_CH_CH_CH1_SRC __AT (0x4002820C); + + + +// --------------------------- Field Item: DMA_CH_CH_CH1_SRC_ADDR ------------------------------- +// SVD Line: 800 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_SRC_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x4002820C) ADDR +// +// ( (unsigned int)((DMA_CH_CH_CH1_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_SRC = (DMA_CH_CH_CH1_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH1_SRC ------------------------------- +// SVD Line: 795 + +// SFDITEM_REG__DMA_CH_CH_CH1_SRC +// SRC +// +// [Bits 31..0] RW (@ 0x4002820C) Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. +// ( (unsigned int)((DMA_CH_CH_CH1_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_SRC = (DMA_CH_CH_CH1_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH1_SRC_ADDR +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH1_DST ---------------------------- +// SVD Line: 807 + +unsigned int DMA_CH_CH_CH1_DST __AT (0x40028210); + + + +// --------------------------- Field Item: DMA_CH_CH_CH1_DST_ADDR ------------------------------- +// SVD Line: 812 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_DST_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x40028210) ADDR +// +// ( (unsigned int)((DMA_CH_CH_CH1_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_DST = (DMA_CH_CH_CH1_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH1_DST ------------------------------- +// SVD Line: 807 + +// SFDITEM_REG__DMA_CH_CH_CH1_DST +// DST +// +// [Bits 31..0] RW (@ 0x40028210) Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. +// ( (unsigned int)((DMA_CH_CH_CH1_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_DST = (DMA_CH_CH_CH1_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH1_DST_ADDR +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH1_CNT ---------------------------- +// SVD Line: 819 + +unsigned int DMA_CH_CH_CH1_CNT __AT (0x40028214); + + + +// ---------------------------- Field Item: DMA_CH_CH_CH1_CNT_CNT ------------------------------- +// SVD Line: 824 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_CNT +// CNT +// +// [Bits 23..0] RW (@ 0x40028214) DMA Counter. +// +// ( (unsigned int)((DMA_CH_CH_CH1_CNT >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH1_CNT = (DMA_CH_CH_CH1_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH1_CNT ------------------------------- +// SVD Line: 819 + +// SFDITEM_REG__DMA_CH_CH_CH1_CNT +// CNT +// +// [Bits 31..0] RW (@ 0x40028214) DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. +// ( (unsigned int)((DMA_CH_CH_CH1_CNT >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_CNT = (DMA_CH_CH_CH1_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_CNT +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH1_SRC_RLD -------------------------- +// SVD Line: 832 + +unsigned int DMA_CH_CH_CH1_SRC_RLD __AT (0x40028218); + + + +// ------------------------ Field Item: DMA_CH_CH_CH1_SRC_RLD_SRC_RLD --------------------------- +// SVD Line: 837 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_SRC_RLD_SRC_RLD +// SRC_RLD +// +// [Bits 30..0] RW (@ 0x40028218) Source Address Reload Value. +// +// ( (unsigned int)((DMA_CH_CH_CH1_SRC_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH1_SRC_RLD = (DMA_CH_CH_CH1_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH1_SRC_RLD ----------------------------- +// SVD Line: 832 + +// SFDITEM_REG__DMA_CH_CH_CH1_SRC_RLD +// SRC_RLD +// +// [Bits 31..0] RW (@ 0x40028218) Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. +// ( (unsigned int)((DMA_CH_CH_CH1_SRC_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_SRC_RLD = (DMA_CH_CH_CH1_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH1_SRC_RLD_SRC_RLD +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH1_DST_RLD -------------------------- +// SVD Line: 845 + +unsigned int DMA_CH_CH_CH1_DST_RLD __AT (0x4002821C); + + + +// ------------------------ Field Item: DMA_CH_CH_CH1_DST_RLD_DST_RLD --------------------------- +// SVD Line: 850 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_DST_RLD_DST_RLD +// DST_RLD +// +// [Bits 30..0] RW (@ 0x4002821C) Destination Address Reload Value. +// +// ( (unsigned int)((DMA_CH_CH_CH1_DST_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH1_DST_RLD = (DMA_CH_CH_CH1_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH1_DST_RLD ----------------------------- +// SVD Line: 845 + +// SFDITEM_REG__DMA_CH_CH_CH1_DST_RLD +// DST_RLD +// +// [Bits 31..0] RW (@ 0x4002821C) Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. +// ( (unsigned int)((DMA_CH_CH_CH1_DST_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_DST_RLD = (DMA_CH_CH_CH1_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH1_DST_RLD_DST_RLD +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH1_CNT_RLD -------------------------- +// SVD Line: 858 + +unsigned int DMA_CH_CH_CH1_CNT_RLD __AT (0x40028220); + + + +// ------------------------ Field Item: DMA_CH_CH_CH1_CNT_RLD_CNT_RLD --------------------------- +// SVD Line: 863 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_RLD_CNT_RLD +// CNT_RLD +// +// [Bits 23..0] RW (@ 0x40028220) Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. +// +// ( (unsigned int)((DMA_CH_CH_CH1_CNT_RLD >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH1_CNT_RLD = (DMA_CH_CH_CH1_CNT_RLD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------- Field Item: DMA_CH_CH_CH1_CNT_RLD_RLDEN ---------------------------- +// SVD Line: 869 + +// SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_RLD_RLDEN +// RLDEN +// +// [Bit 31] RW (@ 0x40028220) \nReload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH1_CNT_RLD ) +// RLDEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH1_CNT_RLD ----------------------------- +// SVD Line: 858 + +// SFDITEM_REG__DMA_CH_CH_CH1_CNT_RLD +// CNT_RLD +// +// [Bits 31..0] RW (@ 0x40028220) DMA Channel Count Reload Register. +// ( (unsigned int)((DMA_CH_CH_CH1_CNT_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH1_CNT_RLD = (DMA_CH_CH_CH1_CNT_RLD & ~(0x80FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80FFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_RLD_CNT_RLD +// SFDITEM_FIELD__DMA_CH_CH_CH1_CNT_RLD_RLDEN +// +// + + +// ------------------------------ Cluster ITree: DMA_CH_CH_CH1 ---------------------------------- +// SVD Line: 266 + +// SFDITEM_CLUST__DMA_CH_CH_CH1 +// [1] +// DMA Channel registers. +// SFDITEM_REG__DMA_CH_CH_CH1_CFG +// SFDITEM_REG__DMA_CH_CH_CH1_ST +// SFDITEM_REG__DMA_CH_CH_CH1_SRC +// SFDITEM_REG__DMA_CH_CH_CH1_DST +// SFDITEM_REG__DMA_CH_CH_CH1_CNT +// SFDITEM_REG__DMA_CH_CH_CH1_SRC_RLD +// SFDITEM_REG__DMA_CH_CH_CH1_DST_RLD +// SFDITEM_REG__DMA_CH_CH_CH1_CNT_RLD +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH2_CFG ---------------------------- +// SVD Line: 274 + +unsigned int DMA_CH_CH_CH2_CFG __AT (0x40028208); + + + +// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_CHEN ------------------------------- +// SVD Line: 279 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CHEN +// CHEN +// +// [Bit 0] RW (@ 0x40028208) \nChannel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// CHEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_RLDEN ------------------------------ +// SVD Line: 297 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_RLDEN +// RLDEN +// +// [Bit 1] RW (@ 0x40028208) \nReload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// RLDEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: DMA_CH_CH_CH2_CFG_PRI ------------------------------- +// SVD Line: 315 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_PRI +// PRI +// +// [Bits 3..2] RW (@ 0x40028208) \nDMA Priority.\n0 : high = Highest Priority.\n1 : medHigh = Medium High Priority.\n2 : medLow = Medium Low Priority.\n3 : low = Lowest Priority. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// PRI +// <0=> 0: high = Highest Priority. +// <1=> 1: medHigh = Medium High Priority. +// <2=> 2: medLow = Medium Low Priority. +// <3=> 3: low = Lowest Priority. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_REQSEL ------------------------------ +// SVD Line: 343 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_REQSEL +// REQSEL +// +// [Bits 9..4] RW (@ 0x40028208) \nRequest Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n0 : MEMTOMEM = Memory To Memory\n1 : SPI0RX = SPI0 RX\n2 : SPI1RX = SPI1 RX\n3 : Reserved - do not use\n4 : UART0RX = UART0 RX\n5 : UART1RX = UART1 RX\n6 : Reserved - do not use\n7 : I2C0RX = I2C0 RX\n8 : I2C1RX = I2C1 RX\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : SPI0TX = SPI0 TX\n34 : SPI1TX = SPI1 TX\n35 : Reserved - do not use\n36 : UART0TX = UART0 TX\n37 : UART1TX = UART1 TX\n38 : Reserved - do not use\n39 : I2C0TX = I2C0 TX\n40 : I2C1TX = I2C1 TX\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// REQSEL +// <0=> 0: MEMTOMEM = Memory To Memory +// <1=> 1: SPI0RX = SPI0 RX +// <2=> 2: SPI1RX = SPI1 RX +// <3=> 3: +// <4=> 4: UART0RX = UART0 RX +// <5=> 5: UART1RX = UART1 RX +// <6=> 6: +// <7=> 7: I2C0RX = I2C0 RX +// <8=> 8: I2C1RX = I2C1 RX +// <9=> 9: +// <10=> 10: +// <11=> 11: +// <12=> 12: +// <13=> 13: +// <14=> 14: +// <15=> 15: +// <16=> 16: +// <17=> 17: +// <18=> 18: +// <19=> 19: +// <20=> 20: +// <21=> 21: +// <22=> 22: +// <23=> 23: +// <24=> 24: +// <25=> 25: +// <26=> 26: +// <27=> 27: +// <28=> 28: +// <29=> 29: +// <30=> 30: +// <31=> 31: +// <32=> 32: +// <33=> 33: SPI0TX = SPI0 TX +// <34=> 34: SPI1TX = SPI1 TX +// <35=> 35: +// <36=> 36: UART0TX = UART0 TX +// <37=> 37: UART1TX = UART1 TX +// <38=> 38: +// <39=> 39: I2C0TX = I2C0 TX +// <40=> 40: I2C1TX = I2C1 TX +// <41=> 41: +// <42=> 42: +// <43=> 43: +// <44=> 44: +// <45=> 45: +// <46=> 46: +// <47=> 47: +// <48=> 48: +// <49=> 49: +// <50=> 50: +// <51=> 51: +// <52=> 52: +// <53=> 53: +// <54=> 54: +// <55=> 55: +// <56=> 56: +// <57=> 57: +// <58=> 58: +// <59=> 59: +// <60=> 60: +// <61=> 61: +// <62=> 62: +// <63=> 63: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_REQWAIT ----------------------------- +// SVD Line: 416 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_REQWAIT +// REQWAIT +// +// [Bit 10] RW (@ 0x40028208) \nRequest Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// REQWAIT +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_TOSEL ------------------------------ +// SVD Line: 434 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_TOSEL +// TOSEL +// +// [Bits 13..11] RW (@ 0x40028208) \nTime-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.\n0 : to4 = Timeout of 3 to 4 prescale clocks.\n1 : to8 = Timeout of 7 to 8 prescale clocks.\n2 : to16 = Timeout of 15 to 16 prescale clocks.\n3 : to32 = Timeout of 31 to 32 prescale clocks.\n4 : to64 = Timeout of 63 to 64 prescale clocks.\n5 : to128 = Timeout of 127 to 128 prescale clocks.\n6 : to256 = Timeout of 255 to 256 prescale clocks.\n7 : to512 = Timeout of 511 to 512 prescale clocks. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// TOSEL +// <0=> 0: to4 = Timeout of 3 to 4 prescale clocks. +// <1=> 1: to8 = Timeout of 7 to 8 prescale clocks. +// <2=> 2: to16 = Timeout of 15 to 16 prescale clocks. +// <3=> 3: to32 = Timeout of 31 to 32 prescale clocks. +// <4=> 4: to64 = Timeout of 63 to 64 prescale clocks. +// <5=> 5: to128 = Timeout of 127 to 128 prescale clocks. +// <6=> 6: to256 = Timeout of 255 to 256 prescale clocks. +// <7=> 7: to512 = Timeout of 511 to 512 prescale clocks. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_PSSEL ------------------------------ +// SVD Line: 482 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_PSSEL +// PSSEL +// +// [Bits 15..14] RW (@ 0x40028208) \nPre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n0 : dis = Disable timer.\n1 : div256 = hclk / 256.\n2 : div64k = hclk / 64k.\n3 : div16M = hclk / 16M. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// PSSEL +// <0=> 0: dis = Disable timer. +// <1=> 1: div256 = hclk / 256. +// <2=> 2: div64k = hclk / 64k. +// <3=> 3: div16M = hclk / 16M. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_SRCWD ------------------------------ +// SVD Line: 510 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_SRCWD +// SRCWD +// +// [Bits 17..16] RW (@ 0x40028208) \nSource Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// SRCWD +// <0=> 0: byte = Byte. +// <1=> 1: halfWord = Halfword. +// <2=> 2: word = Word. +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_SRCINC ------------------------------ +// SVD Line: 533 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_SRCINC +// SRCINC +// +// [Bit 18] RW (@ 0x40028208) \nSource Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// SRCINC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_DSTWD ------------------------------ +// SVD Line: 551 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_DSTWD +// DSTWD +// +// [Bits 21..20] RW (@ 0x40028208) \nDestination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// DSTWD +// <0=> 0: byte = Byte. +// <1=> 1: halfWord = Halfword. +// <2=> 2: word = Word. +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_DSTINC ------------------------------ +// SVD Line: 574 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_DSTINC +// DSTINC +// +// [Bit 22] RW (@ 0x40028208) \nDestination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// DSTINC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_CFG_BRST ------------------------------- +// SVD Line: 592 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_BRST +// BRST +// +// [Bits 28..24] RW (@ 0x40028208) Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. +// +// ( (unsigned char)((DMA_CH_CH_CH2_CFG >> 24) & 0x1F), ((DMA_CH_CH_CH2_CFG = (DMA_CH_CH_CH2_CFG & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) )) +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_CHDIEN ------------------------------ +// SVD Line: 598 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CHDIEN +// CHDIEN +// +// [Bit 30] RW (@ 0x40028208) \nChannel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// CHDIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH2_CFG_CTZIEN ------------------------------ +// SVD Line: 616 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CTZIEN +// CTZIEN +// +// [Bit 31] RW (@ 0x40028208) \nCount-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_CFG ) +// CTZIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH2_CFG ------------------------------- +// SVD Line: 274 + +// SFDITEM_REG__DMA_CH_CH_CH2_CFG +// CFG +// +// [Bits 31..0] RW (@ 0x40028208) DMA Channel Configuration Register. +// ( (unsigned int)((DMA_CH_CH_CH2_CFG >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_CFG = (DMA_CH_CH_CH2_CFG & ~(0xDF77FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF77FFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CHEN +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_RLDEN +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_PRI +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_REQSEL +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_REQWAIT +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_TOSEL +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_PSSEL +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_SRCWD +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_SRCINC +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_DSTWD +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_DSTINC +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_BRST +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CHDIEN +// SFDITEM_FIELD__DMA_CH_CH_CH2_CFG_CTZIEN +// +// + + +// ------------------------- Register Item Address: DMA_CH_CH_CH2_ST ---------------------------- +// SVD Line: 636 + +unsigned int DMA_CH_CH_CH2_ST __AT (0x4002820C); + + + +// --------------------------- Field Item: DMA_CH_CH_CH2_ST_CH_ST ------------------------------- +// SVD Line: 641 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_CH_ST +// CH_ST +// +// [Bit 0] RO (@ 0x4002820C) \nChannel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_ST ) +// CH_ST +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_ST_IPEND ------------------------------- +// SVD Line: 660 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_IPEND +// IPEND +// +// [Bit 1] RO (@ 0x4002820C) \nChannel Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) DMA_CH_CH_CH2_ST ) +// IPEND +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_ST_CTZ_ST ------------------------------ +// SVD Line: 679 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_CTZ_ST +// CTZ_ST +// +// [Bit 2] RW (@ 0x4002820C) \nCount-to-Zero (CTZ) Status\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH2_ST ) +// CTZ_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_ST_RLD_ST ------------------------------ +// SVD Line: 709 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_RLD_ST +// RLD_ST +// +// [Bit 3] RW (@ 0x4002820C) \nReload Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH2_ST ) +// RLD_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH2_ST_BUS_ERR ------------------------------ +// SVD Line: 737 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_BUS_ERR +// BUS_ERR +// +// [Bit 4] RW (@ 0x4002820C) \nBus Error. Indicates that an AHB abort was received and the channel has been disabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH2_ST ) +// BUS_ERR +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH2_ST_TO_ST ------------------------------- +// SVD Line: 765 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_TO_ST +// TO_ST +// +// [Bit 6] RW (@ 0x4002820C) \nTime-Out Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH2_ST ) +// TO_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH2_ST -------------------------------- +// SVD Line: 636 + +// SFDITEM_REG__DMA_CH_CH_CH2_ST +// ST +// +// [Bits 31..0] RW (@ 0x4002820C) DMA Channel Status Register. +// ( (unsigned int)((DMA_CH_CH_CH2_ST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_ST = (DMA_CH_CH_CH2_ST & ~(0x5CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5C) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_CH_ST +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_IPEND +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_CTZ_ST +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_RLD_ST +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_BUS_ERR +// SFDITEM_FIELD__DMA_CH_CH_CH2_ST_TO_ST +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH2_SRC ---------------------------- +// SVD Line: 795 + +unsigned int DMA_CH_CH_CH2_SRC __AT (0x40028210); + + + +// --------------------------- Field Item: DMA_CH_CH_CH2_SRC_ADDR ------------------------------- +// SVD Line: 800 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_SRC_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x40028210) ADDR +// +// ( (unsigned int)((DMA_CH_CH_CH2_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_SRC = (DMA_CH_CH_CH2_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH2_SRC ------------------------------- +// SVD Line: 795 + +// SFDITEM_REG__DMA_CH_CH_CH2_SRC +// SRC +// +// [Bits 31..0] RW (@ 0x40028210) Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. +// ( (unsigned int)((DMA_CH_CH_CH2_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_SRC = (DMA_CH_CH_CH2_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH2_SRC_ADDR +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH2_DST ---------------------------- +// SVD Line: 807 + +unsigned int DMA_CH_CH_CH2_DST __AT (0x40028214); + + + +// --------------------------- Field Item: DMA_CH_CH_CH2_DST_ADDR ------------------------------- +// SVD Line: 812 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_DST_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x40028214) ADDR +// +// ( (unsigned int)((DMA_CH_CH_CH2_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_DST = (DMA_CH_CH_CH2_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH2_DST ------------------------------- +// SVD Line: 807 + +// SFDITEM_REG__DMA_CH_CH_CH2_DST +// DST +// +// [Bits 31..0] RW (@ 0x40028214) Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. +// ( (unsigned int)((DMA_CH_CH_CH2_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_DST = (DMA_CH_CH_CH2_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH2_DST_ADDR +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH2_CNT ---------------------------- +// SVD Line: 819 + +unsigned int DMA_CH_CH_CH2_CNT __AT (0x40028218); + + + +// ---------------------------- Field Item: DMA_CH_CH_CH2_CNT_CNT ------------------------------- +// SVD Line: 824 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_CNT +// CNT +// +// [Bits 23..0] RW (@ 0x40028218) DMA Counter. +// +// ( (unsigned int)((DMA_CH_CH_CH2_CNT >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH2_CNT = (DMA_CH_CH_CH2_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH2_CNT ------------------------------- +// SVD Line: 819 + +// SFDITEM_REG__DMA_CH_CH_CH2_CNT +// CNT +// +// [Bits 31..0] RW (@ 0x40028218) DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. +// ( (unsigned int)((DMA_CH_CH_CH2_CNT >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_CNT = (DMA_CH_CH_CH2_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_CNT +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH2_SRC_RLD -------------------------- +// SVD Line: 832 + +unsigned int DMA_CH_CH_CH2_SRC_RLD __AT (0x4002821C); + + + +// ------------------------ Field Item: DMA_CH_CH_CH2_SRC_RLD_SRC_RLD --------------------------- +// SVD Line: 837 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_SRC_RLD_SRC_RLD +// SRC_RLD +// +// [Bits 30..0] RW (@ 0x4002821C) Source Address Reload Value. +// +// ( (unsigned int)((DMA_CH_CH_CH2_SRC_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH2_SRC_RLD = (DMA_CH_CH_CH2_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH2_SRC_RLD ----------------------------- +// SVD Line: 832 + +// SFDITEM_REG__DMA_CH_CH_CH2_SRC_RLD +// SRC_RLD +// +// [Bits 31..0] RW (@ 0x4002821C) Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. +// ( (unsigned int)((DMA_CH_CH_CH2_SRC_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_SRC_RLD = (DMA_CH_CH_CH2_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH2_SRC_RLD_SRC_RLD +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH2_DST_RLD -------------------------- +// SVD Line: 845 + +unsigned int DMA_CH_CH_CH2_DST_RLD __AT (0x40028220); + + + +// ------------------------ Field Item: DMA_CH_CH_CH2_DST_RLD_DST_RLD --------------------------- +// SVD Line: 850 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_DST_RLD_DST_RLD +// DST_RLD +// +// [Bits 30..0] RW (@ 0x40028220) Destination Address Reload Value. +// +// ( (unsigned int)((DMA_CH_CH_CH2_DST_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH2_DST_RLD = (DMA_CH_CH_CH2_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH2_DST_RLD ----------------------------- +// SVD Line: 845 + +// SFDITEM_REG__DMA_CH_CH_CH2_DST_RLD +// DST_RLD +// +// [Bits 31..0] RW (@ 0x40028220) Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. +// ( (unsigned int)((DMA_CH_CH_CH2_DST_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_DST_RLD = (DMA_CH_CH_CH2_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH2_DST_RLD_DST_RLD +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH2_CNT_RLD -------------------------- +// SVD Line: 858 + +unsigned int DMA_CH_CH_CH2_CNT_RLD __AT (0x40028224); + + + +// ------------------------ Field Item: DMA_CH_CH_CH2_CNT_RLD_CNT_RLD --------------------------- +// SVD Line: 863 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_RLD_CNT_RLD +// CNT_RLD +// +// [Bits 23..0] RW (@ 0x40028224) Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. +// +// ( (unsigned int)((DMA_CH_CH_CH2_CNT_RLD >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH2_CNT_RLD = (DMA_CH_CH_CH2_CNT_RLD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------- Field Item: DMA_CH_CH_CH2_CNT_RLD_RLDEN ---------------------------- +// SVD Line: 869 + +// SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_RLD_RLDEN +// RLDEN +// +// [Bit 31] RW (@ 0x40028224) \nReload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH2_CNT_RLD ) +// RLDEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH2_CNT_RLD ----------------------------- +// SVD Line: 858 + +// SFDITEM_REG__DMA_CH_CH_CH2_CNT_RLD +// CNT_RLD +// +// [Bits 31..0] RW (@ 0x40028224) DMA Channel Count Reload Register. +// ( (unsigned int)((DMA_CH_CH_CH2_CNT_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH2_CNT_RLD = (DMA_CH_CH_CH2_CNT_RLD & ~(0x80FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80FFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_RLD_CNT_RLD +// SFDITEM_FIELD__DMA_CH_CH_CH2_CNT_RLD_RLDEN +// +// + + +// ------------------------------ Cluster ITree: DMA_CH_CH_CH2 ---------------------------------- +// SVD Line: 266 + +// SFDITEM_CLUST__DMA_CH_CH_CH2 +// [2] +// DMA Channel registers. +// SFDITEM_REG__DMA_CH_CH_CH2_CFG +// SFDITEM_REG__DMA_CH_CH_CH2_ST +// SFDITEM_REG__DMA_CH_CH_CH2_SRC +// SFDITEM_REG__DMA_CH_CH_CH2_DST +// SFDITEM_REG__DMA_CH_CH_CH2_CNT +// SFDITEM_REG__DMA_CH_CH_CH2_SRC_RLD +// SFDITEM_REG__DMA_CH_CH_CH2_DST_RLD +// SFDITEM_REG__DMA_CH_CH_CH2_CNT_RLD +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH3_CFG ---------------------------- +// SVD Line: 274 + +unsigned int DMA_CH_CH_CH3_CFG __AT (0x4002820C); + + + +// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_CHEN ------------------------------- +// SVD Line: 279 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CHEN +// CHEN +// +// [Bit 0] RW (@ 0x4002820C) \nChannel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// CHEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_RLDEN ------------------------------ +// SVD Line: 297 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_RLDEN +// RLDEN +// +// [Bit 1] RW (@ 0x4002820C) \nReload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// RLDEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: DMA_CH_CH_CH3_CFG_PRI ------------------------------- +// SVD Line: 315 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_PRI +// PRI +// +// [Bits 3..2] RW (@ 0x4002820C) \nDMA Priority.\n0 : high = Highest Priority.\n1 : medHigh = Medium High Priority.\n2 : medLow = Medium Low Priority.\n3 : low = Lowest Priority. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// PRI +// <0=> 0: high = Highest Priority. +// <1=> 1: medHigh = Medium High Priority. +// <2=> 2: medLow = Medium Low Priority. +// <3=> 3: low = Lowest Priority. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_REQSEL ------------------------------ +// SVD Line: 343 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_REQSEL +// REQSEL +// +// [Bits 9..4] RW (@ 0x4002820C) \nRequest Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n0 : MEMTOMEM = Memory To Memory\n1 : SPI0RX = SPI0 RX\n2 : SPI1RX = SPI1 RX\n3 : Reserved - do not use\n4 : UART0RX = UART0 RX\n5 : UART1RX = UART1 RX\n6 : Reserved - do not use\n7 : I2C0RX = I2C0 RX\n8 : I2C1RX = I2C1 RX\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use\n16 : Reserved - do not use\n17 : Reserved - do not use\n18 : Reserved - do not use\n19 : Reserved - do not use\n20 : Reserved - do not use\n21 : Reserved - do not use\n22 : Reserved - do not use\n23 : Reserved - do not use\n24 : Reserved - do not use\n25 : Reserved - do not use\n26 : Reserved - do not use\n27 : Reserved - do not use\n28 : Reserved - do not use\n29 : Reserved - do not use\n30 : Reserved - do not use\n31 : Reserved - do not use\n32 : Reserved - do not use\n33 : SPI0TX = SPI0 TX\n34 : SPI1TX = SPI1 TX\n35 : Reserved - do not use\n36 : UART0TX = UART0 TX\n37 : UART1TX = UART1 TX\n38 : Reserved - do not use\n39 : I2C0TX = I2C0 TX\n40 : I2C1TX = I2C1 TX\n41 : Reserved - do not use\n42 : Reserved - do not use\n43 : Reserved - do not use\n44 : Reserved - do not use\n45 : Reserved - do not use\n46 : Reserved - do not use\n47 : Reserved - do not use\n48 : Reserved - do not use\n49 : Reserved - do not use\n50 : Reserved - do not use\n51 : Reserved - do not use\n52 : Reserved - do not use\n53 : Reserved - do not use\n54 : Reserved - do not use\n55 : Reserved - do not use\n56 : Reserved - do not use\n57 : Reserved - do not use\n58 : Reserved - do not use\n59 : Reserved - do not use\n60 : Reserved - do not use\n61 : Reserved - do not use\n62 : Reserved - do not use\n63 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// REQSEL +// <0=> 0: MEMTOMEM = Memory To Memory +// <1=> 1: SPI0RX = SPI0 RX +// <2=> 2: SPI1RX = SPI1 RX +// <3=> 3: +// <4=> 4: UART0RX = UART0 RX +// <5=> 5: UART1RX = UART1 RX +// <6=> 6: +// <7=> 7: I2C0RX = I2C0 RX +// <8=> 8: I2C1RX = I2C1 RX +// <9=> 9: +// <10=> 10: +// <11=> 11: +// <12=> 12: +// <13=> 13: +// <14=> 14: +// <15=> 15: +// <16=> 16: +// <17=> 17: +// <18=> 18: +// <19=> 19: +// <20=> 20: +// <21=> 21: +// <22=> 22: +// <23=> 23: +// <24=> 24: +// <25=> 25: +// <26=> 26: +// <27=> 27: +// <28=> 28: +// <29=> 29: +// <30=> 30: +// <31=> 31: +// <32=> 32: +// <33=> 33: SPI0TX = SPI0 TX +// <34=> 34: SPI1TX = SPI1 TX +// <35=> 35: +// <36=> 36: UART0TX = UART0 TX +// <37=> 37: UART1TX = UART1 TX +// <38=> 38: +// <39=> 39: I2C0TX = I2C0 TX +// <40=> 40: I2C1TX = I2C1 TX +// <41=> 41: +// <42=> 42: +// <43=> 43: +// <44=> 44: +// <45=> 45: +// <46=> 46: +// <47=> 47: +// <48=> 48: +// <49=> 49: +// <50=> 50: +// <51=> 51: +// <52=> 52: +// <53=> 53: +// <54=> 54: +// <55=> 55: +// <56=> 56: +// <57=> 57: +// <58=> 58: +// <59=> 59: +// <60=> 60: +// <61=> 61: +// <62=> 62: +// <63=> 63: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_REQWAIT ----------------------------- +// SVD Line: 416 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_REQWAIT +// REQWAIT +// +// [Bit 10] RW (@ 0x4002820C) \nRequest Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// REQWAIT +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_TOSEL ------------------------------ +// SVD Line: 434 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_TOSEL +// TOSEL +// +// [Bits 13..11] RW (@ 0x4002820C) \nTime-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.\n0 : to4 = Timeout of 3 to 4 prescale clocks.\n1 : to8 = Timeout of 7 to 8 prescale clocks.\n2 : to16 = Timeout of 15 to 16 prescale clocks.\n3 : to32 = Timeout of 31 to 32 prescale clocks.\n4 : to64 = Timeout of 63 to 64 prescale clocks.\n5 : to128 = Timeout of 127 to 128 prescale clocks.\n6 : to256 = Timeout of 255 to 256 prescale clocks.\n7 : to512 = Timeout of 511 to 512 prescale clocks. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// TOSEL +// <0=> 0: to4 = Timeout of 3 to 4 prescale clocks. +// <1=> 1: to8 = Timeout of 7 to 8 prescale clocks. +// <2=> 2: to16 = Timeout of 15 to 16 prescale clocks. +// <3=> 3: to32 = Timeout of 31 to 32 prescale clocks. +// <4=> 4: to64 = Timeout of 63 to 64 prescale clocks. +// <5=> 5: to128 = Timeout of 127 to 128 prescale clocks. +// <6=> 6: to256 = Timeout of 255 to 256 prescale clocks. +// <7=> 7: to512 = Timeout of 511 to 512 prescale clocks. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_PSSEL ------------------------------ +// SVD Line: 482 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_PSSEL +// PSSEL +// +// [Bits 15..14] RW (@ 0x4002820C) \nPre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n0 : dis = Disable timer.\n1 : div256 = hclk / 256.\n2 : div64k = hclk / 64k.\n3 : div16M = hclk / 16M. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// PSSEL +// <0=> 0: dis = Disable timer. +// <1=> 1: div256 = hclk / 256. +// <2=> 2: div64k = hclk / 64k. +// <3=> 3: div16M = hclk / 16M. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_SRCWD ------------------------------ +// SVD Line: 510 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_SRCWD +// SRCWD +// +// [Bits 17..16] RW (@ 0x4002820C) \nSource Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// SRCWD +// <0=> 0: byte = Byte. +// <1=> 1: halfWord = Halfword. +// <2=> 2: word = Word. +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_SRCINC ------------------------------ +// SVD Line: 533 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_SRCINC +// SRCINC +// +// [Bit 18] RW (@ 0x4002820C) \nSource Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// SRCINC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_DSTWD ------------------------------ +// SVD Line: 551 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_DSTWD +// DSTWD +// +// [Bits 21..20] RW (@ 0x4002820C) \nDestination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n0 : byte = Byte.\n1 : halfWord = Halfword.\n2 : word = Word.\n3 : Reserved - do not use +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// DSTWD +// <0=> 0: byte = Byte. +// <1=> 1: halfWord = Halfword. +// <2=> 2: word = Word. +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_DSTINC ------------------------------ +// SVD Line: 574 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_DSTINC +// DSTINC +// +// [Bit 22] RW (@ 0x4002820C) \nDestination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// DSTINC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_CFG_BRST ------------------------------- +// SVD Line: 592 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_BRST +// BRST +// +// [Bits 28..24] RW (@ 0x4002820C) Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. +// +// ( (unsigned char)((DMA_CH_CH_CH3_CFG >> 24) & 0x1F), ((DMA_CH_CH_CH3_CFG = (DMA_CH_CH_CH3_CFG & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) )) +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_CHDIEN ------------------------------ +// SVD Line: 598 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CHDIEN +// CHDIEN +// +// [Bit 30] RW (@ 0x4002820C) \nChannel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// CHDIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH3_CFG_CTZIEN ------------------------------ +// SVD Line: 616 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CTZIEN +// CTZIEN +// +// [Bit 31] RW (@ 0x4002820C) \nCount-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_CFG ) +// CTZIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH3_CFG ------------------------------- +// SVD Line: 274 + +// SFDITEM_REG__DMA_CH_CH_CH3_CFG +// CFG +// +// [Bits 31..0] RW (@ 0x4002820C) DMA Channel Configuration Register. +// ( (unsigned int)((DMA_CH_CH_CH3_CFG >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_CFG = (DMA_CH_CH_CH3_CFG & ~(0xDF77FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF77FFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CHEN +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_RLDEN +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_PRI +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_REQSEL +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_REQWAIT +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_TOSEL +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_PSSEL +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_SRCWD +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_SRCINC +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_DSTWD +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_DSTINC +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_BRST +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CHDIEN +// SFDITEM_FIELD__DMA_CH_CH_CH3_CFG_CTZIEN +// +// + + +// ------------------------- Register Item Address: DMA_CH_CH_CH3_ST ---------------------------- +// SVD Line: 636 + +unsigned int DMA_CH_CH_CH3_ST __AT (0x40028210); + + + +// --------------------------- Field Item: DMA_CH_CH_CH3_ST_CH_ST ------------------------------- +// SVD Line: 641 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_CH_ST +// CH_ST +// +// [Bit 0] RO (@ 0x40028210) \nChannel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_ST ) +// CH_ST +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_ST_IPEND ------------------------------- +// SVD Line: 660 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_IPEND +// IPEND +// +// [Bit 1] RO (@ 0x40028210) \nChannel Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) DMA_CH_CH_CH3_ST ) +// IPEND +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_ST_CTZ_ST ------------------------------ +// SVD Line: 679 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_CTZ_ST +// CTZ_ST +// +// [Bit 2] RW (@ 0x40028210) \nCount-to-Zero (CTZ) Status\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH3_ST ) +// CTZ_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_ST_RLD_ST ------------------------------ +// SVD Line: 709 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_RLD_ST +// RLD_ST +// +// [Bit 3] RW (@ 0x40028210) \nReload Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH3_ST ) +// RLD_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// -------------------------- Field Item: DMA_CH_CH_CH3_ST_BUS_ERR ------------------------------ +// SVD Line: 737 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_BUS_ERR +// BUS_ERR +// +// [Bit 4] RW (@ 0x40028210) \nBus Error. Indicates that an AHB abort was received and the channel has been disabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH3_ST ) +// BUS_ERR +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// --------------------------- Field Item: DMA_CH_CH_CH3_ST_TO_ST ------------------------------- +// SVD Line: 765 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_TO_ST +// TO_ST +// +// [Bit 6] RW (@ 0x40028210) \nTime-Out Status.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) DMA_CH_CH_CH3_ST ) +// TO_ST +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH3_ST -------------------------------- +// SVD Line: 636 + +// SFDITEM_REG__DMA_CH_CH_CH3_ST +// ST +// +// [Bits 31..0] RW (@ 0x40028210) DMA Channel Status Register. +// ( (unsigned int)((DMA_CH_CH_CH3_ST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_ST = (DMA_CH_CH_CH3_ST & ~(0x5CUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5C) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_CH_ST +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_IPEND +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_CTZ_ST +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_RLD_ST +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_BUS_ERR +// SFDITEM_FIELD__DMA_CH_CH_CH3_ST_TO_ST +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH3_SRC ---------------------------- +// SVD Line: 795 + +unsigned int DMA_CH_CH_CH3_SRC __AT (0x40028214); + + + +// --------------------------- Field Item: DMA_CH_CH_CH3_SRC_ADDR ------------------------------- +// SVD Line: 800 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_SRC_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x40028214) ADDR +// +// ( (unsigned int)((DMA_CH_CH_CH3_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_SRC = (DMA_CH_CH_CH3_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH3_SRC ------------------------------- +// SVD Line: 795 + +// SFDITEM_REG__DMA_CH_CH_CH3_SRC +// SRC +// +// [Bits 31..0] RW (@ 0x40028214) Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. +// ( (unsigned int)((DMA_CH_CH_CH3_SRC >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_SRC = (DMA_CH_CH_CH3_SRC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH3_SRC_ADDR +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH3_DST ---------------------------- +// SVD Line: 807 + +unsigned int DMA_CH_CH_CH3_DST __AT (0x40028218); + + + +// --------------------------- Field Item: DMA_CH_CH_CH3_DST_ADDR ------------------------------- +// SVD Line: 812 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_DST_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x40028218) ADDR +// +// ( (unsigned int)((DMA_CH_CH_CH3_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_DST = (DMA_CH_CH_CH3_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH3_DST ------------------------------- +// SVD Line: 807 + +// SFDITEM_REG__DMA_CH_CH_CH3_DST +// DST +// +// [Bits 31..0] RW (@ 0x40028218) Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. +// ( (unsigned int)((DMA_CH_CH_CH3_DST >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_DST = (DMA_CH_CH_CH3_DST & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH3_DST_ADDR +// +// + + +// ------------------------ Register Item Address: DMA_CH_CH_CH3_CNT ---------------------------- +// SVD Line: 819 + +unsigned int DMA_CH_CH_CH3_CNT __AT (0x4002821C); + + + +// ---------------------------- Field Item: DMA_CH_CH_CH3_CNT_CNT ------------------------------- +// SVD Line: 824 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_CNT +// CNT +// +// [Bits 23..0] RW (@ 0x4002821C) DMA Counter. +// +// ( (unsigned int)((DMA_CH_CH_CH3_CNT >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH3_CNT = (DMA_CH_CH_CH3_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: DMA_CH_CH_CH3_CNT ------------------------------- +// SVD Line: 819 + +// SFDITEM_REG__DMA_CH_CH_CH3_CNT +// CNT +// +// [Bits 31..0] RW (@ 0x4002821C) DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. +// ( (unsigned int)((DMA_CH_CH_CH3_CNT >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_CNT = (DMA_CH_CH_CH3_CNT & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_CNT +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH3_SRC_RLD -------------------------- +// SVD Line: 832 + +unsigned int DMA_CH_CH_CH3_SRC_RLD __AT (0x40028220); + + + +// ------------------------ Field Item: DMA_CH_CH_CH3_SRC_RLD_SRC_RLD --------------------------- +// SVD Line: 837 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_SRC_RLD_SRC_RLD +// SRC_RLD +// +// [Bits 30..0] RW (@ 0x40028220) Source Address Reload Value. +// +// ( (unsigned int)((DMA_CH_CH_CH3_SRC_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH3_SRC_RLD = (DMA_CH_CH_CH3_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH3_SRC_RLD ----------------------------- +// SVD Line: 832 + +// SFDITEM_REG__DMA_CH_CH_CH3_SRC_RLD +// SRC_RLD +// +// [Bits 31..0] RW (@ 0x40028220) Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. +// ( (unsigned int)((DMA_CH_CH_CH3_SRC_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_SRC_RLD = (DMA_CH_CH_CH3_SRC_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH3_SRC_RLD_SRC_RLD +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH3_DST_RLD -------------------------- +// SVD Line: 845 + +unsigned int DMA_CH_CH_CH3_DST_RLD __AT (0x40028224); + + + +// ------------------------ Field Item: DMA_CH_CH_CH3_DST_RLD_DST_RLD --------------------------- +// SVD Line: 850 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_DST_RLD_DST_RLD +// DST_RLD +// +// [Bits 30..0] RW (@ 0x40028224) Destination Address Reload Value. +// +// ( (unsigned int)((DMA_CH_CH_CH3_DST_RLD >> 0) & 0x7FFFFFFF), ((DMA_CH_CH_CH3_DST_RLD = (DMA_CH_CH_CH3_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH3_DST_RLD ----------------------------- +// SVD Line: 845 + +// SFDITEM_REG__DMA_CH_CH_CH3_DST_RLD +// DST_RLD +// +// [Bits 31..0] RW (@ 0x40028224) Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. +// ( (unsigned int)((DMA_CH_CH_CH3_DST_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_DST_RLD = (DMA_CH_CH_CH3_DST_RLD & ~(0x7FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH3_DST_RLD_DST_RLD +// +// + + +// ---------------------- Register Item Address: DMA_CH_CH_CH3_CNT_RLD -------------------------- +// SVD Line: 858 + +unsigned int DMA_CH_CH_CH3_CNT_RLD __AT (0x40028228); + + + +// ------------------------ Field Item: DMA_CH_CH_CH3_CNT_RLD_CNT_RLD --------------------------- +// SVD Line: 863 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_RLD_CNT_RLD +// CNT_RLD +// +// [Bits 23..0] RW (@ 0x40028228) Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. +// +// ( (unsigned int)((DMA_CH_CH_CH3_CNT_RLD >> 0) & 0xFFFFFF), ((DMA_CH_CH_CH3_CNT_RLD = (DMA_CH_CH_CH3_CNT_RLD & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------- Field Item: DMA_CH_CH_CH3_CNT_RLD_RLDEN ---------------------------- +// SVD Line: 869 + +// SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_RLD_RLDEN +// RLDEN +// +// [Bit 31] RW (@ 0x40028228) \nReload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) DMA_CH_CH_CH3_CNT_RLD ) +// RLDEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------- Register RTree: DMA_CH_CH_CH3_CNT_RLD ----------------------------- +// SVD Line: 858 + +// SFDITEM_REG__DMA_CH_CH_CH3_CNT_RLD +// CNT_RLD +// +// [Bits 31..0] RW (@ 0x40028228) DMA Channel Count Reload Register. +// ( (unsigned int)((DMA_CH_CH_CH3_CNT_RLD >> 0) & 0xFFFFFFFF), ((DMA_CH_CH_CH3_CNT_RLD = (DMA_CH_CH_CH3_CNT_RLD & ~(0x80FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80FFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_RLD_CNT_RLD +// SFDITEM_FIELD__DMA_CH_CH_CH3_CNT_RLD_RLDEN +// +// + + +// ------------------------------ Cluster ITree: DMA_CH_CH_CH3 ---------------------------------- +// SVD Line: 266 + +// SFDITEM_CLUST__DMA_CH_CH_CH3 +// [3] +// DMA Channel registers. +// SFDITEM_REG__DMA_CH_CH_CH3_CFG +// SFDITEM_REG__DMA_CH_CH_CH3_ST +// SFDITEM_REG__DMA_CH_CH_CH3_SRC +// SFDITEM_REG__DMA_CH_CH_CH3_DST +// SFDITEM_REG__DMA_CH_CH_CH3_CNT +// SFDITEM_REG__DMA_CH_CH_CH3_SRC_RLD +// SFDITEM_REG__DMA_CH_CH_CH3_DST_RLD +// SFDITEM_REG__DMA_CH_CH_CH3_CNT_RLD +// +// + + +// ------------------------------- Cluster Array ITree: DMA_CH ---------------------------------- +// SVD Line: 266 + +// SFDITEM_CLUST__DMA_CH +// CH +// DMA Channel registers. +// SFDITEM_CLUST__DMA_CH_CH_CH0 +// SFDITEM_CLUST__DMA_CH_CH_CH1 +// SFDITEM_CLUST__DMA_CH_CH_CH2 +// SFDITEM_CLUST__DMA_CH_CH_CH3 +// +// + + +// ---------------------------------- Peripheral View: DMA -------------------------------------- +// SVD Line: 106 + +// DMA +// DMA +// SFDITEM_REG__DMA_CN +// SFDITEM_REG__DMA_INTR +// SFDITEM_CLUST__DMA_CH +// +// + + +// ----------------------------- Register Item Address: FLC_ADDR -------------------------------- +// SVD Line: 909 + +unsigned int FLC_ADDR __AT (0x40029000); + + + +// -------------------------------- Field Item: FLC_ADDR_ADDR ----------------------------------- +// SVD Line: 914 + +// SFDITEM_FIELD__FLC_ADDR_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x40029000) Address for next operation. +// +// ( (unsigned int)((FLC_ADDR >> 0) & 0xFFFFFFFF), ((FLC_ADDR = (FLC_ADDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: FLC_ADDR ------------------------------------ +// SVD Line: 909 + +// SFDITEM_REG__FLC_ADDR +// ADDR +// +// [Bits 31..0] RW (@ 0x40029000) Flash Write Address. +// ( (unsigned int)((FLC_ADDR >> 0) & 0xFFFFFFFF), ((FLC_ADDR = (FLC_ADDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__FLC_ADDR_ADDR +// +// + + +// ---------------------------- Register Item Address: FLC_CLKDIV ------------------------------- +// SVD Line: 922 + +unsigned int FLC_CLKDIV __AT (0x40029004); + + + +// ------------------------------ Field Item: FLC_CLKDIV_CLKDIV --------------------------------- +// SVD Line: 928 + +// SFDITEM_FIELD__FLC_CLKDIV_CLKDIV +// CLKDIV +// +// [Bits 7..0] RW (@ 0x40029004) Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. +// +// ( (unsigned char)((FLC_CLKDIV >> 0) & 0xFF), ((FLC_CLKDIV = (FLC_CLKDIV & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: FLC_CLKDIV ----------------------------------- +// SVD Line: 922 + +// SFDITEM_REG__FLC_CLKDIV +// CLKDIV +// +// [Bits 31..0] RW (@ 0x40029004) Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. +// ( (unsigned int)((FLC_CLKDIV >> 0) & 0xFFFFFFFF), ((FLC_CLKDIV = (FLC_CLKDIV & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__FLC_CLKDIV_CLKDIV +// +// + + +// ------------------------------ Register Item Address: FLC_CN --------------------------------- +// SVD Line: 936 + +unsigned int FLC_CN __AT (0x40029008); + + + +// ---------------------------------- Field Item: FLC_CN_WR ------------------------------------- +// SVD Line: 941 + +// SFDITEM_FIELD__FLC_CN_WR +// WR +// +// [Bit 0] RW (@ 0x40029008) \nWrite. This bit is automatically cleared after the operation.\n0 : complete = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) FLC_CN ) +// WR +// <0=> 0: complete = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// ---------------------------------- Field Item: FLC_CN_ME ------------------------------------- +// SVD Line: 959 + +// SFDITEM_FIELD__FLC_CN_ME +// ME +// +// [Bit 1] RW (@ 0x40029008) \nMass Erase. This bit is automatically cleared after the operation.\n0 : complete = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) FLC_CN ) +// ME +// <0=> 0: complete = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// --------------------------------- Field Item: FLC_CN_PGE ------------------------------------- +// SVD Line: 965 + +// SFDITEM_FIELD__FLC_CN_PGE +// PGE +// +// [Bit 2] RW (@ 0x40029008) \nPage Erase. This bit is automatically cleared after the operation.\n0 : complete = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) FLC_CN ) +// PGE +// <0=> 0: complete = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// --------------------------------- Field Item: FLC_CN_WDTH ------------------------------------ +// SVD Line: 971 + +// SFDITEM_FIELD__FLC_CN_WDTH +// WDTH +// +// [Bit 4] RW (@ 0x40029008) \nData Width. This bits selects write data width.\n0 : size128 = 128-bit.\n1 : size32 = 32-bit. +// +// ( (unsigned int) FLC_CN ) +// WDTH +// <0=> 0: size128 = 128-bit. +// <1=> 1: size32 = 32-bit. +// +// +// + + +// ------------------------------ Field Item: FLC_CN_ERASE_CODE --------------------------------- +// SVD Line: 989 + +// SFDITEM_FIELD__FLC_CN_ERASE_CODE +// ERASE_CODE +// +// [Bits 15..8] RW (@ 0x40029008) Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. +// +// ( (unsigned char)((FLC_CN >> 8) & 0xFF), ((FLC_CN = (FLC_CN & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) +// +// +// + + +// --------------------------------- Field Item: FLC_CN_PEND ------------------------------------ +// SVD Line: 1012 + +// SFDITEM_FIELD__FLC_CN_PEND +// PEND +// +// [Bit 24] RO (@ 0x40029008) \nFlash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.\n0 : idle = Idle.\n1 : busy = Busy. +// +// ( (unsigned int) FLC_CN ) +// PEND +// <0=> 0: idle = Idle. +// <1=> 1: busy = Busy. +// +// +// + + +// --------------------------------- Field Item: FLC_CN_LVE ------------------------------------- +// SVD Line: 1031 + +// SFDITEM_FIELD__FLC_CN_LVE +// LVE +// +// [Bit 25] RO (@ 0x40029008) \nLow Voltage Read Enable\n0 : dis = Disabled\n1 : en = Enabled +// +// ( (unsigned int) FLC_CN ) +// LVE +// <0=> 0: dis = Disabled +// <1=> 1: en = Enabled +// +// +// + + +// --------------------------------- Field Item: FLC_CN_BRST ------------------------------------ +// SVD Line: 1052 + +// SFDITEM_FIELD__FLC_CN_BRST +// BRST +// +// [Bit 27] RW (@ 0x40029008) \nBurst Mode Enable.\n0 : disable = Disable\n1 : enable = Enable +// +// ( (unsigned int) FLC_CN ) +// BRST +// <0=> 0: disable = Disable +// <1=> 1: enable = Enable +// +// +// + + +// -------------------------------- Field Item: FLC_CN_UNLOCK ----------------------------------- +// SVD Line: 1070 + +// SFDITEM_FIELD__FLC_CN_UNLOCK +// UNLOCK +// +// [Bits 31..28] RW (@ 0x40029008) \nFlash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.\n0 : Reserved - do not use\n1 : Reserved - do not use\n2 : unlocked = Flash Unlocked\n3 : locked = Flash Locked\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use +// +// ( (unsigned int) FLC_CN ) +// UNLOCK +// <0=> 0: +// <1=> 1: +// <2=> 2: unlocked = Flash Unlocked +// <3=> 3: locked = Flash Locked +// <4=> 4: +// <5=> 5: +// <6=> 6: +// <7=> 7: +// <8=> 8: +// <9=> 9: +// <10=> 10: +// <11=> 11: +// <12=> 12: +// <13=> 13: +// <14=> 14: +// <15=> 15: +// +// +// + + +// --------------------------------- Register RTree: FLC_CN ------------------------------------- +// SVD Line: 936 + +// SFDITEM_REG__FLC_CN +// CN +// +// [Bits 31..0] RW (@ 0x40029008) Flash Control Register. +// ( (unsigned int)((FLC_CN >> 0) & 0xFFFFFFFF), ((FLC_CN = (FLC_CN & ~(0xF800FF17UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF800FF17) << 0 ) ) )) +// SFDITEM_FIELD__FLC_CN_WR +// SFDITEM_FIELD__FLC_CN_ME +// SFDITEM_FIELD__FLC_CN_PGE +// SFDITEM_FIELD__FLC_CN_WDTH +// SFDITEM_FIELD__FLC_CN_ERASE_CODE +// SFDITEM_FIELD__FLC_CN_PEND +// SFDITEM_FIELD__FLC_CN_LVE +// SFDITEM_FIELD__FLC_CN_BRST +// SFDITEM_FIELD__FLC_CN_UNLOCK +// +// + + +// ----------------------------- Register Item Address: FLC_INTR -------------------------------- +// SVD Line: 1090 + +unsigned int FLC_INTR __AT (0x40029024); + + + +// -------------------------------- Field Item: FLC_INTR_DONE ----------------------------------- +// SVD Line: 1095 + +// SFDITEM_FIELD__FLC_INTR_DONE +// DONE +// +// [Bit 0] RW (@ 0x40029024) \nFlash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.\n0 : inactive = No interrupt is pending\n1 : pending = An interrupt is pending +// +// ( (unsigned int) FLC_INTR ) +// DONE +// <0=> 0: inactive = No interrupt is pending +// <1=> 1: pending = An interrupt is pending +// +// +// + + +// --------------------------------- Field Item: FLC_INTR_AF ------------------------------------ +// SVD Line: 1113 + +// SFDITEM_FIELD__FLC_INTR_AF +// AF +// +// [Bit 1] RW (@ 0x40029024) \nFlash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.\n0 : noError = No Failure.\n1 : error = Failure occurs. +// +// ( (unsigned int) FLC_INTR ) +// AF +// <0=> 0: noError = No Failure. +// <1=> 1: error = Failure occurs. +// +// +// + + +// ------------------------------- Field Item: FLC_INTR_DONEIE ---------------------------------- +// SVD Line: 1131 + +// SFDITEM_FIELD__FLC_INTR_DONEIE +// DONEIE +// +// [Bit 8] RW (@ 0x40029024) \nFlash Done Interrupt Enable.\n0 : disable = Disable.\n1 : enable = Enable. +// +// ( (unsigned int) FLC_INTR ) +// DONEIE +// <0=> 0: disable = Disable. +// <1=> 1: enable = Enable. +// +// +// + + +// -------------------------------- Field Item: FLC_INTR_AFIE ----------------------------------- +// SVD Line: 1149 + +// SFDITEM_FIELD__FLC_INTR_AFIE +// AFIE +// +// [Bit 9] RW (@ 0x40029024) \nFlash Done Interrupt Enable.\n0 : disable = Disable.\n1 : enable = Enable. +// +// ( (unsigned int) FLC_INTR ) +// AFIE +// <0=> 0: disable = Disable. +// <1=> 1: enable = Enable. +// +// +// + + +// -------------------------------- Register RTree: FLC_INTR ------------------------------------ +// SVD Line: 1090 + +// SFDITEM_REG__FLC_INTR +// INTR +// +// [Bits 31..0] RW (@ 0x40029024) Flash Interrupt Register. +// ( (unsigned int)((FLC_INTR >> 0) & 0xFFFFFFFF), ((FLC_INTR = (FLC_INTR & ~(0x303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x303) << 0 ) ) )) +// SFDITEM_FIELD__FLC_INTR_DONE +// SFDITEM_FIELD__FLC_INTR_AF +// SFDITEM_FIELD__FLC_INTR_DONEIE +// SFDITEM_FIELD__FLC_INTR_AFIE +// +// + + +// -------------------- Register Array Item Address: FLC_DATA_DATA_DATA0 ------------------------ +// SVD Line: 1156 + +unsigned int FLC_DATA_DATA_DATA0 __AT (0x40029030); + + + +// -------------------------- Field Item: FLC_DATA_DATA_DATA0_DATA ------------------------------ +// SVD Line: 1163 + +// SFDITEM_FIELD__FLC_DATA_DATA_DATA0_DATA +// DATA +// +// [Bits 31..0] RW (@ 0x40029030) Data next operation. +// +// ( (unsigned int)((FLC_DATA_DATA_DATA0 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA0 = (FLC_DATA_DATA_DATA0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------ Register Array RTree: FLC_DATA_DATA_DATA0 --------------------------- +// SVD Line: 1156 + +// SFDITEM_REG__FLC_DATA_DATA_DATA0 +// [0] +// +// [Bits 31..0] RW (@ 0x40029030) Flash Write Data. +// ( (unsigned int)((FLC_DATA_DATA_DATA0 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA0 = (FLC_DATA_DATA_DATA0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__FLC_DATA_DATA_DATA0_DATA +// +// + + +// -------------------- Register Array Item Address: FLC_DATA_DATA_DATA1 ------------------------ +// SVD Line: 1156 + +unsigned int FLC_DATA_DATA_DATA1 __AT (0x40029034); + + + +// -------------------------- Field Item: FLC_DATA_DATA_DATA1_DATA ------------------------------ +// SVD Line: 1163 + +// SFDITEM_FIELD__FLC_DATA_DATA_DATA1_DATA +// DATA +// +// [Bits 31..0] RW (@ 0x40029034) Data next operation. +// +// ( (unsigned int)((FLC_DATA_DATA_DATA1 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA1 = (FLC_DATA_DATA_DATA1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------ Register Array RTree: FLC_DATA_DATA_DATA1 --------------------------- +// SVD Line: 1156 + +// SFDITEM_REG__FLC_DATA_DATA_DATA1 +// [1] +// +// [Bits 31..0] RW (@ 0x40029034) Flash Write Data. +// ( (unsigned int)((FLC_DATA_DATA_DATA1 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA1 = (FLC_DATA_DATA_DATA1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__FLC_DATA_DATA_DATA1_DATA +// +// + + +// -------------------- Register Array Item Address: FLC_DATA_DATA_DATA2 ------------------------ +// SVD Line: 1156 + +unsigned int FLC_DATA_DATA_DATA2 __AT (0x40029038); + + + +// -------------------------- Field Item: FLC_DATA_DATA_DATA2_DATA ------------------------------ +// SVD Line: 1163 + +// SFDITEM_FIELD__FLC_DATA_DATA_DATA2_DATA +// DATA +// +// [Bits 31..0] RW (@ 0x40029038) Data next operation. +// +// ( (unsigned int)((FLC_DATA_DATA_DATA2 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA2 = (FLC_DATA_DATA_DATA2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------ Register Array RTree: FLC_DATA_DATA_DATA2 --------------------------- +// SVD Line: 1156 + +// SFDITEM_REG__FLC_DATA_DATA_DATA2 +// [2] +// +// [Bits 31..0] RW (@ 0x40029038) Flash Write Data. +// ( (unsigned int)((FLC_DATA_DATA_DATA2 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA2 = (FLC_DATA_DATA_DATA2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__FLC_DATA_DATA_DATA2_DATA +// +// + + +// -------------------- Register Array Item Address: FLC_DATA_DATA_DATA3 ------------------------ +// SVD Line: 1156 + +unsigned int FLC_DATA_DATA_DATA3 __AT (0x4002903C); + + + +// -------------------------- Field Item: FLC_DATA_DATA_DATA3_DATA ------------------------------ +// SVD Line: 1163 + +// SFDITEM_FIELD__FLC_DATA_DATA_DATA3_DATA +// DATA +// +// [Bits 31..0] RW (@ 0x4002903C) Data next operation. +// +// ( (unsigned int)((FLC_DATA_DATA_DATA3 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA3 = (FLC_DATA_DATA_DATA3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------ Register Array RTree: FLC_DATA_DATA_DATA3 --------------------------- +// SVD Line: 1156 + +// SFDITEM_REG__FLC_DATA_DATA_DATA3 +// [3] +// +// [Bits 31..0] RW (@ 0x4002903C) Flash Write Data. +// ( (unsigned int)((FLC_DATA_DATA_DATA3 >> 0) & 0xFFFFFFFF), ((FLC_DATA_DATA_DATA3 = (FLC_DATA_DATA_DATA3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__FLC_DATA_DATA_DATA3_DATA +// +// + + +// ----------------------------- Register Array ITree: FLC_DATA --------------------------------- +// SVD Line: 1156 + +// SFDITEM_REG__FLC_DATA +// DATA +// Flash Write Data. +// SFDITEM_REG__FLC_DATA_DATA_DATA0 +// SFDITEM_REG__FLC_DATA_DATA_DATA1 +// SFDITEM_REG__FLC_DATA_DATA_DATA2 +// SFDITEM_REG__FLC_DATA_DATA_DATA3 +// +// + + +// ---------------------------- Register Item Address: FLC_ACNTL -------------------------------- +// SVD Line: 1171 + +unsigned int FLC_ACNTL __AT (0x40029040); + + + +// ------------------------------- Field Item: FLC_ACNTL_ACNTL ---------------------------------- +// SVD Line: 1177 + +// SFDITEM_FIELD__FLC_ACNTL_ACNTL +// ACNTL +// +// [Bits 31..0] WO (@ 0x40029040) Access control. +// +// ( (unsigned int)((FLC_ACNTL >> 0) & 0x0), ((FLC_ACNTL = (FLC_ACNTL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: FLC_ACNTL ----------------------------------- +// SVD Line: 1171 + +// SFDITEM_REG__FLC_ACNTL +// ACNTL +// +// [Bits 31..0] WO (@ 0x40029040) Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. +// ( (unsigned int)((FLC_ACNTL >> 0) & 0xFFFFFFFF), ((FLC_ACNTL = (FLC_ACNTL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__FLC_ACNTL_ACNTL +// +// + + +// ---------------------------------- Peripheral View: FLC -------------------------------------- +// SVD Line: 893 + +// FLC +// FLC +// SFDITEM_REG__FLC_ADDR +// SFDITEM_REG__FLC_CLKDIV +// SFDITEM_REG__FLC_CN +// SFDITEM_REG__FLC_INTR +// SFDITEM_REG__FLC_DATA +// SFDITEM_REG__FLC_ACNTL +// +// + + +// ----------------------------- Register Item Address: GCR_SCON -------------------------------- +// SVD Line: 1198 + +unsigned int GCR_SCON __AT (0x40000000); + + + +// ------------------------------ Field Item: GCR_SCON_SBUSARB ---------------------------------- +// SVD Line: 1204 + +// SFDITEM_FIELD__GCR_SCON_SBUSARB +// SBUSARB +// +// [Bits 2..1] RW (@ 0x40000000) \nSystem bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.\n0 : fix = Fixed Burst abritration.\n1 : round = Round-robin scheme.\n2 : Reserved - do not use\n3 : Reserved - do not use +// +// ( (unsigned int) GCR_SCON ) +// SBUSARB +// <0=> 0: fix = Fixed Burst abritration. +// <1=> 1: round = Round-robin scheme. +// <2=> 2: +// <3=> 3: +// +// +// + + +// -------------------------- Field Item: GCR_SCON_FLASH_PAGE_FLIP ------------------------------ +// SVD Line: 1222 + +// SFDITEM_FIELD__GCR_SCON_FLASH_PAGE_FLIP +// FLASH_PAGE_FLIP +// +// [Bit 4] RW (@ 0x40000000) \nFlips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.\n0 : normal = Physical layout matches logical layout.\n1 : swapped = Bottom half mapped to logical top half and vice versa. +// +// ( (unsigned int) GCR_SCON ) +// FLASH_PAGE_FLIP +// <0=> 0: normal = Physical layout matches logical layout. +// <1=> 1: swapped = Bottom half mapped to logical top half and vice versa. +// +// +// + + +// ------------------------------ Field Item: GCR_SCON_FPU_DIS ---------------------------------- +// SVD Line: 1240 + +// SFDITEM_FIELD__GCR_SCON_FPU_DIS +// FPU_DIS +// +// [Bit 5] RW (@ 0x40000000) \nFloating Point Unit Disable\n0 : enable = enable Floating point unit\n1 : disable = disable floating point unit +// +// ( (unsigned int) GCR_SCON ) +// FPU_DIS +// <0=> 0: enable = enable Floating point unit +// <1=> 1: disable = disable floating point unit +// +// +// + + +// ---------------------------- Field Item: GCR_SCON_CCACHE_FLUSH ------------------------------- +// SVD Line: 1258 + +// SFDITEM_FIELD__GCR_SCON_CCACHE_FLUSH +// CCACHE_FLUSH +// +// [Bit 6] RW (@ 0x40000000) \nCode Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4.\n0 : normal = Normal Code Cache Operation\n1 : flush = Code Caches and CPU instruction buffer are flushed +// +// ( (unsigned int) GCR_SCON ) +// CCACHE_FLUSH +// <0=> 0: normal = Normal Code Cache Operation +// <1=> 1: flush = Code Caches and CPU instruction buffer are flushed +// +// +// + + +// ------------------------------ Field Item: GCR_SCON_SWD_DIS ---------------------------------- +// SVD Line: 1276 + +// SFDITEM_FIELD__GCR_SCON_SWD_DIS +// SWD_DIS +// +// [Bit 14] RW (@ 0x40000000) \nSerial Wire Debug Disable\n0 : enable = Enable JTAG SWD\n1 : disable = Disable JTAG SWD +// +// ( (unsigned int) GCR_SCON ) +// SWD_DIS +// <0=> 0: enable = Enable JTAG SWD +// <1=> 1: disable = Disable JTAG SWD +// +// +// + + +// -------------------------------- Register RTree: GCR_SCON ------------------------------------ +// SVD Line: 1198 + +// SFDITEM_REG__GCR_SCON +// SCON +// +// [Bits 31..0] RW (@ 0x40000000) System Control. +// ( (unsigned int)((GCR_SCON >> 0) & 0xFFFFFFFF), ((GCR_SCON = (GCR_SCON & ~(0x4076UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x4076) << 0 ) ) )) +// SFDITEM_FIELD__GCR_SCON_SBUSARB +// SFDITEM_FIELD__GCR_SCON_FLASH_PAGE_FLIP +// SFDITEM_FIELD__GCR_SCON_FPU_DIS +// SFDITEM_FIELD__GCR_SCON_CCACHE_FLUSH +// SFDITEM_FIELD__GCR_SCON_SWD_DIS +// +// + + +// ---------------------------- Register Item Address: GCR_RSTR0 -------------------------------- +// SVD Line: 1296 + +unsigned int GCR_RSTR0 __AT (0x40000004); + + + +// -------------------------------- Field Item: GCR_RSTR0_DMA ----------------------------------- +// SVD Line: 1301 + +// SFDITEM_FIELD__GCR_RSTR0_DMA +// DMA +// +// [Bit 0] RW (@ 0x40000004) \nDMA Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// DMA +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// -------------------------------- Field Item: GCR_RSTR0_WDT ----------------------------------- +// SVD Line: 1335 + +// SFDITEM_FIELD__GCR_RSTR0_WDT +// WDT +// +// [Bit 1] RW (@ 0x40000004) \nWatchdog Timer Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// WDT +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------- Field Item: GCR_RSTR0_GPIO0 ---------------------------------- +// SVD Line: 1369 + +// SFDITEM_FIELD__GCR_RSTR0_GPIO0 +// GPIO0 +// +// [Bit 2] RW (@ 0x40000004) \nGPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// GPIO0 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------ Field Item: GCR_RSTR0_TIMER0 ---------------------------------- +// SVD Line: 1403 + +// SFDITEM_FIELD__GCR_RSTR0_TIMER0 +// TIMER0 +// +// [Bit 5] RW (@ 0x40000004) \nTimer0 Reset. Setting this bit to 1 resets Timer 0 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// TIMER0 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------ Field Item: GCR_RSTR0_TIMER1 ---------------------------------- +// SVD Line: 1437 + +// SFDITEM_FIELD__GCR_RSTR0_TIMER1 +// TIMER1 +// +// [Bit 6] RW (@ 0x40000004) \nTimer1 Reset. Setting this bit to 1 resets Timer 1 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// TIMER1 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------ Field Item: GCR_RSTR0_TIMER2 ---------------------------------- +// SVD Line: 1471 + +// SFDITEM_FIELD__GCR_RSTR0_TIMER2 +// TIMER2 +// +// [Bit 7] RW (@ 0x40000004) \nTimer2 Reset. Setting this bit to 1 resets Timer 2 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// TIMER2 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------- Field Item: GCR_RSTR0_UART0 ---------------------------------- +// SVD Line: 1505 + +// SFDITEM_FIELD__GCR_RSTR0_UART0 +// UART0 +// +// [Bit 11] RW (@ 0x40000004) \nUART0 Reset. Setting this bit to 1 resets all UART 0 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// UART0 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------- Field Item: GCR_RSTR0_UART1 ---------------------------------- +// SVD Line: 1539 + +// SFDITEM_FIELD__GCR_RSTR0_UART1 +// UART1 +// +// [Bit 12] RW (@ 0x40000004) \nUART1 Reset. Setting this bit to 1 resets all UART 1 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// UART1 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------- Field Item: GCR_RSTR0_SPI0 ----------------------------------- +// SVD Line: 1573 + +// SFDITEM_FIELD__GCR_RSTR0_SPI0 +// SPI0 +// +// [Bit 13] RW (@ 0x40000004) \nSPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// SPI0 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------- Field Item: GCR_RSTR0_SPI1 ----------------------------------- +// SVD Line: 1607 + +// SFDITEM_FIELD__GCR_RSTR0_SPI1 +// SPI1 +// +// [Bit 14] RW (@ 0x40000004) \nSPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// SPI1 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------- Field Item: GCR_RSTR0_I2C0 ----------------------------------- +// SVD Line: 1641 + +// SFDITEM_FIELD__GCR_RSTR0_I2C0 +// I2C0 +// +// [Bit 16] RW (@ 0x40000004) \nI2C0 Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// I2C0 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// -------------------------------- Field Item: GCR_RSTR0_RTC ----------------------------------- +// SVD Line: 1675 + +// SFDITEM_FIELD__GCR_RSTR0_RTC +// RTC +// +// [Bit 17] RW (@ 0x40000004) \nReal Time Clock Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// RTC +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------- Field Item: GCR_RSTR0_SRST ----------------------------------- +// SVD Line: 1709 + +// SFDITEM_FIELD__GCR_RSTR0_SRST +// SRST +// +// [Bit 29] RW (@ 0x40000004) \nSoft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// SRST +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------- Field Item: GCR_RSTR0_PRST ----------------------------------- +// SVD Line: 1743 + +// SFDITEM_FIELD__GCR_RSTR0_PRST +// PRST +// +// [Bit 30] RW (@ 0x40000004) \nPeripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// PRST +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// ------------------------------ Field Item: GCR_RSTR0_SYSTEM ---------------------------------- +// SVD Line: 1777 + +// SFDITEM_FIELD__GCR_RSTR0_SYSTEM +// SYSTEM +// +// [Bit 31] RW (@ 0x40000004) \nSystem Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR0 ) +// SYSTEM +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// -------------------------------- Register RTree: GCR_RSTR0 ----------------------------------- +// SVD Line: 1296 + +// SFDITEM_REG__GCR_RSTR0 +// RSTR0 +// +// [Bits 31..0] RW (@ 0x40000004) Reset. +// ( (unsigned int)((GCR_RSTR0 >> 0) & 0xFFFFFFFF), ((GCR_RSTR0 = (GCR_RSTR0 & ~(0xE00378E7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xE00378E7) << 0 ) ) )) +// SFDITEM_FIELD__GCR_RSTR0_DMA +// SFDITEM_FIELD__GCR_RSTR0_WDT +// SFDITEM_FIELD__GCR_RSTR0_GPIO0 +// SFDITEM_FIELD__GCR_RSTR0_TIMER0 +// SFDITEM_FIELD__GCR_RSTR0_TIMER1 +// SFDITEM_FIELD__GCR_RSTR0_TIMER2 +// SFDITEM_FIELD__GCR_RSTR0_UART0 +// SFDITEM_FIELD__GCR_RSTR0_UART1 +// SFDITEM_FIELD__GCR_RSTR0_SPI0 +// SFDITEM_FIELD__GCR_RSTR0_SPI1 +// SFDITEM_FIELD__GCR_RSTR0_I2C0 +// SFDITEM_FIELD__GCR_RSTR0_RTC +// SFDITEM_FIELD__GCR_RSTR0_SRST +// SFDITEM_FIELD__GCR_RSTR0_PRST +// SFDITEM_FIELD__GCR_RSTR0_SYSTEM +// +// + + +// ---------------------------- Register Item Address: GCR_CLKCN -------------------------------- +// SVD Line: 1813 + +unsigned int GCR_CLKCN __AT (0x40000008); + + + +// -------------------------------- Field Item: GCR_CLKCN_PSC ----------------------------------- +// SVD Line: 1819 + +// SFDITEM_FIELD__GCR_CLKCN_PSC +// PSC +// +// [Bits 8..6] RW (@ 0x40000008) \nPrescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.\n0 : div1 = Divide by 1.\n1 : div2 = Divide by 2.\n2 : div4 = Divide by 4.\n3 : div8 = Divide by 8.\n4 : div16 = Divide by 16.\n5 : div32 = Divide by 32.\n6 : div64 = Divide by 64.\n7 : div128 = Divide by 128. +// +// ( (unsigned int) GCR_CLKCN ) +// PSC +// <0=> 0: div1 = Divide by 1. +// <1=> 1: div2 = Divide by 2. +// <2=> 2: div4 = Divide by 4. +// <3=> 3: div8 = Divide by 8. +// <4=> 4: div16 = Divide by 16. +// <5=> 5: div32 = Divide by 32. +// <6=> 6: div64 = Divide by 64. +// <7=> 7: div128 = Divide by 128. +// +// +// + + +// ------------------------------ Field Item: GCR_CLKCN_CLKSEL ---------------------------------- +// SVD Line: 1867 + +// SFDITEM_FIELD__GCR_CLKCN_CLKSEL +// CLKSEL +// +// [Bits 11..9] RW (@ 0x40000008) \nClock Source Select. This 3 bit field selects the source for the system clock.\n0 : HIRC = The internal 96 MHz oscillator is used for the system clock.\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : nanoRing = The nano-ring output is used for the system clock.\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : hfxIn = HFXIN is used for the system clock.\n7 : Reserved - do not use +// +// ( (unsigned int) GCR_CLKCN ) +// CLKSEL +// <0=> 0: HIRC = The internal 96 MHz oscillator is used for the system clock. +// <1=> 1: +// <2=> 2: +// <3=> 3: nanoRing = The nano-ring output is used for the system clock. +// <4=> 4: +// <5=> 5: +// <6=> 6: hfxIn = HFXIN is used for the system clock. +// <7=> 7: +// +// +// + + +// ------------------------------- Field Item: GCR_CLKCN_CKRDY ---------------------------------- +// SVD Line: 1890 + +// SFDITEM_FIELD__GCR_CLKCN_CKRDY +// CKRDY +// +// [Bit 13] RO (@ 0x40000008) \nClock Ready. This read only bit reflects whether the currently selected system clock source is running.\n0 : busy = Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.\n1 : ready = System clock running from CLKSEL clock source. +// +// ( (unsigned int) GCR_CLKCN ) +// CKRDY +// <0=> 0: busy = Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. +// <1=> 1: ready = System clock running from CLKSEL clock source. +// +// +// + + +// ------------------------------ Field Item: GCR_CLKCN_X32K_EN --------------------------------- +// SVD Line: 1909 + +// SFDITEM_FIELD__GCR_CLKCN_X32K_EN +// X32K_EN +// +// [Bit 17] RW (@ 0x40000008) \n32kHz Crystal Oscillator Enable.\n0 : dis = Is Disabled.\n1 : en = Is Enabled. +// +// ( (unsigned int) GCR_CLKCN ) +// X32K_EN +// <0=> 0: dis = Is Disabled. +// <1=> 1: en = Is Enabled. +// +// +// + + +// ------------------------------ Field Item: GCR_CLKCN_HIRC_EN --------------------------------- +// SVD Line: 1927 + +// SFDITEM_FIELD__GCR_CLKCN_HIRC_EN +// HIRC_EN +// +// [Bit 18] RW (@ 0x40000008) \n60MHz High Frequency Internal Reference Clock Enable.\n0 : dis = Is Disabled.\n1 : en = Is Enabled. +// +// ( (unsigned int) GCR_CLKCN ) +// HIRC_EN +// <0=> 0: dis = Is Disabled. +// <1=> 1: en = Is Enabled. +// +// +// + + +// ----------------------------- Field Item: GCR_CLKCN_X32K_RDY --------------------------------- +// SVD Line: 1945 + +// SFDITEM_FIELD__GCR_CLKCN_X32K_RDY +// X32K_RDY +// +// [Bit 25] RO (@ 0x40000008) \n32kHz Crystal Oscillator Ready\n0 : not = Not Ready\n1 : Ready = X32K Ready +// +// ( (unsigned int) GCR_CLKCN ) +// X32K_RDY +// <0=> 0: not = Not Ready +// <1=> 1: Ready = X32K Ready +// +// +// + + +// ----------------------------- Field Item: GCR_CLKCN_HIRC_RDY --------------------------------- +// SVD Line: 1964 + +// SFDITEM_FIELD__GCR_CLKCN_HIRC_RDY +// HIRC_RDY +// +// [Bit 26] RW (@ 0x40000008) \n60MHz HIRC Ready.\n0 : not = Not Ready\n1 : ready = HIRC Ready +// +// ( (unsigned int) GCR_CLKCN ) +// HIRC_RDY +// <0=> 0: not = Not Ready +// <1=> 1: ready = HIRC Ready +// +// +// + + +// ---------------------------- Field Item: GCR_CLKCN_LIRC8K_RDY -------------------------------- +// SVD Line: 1982 + +// SFDITEM_FIELD__GCR_CLKCN_LIRC8K_RDY +// LIRC8K_RDY +// +// [Bit 29] RW (@ 0x40000008) \n8kHz Low Frequency Reference Clock Ready.\n0 : not = Not Ready\n1 : ready = Clock Ready +// +// ( (unsigned int) GCR_CLKCN ) +// LIRC8K_RDY +// <0=> 0: not = Not Ready +// <1=> 1: ready = Clock Ready +// +// +// + + +// -------------------------------- Register RTree: GCR_CLKCN ----------------------------------- +// SVD Line: 1813 + +// SFDITEM_REG__GCR_CLKCN +// CLKCN +// +// [Bits 31..0] RW (@ 0x40000008) Clock Control. +// ( (unsigned int)((GCR_CLKCN >> 0) & 0xFFFFFFFF), ((GCR_CLKCN = (GCR_CLKCN & ~(0x24060FC0UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x24060FC0) << 0 ) ) )) +// SFDITEM_FIELD__GCR_CLKCN_PSC +// SFDITEM_FIELD__GCR_CLKCN_CLKSEL +// SFDITEM_FIELD__GCR_CLKCN_CKRDY +// SFDITEM_FIELD__GCR_CLKCN_X32K_EN +// SFDITEM_FIELD__GCR_CLKCN_HIRC_EN +// SFDITEM_FIELD__GCR_CLKCN_X32K_RDY +// SFDITEM_FIELD__GCR_CLKCN_HIRC_RDY +// SFDITEM_FIELD__GCR_CLKCN_LIRC8K_RDY +// +// + + +// ------------------------------ Register Item Address: GCR_PM --------------------------------- +// SVD Line: 2002 + +unsigned int GCR_PM __AT (0x4000000C); + + + +// --------------------------------- Field Item: GCR_PM_MODE ------------------------------------ +// SVD Line: 2007 + +// SFDITEM_FIELD__GCR_PM_MODE +// MODE +// +// [Bits 2..0] RW (@ 0x4000000C) \nOperating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.\n0 : active = Active Mode.\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : shutdown = Shutdown Mode.\n4 : backup = Backup Mode.\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use +// +// ( (unsigned int) GCR_PM ) +// MODE +// <0=> 0: active = Active Mode. +// <1=> 1: +// <2=> 2: +// <3=> 3: shutdown = Shutdown Mode. +// <4=> 4: backup = Backup Mode. +// <5=> 5: +// <6=> 6: +// <7=> 7: +// +// +// + + +// ------------------------------- Field Item: GCR_PM_GPIOWKEN ---------------------------------- +// SVD Line: 2030 + +// SFDITEM_FIELD__GCR_PM_GPIOWKEN +// GPIOWKEN +// +// [Bit 4] RW (@ 0x4000000C) \nGPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.\n0 : dis = Wake Up Disable.\n1 : en = Wake Up Enable. +// +// ( (unsigned int) GCR_PM ) +// GPIOWKEN +// <0=> 0: dis = Wake Up Disable. +// <1=> 1: en = Wake Up Enable. +// +// +// + + +// ------------------------------- Field Item: GCR_PM_RTCWKEN ----------------------------------- +// SVD Line: 2048 + +// SFDITEM_FIELD__GCR_PM_RTCWKEN +// RTCWKEN +// +// [Bit 5] RW (@ 0x4000000C) \nRTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.\n0 : dis = Wake Up Disable.\n1 : en = Wake Up Enable. +// +// ( (unsigned int) GCR_PM ) +// RTCWKEN +// <0=> 0: dis = Wake Up Disable. +// <1=> 1: en = Wake Up Enable. +// +// +// + + +// -------------------------------- Field Item: GCR_PM_HIRCPD ----------------------------------- +// SVD Line: 2066 + +// SFDITEM_FIELD__GCR_PM_HIRCPD +// HIRCPD +// +// [Bit 15] RW (@ 0x4000000C) \nHIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode.\n0 : active = Mode is Active.\n1 : deepsleep = Powered down in DEEPSLEEP. +// +// ( (unsigned int) GCR_PM ) +// HIRCPD +// <0=> 0: active = Mode is Active. +// <1=> 1: deepsleep = Powered down in DEEPSLEEP. +// +// +// + + +// --------------------------------- Register RTree: GCR_PM ------------------------------------- +// SVD Line: 2002 + +// SFDITEM_REG__GCR_PM +// PM +// +// [Bits 31..0] RW (@ 0x4000000C) Power Management. +// ( (unsigned int)((GCR_PM >> 0) & 0xFFFFFFFF), ((GCR_PM = (GCR_PM & ~(0x8037UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8037) << 0 ) ) )) +// SFDITEM_FIELD__GCR_PM_MODE +// SFDITEM_FIELD__GCR_PM_GPIOWKEN +// SFDITEM_FIELD__GCR_PM_RTCWKEN +// SFDITEM_FIELD__GCR_PM_HIRCPD +// +// + + +// ---------------------------- Register Item Address: GCR_PCKDIV ------------------------------- +// SVD Line: 2086 + +unsigned int GCR_PCKDIV __AT (0x40000018); + + + +// ------------------------------ Field Item: GCR_PCKDIV_AONCD ---------------------------------- +// SVD Line: 2092 + +// SFDITEM_FIELD__GCR_PCKDIV_AONCD +// AONCD +// +// [Bits 1..0] RW (@ 0x40000018) \nAlways-ON(AON) domain CLock Divider. These bits define the AON domain clock divider.\n0 : div_4 = PCLK divide by 4.\n1 : div_8 = PCLK divide by 8.\n2 : div_16 = PCLK divide by 16.\n3 : div_32 = PCLK divide by 32. +// +// ( (unsigned int) GCR_PCKDIV ) +// AONCD +// <0=> 0: div_4 = PCLK divide by 4. +// <1=> 1: div_8 = PCLK divide by 8. +// <2=> 2: div_16 = PCLK divide by 16. +// <3=> 3: div_32 = PCLK divide by 32. +// +// +// + + +// ------------------------------- Register RTree: GCR_PCKDIV ----------------------------------- +// SVD Line: 2086 + +// SFDITEM_REG__GCR_PCKDIV +// PCKDIV +// +// [Bits 31..0] RW (@ 0x40000018) Peripheral Clock Divider. +// ( (unsigned int)((GCR_PCKDIV >> 0) & 0xFFFFFFFF), ((GCR_PCKDIV = (GCR_PCKDIV & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__GCR_PCKDIV_AONCD +// +// + + +// --------------------------- Register Item Address: GCR_PERCKCN0 ------------------------------ +// SVD Line: 2122 + +unsigned int GCR_PERCKCN0 __AT (0x40000024); + + + +// ----------------------------- Field Item: GCR_PERCKCN0_GPIO0D -------------------------------- +// SVD Line: 2127 + +// SFDITEM_FIELD__GCR_PERCKCN0_GPIO0D +// GPIO0D +// +// [Bit 0] RW (@ 0x40000024) \nGPIO0 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// GPIO0D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ------------------------------ Field Item: GCR_PERCKCN0_DMAD --------------------------------- +// SVD Line: 2146 + +// SFDITEM_FIELD__GCR_PERCKCN0_DMAD +// DMAD +// +// [Bit 5] RW (@ 0x40000024) \nDMA Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// DMAD +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ----------------------------- Field Item: GCR_PERCKCN0_SPI0D --------------------------------- +// SVD Line: 2165 + +// SFDITEM_FIELD__GCR_PERCKCN0_SPI0D +// SPI0D +// +// [Bit 6] RW (@ 0x40000024) \nSPI 0 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// SPI0D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ----------------------------- Field Item: GCR_PERCKCN0_SPI1D --------------------------------- +// SVD Line: 2184 + +// SFDITEM_FIELD__GCR_PERCKCN0_SPI1D +// SPI1D +// +// [Bit 7] RW (@ 0x40000024) \nSPI 1 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// SPI1D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ----------------------------- Field Item: GCR_PERCKCN0_UART0D -------------------------------- +// SVD Line: 2203 + +// SFDITEM_FIELD__GCR_PERCKCN0_UART0D +// UART0D +// +// [Bit 9] RW (@ 0x40000024) \nUART 0 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// UART0D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ----------------------------- Field Item: GCR_PERCKCN0_UART1D -------------------------------- +// SVD Line: 2222 + +// SFDITEM_FIELD__GCR_PERCKCN0_UART1D +// UART1D +// +// [Bit 10] RW (@ 0x40000024) \nUART 1 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// UART1D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ----------------------------- Field Item: GCR_PERCKCN0_I2C0D --------------------------------- +// SVD Line: 2241 + +// SFDITEM_FIELD__GCR_PERCKCN0_I2C0D +// I2C0D +// +// [Bit 13] RW (@ 0x40000024) \nI2C 0 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// I2C0D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ------------------------------ Field Item: GCR_PERCKCN0_T0D ---------------------------------- +// SVD Line: 2260 + +// SFDITEM_FIELD__GCR_PERCKCN0_T0D +// T0D +// +// [Bit 15] RW (@ 0x40000024) \nTimer 0 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// T0D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ------------------------------ Field Item: GCR_PERCKCN0_T1D ---------------------------------- +// SVD Line: 2279 + +// SFDITEM_FIELD__GCR_PERCKCN0_T1D +// T1D +// +// [Bit 16] RW (@ 0x40000024) \nTimer 1 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// T1D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ------------------------------ Field Item: GCR_PERCKCN0_T2D ---------------------------------- +// SVD Line: 2298 + +// SFDITEM_FIELD__GCR_PERCKCN0_T2D +// T2D +// +// [Bit 17] RW (@ 0x40000024) \nTimer 2 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// T2D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ----------------------------- Field Item: GCR_PERCKCN0_I2C1D --------------------------------- +// SVD Line: 2317 + +// SFDITEM_FIELD__GCR_PERCKCN0_I2C1D +// I2C1D +// +// [Bit 28] RW (@ 0x40000024) \nI2C 1 Disable.\n0 : en = enable it.\n1 : dis = disable it. +// +// ( (unsigned int) GCR_PERCKCN0 ) +// I2C1D +// <0=> 0: en = enable it. +// <1=> 1: dis = disable it. +// +// +// + + +// ------------------------------ Register RTree: GCR_PERCKCN0 ---------------------------------- +// SVD Line: 2122 + +// SFDITEM_REG__GCR_PERCKCN0 +// PERCKCN0 +// +// [Bits 31..0] RW (@ 0x40000024) Peripheral Clock Disable. +// ( (unsigned int)((GCR_PERCKCN0 >> 0) & 0xFFFFFFFF), ((GCR_PERCKCN0 = (GCR_PERCKCN0 & ~(0x1003A6E1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1003A6E1) << 0 ) ) )) +// SFDITEM_FIELD__GCR_PERCKCN0_GPIO0D +// SFDITEM_FIELD__GCR_PERCKCN0_DMAD +// SFDITEM_FIELD__GCR_PERCKCN0_SPI0D +// SFDITEM_FIELD__GCR_PERCKCN0_SPI1D +// SFDITEM_FIELD__GCR_PERCKCN0_UART0D +// SFDITEM_FIELD__GCR_PERCKCN0_UART1D +// SFDITEM_FIELD__GCR_PERCKCN0_I2C0D +// SFDITEM_FIELD__GCR_PERCKCN0_T0D +// SFDITEM_FIELD__GCR_PERCKCN0_T1D +// SFDITEM_FIELD__GCR_PERCKCN0_T2D +// SFDITEM_FIELD__GCR_PERCKCN0_I2C1D +// +// + + +// --------------------------- Register Item Address: GCR_MEMCKCN ------------------------------- +// SVD Line: 2338 + +unsigned int GCR_MEMCKCN __AT (0x40000028); + + + +// ------------------------------- Field Item: GCR_MEMCKCN_FWS ---------------------------------- +// SVD Line: 2343 + +// SFDITEM_FIELD__GCR_MEMCKCN_FWS +// FWS +// +// [Bits 2..0] RW (@ 0x40000028) Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. +// +// ( (unsigned char)((GCR_MEMCKCN >> 0) & 0x7), ((GCR_MEMCKCN = (GCR_MEMCKCN & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) )) +// +// +// + + +// ---------------------------- Field Item: GCR_MEMCKCN_SYSRAM0LS ------------------------------- +// SVD Line: 2349 + +// SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM0LS +// SYSRAM0LS +// +// [Bit 8] RW (@ 0x40000028) \nSystem RAM 0 Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. +// +// ( (unsigned int) GCR_MEMCKCN ) +// SYSRAM0LS +// <0=> 0: active = Memory is active. +// <1=> 1: light_sleep = Memory is in Light Sleep mode. +// +// +// + + +// ---------------------------- Field Item: GCR_MEMCKCN_SYSRAM1LS ------------------------------- +// SVD Line: 2367 + +// SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM1LS +// SYSRAM1LS +// +// [Bit 9] RW (@ 0x40000028) \nSystem RAM 1 Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. +// +// ( (unsigned int) GCR_MEMCKCN ) +// SYSRAM1LS +// <0=> 0: active = Memory is active. +// <1=> 1: light_sleep = Memory is in Light Sleep mode. +// +// +// + + +// ---------------------------- Field Item: GCR_MEMCKCN_SYSRAM2LS ------------------------------- +// SVD Line: 2385 + +// SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM2LS +// SYSRAM2LS +// +// [Bit 10] RW (@ 0x40000028) \nSystem RAM 2 Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. +// +// ( (unsigned int) GCR_MEMCKCN ) +// SYSRAM2LS +// <0=> 0: active = Memory is active. +// <1=> 1: light_sleep = Memory is in Light Sleep mode. +// +// +// + + +// ---------------------------- Field Item: GCR_MEMCKCN_SYSRAM3LS ------------------------------- +// SVD Line: 2403 + +// SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM3LS +// SYSRAM3LS +// +// [Bit 11] RW (@ 0x40000028) \nSystem RAM 3 Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. +// +// ( (unsigned int) GCR_MEMCKCN ) +// SYSRAM3LS +// <0=> 0: active = Memory is active. +// <1=> 1: light_sleep = Memory is in Light Sleep mode. +// +// +// + + +// ---------------------------- Field Item: GCR_MEMCKCN_ICACHELS -------------------------------- +// SVD Line: 2421 + +// SFDITEM_FIELD__GCR_MEMCKCN_ICACHELS +// ICACHELS +// +// [Bit 12] RW (@ 0x40000028) \nICache RAM Light Sleep Mode.\n0 : active = Memory is active.\n1 : light_sleep = Memory is in Light Sleep mode. +// +// ( (unsigned int) GCR_MEMCKCN ) +// ICACHELS +// <0=> 0: active = Memory is active. +// <1=> 1: light_sleep = Memory is in Light Sleep mode. +// +// +// + + +// ------------------------------- Register RTree: GCR_MEMCKCN ---------------------------------- +// SVD Line: 2338 + +// SFDITEM_REG__GCR_MEMCKCN +// MEMCKCN +// +// [Bits 31..0] RW (@ 0x40000028) Memory Clock Control Register. +// ( (unsigned int)((GCR_MEMCKCN >> 0) & 0xFFFFFFFF), ((GCR_MEMCKCN = (GCR_MEMCKCN & ~(0x1F07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F07) << 0 ) ) )) +// SFDITEM_FIELD__GCR_MEMCKCN_FWS +// SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM0LS +// SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM1LS +// SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM2LS +// SFDITEM_FIELD__GCR_MEMCKCN_SYSRAM3LS +// SFDITEM_FIELD__GCR_MEMCKCN_ICACHELS +// +// + + +// ---------------------------- Register Item Address: GCR_MEMZCN ------------------------------- +// SVD Line: 2441 + +unsigned int GCR_MEMZCN __AT (0x4000002C); + + + +// ------------------------------ Field Item: GCR_MEMZCN_SRAM0Z --------------------------------- +// SVD Line: 2446 + +// SFDITEM_FIELD__GCR_MEMZCN_SRAM0Z +// SRAM0Z +// +// [Bit 0] RW (@ 0x4000002C) \nSystem RAM Block 0.\n0 : nop = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) GCR_MEMZCN ) +// SRAM0Z +// <0=> 0: nop = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// ----------------------------- Field Item: GCR_MEMZCN_ICACHEZ --------------------------------- +// SVD Line: 2464 + +// SFDITEM_FIELD__GCR_MEMZCN_ICACHEZ +// ICACHEZ +// +// [Bit 1] RW (@ 0x4000002C) \nInstruction Cache.\n0 : nop = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) GCR_MEMZCN ) +// ICACHEZ +// <0=> 0: nop = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// ------------------------------- Register RTree: GCR_MEMZCN ----------------------------------- +// SVD Line: 2441 + +// SFDITEM_REG__GCR_MEMZCN +// MEMZCN +// +// [Bits 31..0] RW (@ 0x4000002C) Memory Zeroize Control. +// ( (unsigned int)((GCR_MEMZCN >> 0) & 0xFFFFFFFF), ((GCR_MEMZCN = (GCR_MEMZCN & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__GCR_MEMZCN_SRAM0Z +// SFDITEM_FIELD__GCR_MEMZCN_ICACHEZ +// +// + + +// ----------------------------- Register Item Address: GCR_SCCK -------------------------------- +// SVD Line: 2484 + +unsigned int GCR_SCCK __AT (0x40000034); + + + +// --------------------------------- Register Item: GCR_SCCK ------------------------------------ +// SVD Line: 2484 + +// SFDITEM_REG__GCR_SCCK +// SCCK +// [Bits 31..0] RW (@ 0x40000034) Smart Card Clock Control. +// +// ( (unsigned int)((GCR_SCCK >> 0) & 0xFFFFFFFF), ((GCR_SCCK = (GCR_SCCK & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register Item Address: GCR_MPRI0 -------------------------------- +// SVD Line: 2490 + +unsigned int GCR_MPRI0 __AT (0x40000038); + + + +// -------------------------------- Register Item: GCR_MPRI0 ------------------------------------ +// SVD Line: 2490 + +// SFDITEM_REG__GCR_MPRI0 +// MPRI0 +// [Bits 31..0] RW (@ 0x40000038) Master Priority Control Register 0. +// +// ( (unsigned int)((GCR_MPRI0 >> 0) & 0xFFFFFFFF), ((GCR_MPRI0 = (GCR_MPRI0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register Item Address: GCR_MPRI1 -------------------------------- +// SVD Line: 2496 + +unsigned int GCR_MPRI1 __AT (0x4000003C); + + + +// -------------------------------- Register Item: GCR_MPRI1 ------------------------------------ +// SVD Line: 2496 + +// SFDITEM_REG__GCR_MPRI1 +// MPRI1 +// [Bits 31..0] RW (@ 0x4000003C) Mater Priority Control Register 1. +// +// ( (unsigned int)((GCR_MPRI1 >> 0) & 0xFFFFFFFF), ((GCR_MPRI1 = (GCR_MPRI1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register Item Address: GCR_SYSST -------------------------------- +// SVD Line: 2502 + +unsigned int GCR_SYSST __AT (0x40000040); + + + +// ----------------------------- Field Item: GCR_SYSST_ICECLOCK --------------------------------- +// SVD Line: 2507 + +// SFDITEM_FIELD__GCR_SYSST_ICECLOCK +// ICECLOCK +// +// [Bit 0] RW (@ 0x40000040) \nARM ICE Lock Status.\n0 : unlocked = ICE is unlocked.\n1 : locked = ICE is locked. +// +// ( (unsigned int) GCR_SYSST ) +// ICECLOCK +// <0=> 0: unlocked = ICE is unlocked. +// <1=> 1: locked = ICE is locked. +// +// +// + + +// ---------------------------- Field Item: GCR_SYSST_CODEINTERR -------------------------------- +// SVD Line: 2525 + +// SFDITEM_FIELD__GCR_SYSST_CODEINTERR +// CODEINTERR +// +// [Bit 1] RW (@ 0x40000040) \nCode Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface.\n0 : norm = Normal Operating Condition.\n1 : code = Code Integrity Error. +// +// ( (unsigned int) GCR_SYSST ) +// CODEINTERR +// <0=> 0: norm = Normal Operating Condition. +// <1=> 1: code = Code Integrity Error. +// +// +// + + +// ------------------------------ Field Item: GCR_SYSST_SCMEMF ---------------------------------- +// SVD Line: 2543 + +// SFDITEM_FIELD__GCR_SYSST_SCMEMF +// SCMEMF +// +// [Bit 5] RW (@ 0x40000040) \nSystem Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.\n0 : norm = Normal Operating Condition.\n1 : memory = Memory Fault. +// +// ( (unsigned int) GCR_SYSST ) +// SCMEMF +// <0=> 0: norm = Normal Operating Condition. +// <1=> 1: memory = Memory Fault. +// +// +// + + +// -------------------------------- Register RTree: GCR_SYSST ----------------------------------- +// SVD Line: 2502 + +// SFDITEM_REG__GCR_SYSST +// SYSST +// +// [Bits 31..0] RW (@ 0x40000040) System Status Register. +// ( (unsigned int)((GCR_SYSST >> 0) & 0xFFFFFFFF), ((GCR_SYSST = (GCR_SYSST & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) )) +// SFDITEM_FIELD__GCR_SYSST_ICECLOCK +// SFDITEM_FIELD__GCR_SYSST_CODEINTERR +// SFDITEM_FIELD__GCR_SYSST_SCMEMF +// +// + + +// ---------------------------- Register Item Address: GCR_RSTR1 -------------------------------- +// SVD Line: 2563 + +unsigned int GCR_RSTR1 __AT (0x40000044); + + + +// ------------------------------- Field Item: GCR_RSTR1_I2C1 ----------------------------------- +// SVD Line: 2568 + +// SFDITEM_FIELD__GCR_RSTR1_I2C1 +// I2C1 +// +// [Bit 0] RW (@ 0x40000044) \nI2C1 Reset.\n0 : RFU = Reserved. Do not use.\n1 : reset = Starts reset operation. +// +// ( (unsigned int) GCR_RSTR1 ) +// I2C1 +// <0=> 0: RFU = Reserved. Do not use. +// <1=> 1: reset = Starts reset operation. +// +// +// + + +// -------------------------------- Register RTree: GCR_RSTR1 ----------------------------------- +// SVD Line: 2563 + +// SFDITEM_REG__GCR_RSTR1 +// RSTR1 +// +// [Bits 31..0] RW (@ 0x40000044) Reset 1. +// ( (unsigned int)((GCR_RSTR1 >> 0) & 0xFFFFFFFF), ((GCR_RSTR1 = (GCR_RSTR1 & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) +// SFDITEM_FIELD__GCR_RSTR1_I2C1 +// +// + + +// --------------------------- Register Item Address: GCR_PERCKCN1 ------------------------------ +// SVD Line: 2604 + +unsigned int GCR_PERCKCN1 __AT (0x40000048); + + + +// ------------------------------ Field Item: GCR_PERCKCN1_FLCD --------------------------------- +// SVD Line: 2609 + +// SFDITEM_FIELD__GCR_PERCKCN1_FLCD +// FLCD +// +// [Bit 3] RW (@ 0x40000048) \nSecure Flash Controller Disable.\n0 : en = Enable.\n1 : dis = Disable. +// +// ( (unsigned int) GCR_PERCKCN1 ) +// FLCD +// <0=> 0: en = Enable. +// <1=> 1: dis = Disable. +// +// +// + + +// ---------------------------- Field Item: GCR_PERCKCN1_ICACHED -------------------------------- +// SVD Line: 2627 + +// SFDITEM_FIELD__GCR_PERCKCN1_ICACHED +// ICACHED +// +// [Bit 11] RW (@ 0x40000048) \nICache Clock Disable.\n0 : en = Enable.\n1 : dis = Disable. +// +// ( (unsigned int) GCR_PERCKCN1 ) +// ICACHED +// <0=> 0: en = Enable. +// <1=> 1: dis = Disable. +// +// +// + + +// ------------------------------ Register RTree: GCR_PERCKCN1 ---------------------------------- +// SVD Line: 2604 + +// SFDITEM_REG__GCR_PERCKCN1 +// PERCKCN1 +// +// [Bits 31..0] RW (@ 0x40000048) Peripheral Clock Disable. +// ( (unsigned int)((GCR_PERCKCN1 >> 0) & 0xFFFFFFFF), ((GCR_PERCKCN1 = (GCR_PERCKCN1 & ~(0x808UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x808) << 0 ) ) )) +// SFDITEM_FIELD__GCR_PERCKCN1_FLCD +// SFDITEM_FIELD__GCR_PERCKCN1_ICACHED +// +// + + +// ---------------------------- Register Item Address: GCR_EVTEN -------------------------------- +// SVD Line: 2647 + +unsigned int GCR_EVTEN __AT (0x4000004C); + + + +// ----------------------------- Field Item: GCR_EVTEN_DMAEVENT --------------------------------- +// SVD Line: 2652 + +// SFDITEM_FIELD__GCR_EVTEN_DMAEVENT +// DMAEVENT +// +// [Bit 0] RW (@ 0x4000004C) Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. +// +// ( (unsigned int) GCR_EVTEN ) +// DMAEVENT +// +// +// + + +// ------------------------------ Field Item: GCR_EVTEN_RXEVENT --------------------------------- +// SVD Line: 2658 + +// SFDITEM_FIELD__GCR_EVTEN_RXEVENT +// RXEVENT +// +// [Bit 1] RW (@ 0x4000004C) Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. +// +// ( (unsigned int) GCR_EVTEN ) +// RXEVENT +// +// +// + + +// -------------------------------- Register RTree: GCR_EVTEN ----------------------------------- +// SVD Line: 2647 + +// SFDITEM_REG__GCR_EVTEN +// EVTEN +// +// [Bits 31..0] RW (@ 0x4000004C) Event Enable Register. +// ( (unsigned int)((GCR_EVTEN >> 0) & 0xFFFFFFFF), ((GCR_EVTEN = (GCR_EVTEN & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__GCR_EVTEN_DMAEVENT +// SFDITEM_FIELD__GCR_EVTEN_RXEVENT +// +// + + +// --------------------------- Register Item Address: GCR_REVISION ------------------------------ +// SVD Line: 2666 + +unsigned int GCR_REVISION __AT (0x40000050); + + + +// ---------------------------- Field Item: GCR_REVISION_REVISION ------------------------------- +// SVD Line: 2672 + +// SFDITEM_FIELD__GCR_REVISION_REVISION +// REVISION +// +// [Bits 15..0] RO (@ 0x40000050) Manufacturer Chip Revision. +// +// ( (unsigned short)((GCR_REVISION >> 0) & 0xFFFF) ) +// +// +// + + +// ------------------------------ Register RTree: GCR_REVISION ---------------------------------- +// SVD Line: 2666 + +// SFDITEM_REG__GCR_REVISION +// REVISION +// +// [Bits 31..0] RO (@ 0x40000050) Revision Register. +// ( (unsigned int)((GCR_REVISION >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__GCR_REVISION_REVISION +// +// + + +// ---------------------------- Register Item Address: GCR_SYSSIE ------------------------------- +// SVD Line: 2680 + +unsigned int GCR_SYSSIE __AT (0x40000054); + + + +// ----------------------------- Field Item: GCR_SYSSIE_ICEULIE --------------------------------- +// SVD Line: 2685 + +// SFDITEM_FIELD__GCR_SYSSIE_ICEULIE +// ICEULIE +// +// [Bit 0] RW (@ 0x40000054) \nARM ICE Unlock Interrupt Enable.\n0 : dis = disabled.\n1 : en = enabled. +// +// ( (unsigned int) GCR_SYSSIE ) +// ICEULIE +// <0=> 0: dis = disabled. +// <1=> 1: en = enabled. +// +// +// + + +// ------------------------------ Field Item: GCR_SYSSIE_CIEIE ---------------------------------- +// SVD Line: 2703 + +// SFDITEM_FIELD__GCR_SYSSIE_CIEIE +// CIEIE +// +// [Bit 1] RW (@ 0x40000054) \nCode Integrity Error Interrupt Enable.\n0 : dis = disabled.\n1 : en = enabled. +// +// ( (unsigned int) GCR_SYSSIE ) +// CIEIE +// <0=> 0: dis = disabled. +// <1=> 1: en = enabled. +// +// +// + + +// ------------------------------ Field Item: GCR_SYSSIE_SCMFIE --------------------------------- +// SVD Line: 2721 + +// SFDITEM_FIELD__GCR_SYSSIE_SCMFIE +// SCMFIE +// +// [Bit 5] RW (@ 0x40000054) \nSystem Cache Memory Fault Interrupt Enable.\n0 : dis = disabled.\n1 : en = enabled. +// +// ( (unsigned int) GCR_SYSSIE ) +// SCMFIE +// <0=> 0: dis = disabled. +// <1=> 1: en = enabled. +// +// +// + + +// ------------------------------- Register RTree: GCR_SYSSIE ----------------------------------- +// SVD Line: 2680 + +// SFDITEM_REG__GCR_SYSSIE +// SYSSIE +// +// [Bits 31..0] RW (@ 0x40000054) System Status Interrupt Enable Register. +// ( (unsigned int)((GCR_SYSSIE >> 0) & 0xFFFFFFFF), ((GCR_SYSSIE = (GCR_SYSSIE & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) )) +// SFDITEM_FIELD__GCR_SYSSIE_ICEULIE +// SFDITEM_FIELD__GCR_SYSSIE_CIEIE +// SFDITEM_FIELD__GCR_SYSSIE_SCMFIE +// +// + + +// ---------------------------------- Peripheral View: GCR -------------------------------------- +// SVD Line: 1188 + +// GCR +// GCR +// SFDITEM_REG__GCR_SCON +// SFDITEM_REG__GCR_RSTR0 +// SFDITEM_REG__GCR_CLKCN +// SFDITEM_REG__GCR_PM +// SFDITEM_REG__GCR_PCKDIV +// SFDITEM_REG__GCR_PERCKCN0 +// SFDITEM_REG__GCR_MEMCKCN +// SFDITEM_REG__GCR_MEMZCN +// SFDITEM_REG__GCR_SCCK +// SFDITEM_REG__GCR_MPRI0 +// SFDITEM_REG__GCR_MPRI1 +// SFDITEM_REG__GCR_SYSST +// SFDITEM_REG__GCR_RSTR1 +// SFDITEM_REG__GCR_PERCKCN1 +// SFDITEM_REG__GCR_EVTEN +// SFDITEM_REG__GCR_REVISION +// SFDITEM_REG__GCR_SYSSIE +// +// + + +// ----------------------------- Register Item Address: GPIO0_EN -------------------------------- +// SVD Line: 2760 + +unsigned int GPIO0_EN __AT (0x40008000); + + + +// ------------------------------ Field Item: GPIO0_EN_GPIO_EN ---------------------------------- +// SVD Line: 2765 + +// SFDITEM_FIELD__GPIO0_EN_GPIO_EN +// GPIO_EN +// +// [Bits 31..0] RW (@ 0x40008000) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN >> 0) & 0xFFFFFFFF), ((GPIO0_EN = (GPIO0_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: GPIO0_EN ------------------------------------ +// SVD Line: 2760 + +// SFDITEM_REG__GPIO0_EN +// EN +// +// [Bits 31..0] RW (@ 0x40008000) GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. +// ( (unsigned int)((GPIO0_EN >> 0) & 0xFFFFFFFF), ((GPIO0_EN = (GPIO0_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN_GPIO_EN +// +// + + +// --------------------------- Register Item Address: GPIO0_EN_SET ------------------------------ +// SVD Line: 2785 + +unsigned int GPIO0_EN_SET __AT (0x40008004); + + + +// ------------------------------ Field Item: GPIO0_EN_SET_ALL ---------------------------------- +// SVD Line: 2790 + +// SFDITEM_FIELD__GPIO0_EN_SET_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008004) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN_SET = (GPIO0_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_EN_SET ---------------------------------- +// SVD Line: 2785 + +// SFDITEM_REG__GPIO0_EN_SET +// EN_SET +// +// [Bits 31..0] RW (@ 0x40008004) GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN_SET = (GPIO0_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN_SET_ALL +// +// + + +// --------------------------- Register Item Address: GPIO0_EN_CLR ------------------------------ +// SVD Line: 2798 + +unsigned int GPIO0_EN_CLR __AT (0x40008008); + + + +// ------------------------------ Field Item: GPIO0_EN_CLR_ALL ---------------------------------- +// SVD Line: 2803 + +// SFDITEM_FIELD__GPIO0_EN_CLR_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008008) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN_CLR = (GPIO0_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_EN_CLR ---------------------------------- +// SVD Line: 2798 + +// SFDITEM_REG__GPIO0_EN_CLR +// EN_CLR +// +// [Bits 31..0] RW (@ 0x40008008) GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN_CLR = (GPIO0_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN_CLR_ALL +// +// + + +// --------------------------- Register Item Address: GPIO0_OUT_EN ------------------------------ +// SVD Line: 2811 + +unsigned int GPIO0_OUT_EN __AT (0x4000800C); + + + +// -------------------------- Field Item: GPIO0_OUT_EN_GPIO_OUT_EN ------------------------------ +// SVD Line: 2816 + +// SFDITEM_FIELD__GPIO0_OUT_EN_GPIO_OUT_EN +// GPIO_OUT_EN +// +// [Bits 31..0] RW (@ 0x4000800C) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_OUT_EN >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN = (GPIO0_OUT_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_OUT_EN ---------------------------------- +// SVD Line: 2811 + +// SFDITEM_REG__GPIO0_OUT_EN +// OUT_EN +// +// [Bits 31..0] RW (@ 0x4000800C) GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. +// ( (unsigned int)((GPIO0_OUT_EN >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN = (GPIO0_OUT_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_OUT_EN_GPIO_OUT_EN +// +// + + +// ------------------------- Register Item Address: GPIO0_OUT_EN_SET ---------------------------- +// SVD Line: 2836 + +unsigned int GPIO0_OUT_EN_SET __AT (0x40008010); + + + +// ---------------------------- Field Item: GPIO0_OUT_EN_SET_ALL -------------------------------- +// SVD Line: 2841 + +// SFDITEM_FIELD__GPIO0_OUT_EN_SET_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008010) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_OUT_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN_SET = (GPIO0_OUT_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: GPIO0_OUT_EN_SET -------------------------------- +// SVD Line: 2836 + +// SFDITEM_REG__GPIO0_OUT_EN_SET +// OUT_EN_SET +// +// [Bits 31..0] RW (@ 0x40008010) GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_OUT_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN_SET = (GPIO0_OUT_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_OUT_EN_SET_ALL +// +// + + +// ------------------------- Register Item Address: GPIO0_OUT_EN_CLR ---------------------------- +// SVD Line: 2849 + +unsigned int GPIO0_OUT_EN_CLR __AT (0x40008014); + + + +// ---------------------------- Field Item: GPIO0_OUT_EN_CLR_ALL -------------------------------- +// SVD Line: 2854 + +// SFDITEM_FIELD__GPIO0_OUT_EN_CLR_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008014) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_OUT_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN_CLR = (GPIO0_OUT_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: GPIO0_OUT_EN_CLR -------------------------------- +// SVD Line: 2849 + +// SFDITEM_REG__GPIO0_OUT_EN_CLR +// OUT_EN_CLR +// +// [Bits 31..0] RW (@ 0x40008014) GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_OUT_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_EN_CLR = (GPIO0_OUT_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_OUT_EN_CLR_ALL +// +// + + +// ---------------------------- Register Item Address: GPIO0_OUT -------------------------------- +// SVD Line: 2862 + +unsigned int GPIO0_OUT __AT (0x40008018); + + + +// ----------------------------- Field Item: GPIO0_OUT_GPIO_OUT --------------------------------- +// SVD Line: 2867 + +// SFDITEM_FIELD__GPIO0_OUT_GPIO_OUT +// GPIO_OUT +// +// [Bits 31..0] RW (@ 0x40008018) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_OUT >> 0) & 0xFFFFFFFF), ((GPIO0_OUT = (GPIO0_OUT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: GPIO0_OUT ----------------------------------- +// SVD Line: 2862 + +// SFDITEM_REG__GPIO0_OUT +// OUT +// +// [Bits 31..0] RW (@ 0x40008018) GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. +// ( (unsigned int)((GPIO0_OUT >> 0) & 0xFFFFFFFF), ((GPIO0_OUT = (GPIO0_OUT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_OUT_GPIO_OUT +// +// + + +// -------------------------- Register Item Address: GPIO0_OUT_SET ------------------------------ +// SVD Line: 2887 + +unsigned int GPIO0_OUT_SET __AT (0x4000801C); + + + +// ------------------------- Field Item: GPIO0_OUT_SET_GPIO_OUT_SET ----------------------------- +// SVD Line: 2893 + +// SFDITEM_FIELD__GPIO0_OUT_SET_GPIO_OUT_SET +// GPIO_OUT_SET +// +// [Bits 31..0] WO (@ 0x4000801C) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_OUT_SET >> 0) & 0x0), ((GPIO0_OUT_SET = (GPIO0_OUT_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_OUT_SET --------------------------------- +// SVD Line: 2887 + +// SFDITEM_REG__GPIO0_OUT_SET +// OUT_SET +// +// [Bits 31..0] WO (@ 0x4000801C) GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_OUT_SET >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_SET = (GPIO0_OUT_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_OUT_SET_GPIO_OUT_SET +// +// + + +// -------------------------- Register Item Address: GPIO0_OUT_CLR ------------------------------ +// SVD Line: 2913 + +unsigned int GPIO0_OUT_CLR __AT (0x40008020); + + + +// ------------------------- Field Item: GPIO0_OUT_CLR_GPIO_OUT_CLR ----------------------------- +// SVD Line: 2919 + +// SFDITEM_FIELD__GPIO0_OUT_CLR_GPIO_OUT_CLR +// GPIO_OUT_CLR +// +// [Bits 31..0] WO (@ 0x40008020) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_OUT_CLR >> 0) & 0x0), ((GPIO0_OUT_CLR = (GPIO0_OUT_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_OUT_CLR --------------------------------- +// SVD Line: 2913 + +// SFDITEM_REG__GPIO0_OUT_CLR +// OUT_CLR +// +// [Bits 31..0] WO (@ 0x40008020) GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_OUT_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_OUT_CLR = (GPIO0_OUT_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_OUT_CLR_GPIO_OUT_CLR +// +// + + +// ----------------------------- Register Item Address: GPIO0_IN -------------------------------- +// SVD Line: 2927 + +unsigned int GPIO0_IN __AT (0x40008024); + + + +// ------------------------------ Field Item: GPIO0_IN_GPIO_IN ---------------------------------- +// SVD Line: 2933 + +// SFDITEM_FIELD__GPIO0_IN_GPIO_IN +// GPIO_IN +// +// [Bits 31..0] RO (@ 0x40008024) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_IN >> 0) & 0xFFFFFFFF) ) +// +// +// + + +// -------------------------------- Register RTree: GPIO0_IN ------------------------------------ +// SVD Line: 2927 + +// SFDITEM_REG__GPIO0_IN +// IN +// +// [Bits 31..0] RO (@ 0x40008024) GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. +// ( (unsigned int)((GPIO0_IN >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__GPIO0_IN_GPIO_IN +// +// + + +// -------------------------- Register Item Address: GPIO0_INT_MOD ------------------------------ +// SVD Line: 2941 + +unsigned int GPIO0_INT_MOD __AT (0x40008028); + + + +// ------------------------- Field Item: GPIO0_INT_MOD_GPIO_INT_MOD ----------------------------- +// SVD Line: 2946 + +// SFDITEM_FIELD__GPIO0_INT_MOD_GPIO_INT_MOD +// GPIO_INT_MOD +// +// [Bits 31..0] RW (@ 0x40008028) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_INT_MOD >> 0) & 0xFFFFFFFF), ((GPIO0_INT_MOD = (GPIO0_INT_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_INT_MOD --------------------------------- +// SVD Line: 2941 + +// SFDITEM_REG__GPIO0_INT_MOD +// INT_MOD +// +// [Bits 31..0] RW (@ 0x40008028) GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. +// ( (unsigned int)((GPIO0_INT_MOD >> 0) & 0xFFFFFFFF), ((GPIO0_INT_MOD = (GPIO0_INT_MOD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_INT_MOD_GPIO_INT_MOD +// +// + + +// -------------------------- Register Item Address: GPIO0_INT_POL ------------------------------ +// SVD Line: 2966 + +unsigned int GPIO0_INT_POL __AT (0x4000802C); + + + +// ------------------------- Field Item: GPIO0_INT_POL_GPIO_INT_POL ----------------------------- +// SVD Line: 2971 + +// SFDITEM_FIELD__GPIO0_INT_POL_GPIO_INT_POL +// GPIO_INT_POL +// +// [Bits 31..0] RW (@ 0x4000802C) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_INT_POL >> 0) & 0xFFFFFFFF), ((GPIO0_INT_POL = (GPIO0_INT_POL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_INT_POL --------------------------------- +// SVD Line: 2966 + +// SFDITEM_REG__GPIO0_INT_POL +// INT_POL +// +// [Bits 31..0] RW (@ 0x4000802C) GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. +// ( (unsigned int)((GPIO0_INT_POL >> 0) & 0xFFFFFFFF), ((GPIO0_INT_POL = (GPIO0_INT_POL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_INT_POL_GPIO_INT_POL +// +// + + +// --------------------------- Register Item Address: GPIO0_INT_EN ------------------------------ +// SVD Line: 2991 + +unsigned int GPIO0_INT_EN __AT (0x40008034); + + + +// -------------------------- Field Item: GPIO0_INT_EN_GPIO_INT_EN ------------------------------ +// SVD Line: 2996 + +// SFDITEM_FIELD__GPIO0_INT_EN_GPIO_INT_EN +// GPIO_INT_EN +// +// [Bits 31..0] RW (@ 0x40008034) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_INT_EN >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN = (GPIO0_INT_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_INT_EN ---------------------------------- +// SVD Line: 2991 + +// SFDITEM_REG__GPIO0_INT_EN +// INT_EN +// +// [Bits 31..0] RW (@ 0x40008034) GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. +// ( (unsigned int)((GPIO0_INT_EN >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN = (GPIO0_INT_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_INT_EN_GPIO_INT_EN +// +// + + +// ------------------------- Register Item Address: GPIO0_INT_EN_SET ---------------------------- +// SVD Line: 3016 + +unsigned int GPIO0_INT_EN_SET __AT (0x40008038); + + + +// ---------------------- Field Item: GPIO0_INT_EN_SET_GPIO_INT_EN_SET -------------------------- +// SVD Line: 3021 + +// SFDITEM_FIELD__GPIO0_INT_EN_SET_GPIO_INT_EN_SET +// GPIO_INT_EN_SET +// +// [Bits 31..0] RW (@ 0x40008038) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_INT_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN_SET = (GPIO0_INT_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: GPIO0_INT_EN_SET -------------------------------- +// SVD Line: 3016 + +// SFDITEM_REG__GPIO0_INT_EN_SET +// INT_EN_SET +// +// [Bits 31..0] RW (@ 0x40008038) GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_INT_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN_SET = (GPIO0_INT_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_INT_EN_SET_GPIO_INT_EN_SET +// +// + + +// ------------------------- Register Item Address: GPIO0_INT_EN_CLR ---------------------------- +// SVD Line: 3041 + +unsigned int GPIO0_INT_EN_CLR __AT (0x4000803C); + + + +// ---------------------- Field Item: GPIO0_INT_EN_CLR_GPIO_INT_EN_CLR -------------------------- +// SVD Line: 3046 + +// SFDITEM_FIELD__GPIO0_INT_EN_CLR_GPIO_INT_EN_CLR +// GPIO_INT_EN_CLR +// +// [Bits 31..0] RW (@ 0x4000803C) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_INT_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN_CLR = (GPIO0_INT_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: GPIO0_INT_EN_CLR -------------------------------- +// SVD Line: 3041 + +// SFDITEM_REG__GPIO0_INT_EN_CLR +// INT_EN_CLR +// +// [Bits 31..0] RW (@ 0x4000803C) GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_INT_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_INT_EN_CLR = (GPIO0_INT_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_INT_EN_CLR_GPIO_INT_EN_CLR +// +// + + +// -------------------------- Register Item Address: GPIO0_INT_STAT ----------------------------- +// SVD Line: 3066 + +unsigned int GPIO0_INT_STAT __AT (0x40008040); + + + +// ------------------------ Field Item: GPIO0_INT_STAT_GPIO_INT_STAT ---------------------------- +// SVD Line: 3072 + +// SFDITEM_FIELD__GPIO0_INT_STAT_GPIO_INT_STAT +// GPIO_INT_STAT +// +// [Bits 31..0] RO (@ 0x40008040) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_INT_STAT >> 0) & 0xFFFFFFFF) ) +// +// +// + + +// ----------------------------- Register RTree: GPIO0_INT_STAT --------------------------------- +// SVD Line: 3066 + +// SFDITEM_REG__GPIO0_INT_STAT +// INT_STAT +// +// [Bits 31..0] RO (@ 0x40008040) GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. +// ( (unsigned int)((GPIO0_INT_STAT >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__GPIO0_INT_STAT_GPIO_INT_STAT +// +// + + +// -------------------------- Register Item Address: GPIO0_INT_CLR ------------------------------ +// SVD Line: 3092 + +unsigned int GPIO0_INT_CLR __AT (0x40008048); + + + +// ------------------------------ Field Item: GPIO0_INT_CLR_ALL --------------------------------- +// SVD Line: 3097 + +// SFDITEM_FIELD__GPIO0_INT_CLR_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008048) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_INT_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_INT_CLR = (GPIO0_INT_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_INT_CLR --------------------------------- +// SVD Line: 3092 + +// SFDITEM_REG__GPIO0_INT_CLR +// INT_CLR +// +// [Bits 31..0] RW (@ 0x40008048) GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_INT_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_INT_CLR = (GPIO0_INT_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_INT_CLR_ALL +// +// + + +// -------------------------- Register Item Address: GPIO0_WAKE_EN ------------------------------ +// SVD Line: 3105 + +unsigned int GPIO0_WAKE_EN __AT (0x4000804C); + + + +// ------------------------- Field Item: GPIO0_WAKE_EN_GPIO_WAKE_EN ----------------------------- +// SVD Line: 3110 + +// SFDITEM_FIELD__GPIO0_WAKE_EN_GPIO_WAKE_EN +// GPIO_WAKE_EN +// +// [Bits 31..0] RW (@ 0x4000804C) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_WAKE_EN >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN = (GPIO0_WAKE_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_WAKE_EN --------------------------------- +// SVD Line: 3105 + +// SFDITEM_REG__GPIO0_WAKE_EN +// WAKE_EN +// +// [Bits 31..0] RW (@ 0x4000804C) GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. +// ( (unsigned int)((GPIO0_WAKE_EN >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN = (GPIO0_WAKE_EN & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_WAKE_EN_GPIO_WAKE_EN +// +// + + +// ------------------------ Register Item Address: GPIO0_WAKE_EN_SET ---------------------------- +// SVD Line: 3130 + +unsigned int GPIO0_WAKE_EN_SET __AT (0x40008050); + + + +// ---------------------------- Field Item: GPIO0_WAKE_EN_SET_ALL ------------------------------- +// SVD Line: 3135 + +// SFDITEM_FIELD__GPIO0_WAKE_EN_SET_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008050) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_WAKE_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN_SET = (GPIO0_WAKE_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: GPIO0_WAKE_EN_SET ------------------------------- +// SVD Line: 3130 + +// SFDITEM_REG__GPIO0_WAKE_EN_SET +// WAKE_EN_SET +// +// [Bits 31..0] RW (@ 0x40008050) GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_WAKE_EN_SET >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN_SET = (GPIO0_WAKE_EN_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_WAKE_EN_SET_ALL +// +// + + +// ------------------------ Register Item Address: GPIO0_WAKE_EN_CLR ---------------------------- +// SVD Line: 3143 + +unsigned int GPIO0_WAKE_EN_CLR __AT (0x40008054); + + + +// ---------------------------- Field Item: GPIO0_WAKE_EN_CLR_ALL ------------------------------- +// SVD Line: 3148 + +// SFDITEM_FIELD__GPIO0_WAKE_EN_CLR_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008054) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_WAKE_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN_CLR = (GPIO0_WAKE_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: GPIO0_WAKE_EN_CLR ------------------------------- +// SVD Line: 3143 + +// SFDITEM_REG__GPIO0_WAKE_EN_CLR +// WAKE_EN_CLR +// +// [Bits 31..0] RW (@ 0x40008054) GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_WAKE_EN_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_WAKE_EN_CLR = (GPIO0_WAKE_EN_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_WAKE_EN_CLR_ALL +// +// + + +// ----------------------- Register Item Address: GPIO0_INT_DUAL_EDGE --------------------------- +// SVD Line: 3156 + +unsigned int GPIO0_INT_DUAL_EDGE __AT (0x4000805C); + + + +// ------------------- Field Item: GPIO0_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ----------------------- +// SVD Line: 3161 + +// SFDITEM_FIELD__GPIO0_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE +// GPIO_INT_DUAL_EDGE +// +// [Bits 31..0] RW (@ 0x4000805C) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_INT_DUAL_EDGE >> 0) & 0xFFFFFFFF), ((GPIO0_INT_DUAL_EDGE = (GPIO0_INT_DUAL_EDGE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// --------------------------- Register RTree: GPIO0_INT_DUAL_EDGE ------------------------------ +// SVD Line: 3156 + +// SFDITEM_REG__GPIO0_INT_DUAL_EDGE +// INT_DUAL_EDGE +// +// [Bits 31..0] RW (@ 0x4000805C) GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. +// ( (unsigned int)((GPIO0_INT_DUAL_EDGE >> 0) & 0xFFFFFFFF), ((GPIO0_INT_DUAL_EDGE = (GPIO0_INT_DUAL_EDGE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE +// +// + + +// -------------------------- Register Item Address: GPIO0_PAD_CFG1 ----------------------------- +// SVD Line: 3181 + +unsigned int GPIO0_PAD_CFG1 __AT (0x40008060); + + + +// ------------------------ Field Item: GPIO0_PAD_CFG1_GPIO_PAD_CFG1 ---------------------------- +// SVD Line: 3186 + +// SFDITEM_FIELD__GPIO0_PAD_CFG1_GPIO_PAD_CFG1 +// GPIO_PAD_CFG1 +// +// [Bits 31..0] RW (@ 0x40008060) The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. +// +// ( (unsigned int)((GPIO0_PAD_CFG1 >> 0) & 0xFFFFFFFF), ((GPIO0_PAD_CFG1 = (GPIO0_PAD_CFG1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register RTree: GPIO0_PAD_CFG1 --------------------------------- +// SVD Line: 3181 + +// SFDITEM_REG__GPIO0_PAD_CFG1 +// PAD_CFG1 +// +// [Bits 31..0] RW (@ 0x40008060) GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. +// ( (unsigned int)((GPIO0_PAD_CFG1 >> 0) & 0xFFFFFFFF), ((GPIO0_PAD_CFG1 = (GPIO0_PAD_CFG1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_PAD_CFG1_GPIO_PAD_CFG1 +// +// + + +// -------------------------- Register Item Address: GPIO0_PAD_CFG2 ----------------------------- +// SVD Line: 3211 + +unsigned int GPIO0_PAD_CFG2 __AT (0x40008064); + + + +// ------------------------ Field Item: GPIO0_PAD_CFG2_GPIO_PAD_CFG2 ---------------------------- +// SVD Line: 3216 + +// SFDITEM_FIELD__GPIO0_PAD_CFG2_GPIO_PAD_CFG2 +// GPIO_PAD_CFG2 +// +// [Bits 31..0] RW (@ 0x40008064) The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. +// +// ( (unsigned int)((GPIO0_PAD_CFG2 >> 0) & 0xFFFFFFFF), ((GPIO0_PAD_CFG2 = (GPIO0_PAD_CFG2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register RTree: GPIO0_PAD_CFG2 --------------------------------- +// SVD Line: 3211 + +// SFDITEM_REG__GPIO0_PAD_CFG2 +// PAD_CFG2 +// +// [Bits 31..0] RW (@ 0x40008064) GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. +// ( (unsigned int)((GPIO0_PAD_CFG2 >> 0) & 0xFFFFFFFF), ((GPIO0_PAD_CFG2 = (GPIO0_PAD_CFG2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_PAD_CFG2_GPIO_PAD_CFG2 +// +// + + +// ---------------------------- Register Item Address: GPIO0_EN1 -------------------------------- +// SVD Line: 3241 + +unsigned int GPIO0_EN1 __AT (0x40008068); + + + +// ----------------------------- Field Item: GPIO0_EN1_GPIO_EN1 --------------------------------- +// SVD Line: 3246 + +// SFDITEM_FIELD__GPIO0_EN1_GPIO_EN1 +// GPIO_EN1 +// +// [Bits 31..0] RW (@ 0x40008068) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN1 >> 0) & 0xFFFFFFFF), ((GPIO0_EN1 = (GPIO0_EN1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: GPIO0_EN1 ----------------------------------- +// SVD Line: 3241 + +// SFDITEM_REG__GPIO0_EN1 +// EN1 +// +// [Bits 31..0] RW (@ 0x40008068) GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. +// ( (unsigned int)((GPIO0_EN1 >> 0) & 0xFFFFFFFF), ((GPIO0_EN1 = (GPIO0_EN1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN1_GPIO_EN1 +// +// + + +// -------------------------- Register Item Address: GPIO0_EN1_SET ------------------------------ +// SVD Line: 3266 + +unsigned int GPIO0_EN1_SET __AT (0x4000806C); + + + +// ------------------------------ Field Item: GPIO0_EN1_SET_ALL --------------------------------- +// SVD Line: 3271 + +// SFDITEM_FIELD__GPIO0_EN1_SET_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x4000806C) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN1_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN1_SET = (GPIO0_EN1_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_EN1_SET --------------------------------- +// SVD Line: 3266 + +// SFDITEM_REG__GPIO0_EN1_SET +// EN1_SET +// +// [Bits 31..0] RW (@ 0x4000806C) GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_EN1_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN1_SET = (GPIO0_EN1_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN1_SET_ALL +// +// + + +// -------------------------- Register Item Address: GPIO0_EN1_CLR ------------------------------ +// SVD Line: 3279 + +unsigned int GPIO0_EN1_CLR __AT (0x40008070); + + + +// ------------------------------ Field Item: GPIO0_EN1_CLR_ALL --------------------------------- +// SVD Line: 3284 + +// SFDITEM_FIELD__GPIO0_EN1_CLR_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008070) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN1_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN1_CLR = (GPIO0_EN1_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_EN1_CLR --------------------------------- +// SVD Line: 3279 + +// SFDITEM_REG__GPIO0_EN1_CLR +// EN1_CLR +// +// [Bits 31..0] RW (@ 0x40008070) GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_EN1_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN1_CLR = (GPIO0_EN1_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN1_CLR_ALL +// +// + + +// ---------------------------- Register Item Address: GPIO0_EN2 -------------------------------- +// SVD Line: 3292 + +unsigned int GPIO0_EN2 __AT (0x40008074); + + + +// ----------------------------- Field Item: GPIO0_EN2_GPIO_EN2 --------------------------------- +// SVD Line: 3297 + +// SFDITEM_FIELD__GPIO0_EN2_GPIO_EN2 +// GPIO_EN2 +// +// [Bits 31..0] RW (@ 0x40008074) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN2 >> 0) & 0xFFFFFFFF), ((GPIO0_EN2 = (GPIO0_EN2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: GPIO0_EN2 ----------------------------------- +// SVD Line: 3292 + +// SFDITEM_REG__GPIO0_EN2 +// EN2 +// +// [Bits 31..0] RW (@ 0x40008074) GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. +// ( (unsigned int)((GPIO0_EN2 >> 0) & 0xFFFFFFFF), ((GPIO0_EN2 = (GPIO0_EN2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN2_GPIO_EN2 +// +// + + +// -------------------------- Register Item Address: GPIO0_EN2_SET ------------------------------ +// SVD Line: 3317 + +unsigned int GPIO0_EN2_SET __AT (0x40008078); + + + +// ------------------------------ Field Item: GPIO0_EN2_SET_ALL --------------------------------- +// SVD Line: 3322 + +// SFDITEM_FIELD__GPIO0_EN2_SET_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x40008078) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN2_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN2_SET = (GPIO0_EN2_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_EN2_SET --------------------------------- +// SVD Line: 3317 + +// SFDITEM_REG__GPIO0_EN2_SET +// EN2_SET +// +// [Bits 31..0] RW (@ 0x40008078) GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_EN2_SET >> 0) & 0xFFFFFFFF), ((GPIO0_EN2_SET = (GPIO0_EN2_SET & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN2_SET_ALL +// +// + + +// -------------------------- Register Item Address: GPIO0_EN2_CLR ------------------------------ +// SVD Line: 3330 + +unsigned int GPIO0_EN2_CLR __AT (0x4000807C); + + + +// ------------------------------ Field Item: GPIO0_EN2_CLR_ALL --------------------------------- +// SVD Line: 3335 + +// SFDITEM_FIELD__GPIO0_EN2_CLR_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x4000807C) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_EN2_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN2_CLR = (GPIO0_EN2_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: GPIO0_EN2_CLR --------------------------------- +// SVD Line: 3330 + +// SFDITEM_REG__GPIO0_EN2_CLR +// EN2_CLR +// +// [Bits 31..0] RW (@ 0x4000807C) GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. +// ( (unsigned int)((GPIO0_EN2_CLR >> 0) & 0xFFFFFFFF), ((GPIO0_EN2_CLR = (GPIO0_EN2_CLR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_EN2_CLR_ALL +// +// + + +// ----------------------------- Register Item Address: GPIO0_IS -------------------------------- +// SVD Line: 3343 + +unsigned int GPIO0_IS __AT (0x400080A8); + + + +// --------------------------------- Register Item: GPIO0_IS ------------------------------------ +// SVD Line: 3343 + +// SFDITEM_REG__GPIO0_IS +// IS +// [Bits 31..0] RW (@ 0x400080A8) Input Hysteresis Enable Register +// +// ( (unsigned int)((GPIO0_IS >> 0) & 0xFFFFFFFF), ((GPIO0_IS = (GPIO0_IS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: GPIO0_SR -------------------------------- +// SVD Line: 3348 + +unsigned int GPIO0_SR __AT (0x400080AC); + + + +// --------------------------------- Register Item: GPIO0_SR ------------------------------------ +// SVD Line: 3348 + +// SFDITEM_REG__GPIO0_SR +// SR +// [Bits 31..0] RW (@ 0x400080AC) Slew Rate Select Register. +// +// ( (unsigned int)((GPIO0_SR >> 0) & 0xFFFFFFFF), ((GPIO0_SR = (GPIO0_SR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: GPIO0_DS -------------------------------- +// SVD Line: 3353 + +unsigned int GPIO0_DS __AT (0x400080B0); + + + +// --------------------------------- Field Item: GPIO0_DS_DS ------------------------------------ +// SVD Line: 3358 + +// SFDITEM_FIELD__GPIO0_DS_DS +// DS +// +// [Bits 31..0] RW (@ 0x400080B0) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_DS >> 0) & 0xFFFFFFFF), ((GPIO0_DS = (GPIO0_DS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: GPIO0_DS ------------------------------------ +// SVD Line: 3353 + +// SFDITEM_REG__GPIO0_DS +// DS +// +// [Bits 31..0] RW (@ 0x400080B0) GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. +// ( (unsigned int)((GPIO0_DS >> 0) & 0xFFFFFFFF), ((GPIO0_DS = (GPIO0_DS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_DS_DS +// +// + + +// ---------------------------- Register Item Address: GPIO0_DS1 -------------------------------- +// SVD Line: 3378 + +unsigned int GPIO0_DS1 __AT (0x400080B4); + + + +// -------------------------------- Field Item: GPIO0_DS1_ALL ----------------------------------- +// SVD Line: 3383 + +// SFDITEM_FIELD__GPIO0_DS1_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x400080B4) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_DS1 >> 0) & 0xFFFFFFFF), ((GPIO0_DS1 = (GPIO0_DS1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: GPIO0_DS1 ----------------------------------- +// SVD Line: 3378 + +// SFDITEM_REG__GPIO0_DS1 +// DS1 +// +// [Bits 31..0] RW (@ 0x400080B4) GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. +// ( (unsigned int)((GPIO0_DS1 >> 0) & 0xFFFFFFFF), ((GPIO0_DS1 = (GPIO0_DS1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_DS1_ALL +// +// + + +// ----------------------------- Register Item Address: GPIO0_PS -------------------------------- +// SVD Line: 3391 + +unsigned int GPIO0_PS __AT (0x400080B8); + + + +// -------------------------------- Field Item: GPIO0_PS_ALL ------------------------------------ +// SVD Line: 3396 + +// SFDITEM_FIELD__GPIO0_PS_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x400080B8) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_PS >> 0) & 0xFFFFFFFF), ((GPIO0_PS = (GPIO0_PS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: GPIO0_PS ------------------------------------ +// SVD Line: 3391 + +// SFDITEM_REG__GPIO0_PS +// PS +// +// [Bits 31..0] RW (@ 0x400080B8) GPIO Pull Select Mode. +// ( (unsigned int)((GPIO0_PS >> 0) & 0xFFFFFFFF), ((GPIO0_PS = (GPIO0_PS & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_PS_ALL +// +// + + +// --------------------------- Register Item Address: GPIO0_VSSEL ------------------------------- +// SVD Line: 3404 + +unsigned int GPIO0_VSSEL __AT (0x400080C0); + + + +// ------------------------------- Field Item: GPIO0_VSSEL_ALL ---------------------------------- +// SVD Line: 3409 + +// SFDITEM_FIELD__GPIO0_VSSEL_ALL +// ALL +// +// [Bits 31..0] RW (@ 0x400080C0) Mask of all of the pins on the port. +// +// ( (unsigned int)((GPIO0_VSSEL >> 0) & 0xFFFFFFFF), ((GPIO0_VSSEL = (GPIO0_VSSEL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: GPIO0_VSSEL ---------------------------------- +// SVD Line: 3404 + +// SFDITEM_REG__GPIO0_VSSEL +// VSSEL +// +// [Bits 31..0] RW (@ 0x400080C0) GPIO Voltage Select. +// ( (unsigned int)((GPIO0_VSSEL >> 0) & 0xFFFFFFFF), ((GPIO0_VSSEL = (GPIO0_VSSEL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__GPIO0_VSSEL_ALL +// +// + + +// --------------------------------- Peripheral View: GPIO0 ------------------------------------- +// SVD Line: 2744 + +// GPIO0 +// GPIO0 +// SFDITEM_REG__GPIO0_EN +// SFDITEM_REG__GPIO0_EN_SET +// SFDITEM_REG__GPIO0_EN_CLR +// SFDITEM_REG__GPIO0_OUT_EN +// SFDITEM_REG__GPIO0_OUT_EN_SET +// SFDITEM_REG__GPIO0_OUT_EN_CLR +// SFDITEM_REG__GPIO0_OUT +// SFDITEM_REG__GPIO0_OUT_SET +// SFDITEM_REG__GPIO0_OUT_CLR +// SFDITEM_REG__GPIO0_IN +// SFDITEM_REG__GPIO0_INT_MOD +// SFDITEM_REG__GPIO0_INT_POL +// SFDITEM_REG__GPIO0_INT_EN +// SFDITEM_REG__GPIO0_INT_EN_SET +// SFDITEM_REG__GPIO0_INT_EN_CLR +// SFDITEM_REG__GPIO0_INT_STAT +// SFDITEM_REG__GPIO0_INT_CLR +// SFDITEM_REG__GPIO0_WAKE_EN +// SFDITEM_REG__GPIO0_WAKE_EN_SET +// SFDITEM_REG__GPIO0_WAKE_EN_CLR +// SFDITEM_REG__GPIO0_INT_DUAL_EDGE +// SFDITEM_REG__GPIO0_PAD_CFG1 +// SFDITEM_REG__GPIO0_PAD_CFG2 +// SFDITEM_REG__GPIO0_EN1 +// SFDITEM_REG__GPIO0_EN1_SET +// SFDITEM_REG__GPIO0_EN1_CLR +// SFDITEM_REG__GPIO0_EN2 +// SFDITEM_REG__GPIO0_EN2_SET +// SFDITEM_REG__GPIO0_EN2_CLR +// SFDITEM_REG__GPIO0_IS +// SFDITEM_REG__GPIO0_SR +// SFDITEM_REG__GPIO0_DS +// SFDITEM_REG__GPIO0_DS1 +// SFDITEM_REG__GPIO0_PS +// SFDITEM_REG__GPIO0_VSSEL +// +// + + +// ---------------------------- Register Item Address: I2C0_CTRL -------------------------------- +// SVD Line: 3437 + +unsigned int I2C0_CTRL __AT (0x4001D000); + + + +// ------------------------------ Field Item: I2C0_CTRL_I2C_EN ---------------------------------- +// SVD Line: 3442 + +// SFDITEM_FIELD__I2C0_CTRL_I2C_EN +// I2C_EN +// +// [Bit 0] RW (@ 0x4001D000) \nI2C Enable.\n0 : dis = Disable I2C.\n1 : en = enable I2C. +// +// ( (unsigned int) I2C0_CTRL ) +// I2C_EN +// <0=> 0: dis = Disable I2C. +// <1=> 1: en = enable I2C. +// +// +// + + +// -------------------------------- Field Item: I2C0_CTRL_MST ----------------------------------- +// SVD Line: 3460 + +// SFDITEM_FIELD__I2C0_CTRL_MST +// MST +// +// [Bit 1] RW (@ 0x4001D000) \nMaster Mode Enable.\n0 : slave_mode = Slave Mode.\n1 : master_mode = Master Mode. +// +// ( (unsigned int) I2C0_CTRL ) +// MST +// <0=> 0: slave_mode = Slave Mode. +// <1=> 1: master_mode = Master Mode. +// +// +// + + +// --------------------------- Field Item: I2C0_CTRL_GEN_CALL_ADDR ------------------------------ +// SVD Line: 3478 + +// SFDITEM_FIELD__I2C0_CTRL_GEN_CALL_ADDR +// GEN_CALL_ADDR +// +// [Bit 2] RW (@ 0x4001D000) \nGeneral Call Address Enable.\n0 : dis = Ignore Gneral Call Address.\n1 : en = Acknowledge general call address. +// +// ( (unsigned int) I2C0_CTRL ) +// GEN_CALL_ADDR +// <0=> 0: dis = Ignore Gneral Call Address. +// <1=> 1: en = Acknowledge general call address. +// +// +// + + +// ------------------------------ Field Item: I2C0_CTRL_RX_MODE --------------------------------- +// SVD Line: 3496 + +// SFDITEM_FIELD__I2C0_CTRL_RX_MODE +// RX_MODE +// +// [Bit 3] RW (@ 0x4001D000) \nInteractive Receive Mode.\n0 : dis = Disable Interactive Receive Mode.\n1 : en = Enable Interactive Receive Mode. +// +// ( (unsigned int) I2C0_CTRL ) +// RX_MODE +// <0=> 0: dis = Disable Interactive Receive Mode. +// <1=> 1: en = Enable Interactive Receive Mode. +// +// +// + + +// ---------------------------- Field Item: I2C0_CTRL_RX_MODE_ACK ------------------------------- +// SVD Line: 3514 + +// SFDITEM_FIELD__I2C0_CTRL_RX_MODE_ACK +// RX_MODE_ACK +// +// [Bit 4] RW (@ 0x4001D000) \nData Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.\n0 : ack = return ACK (pulling SDA LOW).\n1 : nack = return NACK (leaving SDA HIGH). +// +// ( (unsigned int) I2C0_CTRL ) +// RX_MODE_ACK +// <0=> 0: ack = return ACK (pulling SDA LOW). +// <1=> 1: nack = return NACK (leaving SDA HIGH). +// +// +// + + +// ------------------------------ Field Item: I2C0_CTRL_SCL_OUT --------------------------------- +// SVD Line: 3532 + +// SFDITEM_FIELD__I2C0_CTRL_SCL_OUT +// SCL_OUT +// +// [Bit 6] RW (@ 0x4001D000) \nSCL Output. This bits control SCL output when SWOE =1.\n0 : drive_scl_low = Drive SCL low.\n1 : release_scl = Release SCL. +// +// ( (unsigned int) I2C0_CTRL ) +// SCL_OUT +// <0=> 0: drive_scl_low = Drive SCL low. +// <1=> 1: release_scl = Release SCL. +// +// +// + + +// ------------------------------ Field Item: I2C0_CTRL_SDA_OUT --------------------------------- +// SVD Line: 3550 + +// SFDITEM_FIELD__I2C0_CTRL_SDA_OUT +// SDA_OUT +// +// [Bit 7] RW (@ 0x4001D000) \nSDA Output. This bits control SDA output when SWOE = 1.\n0 : drive_sda_low = Drive SDA low.\n1 : release_sda = Release SDA. +// +// ( (unsigned int) I2C0_CTRL ) +// SDA_OUT +// <0=> 0: drive_sda_low = Drive SDA low. +// <1=> 1: release_sda = Release SDA. +// +// +// + + +// -------------------------------- Field Item: I2C0_CTRL_SCL ----------------------------------- +// SVD Line: 3568 + +// SFDITEM_FIELD__I2C0_CTRL_SCL +// SCL +// +// [Bit 8] RO (@ 0x4001D000) SCL status. This bit reflects the logic gate of SCL signal. +// +// ( (unsigned int) I2C0_CTRL ) +// SCL +// +// +// + + +// -------------------------------- Field Item: I2C0_CTRL_SDA ----------------------------------- +// SVD Line: 3574 + +// SFDITEM_FIELD__I2C0_CTRL_SDA +// SDA +// +// [Bit 9] RO (@ 0x4001D000) SDA status. THis bit reflects the logic gate of SDA signal. +// +// ( (unsigned int) I2C0_CTRL ) +// SDA +// +// +// + + +// ----------------------------- Field Item: I2C0_CTRL_SW_OUT_EN -------------------------------- +// SVD Line: 3580 + +// SFDITEM_FIELD__I2C0_CTRL_SW_OUT_EN +// SW_OUT_EN +// +// [Bit 10] RW (@ 0x4001D000) \nSoftware Output Enable.\n0 : outputs_disable = I2C Outputs SCLO and SDAO disabled.\n1 : outputs_enable = I2C Outputs SCLO and SDAO enabled. +// +// ( (unsigned int) I2C0_CTRL ) +// SW_OUT_EN +// <0=> 0: outputs_disable = I2C Outputs SCLO and SDAO disabled. +// <1=> 1: outputs_enable = I2C Outputs SCLO and SDAO enabled. +// +// +// + + +// ------------------------------- Field Item: I2C0_CTRL_READ ----------------------------------- +// SVD Line: 3598 + +// SFDITEM_FIELD__I2C0_CTRL_READ +// READ +// +// [Bit 11] RO (@ 0x4001D000) \nRead. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.\n0 : write = Write.\n1 : read = Read. +// +// ( (unsigned int) I2C0_CTRL ) +// READ +// <0=> 0: write = Write. +// <1=> 1: read = Read. +// +// +// + + +// ------------------------ Field Item: I2C0_CTRL_SCL_CLK_STRECH_DIS ---------------------------- +// SVD Line: 3616 + +// SFDITEM_FIELD__I2C0_CTRL_SCL_CLK_STRECH_DIS +// SCL_CLK_STRECH_DIS +// +// [Bit 12] RW (@ 0x4001D000) \nThis bit will disable slave clock stretching when set.\n0 : en = Slave clock stretching enabled.\n1 : dis = Slave clock stretching disabled. +// +// ( (unsigned int) I2C0_CTRL ) +// SCL_CLK_STRECH_DIS +// <0=> 0: en = Slave clock stretching enabled. +// <1=> 1: dis = Slave clock stretching disabled. +// +// +// + + +// ---------------------------- Field Item: I2C0_CTRL_SCL_PP_MODE ------------------------------- +// SVD Line: 3634 + +// SFDITEM_FIELD__I2C0_CTRL_SCL_PP_MODE +// SCL_PP_MODE +// +// [Bit 13] RW (@ 0x4001D000) \nSCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.\n0 : dis = Standard open-drain operation: drive low for 0, Hi-Z for 1\n1 : en = Non-standard push-pull operation: drive low for 0, drive high for 1 +// +// ( (unsigned int) I2C0_CTRL ) +// SCL_PP_MODE +// <0=> 0: dis = Standard open-drain operation: drive low for 0, Hi-Z for 1 +// <1=> 1: en = Non-standard push-pull operation: drive low for 0, drive high for 1 +// +// +// + + +// ------------------------------ Field Item: I2C0_CTRL_HS_MODE --------------------------------- +// SVD Line: 3652 + +// SFDITEM_FIELD__I2C0_CTRL_HS_MODE +// HS_MODE +// +// [Bit 15] RW (@ 0x4001D000) \nHs-mode Enable.\n0 : dis = Hs-mode disabled.\n1 : en = Hs-mode enabled. +// +// ( (unsigned int) I2C0_CTRL ) +// HS_MODE +// <0=> 0: dis = Hs-mode disabled. +// <1=> 1: en = Hs-mode enabled. +// +// +// + + +// -------------------------------- Register RTree: I2C0_CTRL ----------------------------------- +// SVD Line: 3437 + +// SFDITEM_REG__I2C0_CTRL +// CTRL +// +// [Bits 31..0] RW (@ 0x4001D000) Control Register0. +// ( (unsigned int)((I2C0_CTRL >> 0) & 0xFFFFFFFF), ((I2C0_CTRL = (I2C0_CTRL & ~(0xB4DFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB4DF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_CTRL_I2C_EN +// SFDITEM_FIELD__I2C0_CTRL_MST +// SFDITEM_FIELD__I2C0_CTRL_GEN_CALL_ADDR +// SFDITEM_FIELD__I2C0_CTRL_RX_MODE +// SFDITEM_FIELD__I2C0_CTRL_RX_MODE_ACK +// SFDITEM_FIELD__I2C0_CTRL_SCL_OUT +// SFDITEM_FIELD__I2C0_CTRL_SDA_OUT +// SFDITEM_FIELD__I2C0_CTRL_SCL +// SFDITEM_FIELD__I2C0_CTRL_SDA +// SFDITEM_FIELD__I2C0_CTRL_SW_OUT_EN +// SFDITEM_FIELD__I2C0_CTRL_READ +// SFDITEM_FIELD__I2C0_CTRL_SCL_CLK_STRECH_DIS +// SFDITEM_FIELD__I2C0_CTRL_SCL_PP_MODE +// SFDITEM_FIELD__I2C0_CTRL_HS_MODE +// +// + + +// --------------------------- Register Item Address: I2C0_STATUS ------------------------------- +// SVD Line: 3672 + +unsigned int I2C0_STATUS __AT (0x4001D004); + + + +// ------------------------------- Field Item: I2C0_STATUS_BUS ---------------------------------- +// SVD Line: 3677 + +// SFDITEM_FIELD__I2C0_STATUS_BUS +// BUS +// +// [Bit 0] RO (@ 0x4001D004) \nBus Status.\n0 : idle = I2C Bus Idle.\n1 : busy = I2C Bus Busy. +// +// ( (unsigned int) I2C0_STATUS ) +// BUS +// <0=> 0: idle = I2C Bus Idle. +// <1=> 1: busy = I2C Bus Busy. +// +// +// + + +// ---------------------------- Field Item: I2C0_STATUS_RX_EMPTY -------------------------------- +// SVD Line: 3695 + +// SFDITEM_FIELD__I2C0_STATUS_RX_EMPTY +// RX_EMPTY +// +// [Bit 1] RO (@ 0x4001D004) \nRX empty.\n0 : not_empty = Not Empty.\n1 : empty = Empty. +// +// ( (unsigned int) I2C0_STATUS ) +// RX_EMPTY +// <0=> 0: not_empty = Not Empty. +// <1=> 1: empty = Empty. +// +// +// + + +// ----------------------------- Field Item: I2C0_STATUS_RX_FULL -------------------------------- +// SVD Line: 3713 + +// SFDITEM_FIELD__I2C0_STATUS_RX_FULL +// RX_FULL +// +// [Bit 2] RO (@ 0x4001D004) \nRX Full.\n0 : not_full = Not Full.\n1 : full = Full. +// +// ( (unsigned int) I2C0_STATUS ) +// RX_FULL +// <0=> 0: not_full = Not Full. +// <1=> 1: full = Full. +// +// +// + + +// ---------------------------- Field Item: I2C0_STATUS_TX_EMPTY -------------------------------- +// SVD Line: 3731 + +// SFDITEM_FIELD__I2C0_STATUS_TX_EMPTY +// TX_EMPTY +// +// [Bit 3] RW (@ 0x4001D004) \nTX Empty.\n0 : not_empty = Not Empty.\n1 : empty = Empty. +// +// ( (unsigned int) I2C0_STATUS ) +// TX_EMPTY +// <0=> 0: not_empty = Not Empty. +// <1=> 1: empty = Empty. +// +// +// + + +// ----------------------------- Field Item: I2C0_STATUS_TX_FULL -------------------------------- +// SVD Line: 3748 + +// SFDITEM_FIELD__I2C0_STATUS_TX_FULL +// TX_FULL +// +// [Bit 4] RW (@ 0x4001D004) \nTX Full.\n0 : not_empty = Not Empty.\n1 : empty = Empty. +// +// ( (unsigned int) I2C0_STATUS ) +// TX_FULL +// <0=> 0: not_empty = Not Empty. +// <1=> 1: empty = Empty. +// +// +// + + +// ---------------------------- Field Item: I2C0_STATUS_CLK_MODE -------------------------------- +// SVD Line: 3765 + +// SFDITEM_FIELD__I2C0_STATUS_CLK_MODE +// CLK_MODE +// +// [Bit 5] RO (@ 0x4001D004) \nClock Mode.\n0 : not_actively_driving_scl_clock = Device not actively driving SCL clock cycles.\n1 : actively_driving_scl_clock = Device operating as master and actively driving SCL clock cycles. +// +// ( (unsigned int) I2C0_STATUS ) +// CLK_MODE +// <0=> 0: not_actively_driving_scl_clock = Device not actively driving SCL clock cycles. +// <1=> 1: actively_driving_scl_clock = Device operating as master and actively driving SCL clock cycles. +// +// +// + + +// ----------------------------- Field Item: I2C0_STATUS_STATUS --------------------------------- +// SVD Line: 3783 + +// SFDITEM_FIELD__I2C0_STATUS_STATUS +// STATUS +// +// [Bits 11..8] RW (@ 0x4001D004) \nController Status.\n0 : idle = Controller Idle.\n1 : mtx_addr = master Transmit address.\n2 : mrx_addr_ack = Master Receive address ACK.\n3 : mtx_ex_addr = Master Transmit extended address.\n4 : mrx_ex_addr = Master Receive extended address ACK.\n5 : srx_addr = Slave Receive address.\n6 : stx_addr_ack = Slave Transmit address ACK.\n7 : srx_ex_addr = Slave Receive extended address.\n8 : stx_ex_addr_ack = Slave Transmit extended address ACK.\n9 : tx = Transmit data (master or slave).\n10 : rx_ack = Receive data ACK (master or slave).\n11 : rx = Receive data (master or slave).\n12 : tx_ack = Transmit data ACK (master or slave).\n13 : nack = NACK stage (master or slave).\n14 : Reserved - do not use\n15 : by_st = Bystander state (ongoing transaction but not participant- another master addressing another slave). +// +// ( (unsigned int) I2C0_STATUS ) +// STATUS +// <0=> 0: idle = Controller Idle. +// <1=> 1: mtx_addr = master Transmit address. +// <2=> 2: mrx_addr_ack = Master Receive address ACK. +// <3=> 3: mtx_ex_addr = Master Transmit extended address. +// <4=> 4: mrx_ex_addr = Master Receive extended address ACK. +// <5=> 5: srx_addr = Slave Receive address. +// <6=> 6: stx_addr_ack = Slave Transmit address ACK. +// <7=> 7: srx_ex_addr = Slave Receive extended address. +// <8=> 8: stx_ex_addr_ack = Slave Transmit extended address ACK. +// <9=> 9: tx = Transmit data (master or slave). +// <10=> 10: rx_ack = Receive data ACK (master or slave). +// <11=> 11: rx = Receive data (master or slave). +// <12=> 12: tx_ack = Transmit data ACK (master or slave). +// <13=> 13: nack = NACK stage (master or slave). +// <14=> 14: +// <15=> 15: by_st = Bystander state (ongoing transaction but not participant- another master addressing another slave). +// +// +// + + +// ------------------------------- Register RTree: I2C0_STATUS ---------------------------------- +// SVD Line: 3672 + +// SFDITEM_REG__I2C0_STATUS +// STATUS +// +// [Bits 31..0] RW (@ 0x4001D004) Status Register. +// ( (unsigned int)((I2C0_STATUS >> 0) & 0xFFFFFFFF), ((I2C0_STATUS = (I2C0_STATUS & ~(0xF18UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF18) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_STATUS_BUS +// SFDITEM_FIELD__I2C0_STATUS_RX_EMPTY +// SFDITEM_FIELD__I2C0_STATUS_RX_FULL +// SFDITEM_FIELD__I2C0_STATUS_TX_EMPTY +// SFDITEM_FIELD__I2C0_STATUS_TX_FULL +// SFDITEM_FIELD__I2C0_STATUS_CLK_MODE +// SFDITEM_FIELD__I2C0_STATUS_STATUS +// +// + + +// --------------------------- Register Item Address: I2C0_INT_FL0 ------------------------------ +// SVD Line: 3867 + +unsigned int I2C0_INT_FL0 __AT (0x4001D008); + + + +// ------------------------------ Field Item: I2C0_INT_FL0_DONE --------------------------------- +// SVD Line: 3872 + +// SFDITEM_FIELD__I2C0_INT_FL0_DONE +// DONE +// +// [Bit 0] RW (@ 0x4001D008) \nTransfer Done Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// DONE +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_FL0_RX_MODE -------------------------------- +// SVD Line: 3890 + +// SFDITEM_FIELD__I2C0_INT_FL0_RX_MODE +// RX_MODE +// +// [Bit 1] RW (@ 0x4001D008) \nInteractive Receive Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// RX_MODE +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ------------------------- Field Item: I2C0_INT_FL0_GEN_CALL_ADDR ----------------------------- +// SVD Line: 3907 + +// SFDITEM_FIELD__I2C0_INT_FL0_GEN_CALL_ADDR +// GEN_CALL_ADDR +// +// [Bit 2] RW (@ 0x4001D008) \nSlave General Call Address Match Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// GEN_CALL_ADDR +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// --------------------------- Field Item: I2C0_INT_FL0_ADDR_MATCH ------------------------------ +// SVD Line: 3924 + +// SFDITEM_FIELD__I2C0_INT_FL0_ADDR_MATCH +// ADDR_MATCH +// +// [Bit 3] RW (@ 0x4001D008) \nSlave Address Match Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// ADDR_MATCH +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// --------------------------- Field Item: I2C0_INT_FL0_RX_THRESH ------------------------------- +// SVD Line: 3941 + +// SFDITEM_FIELD__I2C0_INT_FL0_RX_THRESH +// RX_THRESH +// +// [Bit 4] RW (@ 0x4001D008) \nReceive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. RX_FIFO equal or more bytes than the threshold. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// RX_THRESH +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. RX_FIFO equal or more bytes than the threshold. +// +// +// + + +// --------------------------- Field Item: I2C0_INT_FL0_TX_THRESH ------------------------------- +// SVD Line: 3958 + +// SFDITEM_FIELD__I2C0_INT_FL0_TX_THRESH +// TX_THRESH +// +// [Bit 5] RW (@ 0x4001D008) \nTransmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// TX_THRESH +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. +// +// +// + + +// ------------------------------ Field Item: I2C0_INT_FL0_STOP --------------------------------- +// SVD Line: 3975 + +// SFDITEM_FIELD__I2C0_INT_FL0_STOP +// STOP +// +// [Bit 6] RW (@ 0x4001D008) \nSTOP Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// STOP +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_FL0_ADDR_ACK ------------------------------- +// SVD Line: 3992 + +// SFDITEM_FIELD__I2C0_INT_FL0_ADDR_ACK +// ADDR_ACK +// +// [Bit 7] RW (@ 0x4001D008) \nAddress Acknowledge Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// ADDR_ACK +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ----------------------------- Field Item: I2C0_INT_FL0_ARB_ER -------------------------------- +// SVD Line: 4009 + +// SFDITEM_FIELD__I2C0_INT_FL0_ARB_ER +// ARB_ER +// +// [Bit 8] RW (@ 0x4001D008) \nArbritation error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// ARB_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ----------------------------- Field Item: I2C0_INT_FL0_TO_ER --------------------------------- +// SVD Line: 4026 + +// SFDITEM_FIELD__I2C0_INT_FL0_TO_ER +// TO_ER +// +// [Bit 9] RW (@ 0x4001D008) \ntimeout Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// TO_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// -------------------------- Field Item: I2C0_INT_FL0_ADDR_NACK_ER ----------------------------- +// SVD Line: 4043 + +// SFDITEM_FIELD__I2C0_INT_FL0_ADDR_NACK_ER +// ADDR_NACK_ER +// +// [Bit 10] RW (@ 0x4001D008) \nAddress NACK Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// ADDR_NACK_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_FL0_DATA_ER -------------------------------- +// SVD Line: 4060 + +// SFDITEM_FIELD__I2C0_INT_FL0_DATA_ER +// DATA_ER +// +// [Bit 11] RW (@ 0x4001D008) \nData NACK Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// DATA_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ------------------------- Field Item: I2C0_INT_FL0_DO_NOT_RESP_ER ---------------------------- +// SVD Line: 4077 + +// SFDITEM_FIELD__I2C0_INT_FL0_DO_NOT_RESP_ER +// DO_NOT_RESP_ER +// +// [Bit 12] RW (@ 0x4001D008) \nDo Not Respond Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// DO_NOT_RESP_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_FL0_START_ER ------------------------------- +// SVD Line: 4094 + +// SFDITEM_FIELD__I2C0_INT_FL0_START_ER +// START_ER +// +// [Bit 13] RW (@ 0x4001D008) \nStart Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// START_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_FL0_STOP_ER -------------------------------- +// SVD Line: 4111 + +// SFDITEM_FIELD__I2C0_INT_FL0_STOP_ER +// STOP_ER +// +// [Bit 14] RW (@ 0x4001D008) \nStop Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// STOP_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// -------------------------- Field Item: I2C0_INT_FL0_TX_LOCK_OUT ------------------------------ +// SVD Line: 4128 + +// SFDITEM_FIELD__I2C0_INT_FL0_TX_LOCK_OUT +// TX_LOCK_OUT +// +// [Bit 15] RW (@ 0x4001D008) Transmit Lock Out Interrupt. +// +// ( (unsigned int) I2C0_INT_FL0 ) +// TX_LOCK_OUT +// +// +// + + +// ------------------------------ Register RTree: I2C0_INT_FL0 ---------------------------------- +// SVD Line: 3867 + +// SFDITEM_REG__I2C0_INT_FL0 +// INT_FL0 +// +// [Bits 31..0] RW (@ 0x4001D008) Interrupt Status Register. +// ( (unsigned int)((I2C0_INT_FL0 >> 0) & 0xFFFFFFFF), ((I2C0_INT_FL0 = (I2C0_INT_FL0 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_INT_FL0_DONE +// SFDITEM_FIELD__I2C0_INT_FL0_RX_MODE +// SFDITEM_FIELD__I2C0_INT_FL0_GEN_CALL_ADDR +// SFDITEM_FIELD__I2C0_INT_FL0_ADDR_MATCH +// SFDITEM_FIELD__I2C0_INT_FL0_RX_THRESH +// SFDITEM_FIELD__I2C0_INT_FL0_TX_THRESH +// SFDITEM_FIELD__I2C0_INT_FL0_STOP +// SFDITEM_FIELD__I2C0_INT_FL0_ADDR_ACK +// SFDITEM_FIELD__I2C0_INT_FL0_ARB_ER +// SFDITEM_FIELD__I2C0_INT_FL0_TO_ER +// SFDITEM_FIELD__I2C0_INT_FL0_ADDR_NACK_ER +// SFDITEM_FIELD__I2C0_INT_FL0_DATA_ER +// SFDITEM_FIELD__I2C0_INT_FL0_DO_NOT_RESP_ER +// SFDITEM_FIELD__I2C0_INT_FL0_START_ER +// SFDITEM_FIELD__I2C0_INT_FL0_STOP_ER +// SFDITEM_FIELD__I2C0_INT_FL0_TX_LOCK_OUT +// +// + + +// --------------------------- Register Item Address: I2C0_INT_EN0 ------------------------------ +// SVD Line: 4135 + +unsigned int I2C0_INT_EN0 __AT (0x4001D00C); + + + +// ------------------------------ Field Item: I2C0_INT_EN0_DONE --------------------------------- +// SVD Line: 4141 + +// SFDITEM_FIELD__I2C0_INT_EN0_DONE +// DONE +// +// [Bit 0] RW (@ 0x4001D00C) \nTransfer Done Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when DONE = 1. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// DONE +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when DONE = 1. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_EN0_RX_MODE -------------------------------- +// SVD Line: 4159 + +// SFDITEM_FIELD__I2C0_INT_EN0_RX_MODE +// RX_MODE +// +// [Bit 1] RW (@ 0x4001D00C) \nDescription not available.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when RX_MODE = 1. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// RX_MODE +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when RX_MODE = 1. +// +// +// + + +// ------------------------- Field Item: I2C0_INT_EN0_GEN_CTRL_ADDR ----------------------------- +// SVD Line: 4177 + +// SFDITEM_FIELD__I2C0_INT_EN0_GEN_CTRL_ADDR +// GEN_CTRL_ADDR +// +// [Bit 2] RW (@ 0x4001D00C) \nSlave mode general call address match received input enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when GEN_CTRL_ADDR = 1. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// GEN_CTRL_ADDR +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when GEN_CTRL_ADDR = 1. +// +// +// + + +// --------------------------- Field Item: I2C0_INT_EN0_ADDR_MATCH ------------------------------ +// SVD Line: 4195 + +// SFDITEM_FIELD__I2C0_INT_EN0_ADDR_MATCH +// ADDR_MATCH +// +// [Bit 3] RW (@ 0x4001D00C) \nSlave mode incoming address match interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when ADDR_MATCH = 1. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// ADDR_MATCH +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when ADDR_MATCH = 1. +// +// +// + + +// --------------------------- Field Item: I2C0_INT_EN0_RX_THRESH ------------------------------- +// SVD Line: 4213 + +// SFDITEM_FIELD__I2C0_INT_EN0_RX_THRESH +// RX_THRESH +// +// [Bit 4] RW (@ 0x4001D00C) \nRX FIFO Above Treshold Level Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// RX_THRESH +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// --------------------------- Field Item: I2C0_INT_EN0_TX_THRESH ------------------------------- +// SVD Line: 4231 + +// SFDITEM_FIELD__I2C0_INT_EN0_TX_THRESH +// TX_THRESH +// +// [Bit 5] RW (@ 0x4001D00C) \nTX FIFO Below Treshold Level Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// TX_THRESH +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ------------------------------ Field Item: I2C0_INT_EN0_STOP --------------------------------- +// SVD Line: 4248 + +// SFDITEM_FIELD__I2C0_INT_EN0_STOP +// STOP +// +// [Bit 6] RW (@ 0x4001D00C) \nStop Interrupt Enable\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when STOP = 1. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// STOP +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when STOP = 1. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_EN0_ADDR_ACK ------------------------------- +// SVD Line: 4266 + +// SFDITEM_FIELD__I2C0_INT_EN0_ADDR_ACK +// ADDR_ACK +// +// [Bit 7] RW (@ 0x4001D00C) \nReceived Address ACK from Slave Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// ADDR_ACK +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ----------------------------- Field Item: I2C0_INT_EN0_ARB_ER -------------------------------- +// SVD Line: 4283 + +// SFDITEM_FIELD__I2C0_INT_EN0_ARB_ER +// ARB_ER +// +// [Bit 8] RW (@ 0x4001D00C) \nMaster Mode Arbitration Lost Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// ARB_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ----------------------------- Field Item: I2C0_INT_EN0_TO_ER --------------------------------- +// SVD Line: 4300 + +// SFDITEM_FIELD__I2C0_INT_EN0_TO_ER +// TO_ER +// +// [Bit 9] RW (@ 0x4001D00C) \nTimeout Error Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// TO_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_EN0_ADDR_ER -------------------------------- +// SVD Line: 4317 + +// SFDITEM_FIELD__I2C0_INT_EN0_ADDR_ER +// ADDR_ER +// +// [Bit 10] RW (@ 0x4001D00C) \nMaster Mode Address NACK Received Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// ADDR_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_EN0_DATA_ER -------------------------------- +// SVD Line: 4334 + +// SFDITEM_FIELD__I2C0_INT_EN0_DATA_ER +// DATA_ER +// +// [Bit 11] RW (@ 0x4001D00C) \nMaster Mode Data NACK Received Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// DATA_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ------------------------- Field Item: I2C0_INT_EN0_DO_NOT_RESP_ER ---------------------------- +// SVD Line: 4351 + +// SFDITEM_FIELD__I2C0_INT_EN0_DO_NOT_RESP_ER +// DO_NOT_RESP_ER +// +// [Bit 12] RW (@ 0x4001D00C) \nSlave Mode Do Not Respond Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// DO_NOT_RESP_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_EN0_START_ER ------------------------------- +// SVD Line: 4368 + +// SFDITEM_FIELD__I2C0_INT_EN0_START_ER +// START_ER +// +// [Bit 13] RW (@ 0x4001D00C) \nOut of Sequence START condition detected interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// START_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ---------------------------- Field Item: I2C0_INT_EN0_STOP_ER -------------------------------- +// SVD Line: 4385 + +// SFDITEM_FIELD__I2C0_INT_EN0_STOP_ER +// STOP_ER +// +// [Bit 14] RW (@ 0x4001D00C) \nOut of Sequence STOP condition detected interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// STOP_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// -------------------------- Field Item: I2C0_INT_EN0_TX_LOCK_OUT ------------------------------ +// SVD Line: 4402 + +// SFDITEM_FIELD__I2C0_INT_EN0_TX_LOCK_OUT +// TX_LOCK_OUT +// +// [Bit 15] RW (@ 0x4001D00C) \nTX FIFO Locked Out Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when TXLOIE = 1. +// +// ( (unsigned int) I2C0_INT_EN0 ) +// TX_LOCK_OUT +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when TXLOIE = 1. +// +// +// + + +// ------------------------------ Register RTree: I2C0_INT_EN0 ---------------------------------- +// SVD Line: 4135 + +// SFDITEM_REG__I2C0_INT_EN0 +// INT_EN0 +// +// [Bits 31..0] RW (@ 0x4001D00C) Interrupt Enable Register. +// ( (unsigned int)((I2C0_INT_EN0 >> 0) & 0xFFFFFFFF), ((I2C0_INT_EN0 = (I2C0_INT_EN0 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_INT_EN0_DONE +// SFDITEM_FIELD__I2C0_INT_EN0_RX_MODE +// SFDITEM_FIELD__I2C0_INT_EN0_GEN_CTRL_ADDR +// SFDITEM_FIELD__I2C0_INT_EN0_ADDR_MATCH +// SFDITEM_FIELD__I2C0_INT_EN0_RX_THRESH +// SFDITEM_FIELD__I2C0_INT_EN0_TX_THRESH +// SFDITEM_FIELD__I2C0_INT_EN0_STOP +// SFDITEM_FIELD__I2C0_INT_EN0_ADDR_ACK +// SFDITEM_FIELD__I2C0_INT_EN0_ARB_ER +// SFDITEM_FIELD__I2C0_INT_EN0_TO_ER +// SFDITEM_FIELD__I2C0_INT_EN0_ADDR_ER +// SFDITEM_FIELD__I2C0_INT_EN0_DATA_ER +// SFDITEM_FIELD__I2C0_INT_EN0_DO_NOT_RESP_ER +// SFDITEM_FIELD__I2C0_INT_EN0_START_ER +// SFDITEM_FIELD__I2C0_INT_EN0_STOP_ER +// SFDITEM_FIELD__I2C0_INT_EN0_TX_LOCK_OUT +// +// + + +// --------------------------- Register Item Address: I2C0_INT_FL1 ------------------------------ +// SVD Line: 4421 + +unsigned int I2C0_INT_FL1 __AT (0x4001D010); + + + +// -------------------------- Field Item: I2C0_INT_FL1_RX_OVERFLOW ------------------------------ +// SVD Line: 4426 + +// SFDITEM_FIELD__I2C0_INT_FL1_RX_OVERFLOW +// RX_OVERFLOW +// +// [Bit 0] RW (@ 0x4001D010) \nReceiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL1 ) +// RX_OVERFLOW +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// -------------------------- Field Item: I2C0_INT_FL1_TX_UNDERFLOW ----------------------------- +// SVD Line: 4443 + +// SFDITEM_FIELD__I2C0_INT_FL1_TX_UNDERFLOW +// TX_UNDERFLOW +// +// [Bit 1] RW (@ 0x4001D010) \nTransmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_FL1 ) +// TX_UNDERFLOW +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ------------------------------ Register RTree: I2C0_INT_FL1 ---------------------------------- +// SVD Line: 4421 + +// SFDITEM_REG__I2C0_INT_FL1 +// INT_FL1 +// +// [Bits 31..0] RW (@ 0x4001D010) Interrupt Status Register 1. +// ( (unsigned int)((I2C0_INT_FL1 >> 0) & 0xFFFFFFFF), ((I2C0_INT_FL1 = (I2C0_INT_FL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_INT_FL1_RX_OVERFLOW +// SFDITEM_FIELD__I2C0_INT_FL1_TX_UNDERFLOW +// +// + + +// --------------------------- Register Item Address: I2C0_INT_EN1 ------------------------------ +// SVD Line: 4462 + +unsigned int I2C0_INT_EN1 __AT (0x4001D014); + + + +// -------------------------- Field Item: I2C0_INT_EN1_RX_OVERFLOW ------------------------------ +// SVD Line: 4468 + +// SFDITEM_FIELD__I2C0_INT_EN1_RX_OVERFLOW +// RX_OVERFLOW +// +// [Bit 0] RW (@ 0x4001D014) \nReceiver Overflow Interrupt Enable.\n0 : dis = No Interrupt is Pending.\n1 : en = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_EN1 ) +// RX_OVERFLOW +// <0=> 0: dis = No Interrupt is Pending. +// <1=> 1: en = An interrupt is pending. +// +// +// + + +// -------------------------- Field Item: I2C0_INT_EN1_TX_UNDERFLOW ----------------------------- +// SVD Line: 4485 + +// SFDITEM_FIELD__I2C0_INT_EN1_TX_UNDERFLOW +// TX_UNDERFLOW +// +// [Bit 1] RW (@ 0x4001D014) \nTransmit Underflow Interrupt Enable.\n0 : dis = No Interrupt is Pending.\n1 : en = An interrupt is pending. +// +// ( (unsigned int) I2C0_INT_EN1 ) +// TX_UNDERFLOW +// <0=> 0: dis = No Interrupt is Pending. +// <1=> 1: en = An interrupt is pending. +// +// +// + + +// ------------------------------ Register RTree: I2C0_INT_EN1 ---------------------------------- +// SVD Line: 4462 + +// SFDITEM_REG__I2C0_INT_EN1 +// INT_EN1 +// +// [Bits 31..0] RW (@ 0x4001D014) Interrupt Staus Register 1. +// ( (unsigned int)((I2C0_INT_EN1 >> 0) & 0xFFFFFFFF), ((I2C0_INT_EN1 = (I2C0_INT_EN1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_INT_EN1_RX_OVERFLOW +// SFDITEM_FIELD__I2C0_INT_EN1_TX_UNDERFLOW +// +// + + +// -------------------------- Register Item Address: I2C0_FIFO_LEN ------------------------------ +// SVD Line: 4504 + +unsigned int I2C0_FIFO_LEN __AT (0x4001D018); + + + +// ---------------------------- Field Item: I2C0_FIFO_LEN_RX_LEN -------------------------------- +// SVD Line: 4509 + +// SFDITEM_FIELD__I2C0_FIFO_LEN_RX_LEN +// RX_LEN +// +// [Bits 7..0] RO (@ 0x4001D018) Receive FIFO Length. +// +// ( (unsigned char)((I2C0_FIFO_LEN >> 0) & 0xFF) ) +// +// +// + + +// ---------------------------- Field Item: I2C0_FIFO_LEN_TX_LEN -------------------------------- +// SVD Line: 4515 + +// SFDITEM_FIELD__I2C0_FIFO_LEN_TX_LEN +// TX_LEN +// +// [Bits 15..8] RO (@ 0x4001D018) Transmit FIFO Length. +// +// ( (unsigned char)((I2C0_FIFO_LEN >> 8) & 0xFF) ) +// +// +// + + +// ------------------------------ Register RTree: I2C0_FIFO_LEN --------------------------------- +// SVD Line: 4504 + +// SFDITEM_REG__I2C0_FIFO_LEN +// FIFO_LEN +// +// [Bits 31..0] RW (@ 0x4001D018) FIFO Configuration Register. +// ( (unsigned int)((I2C0_FIFO_LEN >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__I2C0_FIFO_LEN_RX_LEN +// SFDITEM_FIELD__I2C0_FIFO_LEN_TX_LEN +// +// + + +// -------------------------- Register Item Address: I2C0_RX_CTRL0 ------------------------------ +// SVD Line: 4523 + +unsigned int I2C0_RX_CTRL0 __AT (0x4001D01C); + + + +// ------------------------------ Field Item: I2C0_RX_CTRL0_DNR --------------------------------- +// SVD Line: 4528 + +// SFDITEM_FIELD__I2C0_RX_CTRL0_DNR +// DNR +// +// [Bit 0] RW (@ 0x4001D01C) \nDo Not Respond.\n0 : respond = Always respond to address match.\n1 : not_respond_rx_fifo_empty = Do not respond to address match when RX_FIFO is not empty. +// +// ( (unsigned int) I2C0_RX_CTRL0 ) +// DNR +// <0=> 0: respond = Always respond to address match. +// <1=> 1: not_respond_rx_fifo_empty = Do not respond to address match when RX_FIFO is not empty. +// +// +// + + +// --------------------------- Field Item: I2C0_RX_CTRL0_RX_FLUSH ------------------------------- +// SVD Line: 4545 + +// SFDITEM_FIELD__I2C0_RX_CTRL0_RX_FLUSH +// RX_FLUSH +// +// [Bit 7] RW (@ 0x4001D01C) \nReceive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.\n0 : not_flushed = FIFO not flushed.\n1 : flush = Flush RX_FIFO. +// +// ( (unsigned int) I2C0_RX_CTRL0 ) +// RX_FLUSH +// <0=> 0: not_flushed = FIFO not flushed. +// <1=> 1: flush = Flush RX_FIFO. +// +// +// + + +// --------------------------- Field Item: I2C0_RX_CTRL0_RX_THRESH ------------------------------ +// SVD Line: 4562 + +// SFDITEM_FIELD__I2C0_RX_CTRL0_RX_THRESH +// RX_THRESH +// +// [Bits 11..8] RW (@ 0x4001D01C) Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. +// +// ( (unsigned char)((I2C0_RX_CTRL0 >> 8) & 0xF), ((I2C0_RX_CTRL0 = (I2C0_RX_CTRL0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: I2C0_RX_CTRL0 --------------------------------- +// SVD Line: 4523 + +// SFDITEM_REG__I2C0_RX_CTRL0 +// RX_CTRL0 +// +// [Bits 31..0] RW (@ 0x4001D01C) Receive Control Register 0. +// ( (unsigned int)((I2C0_RX_CTRL0 >> 0) & 0xFFFFFFFF), ((I2C0_RX_CTRL0 = (I2C0_RX_CTRL0 & ~(0xF81UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF81) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_RX_CTRL0_DNR +// SFDITEM_FIELD__I2C0_RX_CTRL0_RX_FLUSH +// SFDITEM_FIELD__I2C0_RX_CTRL0_RX_THRESH +// +// + + +// -------------------------- Register Item Address: I2C0_RX_CTRL1 ------------------------------ +// SVD Line: 4569 + +unsigned int I2C0_RX_CTRL1 __AT (0x4001D020); + + + +// ---------------------------- Field Item: I2C0_RX_CTRL1_RX_CNT -------------------------------- +// SVD Line: 4574 + +// SFDITEM_FIELD__I2C0_RX_CTRL1_RX_CNT +// RX_CNT +// +// [Bits 7..0] RW (@ 0x4001D020) Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. +// +// ( (unsigned char)((I2C0_RX_CTRL1 >> 0) & 0xFF), ((I2C0_RX_CTRL1 = (I2C0_RX_CTRL1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Field Item: I2C0_RX_CTRL1_RX_FIFO ------------------------------- +// SVD Line: 4579 + +// SFDITEM_FIELD__I2C0_RX_CTRL1_RX_FIFO +// RX_FIFO +// +// [Bits 11..8] RO (@ 0x4001D020) Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. +// +// ( (unsigned char)((I2C0_RX_CTRL1 >> 8) & 0xF) ) +// +// +// + + +// ------------------------------ Register RTree: I2C0_RX_CTRL1 --------------------------------- +// SVD Line: 4569 + +// SFDITEM_REG__I2C0_RX_CTRL1 +// RX_CTRL1 +// +// [Bits 31..0] RW (@ 0x4001D020) Receive Control Register 1. +// ( (unsigned int)((I2C0_RX_CTRL1 >> 0) & 0xFFFFFFFF), ((I2C0_RX_CTRL1 = (I2C0_RX_CTRL1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_RX_CTRL1_RX_CNT +// SFDITEM_FIELD__I2C0_RX_CTRL1_RX_FIFO +// +// + + +// -------------------------- Register Item Address: I2C0_TX_CTRL0 ------------------------------ +// SVD Line: 4587 + +unsigned int I2C0_TX_CTRL0 __AT (0x4001D024); + + + +// -------------------------- Field Item: I2C0_TX_CTRL0_TX_PRELOAD ------------------------------ +// SVD Line: 4592 + +// SFDITEM_FIELD__I2C0_TX_CTRL0_TX_PRELOAD +// TX_PRELOAD +// +// [Bit 0] RW (@ 0x4001D024) Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. +// +// ( (unsigned int) I2C0_TX_CTRL0 ) +// TX_PRELOAD +// +// +// + + +// ------------------------- Field Item: I2C0_TX_CTRL0_TX_READY_MODE ---------------------------- +// SVD Line: 4597 + +// SFDITEM_FIELD__I2C0_TX_CTRL0_TX_READY_MODE +// TX_READY_MODE +// +// [Bit 1] RW (@ 0x4001D024) \nTransmit FIFO Ready Manual Mode.\n0 : en = HW control of I2CTXRDY enabled.\n1 : dis = HW control of I2CTXRDY disabled. +// +// ( (unsigned int) I2C0_TX_CTRL0 ) +// TX_READY_MODE +// <0=> 0: en = HW control of I2CTXRDY enabled. +// <1=> 1: dis = HW control of I2CTXRDY disabled. +// +// +// + + +// --------------------------- Field Item: I2C0_TX_CTRL0_TX_FLUSH ------------------------------- +// SVD Line: 4614 + +// SFDITEM_FIELD__I2C0_TX_CTRL0_TX_FLUSH +// TX_FLUSH +// +// [Bit 7] RW (@ 0x4001D024) \nTransmit FIFO Flush. This bit is automatically cleared to 0 after the operation.\n0 : not_flushed = FIFO not flushed.\n1 : flush = Flush TX_FIFO. +// +// ( (unsigned int) I2C0_TX_CTRL0 ) +// TX_FLUSH +// <0=> 0: not_flushed = FIFO not flushed. +// <1=> 1: flush = Flush TX_FIFO. +// +// +// + + +// --------------------------- Field Item: I2C0_TX_CTRL0_TX_THRESH ------------------------------ +// SVD Line: 4631 + +// SFDITEM_FIELD__I2C0_TX_CTRL0_TX_THRESH +// TX_THRESH +// +// [Bits 11..8] RW (@ 0x4001D024) Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. +// +// ( (unsigned char)((I2C0_TX_CTRL0 >> 8) & 0xF), ((I2C0_TX_CTRL0 = (I2C0_TX_CTRL0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: I2C0_TX_CTRL0 --------------------------------- +// SVD Line: 4587 + +// SFDITEM_REG__I2C0_TX_CTRL0 +// TX_CTRL0 +// +// [Bits 31..0] RW (@ 0x4001D024) Transmit Control Register 0. +// ( (unsigned int)((I2C0_TX_CTRL0 >> 0) & 0xFFFFFFFF), ((I2C0_TX_CTRL0 = (I2C0_TX_CTRL0 & ~(0xF83UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF83) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_TX_CTRL0_TX_PRELOAD +// SFDITEM_FIELD__I2C0_TX_CTRL0_TX_READY_MODE +// SFDITEM_FIELD__I2C0_TX_CTRL0_TX_FLUSH +// SFDITEM_FIELD__I2C0_TX_CTRL0_TX_THRESH +// +// + + +// -------------------------- Register Item Address: I2C0_TX_CTRL1 ------------------------------ +// SVD Line: 4638 + +unsigned int I2C0_TX_CTRL1 __AT (0x4001D028); + + + +// --------------------------- Field Item: I2C0_TX_CTRL1_TX_READY ------------------------------- +// SVD Line: 4643 + +// SFDITEM_FIELD__I2C0_TX_CTRL1_TX_READY +// TX_READY +// +// [Bit 0] RW (@ 0x4001D028) Transmit FIFO Preload Ready. +// +// ( (unsigned int) I2C0_TX_CTRL1 ) +// TX_READY +// +// +// + + +// ---------------------------- Field Item: I2C0_TX_CTRL1_TX_LAST ------------------------------- +// SVD Line: 4648 + +// SFDITEM_FIELD__I2C0_TX_CTRL1_TX_LAST +// TX_LAST +// +// [Bit 1] RW (@ 0x4001D028) \nTransmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).\n0 : hold_scl_low = Hold SCL low on TX_FIFO empty.\n1 : end_transaction = End transaction on TX_FIFO empty. +// +// ( (unsigned int) I2C0_TX_CTRL1 ) +// TX_LAST +// <0=> 0: hold_scl_low = Hold SCL low on TX_FIFO empty. +// <1=> 1: end_transaction = End transaction on TX_FIFO empty. +// +// +// + + +// ---------------------------- Field Item: I2C0_TX_CTRL1_TX_FIFO ------------------------------- +// SVD Line: 4665 + +// SFDITEM_FIELD__I2C0_TX_CTRL1_TX_FIFO +// TX_FIFO +// +// [Bits 11..8] RO (@ 0x4001D028) Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. +// +// ( (unsigned char)((I2C0_TX_CTRL1 >> 8) & 0xF) ) +// +// +// + + +// ------------------------------ Register RTree: I2C0_TX_CTRL1 --------------------------------- +// SVD Line: 4638 + +// SFDITEM_REG__I2C0_TX_CTRL1 +// TX_CTRL1 +// +// [Bits 31..0] RW (@ 0x4001D028) Transmit Control Register 1. +// ( (unsigned int)((I2C0_TX_CTRL1 >> 0) & 0xFFFFFFFF), ((I2C0_TX_CTRL1 = (I2C0_TX_CTRL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_TX_CTRL1_TX_READY +// SFDITEM_FIELD__I2C0_TX_CTRL1_TX_LAST +// SFDITEM_FIELD__I2C0_TX_CTRL1_TX_FIFO +// +// + + +// ---------------------------- Register Item Address: I2C0_FIFO -------------------------------- +// SVD Line: 4673 + +unsigned int I2C0_FIFO __AT (0x4001D02C); + + + +// ------------------------------- Field Item: I2C0_FIFO_DATA ----------------------------------- +// SVD Line: 4678 + +// SFDITEM_FIELD__I2C0_FIFO_DATA +// DATA +// +// [Bits 7..0] RW (@ 0x4001D02C) Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. +// +// ( (unsigned char)((I2C0_FIFO >> 0) & 0xFF), ((I2C0_FIFO = (I2C0_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: I2C0_FIFO ----------------------------------- +// SVD Line: 4673 + +// SFDITEM_REG__I2C0_FIFO +// FIFO +// +// [Bits 31..0] RW (@ 0x4001D02C) Data Register. +// ( (unsigned int)((I2C0_FIFO >> 0) & 0xFFFFFFFF), ((I2C0_FIFO = (I2C0_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_FIFO_DATA +// +// + + +// ------------------------- Register Item Address: I2C0_MASTER_CTRL ---------------------------- +// SVD Line: 4686 + +unsigned int I2C0_MASTER_CTRL __AT (0x4001D030); + + + +// --------------------------- Field Item: I2C0_MASTER_CTRL_START ------------------------------- +// SVD Line: 4691 + +// SFDITEM_FIELD__I2C0_MASTER_CTRL_START +// START +// +// [Bit 0] RW (@ 0x4001D030) Setting this bit to 1 will start a master transfer. +// +// ( (unsigned int) I2C0_MASTER_CTRL ) +// START +// +// +// + + +// -------------------------- Field Item: I2C0_MASTER_CTRL_RESTART ------------------------------ +// SVD Line: 4696 + +// SFDITEM_FIELD__I2C0_MASTER_CTRL_RESTART +// RESTART +// +// [Bit 1] RW (@ 0x4001D030) Setting this bit to 1 will generate a repeated START. +// +// ( (unsigned int) I2C0_MASTER_CTRL ) +// RESTART +// +// +// + + +// ---------------------------- Field Item: I2C0_MASTER_CTRL_STOP ------------------------------- +// SVD Line: 4701 + +// SFDITEM_FIELD__I2C0_MASTER_CTRL_STOP +// STOP +// +// [Bit 2] RW (@ 0x4001D030) Setting this bit to 1 will generate a STOP condition. +// +// ( (unsigned int) I2C0_MASTER_CTRL ) +// STOP +// +// +// + + +// ------------------------- Field Item: I2C0_MASTER_CTRL_SL_EX_ADDR ---------------------------- +// SVD Line: 4706 + +// SFDITEM_FIELD__I2C0_MASTER_CTRL_SL_EX_ADDR +// SL_EX_ADDR +// +// [Bit 7] RW (@ 0x4001D030) \nSlave Extend Address Select.\n0 : 7_bits_address = 7-bit address.\n1 : 10_bits_address = 10-bit address. +// +// ( (unsigned int) I2C0_MASTER_CTRL ) +// SL_EX_ADDR +// <0=> 0: 7_bits_address = 7-bit address. +// <1=> 1: 10_bits_address = 10-bit address. +// +// +// + + +// ------------------------ Field Item: I2C0_MASTER_CTRL_MASTER_CODE ---------------------------- +// SVD Line: 4723 + +// SFDITEM_FIELD__I2C0_MASTER_CTRL_MASTER_CODE +// MASTER_CODE +// +// [Bits 10..8] RW (@ 0x4001D030) Master Code. These bits set the Master Code used in Hs-mode operation. +// +// ( (unsigned char)((I2C0_MASTER_CTRL >> 8) & 0x7), ((I2C0_MASTER_CTRL = (I2C0_MASTER_CTRL & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) )) +// +// +// + + +// ------------------------ Field Item: I2C0_MASTER_CTRL_SCL_SPEED_UP --------------------------- +// SVD Line: 4728 + +// SFDITEM_FIELD__I2C0_MASTER_CTRL_SCL_SPEED_UP +// SCL_SPEED_UP +// +// [Bit 11] RW (@ 0x4001D030) \nSerial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves.\n0 : en = Master monitors SCL state.\n1 : dis = SCL state monitoring disabled. +// +// ( (unsigned int) I2C0_MASTER_CTRL ) +// SCL_SPEED_UP +// <0=> 0: en = Master monitors SCL state. +// <1=> 1: dis = SCL state monitoring disabled. +// +// +// + + +// ---------------------------- Register RTree: I2C0_MASTER_CTRL -------------------------------- +// SVD Line: 4686 + +// SFDITEM_REG__I2C0_MASTER_CTRL +// MASTER_CTRL +// +// [Bits 31..0] RW (@ 0x4001D030) Master Control Register. +// ( (unsigned int)((I2C0_MASTER_CTRL >> 0) & 0xFFFFFFFF), ((I2C0_MASTER_CTRL = (I2C0_MASTER_CTRL & ~(0xF87UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF87) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_MASTER_CTRL_START +// SFDITEM_FIELD__I2C0_MASTER_CTRL_RESTART +// SFDITEM_FIELD__I2C0_MASTER_CTRL_STOP +// SFDITEM_FIELD__I2C0_MASTER_CTRL_SL_EX_ADDR +// SFDITEM_FIELD__I2C0_MASTER_CTRL_MASTER_CODE +// SFDITEM_FIELD__I2C0_MASTER_CTRL_SCL_SPEED_UP +// +// + + +// --------------------------- Register Item Address: I2C0_CLK_LO ------------------------------- +// SVD Line: 4747 + +unsigned int I2C0_CLK_LO __AT (0x4001D034); + + + +// ----------------------------- Field Item: I2C0_CLK_LO_CLK_LO --------------------------------- +// SVD Line: 4752 + +// SFDITEM_FIELD__I2C0_CLK_LO_CLK_LO +// CLK_LO +// +// [Bits 8..0] RW (@ 0x4001D034) Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. +// +// ( (unsigned short)((I2C0_CLK_LO >> 0) & 0x1FF), ((I2C0_CLK_LO = (I2C0_CLK_LO & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: I2C0_CLK_LO ---------------------------------- +// SVD Line: 4747 + +// SFDITEM_REG__I2C0_CLK_LO +// CLK_LO +// +// [Bits 31..0] RW (@ 0x4001D034) Clock Low Register. +// ( (unsigned int)((I2C0_CLK_LO >> 0) & 0xFFFFFFFF), ((I2C0_CLK_LO = (I2C0_CLK_LO & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_CLK_LO_CLK_LO +// +// + + +// --------------------------- Register Item Address: I2C0_CLK_HI ------------------------------- +// SVD Line: 4759 + +unsigned int I2C0_CLK_HI __AT (0x4001D038); + + + +// ------------------------------- Field Item: I2C0_CLK_HI_CKH ---------------------------------- +// SVD Line: 4764 + +// SFDITEM_FIELD__I2C0_CLK_HI_CKH +// CKH +// +// [Bits 8..0] RW (@ 0x4001D038) Clock High. In master mode, these bits define the SCL high period. +// +// ( (unsigned short)((I2C0_CLK_HI >> 0) & 0x1FF), ((I2C0_CLK_HI = (I2C0_CLK_HI & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: I2C0_CLK_HI ---------------------------------- +// SVD Line: 4759 + +// SFDITEM_REG__I2C0_CLK_HI +// CLK_HI +// +// [Bits 31..0] RW (@ 0x4001D038) Clock high Register. +// ( (unsigned int)((I2C0_CLK_HI >> 0) & 0xFFFFFFFF), ((I2C0_CLK_HI = (I2C0_CLK_HI & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_CLK_HI_CKH +// +// + + +// --------------------------- Register Item Address: I2C0_HS_CLK ------------------------------- +// SVD Line: 4771 + +unsigned int I2C0_HS_CLK __AT (0x4001D03C); + + + +// ---------------------------- Field Item: I2C0_HS_CLK_HS_CLK_LO ------------------------------- +// SVD Line: 4776 + +// SFDITEM_FIELD__I2C0_HS_CLK_HS_CLK_LO +// HS_CLK_LO +// +// [Bits 7..0] RW (@ 0x4001D03C) Slave Address. +// +// ( (unsigned char)((I2C0_HS_CLK >> 0) & 0xFF), ((I2C0_HS_CLK = (I2C0_HS_CLK & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Field Item: I2C0_HS_CLK_HS_CLK_HI ------------------------------- +// SVD Line: 4781 + +// SFDITEM_FIELD__I2C0_HS_CLK_HS_CLK_HI +// HS_CLK_HI +// +// [Bits 15..8] RW (@ 0x4001D03C) Slave Address. +// +// ( (unsigned char)((I2C0_HS_CLK >> 8) & 0xFF), ((I2C0_HS_CLK = (I2C0_HS_CLK & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: I2C0_HS_CLK ---------------------------------- +// SVD Line: 4771 + +// SFDITEM_REG__I2C0_HS_CLK +// HS_CLK +// +// [Bits 31..0] RW (@ 0x4001D03C) HS-Mode Clock Control Register +// ( (unsigned int)((I2C0_HS_CLK >> 0) & 0xFFFFFFFF), ((I2C0_HS_CLK = (I2C0_HS_CLK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_HS_CLK_HS_CLK_LO +// SFDITEM_FIELD__I2C0_HS_CLK_HS_CLK_HI +// +// + + +// --------------------------- Register Item Address: I2C0_TIMEOUT ------------------------------ +// SVD Line: 4788 + +unsigned int I2C0_TIMEOUT __AT (0x4001D040); + + + +// ------------------------------- Field Item: I2C0_TIMEOUT_TO ---------------------------------- +// SVD Line: 4793 + +// SFDITEM_FIELD__I2C0_TIMEOUT_TO +// TO +// +// [Bits 15..0] RW (@ 0x4001D040) Timeout +// +// ( (unsigned short)((I2C0_TIMEOUT >> 0) & 0xFFFF), ((I2C0_TIMEOUT = (I2C0_TIMEOUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: I2C0_TIMEOUT ---------------------------------- +// SVD Line: 4788 + +// SFDITEM_REG__I2C0_TIMEOUT +// TIMEOUT +// +// [Bits 31..0] RW (@ 0x4001D040) Timeout Register +// ( (unsigned int)((I2C0_TIMEOUT >> 0) & 0xFFFFFFFF), ((I2C0_TIMEOUT = (I2C0_TIMEOUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_TIMEOUT_TO +// +// + + +// ------------------------- Register Item Address: I2C0_SLAVE_ADDR ----------------------------- +// SVD Line: 4800 + +unsigned int I2C0_SLAVE_ADDR __AT (0x4001D044); + + + +// ------------------------- Field Item: I2C0_SLAVE_ADDR_SLAVE_ADDR ----------------------------- +// SVD Line: 4805 + +// SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR +// SLAVE_ADDR +// +// [Bits 9..0] RW (@ 0x4001D044) Slave Address. +// +// ( (unsigned short)((I2C0_SLAVE_ADDR >> 0) & 0x3FF), ((I2C0_SLAVE_ADDR = (I2C0_SLAVE_ADDR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) )) +// +// +// + + +// ----------------------- Field Item: I2C0_SLAVE_ADDR_SLAVE_ADDR_DIS --------------------------- +// SVD Line: 4810 + +// SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR_DIS +// SLAVE_ADDR_DIS +// +// [Bit 10] RW (@ 0x4001D044) Slave Address DIS. +// +// ( (unsigned int) I2C0_SLAVE_ADDR ) +// SLAVE_ADDR_DIS +// +// +// + + +// ----------------------- Field Item: I2C0_SLAVE_ADDR_SLAVE_ADDR_IDX --------------------------- +// SVD Line: 4815 + +// SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR_IDX +// SLAVE_ADDR_IDX +// +// [Bits 14..11] RW (@ 0x4001D044) Slave Address Index. +// +// ( (unsigned char)((I2C0_SLAVE_ADDR >> 11) & 0xF), ((I2C0_SLAVE_ADDR = (I2C0_SLAVE_ADDR & ~(0xFUL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 11 ) ) )) +// +// +// + + +// --------------------------- Field Item: I2C0_SLAVE_ADDR_EX_ADDR ------------------------------ +// SVD Line: 4820 + +// SFDITEM_FIELD__I2C0_SLAVE_ADDR_EX_ADDR +// EX_ADDR +// +// [Bit 15] RW (@ 0x4001D044) \nExtended Address Select.\n0 : 7_bits_address = 7-bit address.\n1 : 10_bits_address = 10-bit address. +// +// ( (unsigned int) I2C0_SLAVE_ADDR ) +// EX_ADDR +// <0=> 0: 7_bits_address = 7-bit address. +// <1=> 1: 10_bits_address = 10-bit address. +// +// +// + + +// ----------------------------- Register RTree: I2C0_SLAVE_ADDR -------------------------------- +// SVD Line: 4800 + +// SFDITEM_REG__I2C0_SLAVE_ADDR +// SLAVE_ADDR +// +// [Bits 31..0] RW (@ 0x4001D044) Slave Address Register. +// ( (unsigned int)((I2C0_SLAVE_ADDR >> 0) & 0xFFFFFFFF), ((I2C0_SLAVE_ADDR = (I2C0_SLAVE_ADDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR +// SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR_DIS +// SFDITEM_FIELD__I2C0_SLAVE_ADDR_SLAVE_ADDR_IDX +// SFDITEM_FIELD__I2C0_SLAVE_ADDR_EX_ADDR +// +// + + +// ----------------------------- Register Item Address: I2C0_DMA -------------------------------- +// SVD Line: 4839 + +unsigned int I2C0_DMA __AT (0x4001D048); + + + +// ------------------------------- Field Item: I2C0_DMA_TX_EN ----------------------------------- +// SVD Line: 4844 + +// SFDITEM_FIELD__I2C0_DMA_TX_EN +// TX_EN +// +// [Bit 0] RW (@ 0x4001D048) \nTX channel enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) I2C0_DMA ) +// TX_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: I2C0_DMA_RX_EN ----------------------------------- +// SVD Line: 4861 + +// SFDITEM_FIELD__I2C0_DMA_RX_EN +// RX_EN +// +// [Bit 1] RW (@ 0x4001D048) \nRX channel enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) I2C0_DMA ) +// RX_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Register RTree: I2C0_DMA ------------------------------------ +// SVD Line: 4839 + +// SFDITEM_REG__I2C0_DMA +// DMA +// +// [Bits 31..0] RW (@ 0x4001D048) DMA Register. +// ( (unsigned int)((I2C0_DMA >> 0) & 0xFFFFFFFF), ((I2C0_DMA = (I2C0_DMA & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__I2C0_DMA_TX_EN +// SFDITEM_FIELD__I2C0_DMA_RX_EN +// +// + + +// ---------------------------------- Peripheral View: I2C0 ------------------------------------- +// SVD Line: 3420 + +// I2C0 +// I2C0 +// SFDITEM_REG__I2C0_CTRL +// SFDITEM_REG__I2C0_STATUS +// SFDITEM_REG__I2C0_INT_FL0 +// SFDITEM_REG__I2C0_INT_EN0 +// SFDITEM_REG__I2C0_INT_FL1 +// SFDITEM_REG__I2C0_INT_EN1 +// SFDITEM_REG__I2C0_FIFO_LEN +// SFDITEM_REG__I2C0_RX_CTRL0 +// SFDITEM_REG__I2C0_RX_CTRL1 +// SFDITEM_REG__I2C0_TX_CTRL0 +// SFDITEM_REG__I2C0_TX_CTRL1 +// SFDITEM_REG__I2C0_FIFO +// SFDITEM_REG__I2C0_MASTER_CTRL +// SFDITEM_REG__I2C0_CLK_LO +// SFDITEM_REG__I2C0_CLK_HI +// SFDITEM_REG__I2C0_HS_CLK +// SFDITEM_REG__I2C0_TIMEOUT +// SFDITEM_REG__I2C0_SLAVE_ADDR +// SFDITEM_REG__I2C0_DMA +// +// + + +// ---------------------------- Register Item Address: I2C1_CTRL -------------------------------- +// SVD Line: 3437 + +unsigned int I2C1_CTRL __AT (0x4001E000); + + + +// ------------------------------ Field Item: I2C1_CTRL_I2C_EN ---------------------------------- +// SVD Line: 3442 + +// SFDITEM_FIELD__I2C1_CTRL_I2C_EN +// I2C_EN +// +// [Bit 0] RW (@ 0x4001E000) \nI2C Enable.\n0 : dis = Disable I2C.\n1 : en = enable I2C. +// +// ( (unsigned int) I2C1_CTRL ) +// I2C_EN +// <0=> 0: dis = Disable I2C. +// <1=> 1: en = enable I2C. +// +// +// + + +// -------------------------------- Field Item: I2C1_CTRL_MST ----------------------------------- +// SVD Line: 3460 + +// SFDITEM_FIELD__I2C1_CTRL_MST +// MST +// +// [Bit 1] RW (@ 0x4001E000) \nMaster Mode Enable.\n0 : slave_mode = Slave Mode.\n1 : master_mode = Master Mode. +// +// ( (unsigned int) I2C1_CTRL ) +// MST +// <0=> 0: slave_mode = Slave Mode. +// <1=> 1: master_mode = Master Mode. +// +// +// + + +// --------------------------- Field Item: I2C1_CTRL_GEN_CALL_ADDR ------------------------------ +// SVD Line: 3478 + +// SFDITEM_FIELD__I2C1_CTRL_GEN_CALL_ADDR +// GEN_CALL_ADDR +// +// [Bit 2] RW (@ 0x4001E000) \nGeneral Call Address Enable.\n0 : dis = Ignore Gneral Call Address.\n1 : en = Acknowledge general call address. +// +// ( (unsigned int) I2C1_CTRL ) +// GEN_CALL_ADDR +// <0=> 0: dis = Ignore Gneral Call Address. +// <1=> 1: en = Acknowledge general call address. +// +// +// + + +// ------------------------------ Field Item: I2C1_CTRL_RX_MODE --------------------------------- +// SVD Line: 3496 + +// SFDITEM_FIELD__I2C1_CTRL_RX_MODE +// RX_MODE +// +// [Bit 3] RW (@ 0x4001E000) \nInteractive Receive Mode.\n0 : dis = Disable Interactive Receive Mode.\n1 : en = Enable Interactive Receive Mode. +// +// ( (unsigned int) I2C1_CTRL ) +// RX_MODE +// <0=> 0: dis = Disable Interactive Receive Mode. +// <1=> 1: en = Enable Interactive Receive Mode. +// +// +// + + +// ---------------------------- Field Item: I2C1_CTRL_RX_MODE_ACK ------------------------------- +// SVD Line: 3514 + +// SFDITEM_FIELD__I2C1_CTRL_RX_MODE_ACK +// RX_MODE_ACK +// +// [Bit 4] RW (@ 0x4001E000) \nData Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.\n0 : ack = return ACK (pulling SDA LOW).\n1 : nack = return NACK (leaving SDA HIGH). +// +// ( (unsigned int) I2C1_CTRL ) +// RX_MODE_ACK +// <0=> 0: ack = return ACK (pulling SDA LOW). +// <1=> 1: nack = return NACK (leaving SDA HIGH). +// +// +// + + +// ------------------------------ Field Item: I2C1_CTRL_SCL_OUT --------------------------------- +// SVD Line: 3532 + +// SFDITEM_FIELD__I2C1_CTRL_SCL_OUT +// SCL_OUT +// +// [Bit 6] RW (@ 0x4001E000) \nSCL Output. This bits control SCL output when SWOE =1.\n0 : drive_scl_low = Drive SCL low.\n1 : release_scl = Release SCL. +// +// ( (unsigned int) I2C1_CTRL ) +// SCL_OUT +// <0=> 0: drive_scl_low = Drive SCL low. +// <1=> 1: release_scl = Release SCL. +// +// +// + + +// ------------------------------ Field Item: I2C1_CTRL_SDA_OUT --------------------------------- +// SVD Line: 3550 + +// SFDITEM_FIELD__I2C1_CTRL_SDA_OUT +// SDA_OUT +// +// [Bit 7] RW (@ 0x4001E000) \nSDA Output. This bits control SDA output when SWOE = 1.\n0 : drive_sda_low = Drive SDA low.\n1 : release_sda = Release SDA. +// +// ( (unsigned int) I2C1_CTRL ) +// SDA_OUT +// <0=> 0: drive_sda_low = Drive SDA low. +// <1=> 1: release_sda = Release SDA. +// +// +// + + +// -------------------------------- Field Item: I2C1_CTRL_SCL ----------------------------------- +// SVD Line: 3568 + +// SFDITEM_FIELD__I2C1_CTRL_SCL +// SCL +// +// [Bit 8] RO (@ 0x4001E000) SCL status. This bit reflects the logic gate of SCL signal. +// +// ( (unsigned int) I2C1_CTRL ) +// SCL +// +// +// + + +// -------------------------------- Field Item: I2C1_CTRL_SDA ----------------------------------- +// SVD Line: 3574 + +// SFDITEM_FIELD__I2C1_CTRL_SDA +// SDA +// +// [Bit 9] RO (@ 0x4001E000) SDA status. THis bit reflects the logic gate of SDA signal. +// +// ( (unsigned int) I2C1_CTRL ) +// SDA +// +// +// + + +// ----------------------------- Field Item: I2C1_CTRL_SW_OUT_EN -------------------------------- +// SVD Line: 3580 + +// SFDITEM_FIELD__I2C1_CTRL_SW_OUT_EN +// SW_OUT_EN +// +// [Bit 10] RW (@ 0x4001E000) \nSoftware Output Enable.\n0 : outputs_disable = I2C Outputs SCLO and SDAO disabled.\n1 : outputs_enable = I2C Outputs SCLO and SDAO enabled. +// +// ( (unsigned int) I2C1_CTRL ) +// SW_OUT_EN +// <0=> 0: outputs_disable = I2C Outputs SCLO and SDAO disabled. +// <1=> 1: outputs_enable = I2C Outputs SCLO and SDAO enabled. +// +// +// + + +// ------------------------------- Field Item: I2C1_CTRL_READ ----------------------------------- +// SVD Line: 3598 + +// SFDITEM_FIELD__I2C1_CTRL_READ +// READ +// +// [Bit 11] RO (@ 0x4001E000) \nRead. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.\n0 : write = Write.\n1 : read = Read. +// +// ( (unsigned int) I2C1_CTRL ) +// READ +// <0=> 0: write = Write. +// <1=> 1: read = Read. +// +// +// + + +// ------------------------ Field Item: I2C1_CTRL_SCL_CLK_STRECH_DIS ---------------------------- +// SVD Line: 3616 + +// SFDITEM_FIELD__I2C1_CTRL_SCL_CLK_STRECH_DIS +// SCL_CLK_STRECH_DIS +// +// [Bit 12] RW (@ 0x4001E000) \nThis bit will disable slave clock stretching when set.\n0 : en = Slave clock stretching enabled.\n1 : dis = Slave clock stretching disabled. +// +// ( (unsigned int) I2C1_CTRL ) +// SCL_CLK_STRECH_DIS +// <0=> 0: en = Slave clock stretching enabled. +// <1=> 1: dis = Slave clock stretching disabled. +// +// +// + + +// ---------------------------- Field Item: I2C1_CTRL_SCL_PP_MODE ------------------------------- +// SVD Line: 3634 + +// SFDITEM_FIELD__I2C1_CTRL_SCL_PP_MODE +// SCL_PP_MODE +// +// [Bit 13] RW (@ 0x4001E000) \nSCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.\n0 : dis = Standard open-drain operation: drive low for 0, Hi-Z for 1\n1 : en = Non-standard push-pull operation: drive low for 0, drive high for 1 +// +// ( (unsigned int) I2C1_CTRL ) +// SCL_PP_MODE +// <0=> 0: dis = Standard open-drain operation: drive low for 0, Hi-Z for 1 +// <1=> 1: en = Non-standard push-pull operation: drive low for 0, drive high for 1 +// +// +// + + +// ------------------------------ Field Item: I2C1_CTRL_HS_MODE --------------------------------- +// SVD Line: 3652 + +// SFDITEM_FIELD__I2C1_CTRL_HS_MODE +// HS_MODE +// +// [Bit 15] RW (@ 0x4001E000) \nHs-mode Enable.\n0 : dis = Hs-mode disabled.\n1 : en = Hs-mode enabled. +// +// ( (unsigned int) I2C1_CTRL ) +// HS_MODE +// <0=> 0: dis = Hs-mode disabled. +// <1=> 1: en = Hs-mode enabled. +// +// +// + + +// -------------------------------- Register RTree: I2C1_CTRL ----------------------------------- +// SVD Line: 3437 + +// SFDITEM_REG__I2C1_CTRL +// CTRL +// +// [Bits 31..0] RW (@ 0x4001E000) Control Register0. +// ( (unsigned int)((I2C1_CTRL >> 0) & 0xFFFFFFFF), ((I2C1_CTRL = (I2C1_CTRL & ~(0xB4DFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB4DF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_CTRL_I2C_EN +// SFDITEM_FIELD__I2C1_CTRL_MST +// SFDITEM_FIELD__I2C1_CTRL_GEN_CALL_ADDR +// SFDITEM_FIELD__I2C1_CTRL_RX_MODE +// SFDITEM_FIELD__I2C1_CTRL_RX_MODE_ACK +// SFDITEM_FIELD__I2C1_CTRL_SCL_OUT +// SFDITEM_FIELD__I2C1_CTRL_SDA_OUT +// SFDITEM_FIELD__I2C1_CTRL_SCL +// SFDITEM_FIELD__I2C1_CTRL_SDA +// SFDITEM_FIELD__I2C1_CTRL_SW_OUT_EN +// SFDITEM_FIELD__I2C1_CTRL_READ +// SFDITEM_FIELD__I2C1_CTRL_SCL_CLK_STRECH_DIS +// SFDITEM_FIELD__I2C1_CTRL_SCL_PP_MODE +// SFDITEM_FIELD__I2C1_CTRL_HS_MODE +// +// + + +// --------------------------- Register Item Address: I2C1_STATUS ------------------------------- +// SVD Line: 3672 + +unsigned int I2C1_STATUS __AT (0x4001E004); + + + +// ------------------------------- Field Item: I2C1_STATUS_BUS ---------------------------------- +// SVD Line: 3677 + +// SFDITEM_FIELD__I2C1_STATUS_BUS +// BUS +// +// [Bit 0] RO (@ 0x4001E004) \nBus Status.\n0 : idle = I2C Bus Idle.\n1 : busy = I2C Bus Busy. +// +// ( (unsigned int) I2C1_STATUS ) +// BUS +// <0=> 0: idle = I2C Bus Idle. +// <1=> 1: busy = I2C Bus Busy. +// +// +// + + +// ---------------------------- Field Item: I2C1_STATUS_RX_EMPTY -------------------------------- +// SVD Line: 3695 + +// SFDITEM_FIELD__I2C1_STATUS_RX_EMPTY +// RX_EMPTY +// +// [Bit 1] RO (@ 0x4001E004) \nRX empty.\n0 : not_empty = Not Empty.\n1 : empty = Empty. +// +// ( (unsigned int) I2C1_STATUS ) +// RX_EMPTY +// <0=> 0: not_empty = Not Empty. +// <1=> 1: empty = Empty. +// +// +// + + +// ----------------------------- Field Item: I2C1_STATUS_RX_FULL -------------------------------- +// SVD Line: 3713 + +// SFDITEM_FIELD__I2C1_STATUS_RX_FULL +// RX_FULL +// +// [Bit 2] RO (@ 0x4001E004) \nRX Full.\n0 : not_full = Not Full.\n1 : full = Full. +// +// ( (unsigned int) I2C1_STATUS ) +// RX_FULL +// <0=> 0: not_full = Not Full. +// <1=> 1: full = Full. +// +// +// + + +// ---------------------------- Field Item: I2C1_STATUS_TX_EMPTY -------------------------------- +// SVD Line: 3731 + +// SFDITEM_FIELD__I2C1_STATUS_TX_EMPTY +// TX_EMPTY +// +// [Bit 3] RW (@ 0x4001E004) \nTX Empty.\n0 : not_empty = Not Empty.\n1 : empty = Empty. +// +// ( (unsigned int) I2C1_STATUS ) +// TX_EMPTY +// <0=> 0: not_empty = Not Empty. +// <1=> 1: empty = Empty. +// +// +// + + +// ----------------------------- Field Item: I2C1_STATUS_TX_FULL -------------------------------- +// SVD Line: 3748 + +// SFDITEM_FIELD__I2C1_STATUS_TX_FULL +// TX_FULL +// +// [Bit 4] RW (@ 0x4001E004) \nTX Full.\n0 : not_empty = Not Empty.\n1 : empty = Empty. +// +// ( (unsigned int) I2C1_STATUS ) +// TX_FULL +// <0=> 0: not_empty = Not Empty. +// <1=> 1: empty = Empty. +// +// +// + + +// ---------------------------- Field Item: I2C1_STATUS_CLK_MODE -------------------------------- +// SVD Line: 3765 + +// SFDITEM_FIELD__I2C1_STATUS_CLK_MODE +// CLK_MODE +// +// [Bit 5] RO (@ 0x4001E004) \nClock Mode.\n0 : not_actively_driving_scl_clock = Device not actively driving SCL clock cycles.\n1 : actively_driving_scl_clock = Device operating as master and actively driving SCL clock cycles. +// +// ( (unsigned int) I2C1_STATUS ) +// CLK_MODE +// <0=> 0: not_actively_driving_scl_clock = Device not actively driving SCL clock cycles. +// <1=> 1: actively_driving_scl_clock = Device operating as master and actively driving SCL clock cycles. +// +// +// + + +// ----------------------------- Field Item: I2C1_STATUS_STATUS --------------------------------- +// SVD Line: 3783 + +// SFDITEM_FIELD__I2C1_STATUS_STATUS +// STATUS +// +// [Bits 11..8] RW (@ 0x4001E004) \nController Status.\n0 : idle = Controller Idle.\n1 : mtx_addr = master Transmit address.\n2 : mrx_addr_ack = Master Receive address ACK.\n3 : mtx_ex_addr = Master Transmit extended address.\n4 : mrx_ex_addr = Master Receive extended address ACK.\n5 : srx_addr = Slave Receive address.\n6 : stx_addr_ack = Slave Transmit address ACK.\n7 : srx_ex_addr = Slave Receive extended address.\n8 : stx_ex_addr_ack = Slave Transmit extended address ACK.\n9 : tx = Transmit data (master or slave).\n10 : rx_ack = Receive data ACK (master or slave).\n11 : rx = Receive data (master or slave).\n12 : tx_ack = Transmit data ACK (master or slave).\n13 : nack = NACK stage (master or slave).\n14 : Reserved - do not use\n15 : by_st = Bystander state (ongoing transaction but not participant- another master addressing another slave). +// +// ( (unsigned int) I2C1_STATUS ) +// STATUS +// <0=> 0: idle = Controller Idle. +// <1=> 1: mtx_addr = master Transmit address. +// <2=> 2: mrx_addr_ack = Master Receive address ACK. +// <3=> 3: mtx_ex_addr = Master Transmit extended address. +// <4=> 4: mrx_ex_addr = Master Receive extended address ACK. +// <5=> 5: srx_addr = Slave Receive address. +// <6=> 6: stx_addr_ack = Slave Transmit address ACK. +// <7=> 7: srx_ex_addr = Slave Receive extended address. +// <8=> 8: stx_ex_addr_ack = Slave Transmit extended address ACK. +// <9=> 9: tx = Transmit data (master or slave). +// <10=> 10: rx_ack = Receive data ACK (master or slave). +// <11=> 11: rx = Receive data (master or slave). +// <12=> 12: tx_ack = Transmit data ACK (master or slave). +// <13=> 13: nack = NACK stage (master or slave). +// <14=> 14: +// <15=> 15: by_st = Bystander state (ongoing transaction but not participant- another master addressing another slave). +// +// +// + + +// ------------------------------- Register RTree: I2C1_STATUS ---------------------------------- +// SVD Line: 3672 + +// SFDITEM_REG__I2C1_STATUS +// STATUS +// +// [Bits 31..0] RW (@ 0x4001E004) Status Register. +// ( (unsigned int)((I2C1_STATUS >> 0) & 0xFFFFFFFF), ((I2C1_STATUS = (I2C1_STATUS & ~(0xF18UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF18) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_STATUS_BUS +// SFDITEM_FIELD__I2C1_STATUS_RX_EMPTY +// SFDITEM_FIELD__I2C1_STATUS_RX_FULL +// SFDITEM_FIELD__I2C1_STATUS_TX_EMPTY +// SFDITEM_FIELD__I2C1_STATUS_TX_FULL +// SFDITEM_FIELD__I2C1_STATUS_CLK_MODE +// SFDITEM_FIELD__I2C1_STATUS_STATUS +// +// + + +// --------------------------- Register Item Address: I2C1_INT_FL0 ------------------------------ +// SVD Line: 3867 + +unsigned int I2C1_INT_FL0 __AT (0x4001E008); + + + +// ------------------------------ Field Item: I2C1_INT_FL0_DONE --------------------------------- +// SVD Line: 3872 + +// SFDITEM_FIELD__I2C1_INT_FL0_DONE +// DONE +// +// [Bit 0] RW (@ 0x4001E008) \nTransfer Done Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// DONE +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_FL0_RX_MODE -------------------------------- +// SVD Line: 3890 + +// SFDITEM_FIELD__I2C1_INT_FL0_RX_MODE +// RX_MODE +// +// [Bit 1] RW (@ 0x4001E008) \nInteractive Receive Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// RX_MODE +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ------------------------- Field Item: I2C1_INT_FL0_GEN_CALL_ADDR ----------------------------- +// SVD Line: 3907 + +// SFDITEM_FIELD__I2C1_INT_FL0_GEN_CALL_ADDR +// GEN_CALL_ADDR +// +// [Bit 2] RW (@ 0x4001E008) \nSlave General Call Address Match Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// GEN_CALL_ADDR +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// --------------------------- Field Item: I2C1_INT_FL0_ADDR_MATCH ------------------------------ +// SVD Line: 3924 + +// SFDITEM_FIELD__I2C1_INT_FL0_ADDR_MATCH +// ADDR_MATCH +// +// [Bit 3] RW (@ 0x4001E008) \nSlave Address Match Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// ADDR_MATCH +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// --------------------------- Field Item: I2C1_INT_FL0_RX_THRESH ------------------------------- +// SVD Line: 3941 + +// SFDITEM_FIELD__I2C1_INT_FL0_RX_THRESH +// RX_THRESH +// +// [Bit 4] RW (@ 0x4001E008) \nReceive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. RX_FIFO equal or more bytes than the threshold. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// RX_THRESH +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. RX_FIFO equal or more bytes than the threshold. +// +// +// + + +// --------------------------- Field Item: I2C1_INT_FL0_TX_THRESH ------------------------------- +// SVD Line: 3958 + +// SFDITEM_FIELD__I2C1_INT_FL0_TX_THRESH +// TX_THRESH +// +// [Bit 5] RW (@ 0x4001E008) \nTransmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// TX_THRESH +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. +// +// +// + + +// ------------------------------ Field Item: I2C1_INT_FL0_STOP --------------------------------- +// SVD Line: 3975 + +// SFDITEM_FIELD__I2C1_INT_FL0_STOP +// STOP +// +// [Bit 6] RW (@ 0x4001E008) \nSTOP Interrupt.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// STOP +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_FL0_ADDR_ACK ------------------------------- +// SVD Line: 3992 + +// SFDITEM_FIELD__I2C1_INT_FL0_ADDR_ACK +// ADDR_ACK +// +// [Bit 7] RW (@ 0x4001E008) \nAddress Acknowledge Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// ADDR_ACK +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ----------------------------- Field Item: I2C1_INT_FL0_ARB_ER -------------------------------- +// SVD Line: 4009 + +// SFDITEM_FIELD__I2C1_INT_FL0_ARB_ER +// ARB_ER +// +// [Bit 8] RW (@ 0x4001E008) \nArbritation error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// ARB_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ----------------------------- Field Item: I2C1_INT_FL0_TO_ER --------------------------------- +// SVD Line: 4026 + +// SFDITEM_FIELD__I2C1_INT_FL0_TO_ER +// TO_ER +// +// [Bit 9] RW (@ 0x4001E008) \ntimeout Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// TO_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// -------------------------- Field Item: I2C1_INT_FL0_ADDR_NACK_ER ----------------------------- +// SVD Line: 4043 + +// SFDITEM_FIELD__I2C1_INT_FL0_ADDR_NACK_ER +// ADDR_NACK_ER +// +// [Bit 10] RW (@ 0x4001E008) \nAddress NACK Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// ADDR_NACK_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_FL0_DATA_ER -------------------------------- +// SVD Line: 4060 + +// SFDITEM_FIELD__I2C1_INT_FL0_DATA_ER +// DATA_ER +// +// [Bit 11] RW (@ 0x4001E008) \nData NACK Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// DATA_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ------------------------- Field Item: I2C1_INT_FL0_DO_NOT_RESP_ER ---------------------------- +// SVD Line: 4077 + +// SFDITEM_FIELD__I2C1_INT_FL0_DO_NOT_RESP_ER +// DO_NOT_RESP_ER +// +// [Bit 12] RW (@ 0x4001E008) \nDo Not Respond Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// DO_NOT_RESP_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_FL0_START_ER ------------------------------- +// SVD Line: 4094 + +// SFDITEM_FIELD__I2C1_INT_FL0_START_ER +// START_ER +// +// [Bit 13] RW (@ 0x4001E008) \nStart Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// START_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_FL0_STOP_ER -------------------------------- +// SVD Line: 4111 + +// SFDITEM_FIELD__I2C1_INT_FL0_STOP_ER +// STOP_ER +// +// [Bit 14] RW (@ 0x4001E008) \nStop Error Interrupt.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// STOP_ER +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// -------------------------- Field Item: I2C1_INT_FL0_TX_LOCK_OUT ------------------------------ +// SVD Line: 4128 + +// SFDITEM_FIELD__I2C1_INT_FL0_TX_LOCK_OUT +// TX_LOCK_OUT +// +// [Bit 15] RW (@ 0x4001E008) Transmit Lock Out Interrupt. +// +// ( (unsigned int) I2C1_INT_FL0 ) +// TX_LOCK_OUT +// +// +// + + +// ------------------------------ Register RTree: I2C1_INT_FL0 ---------------------------------- +// SVD Line: 3867 + +// SFDITEM_REG__I2C1_INT_FL0 +// INT_FL0 +// +// [Bits 31..0] RW (@ 0x4001E008) Interrupt Status Register. +// ( (unsigned int)((I2C1_INT_FL0 >> 0) & 0xFFFFFFFF), ((I2C1_INT_FL0 = (I2C1_INT_FL0 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_INT_FL0_DONE +// SFDITEM_FIELD__I2C1_INT_FL0_RX_MODE +// SFDITEM_FIELD__I2C1_INT_FL0_GEN_CALL_ADDR +// SFDITEM_FIELD__I2C1_INT_FL0_ADDR_MATCH +// SFDITEM_FIELD__I2C1_INT_FL0_RX_THRESH +// SFDITEM_FIELD__I2C1_INT_FL0_TX_THRESH +// SFDITEM_FIELD__I2C1_INT_FL0_STOP +// SFDITEM_FIELD__I2C1_INT_FL0_ADDR_ACK +// SFDITEM_FIELD__I2C1_INT_FL0_ARB_ER +// SFDITEM_FIELD__I2C1_INT_FL0_TO_ER +// SFDITEM_FIELD__I2C1_INT_FL0_ADDR_NACK_ER +// SFDITEM_FIELD__I2C1_INT_FL0_DATA_ER +// SFDITEM_FIELD__I2C1_INT_FL0_DO_NOT_RESP_ER +// SFDITEM_FIELD__I2C1_INT_FL0_START_ER +// SFDITEM_FIELD__I2C1_INT_FL0_STOP_ER +// SFDITEM_FIELD__I2C1_INT_FL0_TX_LOCK_OUT +// +// + + +// --------------------------- Register Item Address: I2C1_INT_EN0 ------------------------------ +// SVD Line: 4135 + +unsigned int I2C1_INT_EN0 __AT (0x4001E00C); + + + +// ------------------------------ Field Item: I2C1_INT_EN0_DONE --------------------------------- +// SVD Line: 4141 + +// SFDITEM_FIELD__I2C1_INT_EN0_DONE +// DONE +// +// [Bit 0] RW (@ 0x4001E00C) \nTransfer Done Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when DONE = 1. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// DONE +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when DONE = 1. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_EN0_RX_MODE -------------------------------- +// SVD Line: 4159 + +// SFDITEM_FIELD__I2C1_INT_EN0_RX_MODE +// RX_MODE +// +// [Bit 1] RW (@ 0x4001E00C) \nDescription not available.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when RX_MODE = 1. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// RX_MODE +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when RX_MODE = 1. +// +// +// + + +// ------------------------- Field Item: I2C1_INT_EN0_GEN_CTRL_ADDR ----------------------------- +// SVD Line: 4177 + +// SFDITEM_FIELD__I2C1_INT_EN0_GEN_CTRL_ADDR +// GEN_CTRL_ADDR +// +// [Bit 2] RW (@ 0x4001E00C) \nSlave mode general call address match received input enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when GEN_CTRL_ADDR = 1. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// GEN_CTRL_ADDR +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when GEN_CTRL_ADDR = 1. +// +// +// + + +// --------------------------- Field Item: I2C1_INT_EN0_ADDR_MATCH ------------------------------ +// SVD Line: 4195 + +// SFDITEM_FIELD__I2C1_INT_EN0_ADDR_MATCH +// ADDR_MATCH +// +// [Bit 3] RW (@ 0x4001E00C) \nSlave mode incoming address match interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when ADDR_MATCH = 1. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// ADDR_MATCH +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when ADDR_MATCH = 1. +// +// +// + + +// --------------------------- Field Item: I2C1_INT_EN0_RX_THRESH ------------------------------- +// SVD Line: 4213 + +// SFDITEM_FIELD__I2C1_INT_EN0_RX_THRESH +// RX_THRESH +// +// [Bit 4] RW (@ 0x4001E00C) \nRX FIFO Above Treshold Level Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// RX_THRESH +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// --------------------------- Field Item: I2C1_INT_EN0_TX_THRESH ------------------------------- +// SVD Line: 4231 + +// SFDITEM_FIELD__I2C1_INT_EN0_TX_THRESH +// TX_THRESH +// +// [Bit 5] RW (@ 0x4001E00C) \nTX FIFO Below Treshold Level Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// TX_THRESH +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ------------------------------ Field Item: I2C1_INT_EN0_STOP --------------------------------- +// SVD Line: 4248 + +// SFDITEM_FIELD__I2C1_INT_EN0_STOP +// STOP +// +// [Bit 6] RW (@ 0x4001E00C) \nStop Interrupt Enable\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when STOP = 1. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// STOP +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when STOP = 1. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_EN0_ADDR_ACK ------------------------------- +// SVD Line: 4266 + +// SFDITEM_FIELD__I2C1_INT_EN0_ADDR_ACK +// ADDR_ACK +// +// [Bit 7] RW (@ 0x4001E00C) \nReceived Address ACK from Slave Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// ADDR_ACK +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ----------------------------- Field Item: I2C1_INT_EN0_ARB_ER -------------------------------- +// SVD Line: 4283 + +// SFDITEM_FIELD__I2C1_INT_EN0_ARB_ER +// ARB_ER +// +// [Bit 8] RW (@ 0x4001E00C) \nMaster Mode Arbitration Lost Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// ARB_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ----------------------------- Field Item: I2C1_INT_EN0_TO_ER --------------------------------- +// SVD Line: 4300 + +// SFDITEM_FIELD__I2C1_INT_EN0_TO_ER +// TO_ER +// +// [Bit 9] RW (@ 0x4001E00C) \nTimeout Error Interrupt Enable.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// TO_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_EN0_ADDR_ER -------------------------------- +// SVD Line: 4317 + +// SFDITEM_FIELD__I2C1_INT_EN0_ADDR_ER +// ADDR_ER +// +// [Bit 10] RW (@ 0x4001E00C) \nMaster Mode Address NACK Received Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// ADDR_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_EN0_DATA_ER -------------------------------- +// SVD Line: 4334 + +// SFDITEM_FIELD__I2C1_INT_EN0_DATA_ER +// DATA_ER +// +// [Bit 11] RW (@ 0x4001E00C) \nMaster Mode Data NACK Received Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// DATA_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ------------------------- Field Item: I2C1_INT_EN0_DO_NOT_RESP_ER ---------------------------- +// SVD Line: 4351 + +// SFDITEM_FIELD__I2C1_INT_EN0_DO_NOT_RESP_ER +// DO_NOT_RESP_ER +// +// [Bit 12] RW (@ 0x4001E00C) \nSlave Mode Do Not Respond Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// DO_NOT_RESP_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_EN0_START_ER ------------------------------- +// SVD Line: 4368 + +// SFDITEM_FIELD__I2C1_INT_EN0_START_ER +// START_ER +// +// [Bit 13] RW (@ 0x4001E00C) \nOut of Sequence START condition detected interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// START_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// ---------------------------- Field Item: I2C1_INT_EN0_STOP_ER -------------------------------- +// SVD Line: 4385 + +// SFDITEM_FIELD__I2C1_INT_EN0_STOP_ER +// STOP_ER +// +// [Bit 14] RW (@ 0x4001E00C) \nOut of Sequence STOP condition detected interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// STOP_ER +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled. +// +// +// + + +// -------------------------- Field Item: I2C1_INT_EN0_TX_LOCK_OUT ------------------------------ +// SVD Line: 4402 + +// SFDITEM_FIELD__I2C1_INT_EN0_TX_LOCK_OUT +// TX_LOCK_OUT +// +// [Bit 15] RW (@ 0x4001E00C) \nTX FIFO Locked Out Interrupt.\n0 : dis = Interrupt disabled.\n1 : en = Interrupt enabled when TXLOIE = 1. +// +// ( (unsigned int) I2C1_INT_EN0 ) +// TX_LOCK_OUT +// <0=> 0: dis = Interrupt disabled. +// <1=> 1: en = Interrupt enabled when TXLOIE = 1. +// +// +// + + +// ------------------------------ Register RTree: I2C1_INT_EN0 ---------------------------------- +// SVD Line: 4135 + +// SFDITEM_REG__I2C1_INT_EN0 +// INT_EN0 +// +// [Bits 31..0] RW (@ 0x4001E00C) Interrupt Enable Register. +// ( (unsigned int)((I2C1_INT_EN0 >> 0) & 0xFFFFFFFF), ((I2C1_INT_EN0 = (I2C1_INT_EN0 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_INT_EN0_DONE +// SFDITEM_FIELD__I2C1_INT_EN0_RX_MODE +// SFDITEM_FIELD__I2C1_INT_EN0_GEN_CTRL_ADDR +// SFDITEM_FIELD__I2C1_INT_EN0_ADDR_MATCH +// SFDITEM_FIELD__I2C1_INT_EN0_RX_THRESH +// SFDITEM_FIELD__I2C1_INT_EN0_TX_THRESH +// SFDITEM_FIELD__I2C1_INT_EN0_STOP +// SFDITEM_FIELD__I2C1_INT_EN0_ADDR_ACK +// SFDITEM_FIELD__I2C1_INT_EN0_ARB_ER +// SFDITEM_FIELD__I2C1_INT_EN0_TO_ER +// SFDITEM_FIELD__I2C1_INT_EN0_ADDR_ER +// SFDITEM_FIELD__I2C1_INT_EN0_DATA_ER +// SFDITEM_FIELD__I2C1_INT_EN0_DO_NOT_RESP_ER +// SFDITEM_FIELD__I2C1_INT_EN0_START_ER +// SFDITEM_FIELD__I2C1_INT_EN0_STOP_ER +// SFDITEM_FIELD__I2C1_INT_EN0_TX_LOCK_OUT +// +// + + +// --------------------------- Register Item Address: I2C1_INT_FL1 ------------------------------ +// SVD Line: 4421 + +unsigned int I2C1_INT_FL1 __AT (0x4001E010); + + + +// -------------------------- Field Item: I2C1_INT_FL1_RX_OVERFLOW ------------------------------ +// SVD Line: 4426 + +// SFDITEM_FIELD__I2C1_INT_FL1_RX_OVERFLOW +// RX_OVERFLOW +// +// [Bit 0] RW (@ 0x4001E010) \nReceiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL1 ) +// RX_OVERFLOW +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// -------------------------- Field Item: I2C1_INT_FL1_TX_UNDERFLOW ----------------------------- +// SVD Line: 4443 + +// SFDITEM_FIELD__I2C1_INT_FL1_TX_UNDERFLOW +// TX_UNDERFLOW +// +// [Bit 1] RW (@ 0x4001E010) \nTransmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).\n0 : inactive = No Interrupt is Pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_FL1 ) +// TX_UNDERFLOW +// <0=> 0: inactive = No Interrupt is Pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ------------------------------ Register RTree: I2C1_INT_FL1 ---------------------------------- +// SVD Line: 4421 + +// SFDITEM_REG__I2C1_INT_FL1 +// INT_FL1 +// +// [Bits 31..0] RW (@ 0x4001E010) Interrupt Status Register 1. +// ( (unsigned int)((I2C1_INT_FL1 >> 0) & 0xFFFFFFFF), ((I2C1_INT_FL1 = (I2C1_INT_FL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_INT_FL1_RX_OVERFLOW +// SFDITEM_FIELD__I2C1_INT_FL1_TX_UNDERFLOW +// +// + + +// --------------------------- Register Item Address: I2C1_INT_EN1 ------------------------------ +// SVD Line: 4462 + +unsigned int I2C1_INT_EN1 __AT (0x4001E014); + + + +// -------------------------- Field Item: I2C1_INT_EN1_RX_OVERFLOW ------------------------------ +// SVD Line: 4468 + +// SFDITEM_FIELD__I2C1_INT_EN1_RX_OVERFLOW +// RX_OVERFLOW +// +// [Bit 0] RW (@ 0x4001E014) \nReceiver Overflow Interrupt Enable.\n0 : dis = No Interrupt is Pending.\n1 : en = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_EN1 ) +// RX_OVERFLOW +// <0=> 0: dis = No Interrupt is Pending. +// <1=> 1: en = An interrupt is pending. +// +// +// + + +// -------------------------- Field Item: I2C1_INT_EN1_TX_UNDERFLOW ----------------------------- +// SVD Line: 4485 + +// SFDITEM_FIELD__I2C1_INT_EN1_TX_UNDERFLOW +// TX_UNDERFLOW +// +// [Bit 1] RW (@ 0x4001E014) \nTransmit Underflow Interrupt Enable.\n0 : dis = No Interrupt is Pending.\n1 : en = An interrupt is pending. +// +// ( (unsigned int) I2C1_INT_EN1 ) +// TX_UNDERFLOW +// <0=> 0: dis = No Interrupt is Pending. +// <1=> 1: en = An interrupt is pending. +// +// +// + + +// ------------------------------ Register RTree: I2C1_INT_EN1 ---------------------------------- +// SVD Line: 4462 + +// SFDITEM_REG__I2C1_INT_EN1 +// INT_EN1 +// +// [Bits 31..0] RW (@ 0x4001E014) Interrupt Staus Register 1. +// ( (unsigned int)((I2C1_INT_EN1 >> 0) & 0xFFFFFFFF), ((I2C1_INT_EN1 = (I2C1_INT_EN1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_INT_EN1_RX_OVERFLOW +// SFDITEM_FIELD__I2C1_INT_EN1_TX_UNDERFLOW +// +// + + +// -------------------------- Register Item Address: I2C1_FIFO_LEN ------------------------------ +// SVD Line: 4504 + +unsigned int I2C1_FIFO_LEN __AT (0x4001E018); + + + +// ---------------------------- Field Item: I2C1_FIFO_LEN_RX_LEN -------------------------------- +// SVD Line: 4509 + +// SFDITEM_FIELD__I2C1_FIFO_LEN_RX_LEN +// RX_LEN +// +// [Bits 7..0] RO (@ 0x4001E018) Receive FIFO Length. +// +// ( (unsigned char)((I2C1_FIFO_LEN >> 0) & 0xFF) ) +// +// +// + + +// ---------------------------- Field Item: I2C1_FIFO_LEN_TX_LEN -------------------------------- +// SVD Line: 4515 + +// SFDITEM_FIELD__I2C1_FIFO_LEN_TX_LEN +// TX_LEN +// +// [Bits 15..8] RO (@ 0x4001E018) Transmit FIFO Length. +// +// ( (unsigned char)((I2C1_FIFO_LEN >> 8) & 0xFF) ) +// +// +// + + +// ------------------------------ Register RTree: I2C1_FIFO_LEN --------------------------------- +// SVD Line: 4504 + +// SFDITEM_REG__I2C1_FIFO_LEN +// FIFO_LEN +// +// [Bits 31..0] RW (@ 0x4001E018) FIFO Configuration Register. +// ( (unsigned int)((I2C1_FIFO_LEN >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__I2C1_FIFO_LEN_RX_LEN +// SFDITEM_FIELD__I2C1_FIFO_LEN_TX_LEN +// +// + + +// -------------------------- Register Item Address: I2C1_RX_CTRL0 ------------------------------ +// SVD Line: 4523 + +unsigned int I2C1_RX_CTRL0 __AT (0x4001E01C); + + + +// ------------------------------ Field Item: I2C1_RX_CTRL0_DNR --------------------------------- +// SVD Line: 4528 + +// SFDITEM_FIELD__I2C1_RX_CTRL0_DNR +// DNR +// +// [Bit 0] RW (@ 0x4001E01C) \nDo Not Respond.\n0 : respond = Always respond to address match.\n1 : not_respond_rx_fifo_empty = Do not respond to address match when RX_FIFO is not empty. +// +// ( (unsigned int) I2C1_RX_CTRL0 ) +// DNR +// <0=> 0: respond = Always respond to address match. +// <1=> 1: not_respond_rx_fifo_empty = Do not respond to address match when RX_FIFO is not empty. +// +// +// + + +// --------------------------- Field Item: I2C1_RX_CTRL0_RX_FLUSH ------------------------------- +// SVD Line: 4545 + +// SFDITEM_FIELD__I2C1_RX_CTRL0_RX_FLUSH +// RX_FLUSH +// +// [Bit 7] RW (@ 0x4001E01C) \nReceive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.\n0 : not_flushed = FIFO not flushed.\n1 : flush = Flush RX_FIFO. +// +// ( (unsigned int) I2C1_RX_CTRL0 ) +// RX_FLUSH +// <0=> 0: not_flushed = FIFO not flushed. +// <1=> 1: flush = Flush RX_FIFO. +// +// +// + + +// --------------------------- Field Item: I2C1_RX_CTRL0_RX_THRESH ------------------------------ +// SVD Line: 4562 + +// SFDITEM_FIELD__I2C1_RX_CTRL0_RX_THRESH +// RX_THRESH +// +// [Bits 11..8] RW (@ 0x4001E01C) Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. +// +// ( (unsigned char)((I2C1_RX_CTRL0 >> 8) & 0xF), ((I2C1_RX_CTRL0 = (I2C1_RX_CTRL0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: I2C1_RX_CTRL0 --------------------------------- +// SVD Line: 4523 + +// SFDITEM_REG__I2C1_RX_CTRL0 +// RX_CTRL0 +// +// [Bits 31..0] RW (@ 0x4001E01C) Receive Control Register 0. +// ( (unsigned int)((I2C1_RX_CTRL0 >> 0) & 0xFFFFFFFF), ((I2C1_RX_CTRL0 = (I2C1_RX_CTRL0 & ~(0xF81UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF81) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_RX_CTRL0_DNR +// SFDITEM_FIELD__I2C1_RX_CTRL0_RX_FLUSH +// SFDITEM_FIELD__I2C1_RX_CTRL0_RX_THRESH +// +// + + +// -------------------------- Register Item Address: I2C1_RX_CTRL1 ------------------------------ +// SVD Line: 4569 + +unsigned int I2C1_RX_CTRL1 __AT (0x4001E020); + + + +// ---------------------------- Field Item: I2C1_RX_CTRL1_RX_CNT -------------------------------- +// SVD Line: 4574 + +// SFDITEM_FIELD__I2C1_RX_CTRL1_RX_CNT +// RX_CNT +// +// [Bits 7..0] RW (@ 0x4001E020) Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. +// +// ( (unsigned char)((I2C1_RX_CTRL1 >> 0) & 0xFF), ((I2C1_RX_CTRL1 = (I2C1_RX_CTRL1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Field Item: I2C1_RX_CTRL1_RX_FIFO ------------------------------- +// SVD Line: 4579 + +// SFDITEM_FIELD__I2C1_RX_CTRL1_RX_FIFO +// RX_FIFO +// +// [Bits 11..8] RO (@ 0x4001E020) Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. +// +// ( (unsigned char)((I2C1_RX_CTRL1 >> 8) & 0xF) ) +// +// +// + + +// ------------------------------ Register RTree: I2C1_RX_CTRL1 --------------------------------- +// SVD Line: 4569 + +// SFDITEM_REG__I2C1_RX_CTRL1 +// RX_CTRL1 +// +// [Bits 31..0] RW (@ 0x4001E020) Receive Control Register 1. +// ( (unsigned int)((I2C1_RX_CTRL1 >> 0) & 0xFFFFFFFF), ((I2C1_RX_CTRL1 = (I2C1_RX_CTRL1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_RX_CTRL1_RX_CNT +// SFDITEM_FIELD__I2C1_RX_CTRL1_RX_FIFO +// +// + + +// -------------------------- Register Item Address: I2C1_TX_CTRL0 ------------------------------ +// SVD Line: 4587 + +unsigned int I2C1_TX_CTRL0 __AT (0x4001E024); + + + +// -------------------------- Field Item: I2C1_TX_CTRL0_TX_PRELOAD ------------------------------ +// SVD Line: 4592 + +// SFDITEM_FIELD__I2C1_TX_CTRL0_TX_PRELOAD +// TX_PRELOAD +// +// [Bit 0] RW (@ 0x4001E024) Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. +// +// ( (unsigned int) I2C1_TX_CTRL0 ) +// TX_PRELOAD +// +// +// + + +// ------------------------- Field Item: I2C1_TX_CTRL0_TX_READY_MODE ---------------------------- +// SVD Line: 4597 + +// SFDITEM_FIELD__I2C1_TX_CTRL0_TX_READY_MODE +// TX_READY_MODE +// +// [Bit 1] RW (@ 0x4001E024) \nTransmit FIFO Ready Manual Mode.\n0 : en = HW control of I2CTXRDY enabled.\n1 : dis = HW control of I2CTXRDY disabled. +// +// ( (unsigned int) I2C1_TX_CTRL0 ) +// TX_READY_MODE +// <0=> 0: en = HW control of I2CTXRDY enabled. +// <1=> 1: dis = HW control of I2CTXRDY disabled. +// +// +// + + +// --------------------------- Field Item: I2C1_TX_CTRL0_TX_FLUSH ------------------------------- +// SVD Line: 4614 + +// SFDITEM_FIELD__I2C1_TX_CTRL0_TX_FLUSH +// TX_FLUSH +// +// [Bit 7] RW (@ 0x4001E024) \nTransmit FIFO Flush. This bit is automatically cleared to 0 after the operation.\n0 : not_flushed = FIFO not flushed.\n1 : flush = Flush TX_FIFO. +// +// ( (unsigned int) I2C1_TX_CTRL0 ) +// TX_FLUSH +// <0=> 0: not_flushed = FIFO not flushed. +// <1=> 1: flush = Flush TX_FIFO. +// +// +// + + +// --------------------------- Field Item: I2C1_TX_CTRL0_TX_THRESH ------------------------------ +// SVD Line: 4631 + +// SFDITEM_FIELD__I2C1_TX_CTRL0_TX_THRESH +// TX_THRESH +// +// [Bits 11..8] RW (@ 0x4001E024) Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. +// +// ( (unsigned char)((I2C1_TX_CTRL0 >> 8) & 0xF), ((I2C1_TX_CTRL0 = (I2C1_TX_CTRL0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: I2C1_TX_CTRL0 --------------------------------- +// SVD Line: 4587 + +// SFDITEM_REG__I2C1_TX_CTRL0 +// TX_CTRL0 +// +// [Bits 31..0] RW (@ 0x4001E024) Transmit Control Register 0. +// ( (unsigned int)((I2C1_TX_CTRL0 >> 0) & 0xFFFFFFFF), ((I2C1_TX_CTRL0 = (I2C1_TX_CTRL0 & ~(0xF83UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF83) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_TX_CTRL0_TX_PRELOAD +// SFDITEM_FIELD__I2C1_TX_CTRL0_TX_READY_MODE +// SFDITEM_FIELD__I2C1_TX_CTRL0_TX_FLUSH +// SFDITEM_FIELD__I2C1_TX_CTRL0_TX_THRESH +// +// + + +// -------------------------- Register Item Address: I2C1_TX_CTRL1 ------------------------------ +// SVD Line: 4638 + +unsigned int I2C1_TX_CTRL1 __AT (0x4001E028); + + + +// --------------------------- Field Item: I2C1_TX_CTRL1_TX_READY ------------------------------- +// SVD Line: 4643 + +// SFDITEM_FIELD__I2C1_TX_CTRL1_TX_READY +// TX_READY +// +// [Bit 0] RW (@ 0x4001E028) Transmit FIFO Preload Ready. +// +// ( (unsigned int) I2C1_TX_CTRL1 ) +// TX_READY +// +// +// + + +// ---------------------------- Field Item: I2C1_TX_CTRL1_TX_LAST ------------------------------- +// SVD Line: 4648 + +// SFDITEM_FIELD__I2C1_TX_CTRL1_TX_LAST +// TX_LAST +// +// [Bit 1] RW (@ 0x4001E028) \nTransmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).\n0 : hold_scl_low = Hold SCL low on TX_FIFO empty.\n1 : end_transaction = End transaction on TX_FIFO empty. +// +// ( (unsigned int) I2C1_TX_CTRL1 ) +// TX_LAST +// <0=> 0: hold_scl_low = Hold SCL low on TX_FIFO empty. +// <1=> 1: end_transaction = End transaction on TX_FIFO empty. +// +// +// + + +// ---------------------------- Field Item: I2C1_TX_CTRL1_TX_FIFO ------------------------------- +// SVD Line: 4665 + +// SFDITEM_FIELD__I2C1_TX_CTRL1_TX_FIFO +// TX_FIFO +// +// [Bits 11..8] RO (@ 0x4001E028) Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. +// +// ( (unsigned char)((I2C1_TX_CTRL1 >> 8) & 0xF) ) +// +// +// + + +// ------------------------------ Register RTree: I2C1_TX_CTRL1 --------------------------------- +// SVD Line: 4638 + +// SFDITEM_REG__I2C1_TX_CTRL1 +// TX_CTRL1 +// +// [Bits 31..0] RW (@ 0x4001E028) Transmit Control Register 1. +// ( (unsigned int)((I2C1_TX_CTRL1 >> 0) & 0xFFFFFFFF), ((I2C1_TX_CTRL1 = (I2C1_TX_CTRL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_TX_CTRL1_TX_READY +// SFDITEM_FIELD__I2C1_TX_CTRL1_TX_LAST +// SFDITEM_FIELD__I2C1_TX_CTRL1_TX_FIFO +// +// + + +// ---------------------------- Register Item Address: I2C1_FIFO -------------------------------- +// SVD Line: 4673 + +unsigned int I2C1_FIFO __AT (0x4001E02C); + + + +// ------------------------------- Field Item: I2C1_FIFO_DATA ----------------------------------- +// SVD Line: 4678 + +// SFDITEM_FIELD__I2C1_FIFO_DATA +// DATA +// +// [Bits 7..0] RW (@ 0x4001E02C) Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. +// +// ( (unsigned char)((I2C1_FIFO >> 0) & 0xFF), ((I2C1_FIFO = (I2C1_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: I2C1_FIFO ----------------------------------- +// SVD Line: 4673 + +// SFDITEM_REG__I2C1_FIFO +// FIFO +// +// [Bits 31..0] RW (@ 0x4001E02C) Data Register. +// ( (unsigned int)((I2C1_FIFO >> 0) & 0xFFFFFFFF), ((I2C1_FIFO = (I2C1_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_FIFO_DATA +// +// + + +// ------------------------- Register Item Address: I2C1_MASTER_CTRL ---------------------------- +// SVD Line: 4686 + +unsigned int I2C1_MASTER_CTRL __AT (0x4001E030); + + + +// --------------------------- Field Item: I2C1_MASTER_CTRL_START ------------------------------- +// SVD Line: 4691 + +// SFDITEM_FIELD__I2C1_MASTER_CTRL_START +// START +// +// [Bit 0] RW (@ 0x4001E030) Setting this bit to 1 will start a master transfer. +// +// ( (unsigned int) I2C1_MASTER_CTRL ) +// START +// +// +// + + +// -------------------------- Field Item: I2C1_MASTER_CTRL_RESTART ------------------------------ +// SVD Line: 4696 + +// SFDITEM_FIELD__I2C1_MASTER_CTRL_RESTART +// RESTART +// +// [Bit 1] RW (@ 0x4001E030) Setting this bit to 1 will generate a repeated START. +// +// ( (unsigned int) I2C1_MASTER_CTRL ) +// RESTART +// +// +// + + +// ---------------------------- Field Item: I2C1_MASTER_CTRL_STOP ------------------------------- +// SVD Line: 4701 + +// SFDITEM_FIELD__I2C1_MASTER_CTRL_STOP +// STOP +// +// [Bit 2] RW (@ 0x4001E030) Setting this bit to 1 will generate a STOP condition. +// +// ( (unsigned int) I2C1_MASTER_CTRL ) +// STOP +// +// +// + + +// ------------------------- Field Item: I2C1_MASTER_CTRL_SL_EX_ADDR ---------------------------- +// SVD Line: 4706 + +// SFDITEM_FIELD__I2C1_MASTER_CTRL_SL_EX_ADDR +// SL_EX_ADDR +// +// [Bit 7] RW (@ 0x4001E030) \nSlave Extend Address Select.\n0 : 7_bits_address = 7-bit address.\n1 : 10_bits_address = 10-bit address. +// +// ( (unsigned int) I2C1_MASTER_CTRL ) +// SL_EX_ADDR +// <0=> 0: 7_bits_address = 7-bit address. +// <1=> 1: 10_bits_address = 10-bit address. +// +// +// + + +// ------------------------ Field Item: I2C1_MASTER_CTRL_MASTER_CODE ---------------------------- +// SVD Line: 4723 + +// SFDITEM_FIELD__I2C1_MASTER_CTRL_MASTER_CODE +// MASTER_CODE +// +// [Bits 10..8] RW (@ 0x4001E030) Master Code. These bits set the Master Code used in Hs-mode operation. +// +// ( (unsigned char)((I2C1_MASTER_CTRL >> 8) & 0x7), ((I2C1_MASTER_CTRL = (I2C1_MASTER_CTRL & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) )) +// +// +// + + +// ------------------------ Field Item: I2C1_MASTER_CTRL_SCL_SPEED_UP --------------------------- +// SVD Line: 4728 + +// SFDITEM_FIELD__I2C1_MASTER_CTRL_SCL_SPEED_UP +// SCL_SPEED_UP +// +// [Bit 11] RW (@ 0x4001E030) \nSerial Clock speed Up. Setting this bit disables the master's monitoring of SCL state for other external masters or slaves.\n0 : en = Master monitors SCL state.\n1 : dis = SCL state monitoring disabled. +// +// ( (unsigned int) I2C1_MASTER_CTRL ) +// SCL_SPEED_UP +// <0=> 0: en = Master monitors SCL state. +// <1=> 1: dis = SCL state monitoring disabled. +// +// +// + + +// ---------------------------- Register RTree: I2C1_MASTER_CTRL -------------------------------- +// SVD Line: 4686 + +// SFDITEM_REG__I2C1_MASTER_CTRL +// MASTER_CTRL +// +// [Bits 31..0] RW (@ 0x4001E030) Master Control Register. +// ( (unsigned int)((I2C1_MASTER_CTRL >> 0) & 0xFFFFFFFF), ((I2C1_MASTER_CTRL = (I2C1_MASTER_CTRL & ~(0xF87UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF87) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_MASTER_CTRL_START +// SFDITEM_FIELD__I2C1_MASTER_CTRL_RESTART +// SFDITEM_FIELD__I2C1_MASTER_CTRL_STOP +// SFDITEM_FIELD__I2C1_MASTER_CTRL_SL_EX_ADDR +// SFDITEM_FIELD__I2C1_MASTER_CTRL_MASTER_CODE +// SFDITEM_FIELD__I2C1_MASTER_CTRL_SCL_SPEED_UP +// +// + + +// --------------------------- Register Item Address: I2C1_CLK_LO ------------------------------- +// SVD Line: 4747 + +unsigned int I2C1_CLK_LO __AT (0x4001E034); + + + +// ----------------------------- Field Item: I2C1_CLK_LO_CLK_LO --------------------------------- +// SVD Line: 4752 + +// SFDITEM_FIELD__I2C1_CLK_LO_CLK_LO +// CLK_LO +// +// [Bits 8..0] RW (@ 0x4001E034) Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. +// +// ( (unsigned short)((I2C1_CLK_LO >> 0) & 0x1FF), ((I2C1_CLK_LO = (I2C1_CLK_LO & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: I2C1_CLK_LO ---------------------------------- +// SVD Line: 4747 + +// SFDITEM_REG__I2C1_CLK_LO +// CLK_LO +// +// [Bits 31..0] RW (@ 0x4001E034) Clock Low Register. +// ( (unsigned int)((I2C1_CLK_LO >> 0) & 0xFFFFFFFF), ((I2C1_CLK_LO = (I2C1_CLK_LO & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_CLK_LO_CLK_LO +// +// + + +// --------------------------- Register Item Address: I2C1_CLK_HI ------------------------------- +// SVD Line: 4759 + +unsigned int I2C1_CLK_HI __AT (0x4001E038); + + + +// ------------------------------- Field Item: I2C1_CLK_HI_CKH ---------------------------------- +// SVD Line: 4764 + +// SFDITEM_FIELD__I2C1_CLK_HI_CKH +// CKH +// +// [Bits 8..0] RW (@ 0x4001E038) Clock High. In master mode, these bits define the SCL high period. +// +// ( (unsigned short)((I2C1_CLK_HI >> 0) & 0x1FF), ((I2C1_CLK_HI = (I2C1_CLK_HI & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: I2C1_CLK_HI ---------------------------------- +// SVD Line: 4759 + +// SFDITEM_REG__I2C1_CLK_HI +// CLK_HI +// +// [Bits 31..0] RW (@ 0x4001E038) Clock high Register. +// ( (unsigned int)((I2C1_CLK_HI >> 0) & 0xFFFFFFFF), ((I2C1_CLK_HI = (I2C1_CLK_HI & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_CLK_HI_CKH +// +// + + +// --------------------------- Register Item Address: I2C1_HS_CLK ------------------------------- +// SVD Line: 4771 + +unsigned int I2C1_HS_CLK __AT (0x4001E03C); + + + +// ---------------------------- Field Item: I2C1_HS_CLK_HS_CLK_LO ------------------------------- +// SVD Line: 4776 + +// SFDITEM_FIELD__I2C1_HS_CLK_HS_CLK_LO +// HS_CLK_LO +// +// [Bits 7..0] RW (@ 0x4001E03C) Slave Address. +// +// ( (unsigned char)((I2C1_HS_CLK >> 0) & 0xFF), ((I2C1_HS_CLK = (I2C1_HS_CLK & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Field Item: I2C1_HS_CLK_HS_CLK_HI ------------------------------- +// SVD Line: 4781 + +// SFDITEM_FIELD__I2C1_HS_CLK_HS_CLK_HI +// HS_CLK_HI +// +// [Bits 15..8] RW (@ 0x4001E03C) Slave Address. +// +// ( (unsigned char)((I2C1_HS_CLK >> 8) & 0xFF), ((I2C1_HS_CLK = (I2C1_HS_CLK & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: I2C1_HS_CLK ---------------------------------- +// SVD Line: 4771 + +// SFDITEM_REG__I2C1_HS_CLK +// HS_CLK +// +// [Bits 31..0] RW (@ 0x4001E03C) HS-Mode Clock Control Register +// ( (unsigned int)((I2C1_HS_CLK >> 0) & 0xFFFFFFFF), ((I2C1_HS_CLK = (I2C1_HS_CLK & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_HS_CLK_HS_CLK_LO +// SFDITEM_FIELD__I2C1_HS_CLK_HS_CLK_HI +// +// + + +// --------------------------- Register Item Address: I2C1_TIMEOUT ------------------------------ +// SVD Line: 4788 + +unsigned int I2C1_TIMEOUT __AT (0x4001E040); + + + +// ------------------------------- Field Item: I2C1_TIMEOUT_TO ---------------------------------- +// SVD Line: 4793 + +// SFDITEM_FIELD__I2C1_TIMEOUT_TO +// TO +// +// [Bits 15..0] RW (@ 0x4001E040) Timeout +// +// ( (unsigned short)((I2C1_TIMEOUT >> 0) & 0xFFFF), ((I2C1_TIMEOUT = (I2C1_TIMEOUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: I2C1_TIMEOUT ---------------------------------- +// SVD Line: 4788 + +// SFDITEM_REG__I2C1_TIMEOUT +// TIMEOUT +// +// [Bits 31..0] RW (@ 0x4001E040) Timeout Register +// ( (unsigned int)((I2C1_TIMEOUT >> 0) & 0xFFFFFFFF), ((I2C1_TIMEOUT = (I2C1_TIMEOUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_TIMEOUT_TO +// +// + + +// ------------------------- Register Item Address: I2C1_SLAVE_ADDR ----------------------------- +// SVD Line: 4800 + +unsigned int I2C1_SLAVE_ADDR __AT (0x4001E044); + + + +// ------------------------- Field Item: I2C1_SLAVE_ADDR_SLAVE_ADDR ----------------------------- +// SVD Line: 4805 + +// SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR +// SLAVE_ADDR +// +// [Bits 9..0] RW (@ 0x4001E044) Slave Address. +// +// ( (unsigned short)((I2C1_SLAVE_ADDR >> 0) & 0x3FF), ((I2C1_SLAVE_ADDR = (I2C1_SLAVE_ADDR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) )) +// +// +// + + +// ----------------------- Field Item: I2C1_SLAVE_ADDR_SLAVE_ADDR_DIS --------------------------- +// SVD Line: 4810 + +// SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR_DIS +// SLAVE_ADDR_DIS +// +// [Bit 10] RW (@ 0x4001E044) Slave Address DIS. +// +// ( (unsigned int) I2C1_SLAVE_ADDR ) +// SLAVE_ADDR_DIS +// +// +// + + +// ----------------------- Field Item: I2C1_SLAVE_ADDR_SLAVE_ADDR_IDX --------------------------- +// SVD Line: 4815 + +// SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR_IDX +// SLAVE_ADDR_IDX +// +// [Bits 14..11] RW (@ 0x4001E044) Slave Address Index. +// +// ( (unsigned char)((I2C1_SLAVE_ADDR >> 11) & 0xF), ((I2C1_SLAVE_ADDR = (I2C1_SLAVE_ADDR & ~(0xFUL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 11 ) ) )) +// +// +// + + +// --------------------------- Field Item: I2C1_SLAVE_ADDR_EX_ADDR ------------------------------ +// SVD Line: 4820 + +// SFDITEM_FIELD__I2C1_SLAVE_ADDR_EX_ADDR +// EX_ADDR +// +// [Bit 15] RW (@ 0x4001E044) \nExtended Address Select.\n0 : 7_bits_address = 7-bit address.\n1 : 10_bits_address = 10-bit address. +// +// ( (unsigned int) I2C1_SLAVE_ADDR ) +// EX_ADDR +// <0=> 0: 7_bits_address = 7-bit address. +// <1=> 1: 10_bits_address = 10-bit address. +// +// +// + + +// ----------------------------- Register RTree: I2C1_SLAVE_ADDR -------------------------------- +// SVD Line: 4800 + +// SFDITEM_REG__I2C1_SLAVE_ADDR +// SLAVE_ADDR +// +// [Bits 31..0] RW (@ 0x4001E044) Slave Address Register. +// ( (unsigned int)((I2C1_SLAVE_ADDR >> 0) & 0xFFFFFFFF), ((I2C1_SLAVE_ADDR = (I2C1_SLAVE_ADDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR +// SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR_DIS +// SFDITEM_FIELD__I2C1_SLAVE_ADDR_SLAVE_ADDR_IDX +// SFDITEM_FIELD__I2C1_SLAVE_ADDR_EX_ADDR +// +// + + +// ----------------------------- Register Item Address: I2C1_DMA -------------------------------- +// SVD Line: 4839 + +unsigned int I2C1_DMA __AT (0x4001E048); + + + +// ------------------------------- Field Item: I2C1_DMA_TX_EN ----------------------------------- +// SVD Line: 4844 + +// SFDITEM_FIELD__I2C1_DMA_TX_EN +// TX_EN +// +// [Bit 0] RW (@ 0x4001E048) \nTX channel enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) I2C1_DMA ) +// TX_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: I2C1_DMA_RX_EN ----------------------------------- +// SVD Line: 4861 + +// SFDITEM_FIELD__I2C1_DMA_RX_EN +// RX_EN +// +// [Bit 1] RW (@ 0x4001E048) \nRX channel enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) I2C1_DMA ) +// RX_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Register RTree: I2C1_DMA ------------------------------------ +// SVD Line: 4839 + +// SFDITEM_REG__I2C1_DMA +// DMA +// +// [Bits 31..0] RW (@ 0x4001E048) DMA Register. +// ( (unsigned int)((I2C1_DMA >> 0) & 0xFFFFFFFF), ((I2C1_DMA = (I2C1_DMA & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) )) +// SFDITEM_FIELD__I2C1_DMA_TX_EN +// SFDITEM_FIELD__I2C1_DMA_RX_EN +// +// + + +// ---------------------------------- Peripheral View: I2C1 ------------------------------------- +// SVD Line: 4883 + +// I2C1 +// I2C1 +// SFDITEM_REG__I2C1_CTRL +// SFDITEM_REG__I2C1_STATUS +// SFDITEM_REG__I2C1_INT_FL0 +// SFDITEM_REG__I2C1_INT_EN0 +// SFDITEM_REG__I2C1_INT_FL1 +// SFDITEM_REG__I2C1_INT_EN1 +// SFDITEM_REG__I2C1_FIFO_LEN +// SFDITEM_REG__I2C1_RX_CTRL0 +// SFDITEM_REG__I2C1_RX_CTRL1 +// SFDITEM_REG__I2C1_TX_CTRL0 +// SFDITEM_REG__I2C1_TX_CTRL1 +// SFDITEM_REG__I2C1_FIFO +// SFDITEM_REG__I2C1_MASTER_CTRL +// SFDITEM_REG__I2C1_CLK_LO +// SFDITEM_REG__I2C1_CLK_HI +// SFDITEM_REG__I2C1_HS_CLK +// SFDITEM_REG__I2C1_TIMEOUT +// SFDITEM_REG__I2C1_SLAVE_ADDR +// SFDITEM_REG__I2C1_DMA +// +// + + +// -------------------------- Register Item Address: ICC0_CACHE_ID ------------------------------ +// SVD Line: 4904 + +unsigned int ICC0_CACHE_ID __AT (0x4002A000); + + + +// ---------------------------- Field Item: ICC0_CACHE_ID_RELNUM -------------------------------- +// SVD Line: 4910 + +// SFDITEM_FIELD__ICC0_CACHE_ID_RELNUM +// RELNUM +// +// [Bits 5..0] RO (@ 0x4002A000) Release Number. Identifies the RTL release version. +// +// ( (unsigned char)((ICC0_CACHE_ID >> 0) & 0x3F) ) +// +// +// + + +// ---------------------------- Field Item: ICC0_CACHE_ID_PARTNUM ------------------------------- +// SVD Line: 4916 + +// SFDITEM_FIELD__ICC0_CACHE_ID_PARTNUM +// PARTNUM +// +// [Bits 9..6] RO (@ 0x4002A000) Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. +// +// ( (unsigned char)((ICC0_CACHE_ID >> 6) & 0xF) ) +// +// +// + + +// ----------------------------- Field Item: ICC0_CACHE_ID_CCHID -------------------------------- +// SVD Line: 4922 + +// SFDITEM_FIELD__ICC0_CACHE_ID_CCHID +// CCHID +// +// [Bits 15..10] RO (@ 0x4002A000) Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. +// +// ( (unsigned char)((ICC0_CACHE_ID >> 10) & 0x3F) ) +// +// +// + + +// ------------------------------ Register RTree: ICC0_CACHE_ID --------------------------------- +// SVD Line: 4904 + +// SFDITEM_REG__ICC0_CACHE_ID +// CACHE_ID +// +// [Bits 31..0] RO (@ 0x4002A000) Cache ID Register. +// ( (unsigned int)((ICC0_CACHE_ID >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__ICC0_CACHE_ID_RELNUM +// SFDITEM_FIELD__ICC0_CACHE_ID_PARTNUM +// SFDITEM_FIELD__ICC0_CACHE_ID_CCHID +// +// + + +// --------------------------- Register Item Address: ICC0_MEMCFG ------------------------------- +// SVD Line: 4930 + +unsigned int ICC0_MEMCFG __AT (0x4002A004); + + + +// ------------------------------ Field Item: ICC0_MEMCFG_CCHSZ --------------------------------- +// SVD Line: 4937 + +// SFDITEM_FIELD__ICC0_MEMCFG_CCHSZ +// CCHSZ +// +// [Bits 15..0] RO (@ 0x4002A004) Cache Size. Indicates total size in Kbytes of cache. +// +// ( (unsigned short)((ICC0_MEMCFG >> 0) & 0xFFFF) ) +// +// +// + + +// ------------------------------ Field Item: ICC0_MEMCFG_MEMSZ --------------------------------- +// SVD Line: 4943 + +// SFDITEM_FIELD__ICC0_MEMCFG_MEMSZ +// MEMSZ +// +// [Bits 31..16] RO (@ 0x4002A004) Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. +// +// ( (unsigned short)((ICC0_MEMCFG >> 16) & 0xFFFF) ) +// +// +// + + +// ------------------------------- Register RTree: ICC0_MEMCFG ---------------------------------- +// SVD Line: 4930 + +// SFDITEM_REG__ICC0_MEMCFG +// MEMCFG +// +// [Bits 31..0] RO (@ 0x4002A004) Memory Configuration Register. +// ( (unsigned int)((ICC0_MEMCFG >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__ICC0_MEMCFG_CCHSZ +// SFDITEM_FIELD__ICC0_MEMCFG_MEMSZ +// +// + + +// ------------------------- Register Item Address: ICC0_CACHE_CTRL ----------------------------- +// SVD Line: 4951 + +unsigned int ICC0_CACHE_CTRL __AT (0x4002A100); + + + +// -------------------------- Field Item: ICC0_CACHE_CTRL_CACHE_EN ------------------------------ +// SVD Line: 4956 + +// SFDITEM_FIELD__ICC0_CACHE_CTRL_CACHE_EN +// CACHE_EN +// +// [Bit 0] RW (@ 0x4002A100) \nCache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.\n0 : dis = Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.\n1 : en = Cache Enabled. +// +// ( (unsigned int) ICC0_CACHE_CTRL ) +// CACHE_EN +// <0=> 0: dis = Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. +// <1=> 1: en = Cache Enabled. +// +// +// + + +// -------------------------- Field Item: ICC0_CACHE_CTRL_CACHE_RDY ----------------------------- +// SVD Line: 4974 + +// SFDITEM_FIELD__ICC0_CACHE_CTRL_CACHE_RDY +// CACHE_RDY +// +// [Bit 16] RO (@ 0x4002A100) \nCache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.\n0 : notReady = Not Ready.\n1 : ready = Ready. +// +// ( (unsigned int) ICC0_CACHE_CTRL ) +// CACHE_RDY +// <0=> 0: notReady = Not Ready. +// <1=> 1: ready = Ready. +// +// +// + + +// ----------------------------- Register RTree: ICC0_CACHE_CTRL -------------------------------- +// SVD Line: 4951 + +// SFDITEM_REG__ICC0_CACHE_CTRL +// CACHE_CTRL +// +// [Bits 31..0] RW (@ 0x4002A100) Cache Control and Status Register. +// ( (unsigned int)((ICC0_CACHE_CTRL >> 0) & 0xFFFFFFFF), ((ICC0_CACHE_CTRL = (ICC0_CACHE_CTRL & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) +// SFDITEM_FIELD__ICC0_CACHE_CTRL_CACHE_EN +// SFDITEM_FIELD__ICC0_CACHE_CTRL_CACHE_RDY +// +// + + +// ------------------------- Register Item Address: ICC0_INVALIDATE ----------------------------- +// SVD Line: 4995 + +unsigned int ICC0_INVALIDATE __AT (0x4002A700); + + + +// ----------------------------- Register Item: ICC0_INVALIDATE --------------------------------- +// SVD Line: 4995 + +// SFDITEM_REG__ICC0_INVALIDATE +// INVALIDATE +// [Bits 31..0] RW (@ 0x4002A700) Invalidate All Registers. +// +// ( (unsigned int)((ICC0_INVALIDATE >> 0) & 0xFFFFFFFF), ((ICC0_INVALIDATE = (ICC0_INVALIDATE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------------- Peripheral View: ICC0 ------------------------------------- +// SVD Line: 4894 + +// ICC0 +// ICC0 +// SFDITEM_REG__ICC0_CACHE_ID +// SFDITEM_REG__ICC0_MEMCFG +// SFDITEM_REG__ICC0_CACHE_CTRL +// SFDITEM_REG__ICC0_INVALIDATE +// +// + + +// -------------------------- Register Item Address: ICC1_CACHE_ID ------------------------------ +// SVD Line: 4904 + +unsigned int ICC1_CACHE_ID __AT (0x4002F000); + + + +// ---------------------------- Field Item: ICC1_CACHE_ID_RELNUM -------------------------------- +// SVD Line: 4910 + +// SFDITEM_FIELD__ICC1_CACHE_ID_RELNUM +// RELNUM +// +// [Bits 5..0] RO (@ 0x4002F000) Release Number. Identifies the RTL release version. +// +// ( (unsigned char)((ICC1_CACHE_ID >> 0) & 0x3F) ) +// +// +// + + +// ---------------------------- Field Item: ICC1_CACHE_ID_PARTNUM ------------------------------- +// SVD Line: 4916 + +// SFDITEM_FIELD__ICC1_CACHE_ID_PARTNUM +// PARTNUM +// +// [Bits 9..6] RO (@ 0x4002F000) Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. +// +// ( (unsigned char)((ICC1_CACHE_ID >> 6) & 0xF) ) +// +// +// + + +// ----------------------------- Field Item: ICC1_CACHE_ID_CCHID -------------------------------- +// SVD Line: 4922 + +// SFDITEM_FIELD__ICC1_CACHE_ID_CCHID +// CCHID +// +// [Bits 15..10] RO (@ 0x4002F000) Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. +// +// ( (unsigned char)((ICC1_CACHE_ID >> 10) & 0x3F) ) +// +// +// + + +// ------------------------------ Register RTree: ICC1_CACHE_ID --------------------------------- +// SVD Line: 4904 + +// SFDITEM_REG__ICC1_CACHE_ID +// CACHE_ID +// +// [Bits 31..0] RO (@ 0x4002F000) Cache ID Register. +// ( (unsigned int)((ICC1_CACHE_ID >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__ICC1_CACHE_ID_RELNUM +// SFDITEM_FIELD__ICC1_CACHE_ID_PARTNUM +// SFDITEM_FIELD__ICC1_CACHE_ID_CCHID +// +// + + +// --------------------------- Register Item Address: ICC1_MEMCFG ------------------------------- +// SVD Line: 4930 + +unsigned int ICC1_MEMCFG __AT (0x4002F004); + + + +// ------------------------------ Field Item: ICC1_MEMCFG_CCHSZ --------------------------------- +// SVD Line: 4937 + +// SFDITEM_FIELD__ICC1_MEMCFG_CCHSZ +// CCHSZ +// +// [Bits 15..0] RO (@ 0x4002F004) Cache Size. Indicates total size in Kbytes of cache. +// +// ( (unsigned short)((ICC1_MEMCFG >> 0) & 0xFFFF) ) +// +// +// + + +// ------------------------------ Field Item: ICC1_MEMCFG_MEMSZ --------------------------------- +// SVD Line: 4943 + +// SFDITEM_FIELD__ICC1_MEMCFG_MEMSZ +// MEMSZ +// +// [Bits 31..16] RO (@ 0x4002F004) Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. +// +// ( (unsigned short)((ICC1_MEMCFG >> 16) & 0xFFFF) ) +// +// +// + + +// ------------------------------- Register RTree: ICC1_MEMCFG ---------------------------------- +// SVD Line: 4930 + +// SFDITEM_REG__ICC1_MEMCFG +// MEMCFG +// +// [Bits 31..0] RO (@ 0x4002F004) Memory Configuration Register. +// ( (unsigned int)((ICC1_MEMCFG >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__ICC1_MEMCFG_CCHSZ +// SFDITEM_FIELD__ICC1_MEMCFG_MEMSZ +// +// + + +// ------------------------- Register Item Address: ICC1_CACHE_CTRL ----------------------------- +// SVD Line: 4951 + +unsigned int ICC1_CACHE_CTRL __AT (0x4002F100); + + + +// -------------------------- Field Item: ICC1_CACHE_CTRL_CACHE_EN ------------------------------ +// SVD Line: 4956 + +// SFDITEM_FIELD__ICC1_CACHE_CTRL_CACHE_EN +// CACHE_EN +// +// [Bit 0] RW (@ 0x4002F100) \nCache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.\n0 : dis = Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.\n1 : en = Cache Enabled. +// +// ( (unsigned int) ICC1_CACHE_CTRL ) +// CACHE_EN +// <0=> 0: dis = Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. +// <1=> 1: en = Cache Enabled. +// +// +// + + +// -------------------------- Field Item: ICC1_CACHE_CTRL_CACHE_RDY ----------------------------- +// SVD Line: 4974 + +// SFDITEM_FIELD__ICC1_CACHE_CTRL_CACHE_RDY +// CACHE_RDY +// +// [Bit 16] RO (@ 0x4002F100) \nCache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.\n0 : notReady = Not Ready.\n1 : ready = Ready. +// +// ( (unsigned int) ICC1_CACHE_CTRL ) +// CACHE_RDY +// <0=> 0: notReady = Not Ready. +// <1=> 1: ready = Ready. +// +// +// + + +// ----------------------------- Register RTree: ICC1_CACHE_CTRL -------------------------------- +// SVD Line: 4951 + +// SFDITEM_REG__ICC1_CACHE_CTRL +// CACHE_CTRL +// +// [Bits 31..0] RW (@ 0x4002F100) Cache Control and Status Register. +// ( (unsigned int)((ICC1_CACHE_CTRL >> 0) & 0xFFFFFFFF), ((ICC1_CACHE_CTRL = (ICC1_CACHE_CTRL & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) +// SFDITEM_FIELD__ICC1_CACHE_CTRL_CACHE_EN +// SFDITEM_FIELD__ICC1_CACHE_CTRL_CACHE_RDY +// +// + + +// ------------------------- Register Item Address: ICC1_INVALIDATE ----------------------------- +// SVD Line: 4995 + +unsigned int ICC1_INVALIDATE __AT (0x4002F700); + + + +// ----------------------------- Register Item: ICC1_INVALIDATE --------------------------------- +// SVD Line: 4995 + +// SFDITEM_REG__ICC1_INVALIDATE +// INVALIDATE +// [Bits 31..0] RW (@ 0x4002F700) Invalidate All Registers. +// +// ( (unsigned int)((ICC1_INVALIDATE >> 0) & 0xFFFFFFFF), ((ICC1_INVALIDATE = (ICC1_INVALIDATE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------------- Peripheral View: ICC1 ------------------------------------- +// SVD Line: 5004 + +// ICC1 +// ICC1 +// SFDITEM_REG__ICC1_CACHE_ID +// SFDITEM_REG__ICC1_MEMCFG +// SFDITEM_REG__ICC1_CACHE_CTRL +// SFDITEM_REG__ICC1_INVALIDATE +// +// + + +// -------------------------- Register Item Address: PWRSEQ_LP_CTRL ----------------------------- +// SVD Line: 5020 + +unsigned int PWRSEQ_LP_CTRL __AT (0x40006800); + + + +// ------------------------- Field Item: PWRSEQ_LP_CTRL_RAMRET_SEL0 ----------------------------- +// SVD Line: 5025 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL0 +// RAMRET_SEL0 +// +// [Bit 0] RW (@ 0x40006800) \nSystem RAM 0 Data retention in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// RAMRET_SEL0 +// <0=> 0: dis = Disabled. +// <1=> 1: en = Enabled. +// +// +// + + +// ------------------------- Field Item: PWRSEQ_LP_CTRL_RAMRET_SEL1 ----------------------------- +// SVD Line: 5043 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL1 +// RAMRET_SEL1 +// +// [Bit 1] RW (@ 0x40006800) \nSystem RAM 1 Data retention in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// RAMRET_SEL1 +// <0=> 0: dis = Disabled. +// <1=> 1: en = Enabled. +// +// +// + + +// ------------------------- Field Item: PWRSEQ_LP_CTRL_RAMRET_SEL2 ----------------------------- +// SVD Line: 5061 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL2 +// RAMRET_SEL2 +// +// [Bit 2] RW (@ 0x40006800) \nSystem RAM 2 Data retention in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// RAMRET_SEL2 +// <0=> 0: dis = Disabled. +// <1=> 1: en = Enabled. +// +// +// + + +// ------------------------- Field Item: PWRSEQ_LP_CTRL_RAMRET_SEL3 ----------------------------- +// SVD Line: 5079 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL3 +// RAMRET_SEL3 +// +// [Bit 3] RW (@ 0x40006800) \nSystem RAM 3 Data retention in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// RAMRET_SEL3 +// <0=> 0: dis = Disabled. +// <1=> 1: en = Enabled. +// +// +// + + +// ----------------------------- Field Item: PWRSEQ_LP_CTRL_OVR --------------------------------- +// SVD Line: 5097 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_OVR +// OVR +// +// [Bits 5..4] RW (@ 0x40006800) \nOperating Voltage Range\n0 : 0_9V = 0.9V 24MHz\n1 : 1_0V = 1.0V 48MHz\n2 : 1_1V = 1.1V 96MHz\n3 : Reserved - do not use +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// OVR +// <0=> 0: 0_9V = 0.9V 24MHz +// <1=> 1: 1_0V = 1.0V 48MHz +// <2=> 2: 1_1V = 1.1V 96MHz +// <3=> 3: +// +// +// + + +// ----------------------- Field Item: PWRSEQ_LP_CTRL_VCORE_DET_BYPASS -------------------------- +// SVD Line: 5120 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_DET_BYPASS +// VCORE_DET_BYPASS +// +// [Bit 6] RW (@ 0x40006800) \nBypass V CORE External Supply Detection\n0 : enabled = enable\n1 : Disable = disable +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// VCORE_DET_BYPASS +// <0=> 0: enabled = enable +// <1=> 1: Disable = disable +// +// +// + + +// -------------------------- Field Item: PWRSEQ_LP_CTRL_RETREG_EN ------------------------------ +// SVD Line: 5138 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RETREG_EN +// RETREG_EN +// +// [Bit 8] RW (@ 0x40006800) \nRetention Regulator Enable. This bit controls the retention regulator in BACKUP mode.\n0 : dis = Disabled.\n1 : en = Enabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// RETREG_EN +// <0=> 0: dis = Disabled. +// <1=> 1: en = Enabled. +// +// +// + + +// -------------------------- Field Item: PWRSEQ_LP_CTRL_FAST_WK_EN ----------------------------- +// SVD Line: 5156 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_FAST_WK_EN +// FAST_WK_EN +// +// [Bit 10] RW (@ 0x40006800) \nFast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode.\n0 : dis = Disabled.\n1 : en = Enabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// FAST_WK_EN +// <0=> 0: dis = Disabled. +// <1=> 1: en = Enabled. +// +// +// + + +// ---------------------------- Field Item: PWRSEQ_LP_CTRL_BG_OFF ------------------------------- +// SVD Line: 5174 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_BG_OFF +// BG_OFF +// +// [Bit 11] RW (@ 0x40006800) \nBand Gap Disable for DEEPSLEEP and BACKUP Mode\n0 : on = Bandgap is always ON.\n1 : off = Bandgap is OFF in DeepSleep mode(default). +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// BG_OFF +// <0=> 0: on = Bandgap is always ON. +// <1=> 1: off = Bandgap is OFF in DeepSleep mode(default). +// +// +// + + +// ------------------------ Field Item: PWRSEQ_LP_CTRL_VCORE_POR_DIS ---------------------------- +// SVD Line: 5192 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_POR_DIS +// VCORE_POR_DIS +// +// [Bit 12] RW (@ 0x40006800) \nV CORE POR Disable for DEEPSLEEP and BACKUP Mode\n0 : dis = Disabled.\n1 : en = Enabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// VCORE_POR_DIS +// <0=> 0: dis = Disabled. +// <1=> 1: en = Enabled. +// +// +// + + +// --------------------------- Field Item: PWRSEQ_LP_CTRL_LDO_DIS ------------------------------- +// SVD Line: 5210 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_LDO_DIS +// LDO_DIS +// +// [Bit 16] RW (@ 0x40006800) \nLDO Disable\n0 : en = Enable if Bandgap is ON(default)\n1 : dis = Disabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// LDO_DIS +// <0=> 0: en = Enable if Bandgap is ON(default) +// <1=> 1: dis = Disabled. +// +// +// + + +// ------------------------ Field Item: PWRSEQ_LP_CTRL_VCORE_SVM_DIS ---------------------------- +// SVD Line: 5228 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_SVM_DIS +// VCORE_SVM_DIS +// +// [Bit 20] RW (@ 0x40006800) \nV CORE Supply Voltage Monitor Disable\n0 : en = Enable if Bandgap is ON(default)\n1 : dis = Disabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// VCORE_SVM_DIS +// <0=> 0: en = Enable if Bandgap is ON(default) +// <1=> 1: dis = Disabled. +// +// +// + + +// ------------------------ Field Item: PWRSEQ_LP_CTRL_VDDIO_POR_DIS ---------------------------- +// SVD Line: 5246 + +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_VDDIO_POR_DIS +// VDDIO_POR_DIS +// +// [Bit 25] RW (@ 0x40006800) \nVDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.\n0 : en = Enabled.\n1 : dis = Disabled. +// +// ( (unsigned int) PWRSEQ_LP_CTRL ) +// VDDIO_POR_DIS +// <0=> 0: en = Enabled. +// <1=> 1: dis = Disabled. +// +// +// + + +// ----------------------------- Register RTree: PWRSEQ_LP_CTRL --------------------------------- +// SVD Line: 5020 + +// SFDITEM_REG__PWRSEQ_LP_CTRL +// LP_CTRL +// +// [Bits 31..0] RW (@ 0x40006800) Low Power Control Register. +// ( (unsigned int)((PWRSEQ_LP_CTRL >> 0) & 0xFFFFFFFF), ((PWRSEQ_LP_CTRL = (PWRSEQ_LP_CTRL & ~(0x2111D7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2111D7F) << 0 ) ) )) +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL0 +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL1 +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL2 +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RAMRET_SEL3 +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_OVR +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_DET_BYPASS +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_RETREG_EN +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_FAST_WK_EN +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_BG_OFF +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_POR_DIS +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_LDO_DIS +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_VCORE_SVM_DIS +// SFDITEM_FIELD__PWRSEQ_LP_CTRL_VDDIO_POR_DIS +// +// + + +// ------------------------- Register Item Address: PWRSEQ_LP_WAKEFL ---------------------------- +// SVD Line: 5266 + +unsigned int PWRSEQ_LP_WAKEFL __AT (0x40006804); + + + +// --------------------------- Field Item: PWRSEQ_LP_WAKEFL_WAKEST ------------------------------ +// SVD Line: 5271 + +// SFDITEM_FIELD__PWRSEQ_LP_WAKEFL_WAKEST +// WAKEST +// +// [Bits 13..0] RW (@ 0x40006804) Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. +// +// ( (unsigned short)((PWRSEQ_LP_WAKEFL >> 0) & 0x3FFF), ((PWRSEQ_LP_WAKEFL = (PWRSEQ_LP_WAKEFL & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: PWRSEQ_LP_WAKEFL -------------------------------- +// SVD Line: 5266 + +// SFDITEM_REG__PWRSEQ_LP_WAKEFL +// LP_WAKEFL +// +// [Bits 31..0] RW (@ 0x40006804) Low Power Mode Wakeup Flags for GPIO0 +// ( (unsigned int)((PWRSEQ_LP_WAKEFL >> 0) & 0xFFFFFFFF), ((PWRSEQ_LP_WAKEFL = (PWRSEQ_LP_WAKEFL & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) )) +// SFDITEM_FIELD__PWRSEQ_LP_WAKEFL_WAKEST +// +// + + +// -------------------------- Register Item Address: PWRSEQ_LPWK_EN ----------------------------- +// SVD Line: 5279 + +unsigned int PWRSEQ_LPWK_EN __AT (0x40006808); + + + +// ---------------------------- Field Item: PWRSEQ_LPWK_EN_WAKEEN ------------------------------- +// SVD Line: 5284 + +// SFDITEM_FIELD__PWRSEQ_LPWK_EN_WAKEEN +// WAKEEN +// +// [Bits 13..0] RW (@ 0x40006808) Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. +// +// ( (unsigned short)((PWRSEQ_LPWK_EN >> 0) & 0x3FFF), ((PWRSEQ_LPWK_EN = (PWRSEQ_LPWK_EN & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register RTree: PWRSEQ_LPWK_EN --------------------------------- +// SVD Line: 5279 + +// SFDITEM_REG__PWRSEQ_LPWK_EN +// LPWK_EN +// +// [Bits 31..0] RW (@ 0x40006808) Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. +// ( (unsigned int)((PWRSEQ_LPWK_EN >> 0) & 0xFFFFFFFF), ((PWRSEQ_LPWK_EN = (PWRSEQ_LPWK_EN & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) )) +// SFDITEM_FIELD__PWRSEQ_LPWK_EN_WAKEEN +// +// + + +// -------------------------- Register Item Address: PWRSEQ_LPMEMSD ----------------------------- +// SVD Line: 5292 + +unsigned int PWRSEQ_LPMEMSD __AT (0x40006840); + + + +// -------------------------- Field Item: PWRSEQ_LPMEMSD_SRAM0_OFF ------------------------------ +// SVD Line: 5297 + +// SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM0_OFF +// SRAM0_OFF +// +// [Bit 0] RW (@ 0x40006840) \nSystem RAM block 0 Shut Down.\n0 : normal = Normal Operating Mode.\n1 : shutdown = Shutdown Mode. +// +// ( (unsigned int) PWRSEQ_LPMEMSD ) +// SRAM0_OFF +// <0=> 0: normal = Normal Operating Mode. +// <1=> 1: shutdown = Shutdown Mode. +// +// +// + + +// -------------------------- Field Item: PWRSEQ_LPMEMSD_SRAM1_OFF ------------------------------ +// SVD Line: 5315 + +// SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM1_OFF +// SRAM1_OFF +// +// [Bit 1] RW (@ 0x40006840) \nSystem RAM block 1 Shut Down.\n0 : normal = Normal Operating Mode.\n1 : shutdown = Shutdown Mode. +// +// ( (unsigned int) PWRSEQ_LPMEMSD ) +// SRAM1_OFF +// <0=> 0: normal = Normal Operating Mode. +// <1=> 1: shutdown = Shutdown Mode. +// +// +// + + +// -------------------------- Field Item: PWRSEQ_LPMEMSD_SRAM2_OFF ------------------------------ +// SVD Line: 5333 + +// SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM2_OFF +// SRAM2_OFF +// +// [Bit 2] RW (@ 0x40006840) \nSystem RAM block 2 Shut Down.\n0 : normal = Normal Operating Mode.\n1 : shutdown = Shutdown Mode. +// +// ( (unsigned int) PWRSEQ_LPMEMSD ) +// SRAM2_OFF +// <0=> 0: normal = Normal Operating Mode. +// <1=> 1: shutdown = Shutdown Mode. +// +// +// + + +// -------------------------- Field Item: PWRSEQ_LPMEMSD_SRAM3_OFF ------------------------------ +// SVD Line: 5351 + +// SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM3_OFF +// SRAM3_OFF +// +// [Bit 3] RW (@ 0x40006840) \nSystem RAM block 3 Shut Down.\n0 : normal = Normal Operating Mode.\n1 : shutdown = Shutdown Mode. +// +// ( (unsigned int) PWRSEQ_LPMEMSD ) +// SRAM3_OFF +// <0=> 0: normal = Normal Operating Mode. +// <1=> 1: shutdown = Shutdown Mode. +// +// +// + + +// ----------------------------- Register RTree: PWRSEQ_LPMEMSD --------------------------------- +// SVD Line: 5292 + +// SFDITEM_REG__PWRSEQ_LPMEMSD +// LPMEMSD +// +// [Bits 31..0] RW (@ 0x40006840) Low Power Memory Shutdown Control. +// ( (unsigned int)((PWRSEQ_LPMEMSD >> 0) & 0xFFFFFFFF), ((PWRSEQ_LPMEMSD = (PWRSEQ_LPMEMSD & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) +// SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM0_OFF +// SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM1_OFF +// SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM2_OFF +// SFDITEM_FIELD__PWRSEQ_LPMEMSD_SRAM3_OFF +// +// + + +// --------------------------------- Peripheral View: PWRSEQ ------------------------------------ +// SVD Line: 5010 + +// PWRSEQ +// PWRSEQ +// SFDITEM_REG__PWRSEQ_LP_CTRL +// SFDITEM_REG__PWRSEQ_LP_WAKEFL +// SFDITEM_REG__PWRSEQ_LPWK_EN +// SFDITEM_REG__PWRSEQ_LPMEMSD +// +// + + +// ----------------------------- Register Item Address: RTC_SEC --------------------------------- +// SVD Line: 5389 + +unsigned int RTC_SEC __AT (0x40006000); + + + +// --------------------------------- Register Item: RTC_SEC ------------------------------------- +// SVD Line: 5389 + +// SFDITEM_REG__RTC_SEC +// SEC +// [Bits 31..0] RW (@ 0x40006000) RTC Second Counter. This register contains the 32-bit second counter. +// +// ( (unsigned int)((RTC_SEC >> 0) & 0xFFFFFFFF), ((RTC_SEC = (RTC_SEC & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: RTC_SSEC -------------------------------- +// SVD Line: 5395 + +unsigned int RTC_SSEC __AT (0x40006004); + + + +// -------------------------------- Field Item: RTC_SSEC_RTSS ----------------------------------- +// SVD Line: 5401 + +// SFDITEM_FIELD__RTC_SSEC_RTSS +// RTSS +// +// [Bits 7..0] RW (@ 0x40006004) RTC Sub-second Counter. +// +// ( (unsigned char)((RTC_SSEC >> 0) & 0xFF), ((RTC_SSEC = (RTC_SSEC & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: RTC_SSEC ------------------------------------ +// SVD Line: 5395 + +// SFDITEM_REG__RTC_SSEC +// SSEC +// +// [Bits 31..0] RW (@ 0x40006004) RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. +// ( (unsigned int)((RTC_SSEC >> 0) & 0xFFFFFFFF), ((RTC_SSEC = (RTC_SSEC & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__RTC_SSEC_RTSS +// +// + + +// ----------------------------- Register Item Address: RTC_RAS --------------------------------- +// SVD Line: 5409 + +unsigned int RTC_RAS __AT (0x40006008); + + + +// --------------------------------- Field Item: RTC_RAS_RAS ------------------------------------ +// SVD Line: 5415 + +// SFDITEM_FIELD__RTC_RAS_RAS +// RAS +// +// [Bits 19..0] RW (@ 0x40006008) Time-of-day Alarm. +// +// ( (unsigned int)((RTC_RAS >> 0) & 0xFFFFF), ((RTC_RAS = (RTC_RAS & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) )) +// +// +// + + +// --------------------------------- Register RTree: RTC_RAS ------------------------------------ +// SVD Line: 5409 + +// SFDITEM_REG__RTC_RAS +// RAS +// +// [Bits 31..0] RW (@ 0x40006008) Time-of-day Alarm. +// ( (unsigned int)((RTC_RAS >> 0) & 0xFFFFFFFF), ((RTC_RAS = (RTC_RAS & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__RTC_RAS_RAS +// +// + + +// ----------------------------- Register Item Address: RTC_RSSA -------------------------------- +// SVD Line: 5423 + +unsigned int RTC_RSSA __AT (0x4000600C); + + + +// -------------------------------- Field Item: RTC_RSSA_RSSA ----------------------------------- +// SVD Line: 5429 + +// SFDITEM_FIELD__RTC_RSSA_RSSA +// RSSA +// +// [Bits 31..0] RW (@ 0x4000600C) This register contains the reload value for the sub-second alarm. +// +// ( (unsigned int)((RTC_RSSA >> 0) & 0xFFFFFFFF), ((RTC_RSSA = (RTC_RSSA & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: RTC_RSSA ------------------------------------ +// SVD Line: 5423 + +// SFDITEM_REG__RTC_RSSA +// RSSA +// +// [Bits 31..0] RW (@ 0x4000600C) RTC sub-second alarm. This register contains the reload value for the sub-second alarm. +// ( (unsigned int)((RTC_RSSA >> 0) & 0xFFFFFFFF), ((RTC_RSSA = (RTC_RSSA & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__RTC_RSSA_RSSA +// +// + + +// ----------------------------- Register Item Address: RTC_CTRL -------------------------------- +// SVD Line: 5437 + +unsigned int RTC_CTRL __AT (0x40006010); + + + +// -------------------------------- Field Item: RTC_CTRL_RTCE ----------------------------------- +// SVD Line: 5444 + +// SFDITEM_FIELD__RTC_CTRL_RTCE +// RTCE +// +// [Bit 0] RW (@ 0x40006010) \nReal Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) RTC_CTRL ) +// RTCE +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Field Item: RTC_CTRL_ADE ------------------------------------ +// SVD Line: 5462 + +// SFDITEM_FIELD__RTC_CTRL_ADE +// ADE +// +// [Bit 1] RW (@ 0x40006010) \nAlarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) RTC_CTRL ) +// ADE +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Field Item: RTC_CTRL_ASE ------------------------------------ +// SVD Line: 5480 + +// SFDITEM_FIELD__RTC_CTRL_ASE +// ASE +// +// [Bit 2] RW (@ 0x40006010) \nAlarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) RTC_CTRL ) +// ASE +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Field Item: RTC_CTRL_BUSY ----------------------------------- +// SVD Line: 5498 + +// SFDITEM_FIELD__RTC_CTRL_BUSY +// BUSY +// +// [Bit 3] RO (@ 0x40006010) \nRTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.\n0 : idle = Idle.\n1 : busy = Busy. +// +// ( (unsigned int) RTC_CTRL ) +// BUSY +// <0=> 0: idle = Idle. +// <1=> 1: busy = Busy. +// +// +// + + +// -------------------------------- Field Item: RTC_CTRL_RDY ------------------------------------ +// SVD Line: 5517 + +// SFDITEM_FIELD__RTC_CTRL_RDY +// RDY +// +// [Bit 4] RW (@ 0x40006010) \nRTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.\n0 : busy = Register has not updated.\n1 : ready = Ready. +// +// ( (unsigned int) RTC_CTRL ) +// RDY +// <0=> 0: busy = Register has not updated. +// <1=> 1: ready = Ready. +// +// +// + + +// -------------------------------- Field Item: RTC_CTRL_RDYE ----------------------------------- +// SVD Line: 5535 + +// SFDITEM_FIELD__RTC_CTRL_RDYE +// RDYE +// +// [Bit 5] RW (@ 0x40006010) \nRTC Ready Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) RTC_CTRL ) +// RDYE +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Field Item: RTC_CTRL_ALDF ----------------------------------- +// SVD Line: 5553 + +// SFDITEM_FIELD__RTC_CTRL_ALDF +// ALDF +// +// [Bit 6] RO (@ 0x40006010) \nTime-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.\n0 : inactive = Not active\n1 : Pending = Active +// +// ( (unsigned int) RTC_CTRL ) +// ALDF +// <0=> 0: inactive = Not active +// <1=> 1: Pending = Active +// +// +// + + +// -------------------------------- Field Item: RTC_CTRL_ALSF ----------------------------------- +// SVD Line: 5572 + +// SFDITEM_FIELD__RTC_CTRL_ALSF +// ALSF +// +// [Bit 7] RO (@ 0x40006010) \nSub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.\n0 : inactive = Not active\n1 : Pending = Active +// +// ( (unsigned int) RTC_CTRL ) +// ALSF +// <0=> 0: inactive = Not active +// <1=> 1: Pending = Active +// +// +// + + +// -------------------------------- Field Item: RTC_CTRL_SQE ------------------------------------ +// SVD Line: 5591 + +// SFDITEM_FIELD__RTC_CTRL_SQE +// SQE +// +// [Bit 8] RW (@ 0x40006010) \nSquare Wave Output Enable.\n0 : inactive = Not active\n1 : Pending = Active +// +// ( (unsigned int) RTC_CTRL ) +// SQE +// <0=> 0: inactive = Not active +// <1=> 1: Pending = Active +// +// +// + + +// --------------------------------- Field Item: RTC_CTRL_FT ------------------------------------ +// SVD Line: 5609 + +// SFDITEM_FIELD__RTC_CTRL_FT +// FT +// +// [Bits 10..9] RW (@ 0x40006010) \nFrequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.\n0 : freq1Hz = 1 Hz (Compensated).\n1 : freq512Hz = 512 Hz (Compensated).\n2 : freq4KHz = 4 KHz.\n3 : clkDiv8 = RTC Input Clock / 8. +// +// ( (unsigned int) RTC_CTRL ) +// FT +// <0=> 0: freq1Hz = 1 Hz (Compensated). +// <1=> 1: freq512Hz = 512 Hz (Compensated). +// <2=> 2: freq4KHz = 4 KHz. +// <3=> 3: clkDiv8 = RTC Input Clock / 8. +// +// +// + + +// ------------------------------- Field Item: RTC_CTRL_X32KMD ---------------------------------- +// SVD Line: 5637 + +// SFDITEM_FIELD__RTC_CTRL_X32KMD +// X32KMD +// +// [Bits 12..11] RW (@ 0x40006010) \n32KHz Oscillator Mode.\n0 : noiseImmuneMode = Always operate in Noise Immune Mode. Oscillator warm-up required.\n1 : quietMode = Always operate in Quiet Mode. No oscillator warm-up required.\n2 : quietInStopWithWarmup = Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.\n3 : quietInStopNoWarmup = Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit. +// +// ( (unsigned int) RTC_CTRL ) +// X32KMD +// <0=> 0: noiseImmuneMode = Always operate in Noise Immune Mode. Oscillator warm-up required. +// <1=> 1: quietMode = Always operate in Quiet Mode. No oscillator warm-up required. +// <2=> 2: quietInStopWithWarmup = Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit. +// <3=> 3: quietInStopNoWarmup = Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit. +// +// +// + + +// --------------------------------- Field Item: RTC_CTRL_WE ------------------------------------ +// SVD Line: 5665 + +// SFDITEM_FIELD__RTC_CTRL_WE +// WE +// +// [Bit 15] RW (@ 0x40006010) \nWrite Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.\n0 : inactive = Not active\n1 : Pending = Active +// +// ( (unsigned int) RTC_CTRL ) +// WE +// <0=> 0: inactive = Not active +// <1=> 1: Pending = Active +// +// +// + + +// -------------------------------- Register RTree: RTC_CTRL ------------------------------------ +// SVD Line: 5437 + +// SFDITEM_REG__RTC_CTRL +// CTRL +// +// [Bits 31..0] RW (@ 0x40006010) RTC Control Register. +// ( (unsigned int)((RTC_CTRL >> 0) & 0xFFFFFFFF), ((RTC_CTRL = (RTC_CTRL & ~(0x9F37UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x9F37) << 0 ) ) )) +// SFDITEM_FIELD__RTC_CTRL_RTCE +// SFDITEM_FIELD__RTC_CTRL_ADE +// SFDITEM_FIELD__RTC_CTRL_ASE +// SFDITEM_FIELD__RTC_CTRL_BUSY +// SFDITEM_FIELD__RTC_CTRL_RDY +// SFDITEM_FIELD__RTC_CTRL_RDYE +// SFDITEM_FIELD__RTC_CTRL_ALDF +// SFDITEM_FIELD__RTC_CTRL_ALSF +// SFDITEM_FIELD__RTC_CTRL_SQE +// SFDITEM_FIELD__RTC_CTRL_FT +// SFDITEM_FIELD__RTC_CTRL_X32KMD +// SFDITEM_FIELD__RTC_CTRL_WE +// +// + + +// ----------------------------- Register Item Address: RTC_TRIM -------------------------------- +// SVD Line: 5685 + +unsigned int RTC_TRIM __AT (0x40006014); + + + +// -------------------------------- Field Item: RTC_TRIM_TRIM ----------------------------------- +// SVD Line: 5691 + +// SFDITEM_FIELD__RTC_TRIM_TRIM +// TRIM +// +// [Bits 7..0] RW (@ 0x40006014) RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. +// +// ( (unsigned char)((RTC_TRIM >> 0) & 0xFF), ((RTC_TRIM = (RTC_TRIM & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Field Item: RTC_TRIM_VBATTMR ---------------------------------- +// SVD Line: 5697 + +// SFDITEM_FIELD__RTC_TRIM_VBATTMR +// VBATTMR +// +// [Bits 31..8] RW (@ 0x40006014) VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. +// +// ( (unsigned int)((RTC_TRIM >> 8) & 0xFFFFFF), ((RTC_TRIM = (RTC_TRIM & ~(0xFFFFFFUL << 8 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 8 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: RTC_TRIM ------------------------------------ +// SVD Line: 5685 + +// SFDITEM_REG__RTC_TRIM +// TRIM +// +// [Bits 31..0] RW (@ 0x40006014) RTC Trim Register. +// ( (unsigned int)((RTC_TRIM >> 0) & 0xFFFFFFFF), ((RTC_TRIM = (RTC_TRIM & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__RTC_TRIM_TRIM +// SFDITEM_FIELD__RTC_TRIM_VBATTMR +// +// + + +// --------------------------- Register Item Address: RTC_OSCCTRL ------------------------------- +// SVD Line: 5705 + +unsigned int RTC_OSCCTRL __AT (0x40006018); + + + +// ---------------------------- Field Item: RTC_OSCCTRL_FLITER_EN ------------------------------- +// SVD Line: 5711 + +// SFDITEM_FIELD__RTC_OSCCTRL_FLITER_EN +// FLITER_EN +// +// [Bit 0] RW (@ 0x40006018) RTC Oscillator Filter Enable +// +// ( (unsigned int) RTC_OSCCTRL ) +// FLITER_EN +// +// +// + + +// ---------------------------- Field Item: RTC_OSCCTRL_IBIAS_SEL ------------------------------- +// SVD Line: 5717 + +// SFDITEM_FIELD__RTC_OSCCTRL_IBIAS_SEL +// IBIAS_SEL +// +// [Bit 1] RW (@ 0x40006018) \nRTC Oscillator 4X Bias Current Select\n0 : 2X = Selects 2X bias current for RTC oscillator\n1 : 4X = Selects 4X bias current for RTC oscillator +// +// ( (unsigned int) RTC_OSCCTRL ) +// IBIAS_SEL +// <0=> 0: 2X = Selects 2X bias current for RTC oscillator +// <1=> 1: 4X = Selects 4X bias current for RTC oscillator +// +// +// + + +// ----------------------------- Field Item: RTC_OSCCTRL_HYST_EN -------------------------------- +// SVD Line: 5735 + +// SFDITEM_FIELD__RTC_OSCCTRL_HYST_EN +// HYST_EN +// +// [Bit 2] RW (@ 0x40006018) RTC Oscillator Hysteresis Buffer Enable +// +// ( (unsigned int) RTC_OSCCTRL ) +// HYST_EN +// +// +// + + +// ---------------------------- Field Item: RTC_OSCCTRL_IBIAS_EN -------------------------------- +// SVD Line: 5741 + +// SFDITEM_FIELD__RTC_OSCCTRL_IBIAS_EN +// IBIAS_EN +// +// [Bit 3] RW (@ 0x40006018) RTC Oscillator Bias Current Enable +// +// ( (unsigned int) RTC_OSCCTRL ) +// IBIAS_EN +// +// +// + + +// ----------------------------- Field Item: RTC_OSCCTRL_BYPASS --------------------------------- +// SVD Line: 5747 + +// SFDITEM_FIELD__RTC_OSCCTRL_BYPASS +// BYPASS +// +// [Bit 4] RW (@ 0x40006018) RTC Crystal Bypass +// +// ( (unsigned int) RTC_OSCCTRL ) +// BYPASS +// +// +// + + +// ----------------------------- Field Item: RTC_OSCCTRL_OUT32K --------------------------------- +// SVD Line: 5753 + +// SFDITEM_FIELD__RTC_OSCCTRL_OUT32K +// OUT32K +// +// [Bit 5] RW (@ 0x40006018) RTC 32kHz Square Wave Output +// +// ( (unsigned int) RTC_OSCCTRL ) +// OUT32K +// +// +// + + +// ------------------------------- Register RTree: RTC_OSCCTRL ---------------------------------- +// SVD Line: 5705 + +// SFDITEM_REG__RTC_OSCCTRL +// OSCCTRL +// +// [Bits 31..0] RW (@ 0x40006018) RTC Oscillator Control Register. +// ( (unsigned int)((RTC_OSCCTRL >> 0) & 0xFFFFFFFF), ((RTC_OSCCTRL = (RTC_OSCCTRL & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) )) +// SFDITEM_FIELD__RTC_OSCCTRL_FLITER_EN +// SFDITEM_FIELD__RTC_OSCCTRL_IBIAS_SEL +// SFDITEM_FIELD__RTC_OSCCTRL_HYST_EN +// SFDITEM_FIELD__RTC_OSCCTRL_IBIAS_EN +// SFDITEM_FIELD__RTC_OSCCTRL_BYPASS +// SFDITEM_FIELD__RTC_OSCCTRL_OUT32K +// +// + + +// ---------------------------------- Peripheral View: RTC -------------------------------------- +// SVD Line: 5374 + +// RTC +// RTC +// SFDITEM_REG__RTC_SEC +// SFDITEM_REG__RTC_SSEC +// SFDITEM_REG__RTC_RAS +// SFDITEM_REG__RTC_RSSA +// SFDITEM_REG__RTC_CTRL +// SFDITEM_REG__RTC_TRIM +// SFDITEM_REG__RTC_OSCCTRL +// +// + + +// ---------------------------- Register Item Address: SIR_SISTAT ------------------------------- +// SVD Line: 5775 + +unsigned int SIR_SISTAT __AT (0x40000400); + + + +// ------------------------------ Field Item: SIR_SISTAT_MAGIC ---------------------------------- +// SVD Line: 5781 + +// SFDITEM_FIELD__SIR_SISTAT_MAGIC +// MAGIC +// +// [Bit 0] RO (@ 0x40000400) \nMagic Word Validation. This bit is set by the system initialization block following power-up.\n0 : magicNotSet = Magic word was not set (OTP has not been initialized properly).\n1 : magicSet = Magic word was set (OTP contains valid settings). +// +// ( (unsigned int) SIR_SISTAT ) +// MAGIC +// <0=> 0: magicNotSet = Magic word was not set (OTP has not been initialized properly). +// <1=> 1: magicSet = Magic word was set (OTP contains valid settings). +// +// +// + + +// ------------------------------ Field Item: SIR_SISTAT_CRCERR --------------------------------- +// SVD Line: 5801 + +// SFDITEM_FIELD__SIR_SISTAT_CRCERR +// CRCERR +// +// [Bit 1] RO (@ 0x40000400) \nCRC Error Status. This bit is set by the system initialization block following power-up.\n0 : noError = No CRC errors occurred during the read of the OTP memory block.\n1 : error = A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. +// +// ( (unsigned int) SIR_SISTAT ) +// CRCERR +// <0=> 0: noError = No CRC errors occurred during the read of the OTP memory block. +// <1=> 1: error = A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. +// +// +// + + +// ------------------------------- Register RTree: SIR_SISTAT ----------------------------------- +// SVD Line: 5775 + +// SFDITEM_REG__SIR_SISTAT +// SISTAT +// +// [Bits 31..0] RO (@ 0x40000400) System Initialization Status Register. +// ( (unsigned int)((SIR_SISTAT >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__SIR_SISTAT_MAGIC +// SFDITEM_FIELD__SIR_SISTAT_CRCERR +// +// + + +// --------------------------- Register Item Address: SIR_ERRADDR ------------------------------- +// SVD Line: 5823 + +unsigned int SIR_ERRADDR __AT (0x40000404); + + + +// ----------------------------- Field Item: SIR_ERRADDR_ERRADDR -------------------------------- +// SVD Line: 5829 + +// SFDITEM_FIELD__SIR_ERRADDR_ERRADDR +// ERRADDR +// +// [Bits 31..0] RO (@ 0x40000404) ERRADDR +// +// ( (unsigned int)((SIR_ERRADDR >> 0) & 0xFFFFFFFF) ) +// +// +// + + +// ------------------------------- Register RTree: SIR_ERRADDR ---------------------------------- +// SVD Line: 5823 + +// SFDITEM_REG__SIR_ERRADDR +// ERRADDR +// +// [Bits 31..0] RO (@ 0x40000404) Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). +// ( (unsigned int)((SIR_ERRADDR >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__SIR_ERRADDR_ERRADDR +// +// + + +// ---------------------------- Register Item Address: SIR_FSTAT -------------------------------- +// SVD Line: 5836 + +unsigned int SIR_FSTAT __AT (0x40000500); + + + +// -------------------------------- Field Item: SIR_FSTAT_FPU ----------------------------------- +// SVD Line: 5842 + +// SFDITEM_FIELD__SIR_FSTAT_FPU +// FPU +// +// [Bit 0] RO (@ 0x40000500) \nFPU Function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// FPU +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// -------------------------------- Field Item: SIR_FSTAT_USB ----------------------------------- +// SVD Line: 5858 + +// SFDITEM_FIELD__SIR_FSTAT_USB +// USB +// +// [Bit 1] RO (@ 0x40000500) \nUSB Device.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// USB +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// -------------------------------- Field Item: SIR_FSTAT_ADC ----------------------------------- +// SVD Line: 5874 + +// SFDITEM_FIELD__SIR_FSTAT_ADC +// ADC +// +// [Bit 2] RO (@ 0x40000500) \n10-bit Sigma Delta ADC.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// ADC +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// -------------------------------- Field Item: SIR_FSTAT_XIP ----------------------------------- +// SVD Line: 5890 + +// SFDITEM_FIELD__SIR_FSTAT_XIP +// XIP +// +// [Bit 3] RO (@ 0x40000500) \nXiP function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// XIP +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// -------------------------------- Field Item: SIR_FSTAT_PBM ----------------------------------- +// SVD Line: 5906 + +// SFDITEM_FIELD__SIR_FSTAT_PBM +// PBM +// +// [Bit 4] RO (@ 0x40000500) \nPBM function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// PBM +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// -------------------------------- Field Item: SIR_FSTAT_HBC ----------------------------------- +// SVD Line: 5922 + +// SFDITEM_FIELD__SIR_FSTAT_HBC +// HBC +// +// [Bit 5] RO (@ 0x40000500) \nHBC function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// HBC +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// ------------------------------- Field Item: SIR_FSTAT_SDHC ----------------------------------- +// SVD Line: 5938 + +// SFDITEM_FIELD__SIR_FSTAT_SDHC +// SDHC +// +// [Bit 6] RO (@ 0x40000500) \nSDHC function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// SDHC +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// ------------------------------- Field Item: SIR_FSTAT_SMPHR ---------------------------------- +// SVD Line: 5954 + +// SFDITEM_FIELD__SIR_FSTAT_SMPHR +// SMPHR +// +// [Bit 7] RO (@ 0x40000500) \nSMPHR function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// SMPHR +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// ------------------------------ Field Item: SIR_FSTAT_SCACHE ---------------------------------- +// SVD Line: 5970 + +// SFDITEM_FIELD__SIR_FSTAT_SCACHE +// SCACHE +// +// [Bit 8] RO (@ 0x40000500) \nSystem Cache function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_FSTAT ) +// SCACHE +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// -------------------------------- Register RTree: SIR_FSTAT ----------------------------------- +// SVD Line: 5836 + +// SFDITEM_REG__SIR_FSTAT +// FSTAT +// +// [Bits 31..0] RO (@ 0x40000500) funcstat register. +// ( (unsigned int)((SIR_FSTAT >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__SIR_FSTAT_FPU +// SFDITEM_FIELD__SIR_FSTAT_USB +// SFDITEM_FIELD__SIR_FSTAT_ADC +// SFDITEM_FIELD__SIR_FSTAT_XIP +// SFDITEM_FIELD__SIR_FSTAT_PBM +// SFDITEM_FIELD__SIR_FSTAT_HBC +// SFDITEM_FIELD__SIR_FSTAT_SDHC +// SFDITEM_FIELD__SIR_FSTAT_SMPHR +// SFDITEM_FIELD__SIR_FSTAT_SCACHE +// +// + + +// ---------------------------- Register Item Address: SIR_SFSTAT ------------------------------- +// SVD Line: 5988 + +unsigned int SIR_SFSTAT __AT (0x40000504); + + + +// ------------------------------- Field Item: SIR_SFSTAT_TRNG ---------------------------------- +// SVD Line: 5994 + +// SFDITEM_FIELD__SIR_SFSTAT_TRNG +// TRNG +// +// [Bit 2] RO (@ 0x40000504) \nTRNG function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_SFSTAT ) +// TRNG +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// ------------------------------- Field Item: SIR_SFSTAT_AES ----------------------------------- +// SVD Line: 6010 + +// SFDITEM_FIELD__SIR_SFSTAT_AES +// AES +// +// [Bit 3] RO (@ 0x40000504) \nAES function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_SFSTAT ) +// AES +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// ------------------------------- Field Item: SIR_SFSTAT_SHA ----------------------------------- +// SVD Line: 6026 + +// SFDITEM_FIELD__SIR_SFSTAT_SHA +// SHA +// +// [Bit 4] RO (@ 0x40000504) \nSHA function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_SFSTAT ) +// SHA +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// ------------------------------- Field Item: SIR_SFSTAT_MAA ----------------------------------- +// SVD Line: 6042 + +// SFDITEM_FIELD__SIR_SFSTAT_MAA +// MAA +// +// [Bit 5] RO (@ 0x40000504) \nMAA function.\n0 : no = no\n1 : yes = yes +// +// ( (unsigned int) SIR_SFSTAT ) +// MAA +// <0=> 0: no = no +// <1=> 1: yes = yes +// +// +// + + +// ------------------------------- Register RTree: SIR_SFSTAT ----------------------------------- +// SVD Line: 5988 + +// SFDITEM_REG__SIR_SFSTAT +// SFSTAT +// +// [Bits 31..0] RO (@ 0x40000504) secfuncstat register. +// ( (unsigned int)((SIR_SFSTAT >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__SIR_SFSTAT_TRNG +// SFDITEM_FIELD__SIR_SFSTAT_AES +// SFDITEM_FIELD__SIR_SFSTAT_SHA +// SFDITEM_FIELD__SIR_SFSTAT_MAA +// +// + + +// ---------------------------------- Peripheral View: SIR -------------------------------------- +// SVD Line: 5764 + +// SIR +// SIR +// SFDITEM_REG__SIR_SISTAT +// SFDITEM_REG__SIR_ERRADDR +// SFDITEM_REG__SIR_FSTAT +// SFDITEM_REG__SIR_SFSTAT +// +// + + +// --------------------------- Register Item Address: SMON_EXTSCN ------------------------------- +// SVD Line: 6073 + +unsigned int SMON_EXTSCN __AT (0x40004000); + + + +// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN0 -------------------------------- +// SVD Line: 6079 + +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN0 +// EXTS_EN0 +// +// [Bit 0] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 0.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_EXTSCN ) +// EXTS_EN0 +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN1 -------------------------------- +// SVD Line: 6097 + +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN1 +// EXTS_EN1 +// +// [Bit 1] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 1.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_EXTSCN ) +// EXTS_EN1 +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN2 -------------------------------- +// SVD Line: 6115 + +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN2 +// EXTS_EN2 +// +// [Bit 2] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 2.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_EXTSCN ) +// EXTS_EN2 +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN3 -------------------------------- +// SVD Line: 6133 + +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN3 +// EXTS_EN3 +// +// [Bit 3] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 3.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_EXTSCN ) +// EXTS_EN3 +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN4 -------------------------------- +// SVD Line: 6151 + +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN4 +// EXTS_EN4 +// +// [Bit 4] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 4.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_EXTSCN ) +// EXTS_EN4 +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: SMON_EXTSCN_EXTS_EN5 -------------------------------- +// SVD Line: 6169 + +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN5 +// EXTS_EN5 +// +// [Bit 5] RW (@ 0x40004000) \nExternal Sensor Enable for input/output pair 5.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_EXTSCN ) +// EXTS_EN5 +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ----------------------------- Field Item: SMON_EXTSCN_EXTCNT --------------------------------- +// SVD Line: 6187 + +// SFDITEM_FIELD__SMON_EXTSCN_EXTCNT +// EXTCNT +// +// [Bits 20..16] RW (@ 0x40004000) External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered. +// +// ( (unsigned char)((SMON_EXTSCN >> 16) & 0x1F), ((SMON_EXTSCN = (SMON_EXTSCN & ~(0x1FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 16 ) ) )) +// +// +// + + +// ----------------------------- Field Item: SMON_EXTSCN_EXTFRQ --------------------------------- +// SVD Line: 6193 + +// SFDITEM_FIELD__SMON_EXTSCN_EXTFRQ +// EXTFRQ +// +// [Bits 23..21] RW (@ 0x40004000) \nExternal Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.\n0 : freq2000Hz = Div 4 (2000Hz).\n1 : freq1000Hz = Div 8 (1000Hz).\n2 : freq500Hz = Div 16 (500Hz).\n3 : freq250Hz = Div 32 (250Hz).\n4 : freq125Hz = Div 64 (125Hz).\n5 : freq63Hz = Div 128 (63Hz).\n6 : freq31Hz = Div 256 (31Hz).\n7 : RFU = Reserved. Do not use. +// +// ( (unsigned int) SMON_EXTSCN ) +// EXTFRQ +// <0=> 0: freq2000Hz = Div 4 (2000Hz). +// <1=> 1: freq1000Hz = Div 8 (1000Hz). +// <2=> 2: freq500Hz = Div 16 (500Hz). +// <3=> 3: freq250Hz = Div 32 (250Hz). +// <4=> 4: freq125Hz = Div 64 (125Hz). +// <5=> 5: freq63Hz = Div 128 (63Hz). +// <6=> 6: freq31Hz = Div 256 (31Hz). +// <7=> 7: RFU = Reserved. Do not use. +// +// +// + + +// ----------------------------- Field Item: SMON_EXTSCN_DIVCLK --------------------------------- +// SVD Line: 6241 + +// SFDITEM_FIELD__SMON_EXTSCN_DIVCLK +// DIVCLK +// +// [Bits 26..24] RW (@ 0x40004000) \nClock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.\n0 : div1 = Divide by 1 (8000 Hz).\n1 : div2 = Divide by 2 (4000 Hz).\n2 : div4 = Divide by 4 (2000 Hz).\n3 : div8 = Divide by 8 (1000 Hz).\n4 : div16 = Divide by 16 (500 Hz).\n5 : div32 = Divide by 32 (250 Hz).\n6 : div64 = Divide by 64 (125 Hz).\n7 : Reserved - do not use +// +// ( (unsigned int) SMON_EXTSCN ) +// DIVCLK +// <0=> 0: div1 = Divide by 1 (8000 Hz). +// <1=> 1: div2 = Divide by 2 (4000 Hz). +// <2=> 2: div4 = Divide by 4 (2000 Hz). +// <3=> 3: div8 = Divide by 8 (1000 Hz). +// <4=> 4: div16 = Divide by 16 (500 Hz). +// <5=> 5: div32 = Divide by 32 (250 Hz). +// <6=> 6: div64 = Divide by 64 (125 Hz). +// <7=> 7: +// +// +// + + +// ------------------------------ Field Item: SMON_EXTSCN_BUSY ---------------------------------- +// SVD Line: 6284 + +// SFDITEM_FIELD__SMON_EXTSCN_BUSY +// BUSY +// +// [Bit 30] RO (@ 0x40004000) \nBusy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.\n0 : idle = Idle.\n1 : busy = Update in Progress. +// +// ( (unsigned int) SMON_EXTSCN ) +// BUSY +// <0=> 0: idle = Idle. +// <1=> 1: busy = Update in Progress. +// +// +// + + +// ------------------------------ Field Item: SMON_EXTSCN_LOCK ---------------------------------- +// SVD Line: 6303 + +// SFDITEM_FIELD__SMON_EXTSCN_LOCK +// LOCK +// +// [Bit 31] RW (@ 0x40004000) \nLock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.\n0 : unlocked = Unlocked.\n1 : locked = Locked. +// +// ( (unsigned int) SMON_EXTSCN ) +// LOCK +// <0=> 0: unlocked = Unlocked. +// <1=> 1: locked = Locked. +// +// +// + + +// ------------------------------- Register RTree: SMON_EXTSCN ---------------------------------- +// SVD Line: 6073 + +// SFDITEM_REG__SMON_EXTSCN +// EXTSCN +// +// [Bits 31..0] RW (@ 0x40004000) External Sensor Control Register. +// ( (unsigned int)((SMON_EXTSCN >> 0) & 0xFFFFFFFF), ((SMON_EXTSCN = (SMON_EXTSCN & ~(0x87FF003FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x87FF003F) << 0 ) ) )) +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN0 +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN1 +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN2 +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN3 +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN4 +// SFDITEM_FIELD__SMON_EXTSCN_EXTS_EN5 +// SFDITEM_FIELD__SMON_EXTSCN_EXTCNT +// SFDITEM_FIELD__SMON_EXTSCN_EXTFRQ +// SFDITEM_FIELD__SMON_EXTSCN_DIVCLK +// SFDITEM_FIELD__SMON_EXTSCN_BUSY +// SFDITEM_FIELD__SMON_EXTSCN_LOCK +// +// + + +// --------------------------- Register Item Address: SMON_INTSCN ------------------------------- +// SVD Line: 6323 + +unsigned int SMON_INTSCN __AT (0x40004004); + + + +// ---------------------------- Field Item: SMON_INTSCN_SHIELD_EN ------------------------------- +// SVD Line: 6329 + +// SFDITEM_FIELD__SMON_INTSCN_SHIELD_EN +// SHIELD_EN +// +// [Bit 0] RW (@ 0x40004004) \nDie Shield Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_INTSCN ) +// SHIELD_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ----------------------------- Field Item: SMON_INTSCN_TEMP_EN -------------------------------- +// SVD Line: 6347 + +// SFDITEM_FIELD__SMON_INTSCN_TEMP_EN +// TEMP_EN +// +// [Bit 1] RW (@ 0x40004004) \nTemperature Sensor Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_INTSCN ) +// TEMP_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ----------------------------- Field Item: SMON_INTSCN_VBAT_EN -------------------------------- +// SVD Line: 6365 + +// SFDITEM_FIELD__SMON_INTSCN_VBAT_EN +// VBAT_EN +// +// [Bit 2] RW (@ 0x40004004) \nBattery Monitor Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_INTSCN ) +// VBAT_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// --------------------------- Field Item: SMON_INTSCN_LOTEMP_SEL ------------------------------- +// SVD Line: 6383 + +// SFDITEM_FIELD__SMON_INTSCN_LOTEMP_SEL +// LOTEMP_SEL +// +// [Bit 16] RW (@ 0x40004004) \nLow Temperature Detection Select.\n0 : neg50C = -50 degrees C.\n1 : neg30C = -30 degrees C. +// +// ( (unsigned int) SMON_INTSCN ) +// LOTEMP_SEL +// <0=> 0: neg50C = -50 degrees C. +// <1=> 1: neg30C = -30 degrees C. +// +// +// + + +// ---------------------------- Field Item: SMON_INTSCN_VCORELOEN ------------------------------- +// SVD Line: 6401 + +// SFDITEM_FIELD__SMON_INTSCN_VCORELOEN +// VCORELOEN +// +// [Bit 18] RW (@ 0x40004004) \nVCORE Undervoltage Detect Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_INTSCN ) +// VCORELOEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ---------------------------- Field Item: SMON_INTSCN_VCOREHIEN ------------------------------- +// SVD Line: 6419 + +// SFDITEM_FIELD__SMON_INTSCN_VCOREHIEN +// VCOREHIEN +// +// [Bit 19] RW (@ 0x40004004) \nVCORE Overvoltage Detect Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_INTSCN ) +// VCOREHIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ----------------------------- Field Item: SMON_INTSCN_VDDLOEN -------------------------------- +// SVD Line: 6437 + +// SFDITEM_FIELD__SMON_INTSCN_VDDLOEN +// VDDLOEN +// +// [Bit 20] RW (@ 0x40004004) \nVDD Undervoltage Detect Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_INTSCN ) +// VDDLOEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ----------------------------- Field Item: SMON_INTSCN_VDDHIEN -------------------------------- +// SVD Line: 6455 + +// SFDITEM_FIELD__SMON_INTSCN_VDDHIEN +// VDDHIEN +// +// [Bit 21] RW (@ 0x40004004) \nVDD Overvoltage Detect Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_INTSCN ) +// VDDHIEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------ Field Item: SMON_INTSCN_VGLEN --------------------------------- +// SVD Line: 6473 + +// SFDITEM_FIELD__SMON_INTSCN_VGLEN +// VGLEN +// +// [Bit 22] RW (@ 0x40004004) \nVoltage Glitch Detection Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) SMON_INTSCN ) +// VGLEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------ Field Item: SMON_INTSCN_LOCK ---------------------------------- +// SVD Line: 6491 + +// SFDITEM_FIELD__SMON_INTSCN_LOCK +// LOCK +// +// [Bit 31] RW (@ 0x40004004) \nLock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.\n0 : unlocked = Unlocked.\n1 : locked = Locked. +// +// ( (unsigned int) SMON_INTSCN ) +// LOCK +// <0=> 0: unlocked = Unlocked. +// <1=> 1: locked = Locked. +// +// +// + + +// ------------------------------- Register RTree: SMON_INTSCN ---------------------------------- +// SVD Line: 6323 + +// SFDITEM_REG__SMON_INTSCN +// INTSCN +// +// [Bits 31..0] RW (@ 0x40004004) Internal Sensor Control Register. +// ( (unsigned int)((SMON_INTSCN >> 0) & 0xFFFFFFFF), ((SMON_INTSCN = (SMON_INTSCN & ~(0x807D0007UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x807D0007) << 0 ) ) )) +// SFDITEM_FIELD__SMON_INTSCN_SHIELD_EN +// SFDITEM_FIELD__SMON_INTSCN_TEMP_EN +// SFDITEM_FIELD__SMON_INTSCN_VBAT_EN +// SFDITEM_FIELD__SMON_INTSCN_LOTEMP_SEL +// SFDITEM_FIELD__SMON_INTSCN_VCORELOEN +// SFDITEM_FIELD__SMON_INTSCN_VCOREHIEN +// SFDITEM_FIELD__SMON_INTSCN_VDDLOEN +// SFDITEM_FIELD__SMON_INTSCN_VDDHIEN +// SFDITEM_FIELD__SMON_INTSCN_VGLEN +// SFDITEM_FIELD__SMON_INTSCN_LOCK +// +// + + +// --------------------------- Register Item Address: SMON_SECALM ------------------------------- +// SVD Line: 6511 + +unsigned int SMON_SECALM __AT (0x40004008); + + + +// ------------------------------- Field Item: SMON_SECALM_DRS ---------------------------------- +// SVD Line: 6518 + +// SFDITEM_FIELD__SMON_SECALM_DRS +// DRS +// +// [Bit 0] RW (@ 0x40004008) \nDestructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.\n0 : complete = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) SMON_SECALM ) +// DRS +// <0=> 0: complete = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// ----------------------------- Field Item: SMON_SECALM_KEYWIPE -------------------------------- +// SVD Line: 6536 + +// SFDITEM_FIELD__SMON_SECALM_KEYWIPE +// KEYWIPE +// +// [Bit 1] RW (@ 0x40004008) \nKey Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.\n0 : complete = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) SMON_SECALM ) +// KEYWIPE +// <0=> 0: complete = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// ----------------------------- Field Item: SMON_SECALM_SHIELDF -------------------------------- +// SVD Line: 6554 + +// SFDITEM_FIELD__SMON_SECALM_SHIELDF +// SHIELDF +// +// [Bit 2] RW (@ 0x40004008) \nDie Shield Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// SHIELDF +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECALM_LOTEMP --------------------------------- +// SVD Line: 6572 + +// SFDITEM_FIELD__SMON_SECALM_LOTEMP +// LOTEMP +// +// [Bit 3] RW (@ 0x40004008) \nLow Temperature Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// LOTEMP +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECALM_HITEMP --------------------------------- +// SVD Line: 6590 + +// SFDITEM_FIELD__SMON_SECALM_HITEMP +// HITEMP +// +// [Bit 4] RW (@ 0x40004008) \nHigh Temperature Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// HITEMP +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SMON_SECALM_BATLO --------------------------------- +// SVD Line: 6608 + +// SFDITEM_FIELD__SMON_SECALM_BATLO +// BATLO +// +// [Bit 5] RW (@ 0x40004008) \nBattery Undervoltage Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// BATLO +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SMON_SECALM_BATHI --------------------------------- +// SVD Line: 6626 + +// SFDITEM_FIELD__SMON_SECALM_BATHI +// BATHI +// +// [Bit 6] RW (@ 0x40004008) \nBattery Overvoltage Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// BATHI +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SMON_SECALM_EXTF ---------------------------------- +// SVD Line: 6644 + +// SFDITEM_FIELD__SMON_SECALM_EXTF +// EXTF +// +// [Bit 7] RW (@ 0x40004008) \nExternal Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTF +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SMON_SECALM_VDDLO --------------------------------- +// SVD Line: 6662 + +// SFDITEM_FIELD__SMON_SECALM_VDDLO +// VDDLO +// +// [Bit 8] RW (@ 0x40004008) \nVDD Undervoltage Detect Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// VDDLO +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECALM_VCORELO -------------------------------- +// SVD Line: 6680 + +// SFDITEM_FIELD__SMON_SECALM_VCORELO +// VCORELO +// +// [Bit 9] RW (@ 0x40004008) \nVCORE Undervoltage Detect Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// VCORELO +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECALM_VCOREHI -------------------------------- +// SVD Line: 6698 + +// SFDITEM_FIELD__SMON_SECALM_VCOREHI +// VCOREHI +// +// [Bit 10] RW (@ 0x40004008) \nVCORE Overvoltage Detect Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// VCOREHI +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SMON_SECALM_VDDHI --------------------------------- +// SVD Line: 6716 + +// SFDITEM_FIELD__SMON_SECALM_VDDHI +// VDDHI +// +// [Bit 11] RW (@ 0x40004008) \nVDD Overvoltage Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// VDDHI +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------- Field Item: SMON_SECALM_VGL ---------------------------------- +// SVD Line: 6734 + +// SFDITEM_FIELD__SMON_SECALM_VGL +// VGL +// +// [Bit 12] RW (@ 0x40004008) \nVoltage Glitch Detection Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// VGL +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSTAT0 -------------------------------- +// SVD Line: 6752 + +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT0 +// EXTSTAT0 +// +// [Bit 16] RW (@ 0x40004008) \nExternal Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSTAT0 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSTAT1 -------------------------------- +// SVD Line: 6770 + +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT1 +// EXTSTAT1 +// +// [Bit 17] RW (@ 0x40004008) \nExternal Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSTAT1 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSTAT2 -------------------------------- +// SVD Line: 6788 + +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT2 +// EXTSTAT2 +// +// [Bit 18] RW (@ 0x40004008) \nExternal Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSTAT2 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSTAT3 -------------------------------- +// SVD Line: 6806 + +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT3 +// EXTSTAT3 +// +// [Bit 19] RW (@ 0x40004008) \nExternal Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSTAT3 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSTAT4 -------------------------------- +// SVD Line: 6824 + +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT4 +// EXTSTAT4 +// +// [Bit 20] RW (@ 0x40004008) \nExternal Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSTAT4 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSTAT5 -------------------------------- +// SVD Line: 6842 + +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT5 +// EXTSTAT5 +// +// [Bit 21] RW (@ 0x40004008) \nExternal Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSTAT5 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSWARN0 ------------------------------- +// SVD Line: 6860 + +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN0 +// EXTSWARN0 +// +// [Bit 24] RW (@ 0x40004008) \nExternal Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSWARN0 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSWARN1 ------------------------------- +// SVD Line: 6878 + +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN1 +// EXTSWARN1 +// +// [Bit 25] RW (@ 0x40004008) \nExternal Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSWARN1 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSWARN2 ------------------------------- +// SVD Line: 6896 + +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN2 +// EXTSWARN2 +// +// [Bit 26] RW (@ 0x40004008) \nExternal Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSWARN2 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSWARN3 ------------------------------- +// SVD Line: 6914 + +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN3 +// EXTSWARN3 +// +// [Bit 27] RW (@ 0x40004008) \nExternal Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSWARN3 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSWARN4 ------------------------------- +// SVD Line: 6932 + +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN4 +// EXTSWARN4 +// +// [Bit 28] RW (@ 0x40004008) \nExternal Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSWARN4 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECALM_EXTSWARN5 ------------------------------- +// SVD Line: 6950 + +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN5 +// EXTSWARN5 +// +// [Bit 29] RW (@ 0x40004008) \nExternal Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECALM ) +// EXTSWARN5 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------- Register RTree: SMON_SECALM ---------------------------------- +// SVD Line: 6511 + +// SFDITEM_REG__SMON_SECALM +// SECALM +// +// [Bits 31..0] RW (@ 0x40004008) Security Alarm Register. +// ( (unsigned int)((SMON_SECALM >> 0) & 0xFFFFFFFF), ((SMON_SECALM = (SMON_SECALM & ~(0x3F3F1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F1FFF) << 0 ) ) )) +// SFDITEM_FIELD__SMON_SECALM_DRS +// SFDITEM_FIELD__SMON_SECALM_KEYWIPE +// SFDITEM_FIELD__SMON_SECALM_SHIELDF +// SFDITEM_FIELD__SMON_SECALM_LOTEMP +// SFDITEM_FIELD__SMON_SECALM_HITEMP +// SFDITEM_FIELD__SMON_SECALM_BATLO +// SFDITEM_FIELD__SMON_SECALM_BATHI +// SFDITEM_FIELD__SMON_SECALM_EXTF +// SFDITEM_FIELD__SMON_SECALM_VDDLO +// SFDITEM_FIELD__SMON_SECALM_VCORELO +// SFDITEM_FIELD__SMON_SECALM_VCOREHI +// SFDITEM_FIELD__SMON_SECALM_VDDHI +// SFDITEM_FIELD__SMON_SECALM_VGL +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT0 +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT1 +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT2 +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT3 +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT4 +// SFDITEM_FIELD__SMON_SECALM_EXTSTAT5 +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN0 +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN1 +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN2 +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN3 +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN4 +// SFDITEM_FIELD__SMON_SECALM_EXTSWARN5 +// +// + + +// --------------------------- Register Item Address: SMON_SECDIAG ------------------------------ +// SVD Line: 6970 + +unsigned int SMON_SECDIAG __AT (0x4000400C); + + + +// ------------------------------ Field Item: SMON_SECDIAG_BORF --------------------------------- +// SVD Line: 6978 + +// SFDITEM_FIELD__SMON_SECDIAG_BORF +// BORF +// +// [Bit 0] RO (@ 0x4000400C) \nBattery-On-Reset Flag. This bit is set once the back up battery is conneted.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// BORF +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECDIAG_SHIELDF -------------------------------- +// SVD Line: 6996 + +// SFDITEM_FIELD__SMON_SECDIAG_SHIELDF +// SHIELDF +// +// [Bit 2] RO (@ 0x4000400C) \nDie Shield Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// SHIELDF +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECDIAG_LOTEMP -------------------------------- +// SVD Line: 7014 + +// SFDITEM_FIELD__SMON_SECDIAG_LOTEMP +// LOTEMP +// +// [Bit 3] RO (@ 0x4000400C) \nLow Temperature Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// LOTEMP +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECDIAG_HITEMP -------------------------------- +// SVD Line: 7032 + +// SFDITEM_FIELD__SMON_SECDIAG_HITEMP +// HITEMP +// +// [Bit 4] RO (@ 0x4000400C) \nHigh Temperature Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// HITEMP +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECDIAG_BATLO --------------------------------- +// SVD Line: 7050 + +// SFDITEM_FIELD__SMON_SECDIAG_BATLO +// BATLO +// +// [Bit 5] RO (@ 0x4000400C) \nBattery Undervoltage Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// BATLO +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECDIAG_BATHI --------------------------------- +// SVD Line: 7068 + +// SFDITEM_FIELD__SMON_SECDIAG_BATHI +// BATHI +// +// [Bit 6] RO (@ 0x4000400C) \nBattery Overvoltage Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// BATHI +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SMON_SECDIAG_DYNF --------------------------------- +// SVD Line: 7086 + +// SFDITEM_FIELD__SMON_SECDIAG_DYNF +// DYNF +// +// [Bit 7] RO (@ 0x4000400C) \nDynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// DYNF +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SMON_SECDIAG_AESKT --------------------------------- +// SVD Line: 7104 + +// SFDITEM_FIELD__SMON_SECDIAG_AESKT +// AESKT +// +// [Bit 8] RO (@ 0x4000400C) \nAES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.\n0 : incomplete = Key has not been transferred.\n1 : complete = Key has been transferred. +// +// ( (unsigned int) SMON_SECDIAG ) +// AESKT +// <0=> 0: incomplete = Key has not been transferred. +// <1=> 1: complete = Key has been transferred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT0 ------------------------------- +// SVD Line: 7122 + +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT0 +// EXTSTAT0 +// +// [Bit 16] RO (@ 0x4000400C) \nExternal Sensor 0 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// EXTSTAT0 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT1 ------------------------------- +// SVD Line: 7140 + +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT1 +// EXTSTAT1 +// +// [Bit 17] RO (@ 0x4000400C) \nExternal Sensor 1 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// EXTSTAT1 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT2 ------------------------------- +// SVD Line: 7158 + +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT2 +// EXTSTAT2 +// +// [Bit 18] RO (@ 0x4000400C) \nExternal Sensor 2 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// EXTSTAT2 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT3 ------------------------------- +// SVD Line: 7176 + +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT3 +// EXTSTAT3 +// +// [Bit 19] RO (@ 0x4000400C) \nExternal Sensor 3 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// EXTSTAT3 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT4 ------------------------------- +// SVD Line: 7194 + +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT4 +// EXTSTAT4 +// +// [Bit 20] RO (@ 0x4000400C) \nExternal Sensor 4 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// EXTSTAT4 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ---------------------------- Field Item: SMON_SECDIAG_EXTSTAT5 ------------------------------- +// SVD Line: 7212 + +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT5 +// EXTSTAT5 +// +// [Bit 21] RO (@ 0x4000400C) \nExternal Sensor 5 Detect.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SMON_SECDIAG ) +// EXTSTAT5 +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Register RTree: SMON_SECDIAG ---------------------------------- +// SVD Line: 6970 + +// SFDITEM_REG__SMON_SECDIAG +// SECDIAG +// +// [Bits 31..0] RO (@ 0x4000400C) Security Diagnostic Register. +// ( (unsigned int)((SMON_SECDIAG >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__SMON_SECDIAG_BORF +// SFDITEM_FIELD__SMON_SECDIAG_SHIELDF +// SFDITEM_FIELD__SMON_SECDIAG_LOTEMP +// SFDITEM_FIELD__SMON_SECDIAG_HITEMP +// SFDITEM_FIELD__SMON_SECDIAG_BATLO +// SFDITEM_FIELD__SMON_SECDIAG_BATHI +// SFDITEM_FIELD__SMON_SECDIAG_DYNF +// SFDITEM_FIELD__SMON_SECDIAG_AESKT +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT0 +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT1 +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT2 +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT3 +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT4 +// SFDITEM_FIELD__SMON_SECDIAG_EXTSTAT5 +// +// + + +// ---------------------------- Register Item Address: SMON_DLRTC ------------------------------- +// SVD Line: 7232 + +unsigned int SMON_DLRTC __AT (0x40004010); + + + +// ------------------------------ Field Item: SMON_DLRTC_DLRTC ---------------------------------- +// SVD Line: 7239 + +// SFDITEM_FIELD__SMON_DLRTC_DLRTC +// DLRTC +// +// [Bits 31..0] RO (@ 0x40004010) DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured. +// +// ( (unsigned int)((SMON_DLRTC >> 0) & 0xFFFFFFFF) ) +// +// +// + + +// ------------------------------- Register RTree: SMON_DLRTC ----------------------------------- +// SVD Line: 7232 + +// SFDITEM_REG__SMON_DLRTC +// DLRTC +// +// [Bits 31..0] RO (@ 0x40004010) DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred. +// ( (unsigned int)((SMON_DLRTC >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__SMON_DLRTC_DLRTC +// +// + + +// ---------------------------- Register Item Address: SMON_SECST ------------------------------- +// SVD Line: 7247 + +unsigned int SMON_SECST __AT (0x40004034); + + + +// ------------------------------ Field Item: SMON_SECST_EXTSRS --------------------------------- +// SVD Line: 7253 + +// SFDITEM_FIELD__SMON_SECST_EXTSRS +// EXTSRS +// +// [Bit 0] RO (@ 0x40004034) \nExternal Sensor Control Register Status.\n0 : allowed = Access authorized.\n1 : notAllowed = Access not authorized. +// +// ( (unsigned int) SMON_SECST ) +// EXTSRS +// <0=> 0: allowed = Access authorized. +// <1=> 1: notAllowed = Access not authorized. +// +// +// + + +// ------------------------------ Field Item: SMON_SECST_INTSRS --------------------------------- +// SVD Line: 7271 + +// SFDITEM_FIELD__SMON_SECST_INTSRS +// INTSRS +// +// [Bit 1] RO (@ 0x40004034) \nInternal Sensor Control Register Status.\n0 : allowed = Access authorized.\n1 : notAllowed = Access not authorized. +// +// ( (unsigned int) SMON_SECST ) +// INTSRS +// <0=> 0: allowed = Access authorized. +// <1=> 1: notAllowed = Access not authorized. +// +// +// + + +// ----------------------------- Field Item: SMON_SECST_SECALRS --------------------------------- +// SVD Line: 7289 + +// SFDITEM_FIELD__SMON_SECST_SECALRS +// SECALRS +// +// [Bit 2] RO (@ 0x40004034) \nSecurity Alarm Register Status.\n0 : allowed = Access authorized.\n1 : notAllowed = Access not authorized. +// +// ( (unsigned int) SMON_SECST ) +// SECALRS +// <0=> 0: allowed = Access authorized. +// <1=> 1: notAllowed = Access not authorized. +// +// +// + + +// ------------------------------- Register RTree: SMON_SECST ----------------------------------- +// SVD Line: 7247 + +// SFDITEM_REG__SMON_SECST +// SECST +// +// [Bits 31..0] RO (@ 0x40004034) Security Monitor Status Register. +// ( (unsigned int)((SMON_SECST >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__SMON_SECST_EXTSRS +// SFDITEM_FIELD__SMON_SECST_INTSRS +// SFDITEM_FIELD__SMON_SECST_SECALRS +// +// + + +// ---------------------------------- Peripheral View: SMON ------------------------------------- +// SVD Line: 6063 + +// SMON +// SMON +// SFDITEM_REG__SMON_EXTSCN +// SFDITEM_REG__SMON_INTSCN +// SFDITEM_REG__SMON_SECALM +// SFDITEM_REG__SMON_SECDIAG +// SFDITEM_REG__SMON_DLRTC +// SFDITEM_REG__SMON_SECST +// +// + + +// -------------------------- Register Item Address: SPI17Y_DATA32 ------------------------------ +// SVD Line: 7326 + +unsigned int SPI17Y_DATA32 __AT (0x40046000); + + + +// ----------------------------- Field Item: SPI17Y_DATA32_DATA --------------------------------- +// SVD Line: 7333 + +// SFDITEM_FIELD__SPI17Y_DATA32_DATA +// DATA +// +// [Bits 31..0] RW (@ 0x40046000) Read to pull from RX FIFO, write to put into TX FIFO. +// +// ( (unsigned int)((SPI17Y_DATA32 >> 0) & 0xFFFFFFFF), ((SPI17Y_DATA32 = (SPI17Y_DATA32 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: SPI17Y_DATA32 --------------------------------- +// SVD Line: 7326 + +// SFDITEM_REG__SPI17Y_DATA32 +// DATA32 +// +// [Bits 31..0] RW (@ 0x40046000) Register for reading and writing the FIFO. +// ( (unsigned int)((SPI17Y_DATA32 >> 0) & 0xFFFFFFFF), ((SPI17Y_DATA32 = (SPI17Y_DATA32 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_DATA32_DATA +// +// + + +// ---------------- Register Array Item Address: SPI17Y_DATA16_DATA16_DATA160 ------------------- +// SVD Line: 7341 + +unsigned short SPI17Y_DATA16_DATA16_DATA160 __AT (0x40046000); + + + +// ---------------------- Field Item: SPI17Y_DATA16_DATA16_DATA160_DATA ------------------------- +// SVD Line: 7351 + +// SFDITEM_FIELD__SPI17Y_DATA16_DATA16_DATA160_DATA +// DATA +// +// [Bits 15..0] RW (@ 0x40046000) Read to pull from RX FIFO, write to put into TX FIFO. +// +// ( (unsigned short)((SPI17Y_DATA16_DATA16_DATA160 >> 0) & 0xFFFF), ((SPI17Y_DATA16_DATA16_DATA160 = (SPI17Y_DATA16_DATA16_DATA160 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// +// +// + + +// ------------------- Register Array RTree: SPI17Y_DATA16_DATA16_DATA160 ----------------------- +// SVD Line: 7341 + +// SFDITEM_REG__SPI17Y_DATA16_DATA16_DATA160 +// [0] +// +// [Bits 15..0] RW (@ 0x40046000) Register for reading and writing the FIFO. +// ( (unsigned short)((SPI17Y_DATA16_DATA16_DATA160 >> 0) & 0xFFFF), ((SPI17Y_DATA16_DATA16_DATA160 = (SPI17Y_DATA16_DATA16_DATA160 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_DATA16_DATA16_DATA160_DATA +// +// + + +// ---------------- Register Array Item Address: SPI17Y_DATA16_DATA16_DATA161 ------------------- +// SVD Line: 7341 + +unsigned short SPI17Y_DATA16_DATA16_DATA161 __AT (0x40046002); + + + +// ---------------------- Field Item: SPI17Y_DATA16_DATA16_DATA161_DATA ------------------------- +// SVD Line: 7351 + +// SFDITEM_FIELD__SPI17Y_DATA16_DATA16_DATA161_DATA +// DATA +// +// [Bits 15..0] RW (@ 0x40046002) Read to pull from RX FIFO, write to put into TX FIFO. +// +// ( (unsigned short)((SPI17Y_DATA16_DATA16_DATA161 >> 0) & 0xFFFF), ((SPI17Y_DATA16_DATA16_DATA161 = (SPI17Y_DATA16_DATA16_DATA161 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// +// +// + + +// ------------------- Register Array RTree: SPI17Y_DATA16_DATA16_DATA161 ----------------------- +// SVD Line: 7341 + +// SFDITEM_REG__SPI17Y_DATA16_DATA16_DATA161 +// [1] +// +// [Bits 15..0] RW (@ 0x40046002) Register for reading and writing the FIFO. +// ( (unsigned short)((SPI17Y_DATA16_DATA16_DATA161 >> 0) & 0xFFFF), ((SPI17Y_DATA16_DATA16_DATA161 = (SPI17Y_DATA16_DATA16_DATA161 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_DATA16_DATA16_DATA161_DATA +// +// + + +// --------------------------- Register Array ITree: SPI17Y_DATA16 ------------------------------ +// SVD Line: 7341 + +// SFDITEM_REG__SPI17Y_DATA16 +// DATA16 +// Register for reading and writing the FIFO. +// SFDITEM_REG__SPI17Y_DATA16_DATA16_DATA160 +// SFDITEM_REG__SPI17Y_DATA16_DATA16_DATA161 +// +// + + +// ----------------- Register Array Item Address: SPI17Y_DATA8_DATA8_DATA80 --------------------- +// SVD Line: 7359 + +unsigned char SPI17Y_DATA8_DATA8_DATA80 __AT (0x40046000); + + + +// ----------------------- Field Item: SPI17Y_DATA8_DATA8_DATA80_DATA --------------------------- +// SVD Line: 7369 + +// SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA80_DATA +// DATA +// +// [Bits 7..0] RW (@ 0x40046000) Read to pull from RX FIFO, write to put into TX FIFO. +// +// ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA80 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA80 = (SPI17Y_DATA8_DATA8_DATA80 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// --------------------- Register Array RTree: SPI17Y_DATA8_DATA8_DATA80 ------------------------ +// SVD Line: 7359 + +// SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA80 +// [0] +// +// [Bits 7..0] RW (@ 0x40046000) Register for reading and writing the FIFO. +// ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA80 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA80 = (SPI17Y_DATA8_DATA8_DATA80 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA80_DATA +// +// + + +// ----------------- Register Array Item Address: SPI17Y_DATA8_DATA8_DATA81 --------------------- +// SVD Line: 7359 + +unsigned char SPI17Y_DATA8_DATA8_DATA81 __AT (0x40046001); + + + +// ----------------------- Field Item: SPI17Y_DATA8_DATA8_DATA81_DATA --------------------------- +// SVD Line: 7369 + +// SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA81_DATA +// DATA +// +// [Bits 7..0] RW (@ 0x40046001) Read to pull from RX FIFO, write to put into TX FIFO. +// +// ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA81 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA81 = (SPI17Y_DATA8_DATA8_DATA81 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// --------------------- Register Array RTree: SPI17Y_DATA8_DATA8_DATA81 ------------------------ +// SVD Line: 7359 + +// SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA81 +// [1] +// +// [Bits 7..0] RW (@ 0x40046001) Register for reading and writing the FIFO. +// ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA81 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA81 = (SPI17Y_DATA8_DATA8_DATA81 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA81_DATA +// +// + + +// ----------------- Register Array Item Address: SPI17Y_DATA8_DATA8_DATA82 --------------------- +// SVD Line: 7359 + +unsigned char SPI17Y_DATA8_DATA8_DATA82 __AT (0x40046002); + + + +// ----------------------- Field Item: SPI17Y_DATA8_DATA8_DATA82_DATA --------------------------- +// SVD Line: 7369 + +// SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA82_DATA +// DATA +// +// [Bits 7..0] RW (@ 0x40046002) Read to pull from RX FIFO, write to put into TX FIFO. +// +// ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA82 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA82 = (SPI17Y_DATA8_DATA8_DATA82 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// --------------------- Register Array RTree: SPI17Y_DATA8_DATA8_DATA82 ------------------------ +// SVD Line: 7359 + +// SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA82 +// [2] +// +// [Bits 7..0] RW (@ 0x40046002) Register for reading and writing the FIFO. +// ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA82 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA82 = (SPI17Y_DATA8_DATA8_DATA82 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA82_DATA +// +// + + +// ----------------- Register Array Item Address: SPI17Y_DATA8_DATA8_DATA83 --------------------- +// SVD Line: 7359 + +unsigned char SPI17Y_DATA8_DATA8_DATA83 __AT (0x40046003); + + + +// ----------------------- Field Item: SPI17Y_DATA8_DATA8_DATA83_DATA --------------------------- +// SVD Line: 7369 + +// SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA83_DATA +// DATA +// +// [Bits 7..0] RW (@ 0x40046003) Read to pull from RX FIFO, write to put into TX FIFO. +// +// ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA83 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA83 = (SPI17Y_DATA8_DATA8_DATA83 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// --------------------- Register Array RTree: SPI17Y_DATA8_DATA8_DATA83 ------------------------ +// SVD Line: 7359 + +// SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA83 +// [3] +// +// [Bits 7..0] RW (@ 0x40046003) Register for reading and writing the FIFO. +// ( (unsigned char)((SPI17Y_DATA8_DATA8_DATA83 >> 0) & 0xFF), ((SPI17Y_DATA8_DATA8_DATA83 = (SPI17Y_DATA8_DATA8_DATA83 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_DATA8_DATA8_DATA83_DATA +// +// + + +// --------------------------- Register Array ITree: SPI17Y_DATA8 ------------------------------- +// SVD Line: 7359 + +// SFDITEM_REG__SPI17Y_DATA8 +// DATA8 +// Register for reading and writing the FIFO. +// SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA80 +// SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA81 +// SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA82 +// SFDITEM_REG__SPI17Y_DATA8_DATA8_DATA83 +// +// + + +// --------------------------- Register Item Address: SPI17Y_CTRL0 ------------------------------ +// SVD Line: 7377 + +unsigned int SPI17Y_CTRL0 __AT (0x40046004); + + + +// ------------------------------- Field Item: SPI17Y_CTRL0_EN ---------------------------------- +// SVD Line: 7383 + +// SFDITEM_FIELD__SPI17Y_CTRL0_EN +// EN +// +// [Bit 0] RW (@ 0x40046004) \nSPI Enable.\n0 : dis = SPI is disabled.\n1 : en = SPI is enabled. +// +// ( (unsigned int) SPI17Y_CTRL0 ) +// EN +// <0=> 0: dis = SPI is disabled. +// <1=> 1: en = SPI is enabled. +// +// +// + + +// ----------------------------- Field Item: SPI17Y_CTRL0_MASTER -------------------------------- +// SVD Line: 7401 + +// SFDITEM_FIELD__SPI17Y_CTRL0_MASTER +// MASTER +// +// [Bit 1] RW (@ 0x40046004) \nMaster Mode Enable.\n0 : dis = SPI is Slave mode.\n1 : en = SPI is Master mode. +// +// ( (unsigned int) SPI17Y_CTRL0 ) +// MASTER +// <0=> 0: dis = SPI is Slave mode. +// <1=> 1: en = SPI is Master mode. +// +// +// + + +// ----------------------------- Field Item: SPI17Y_CTRL0_SS_IO --------------------------------- +// SVD Line: 7419 + +// SFDITEM_FIELD__SPI17Y_CTRL0_SS_IO +// SS_IO +// +// [Bit 4] RW (@ 0x40046004) \nSlave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.\n0 : output = Slave select 0 is output.\n1 : input = Slave Select 0 is input, only valid if MMEN=1. +// +// ( (unsigned int) SPI17Y_CTRL0 ) +// SS_IO +// <0=> 0: output = Slave select 0 is output. +// <1=> 1: input = Slave Select 0 is input, only valid if MMEN=1. +// +// +// + + +// ----------------------------- Field Item: SPI17Y_CTRL0_START --------------------------------- +// SVD Line: 7437 + +// SFDITEM_FIELD__SPI17Y_CTRL0_START +// START +// +// [Bit 5] RW (@ 0x40046004) \nStart Transmit.\n0 : Reserved - do not use\n1 : start = Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. +// +// ( (unsigned int) SPI17Y_CTRL0 ) +// START +// <0=> 0: +// <1=> 1: start = Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_CTRL0_SS_CTRL -------------------------------- +// SVD Line: 7450 + +// SFDITEM_FIELD__SPI17Y_CTRL0_SS_CTRL +// SS_CTRL +// +// [Bit 8] RW (@ 0x40046004) \nStart Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.\n0 : DEASSERT = SPI De-asserts Slave Select at the end of a transaction.\n1 : ASSERT = SPI leaves Slave Select asserted at the end of a transaction. +// +// ( (unsigned int) SPI17Y_CTRL0 ) +// SS_CTRL +// <0=> 0: DEASSERT = SPI De-asserts Slave Select at the end of a transaction. +// <1=> 1: ASSERT = SPI leaves Slave Select asserted at the end of a transaction. +// +// +// + + +// ------------------------------- Field Item: SPI17Y_CTRL0_SS ---------------------------------- +// SVD Line: 7468 + +// SFDITEM_FIELD__SPI17Y_CTRL0_SS +// SS +// +// [Bits 19..16] RW (@ 0x40046004) \nSlave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.\n0 : Reserved - do not use\n1 : SS0 = SS0 is selected.\n2 : SS1 = SS1 is selected.\n3 : Reserved - do not use\n4 : SS2 = SS2 is selected.\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : SS3 = SS3 is selected.\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use +// +// ( (unsigned int) SPI17Y_CTRL0 ) +// SS +// <0=> 0: +// <1=> 1: SS0 = SS0 is selected. +// <2=> 2: SS1 = SS1 is selected. +// <3=> 3: +// <4=> 4: SS2 = SS2 is selected. +// <5=> 5: +// <6=> 6: +// <7=> 7: +// <8=> 8: SS3 = SS3 is selected. +// <9=> 9: +// <10=> 10: +// <11=> 11: +// <12=> 12: +// <13=> 13: +// <14=> 14: +// <15=> 15: +// +// +// + + +// ------------------------------ Register RTree: SPI17Y_CTRL0 ---------------------------------- +// SVD Line: 7377 + +// SFDITEM_REG__SPI17Y_CTRL0 +// CTRL0 +// +// [Bits 31..0] RW (@ 0x40046004) Register for controlling SPI peripheral. +// ( (unsigned int)((SPI17Y_CTRL0 >> 0) & 0xFFFFFFFF), ((SPI17Y_CTRL0 = (SPI17Y_CTRL0 & ~(0xF0133UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0133) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_CTRL0_EN +// SFDITEM_FIELD__SPI17Y_CTRL0_MASTER +// SFDITEM_FIELD__SPI17Y_CTRL0_SS_IO +// SFDITEM_FIELD__SPI17Y_CTRL0_START +// SFDITEM_FIELD__SPI17Y_CTRL0_SS_CTRL +// SFDITEM_FIELD__SPI17Y_CTRL0_SS +// +// + + +// --------------------------- Register Item Address: SPI17Y_CTRL1 ------------------------------ +// SVD Line: 7498 + +unsigned int SPI17Y_CTRL1 __AT (0x40046008); + + + +// -------------------------- Field Item: SPI17Y_CTRL1_TX_NUM_CHAR ------------------------------ +// SVD Line: 7504 + +// SFDITEM_FIELD__SPI17Y_CTRL1_TX_NUM_CHAR +// TX_NUM_CHAR +// +// [Bits 15..0] RW (@ 0x40046008) Nubmer of Characters to transmit. +// +// ( (unsigned short)((SPI17Y_CTRL1 >> 0) & 0xFFFF), ((SPI17Y_CTRL1 = (SPI17Y_CTRL1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// +// +// + + +// -------------------------- Field Item: SPI17Y_CTRL1_RX_NUM_CHAR ------------------------------ +// SVD Line: 7510 + +// SFDITEM_FIELD__SPI17Y_CTRL1_RX_NUM_CHAR +// RX_NUM_CHAR +// +// [Bits 31..16] RW (@ 0x40046008) Nubmer of Characters to receive. +// +// ( (unsigned short)((SPI17Y_CTRL1 >> 16) & 0xFFFF), ((SPI17Y_CTRL1 = (SPI17Y_CTRL1 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: SPI17Y_CTRL1 ---------------------------------- +// SVD Line: 7498 + +// SFDITEM_REG__SPI17Y_CTRL1 +// CTRL1 +// +// [Bits 31..0] RW (@ 0x40046008) Register for controlling SPI peripheral. +// ( (unsigned int)((SPI17Y_CTRL1 >> 0) & 0xFFFFFFFF), ((SPI17Y_CTRL1 = (SPI17Y_CTRL1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_CTRL1_TX_NUM_CHAR +// SFDITEM_FIELD__SPI17Y_CTRL1_RX_NUM_CHAR +// +// + + +// --------------------------- Register Item Address: SPI17Y_CTRL2 ------------------------------ +// SVD Line: 7518 + +unsigned int SPI17Y_CTRL2 __AT (0x4004600C); + + + +// ------------------------------ Field Item: SPI17Y_CTRL2_CPHA --------------------------------- +// SVD Line: 7524 + +// SFDITEM_FIELD__SPI17Y_CTRL2_CPHA +// CPHA +// +// [Bit 0] RW (@ 0x4004600C) \nClock Phase.\n0 : Rising_Edge = Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2\n1 : Falling_Edge = Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 +// +// ( (unsigned int) SPI17Y_CTRL2 ) +// CPHA +// <0=> 0: Rising_Edge = Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 +// <1=> 1: Falling_Edge = Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 +// +// +// + + +// ------------------------------ Field Item: SPI17Y_CTRL2_CPOL --------------------------------- +// SVD Line: 7542 + +// SFDITEM_FIELD__SPI17Y_CTRL2_CPOL +// CPOL +// +// [Bit 1] RW (@ 0x4004600C) \nClock Polarity.\n0 : Normal = Normal Clock. Use when in SPI Mode 0 and Mode 1\n1 : Inverted = Inverted Clock. Use when in SPI Mode 2 and Mode 3 +// +// ( (unsigned int) SPI17Y_CTRL2 ) +// CPOL +// <0=> 0: Normal = Normal Clock. Use when in SPI Mode 0 and Mode 1 +// <1=> 1: Inverted = Inverted Clock. Use when in SPI Mode 2 and Mode 3 +// +// +// + + +// ---------------------------- Field Item: SPI17Y_CTRL2_SCLK_INV ------------------------------- +// SVD Line: 7560 + +// SFDITEM_FIELD__SPI17Y_CTRL2_SCLK_INV +// SCLK_INV +// +// [Bit 4] RW (@ 0x4004600C) Reserved - Must Always Be Cleared to 0. +// +// ( (unsigned int) SPI17Y_CTRL2 ) +// SCLK_INV +// +// +// + + +// ---------------------------- Field Item: SPI17Y_CTRL2_NUMBITS -------------------------------- +// SVD Line: 7566 + +// SFDITEM_FIELD__SPI17Y_CTRL2_NUMBITS +// NUMBITS +// +// [Bits 11..8] RW (@ 0x4004600C) \nNumber of Bits per character.\n0 : 0 = 16 bits per character.\n1 : Reserved - do not use\n2 : Reserved - do not use\n3 : Reserved - do not use\n4 : Reserved - do not use\n5 : Reserved - do not use\n6 : Reserved - do not use\n7 : Reserved - do not use\n8 : Reserved - do not use\n9 : Reserved - do not use\n10 : Reserved - do not use\n11 : Reserved - do not use\n12 : Reserved - do not use\n13 : Reserved - do not use\n14 : Reserved - do not use\n15 : Reserved - do not use +// +// ( (unsigned int) SPI17Y_CTRL2 ) +// NUMBITS +// <0=> 0: 0 = 16 bits per character. +// <1=> 1: +// <2=> 2: +// <3=> 3: +// <4=> 4: +// <5=> 5: +// <6=> 6: +// <7=> 7: +// <8=> 8: +// <9=> 9: +// <10=> 10: +// <11=> 11: +// <12=> 12: +// <13=> 13: +// <14=> 14: +// <15=> 15: +// +// +// + + +// --------------------------- Field Item: SPI17Y_CTRL2_DATA_WIDTH ------------------------------ +// SVD Line: 7579 + +// SFDITEM_FIELD__SPI17Y_CTRL2_DATA_WIDTH +// DATA_WIDTH +// +// [Bits 13..12] RW (@ 0x4004600C) \nSPI Data width.\n0 : Mono = 1 data pin.\n1 : Dual = 2 data pins.\n2 : Quad = 4 data pins.\n3 : Reserved - do not use +// +// ( (unsigned int) SPI17Y_CTRL2 ) +// DATA_WIDTH +// <0=> 0: Mono = 1 data pin. +// <1=> 1: Dual = 2 data pins. +// <2=> 2: Quad = 4 data pins. +// <3=> 3: +// +// +// + + +// --------------------------- Field Item: SPI17Y_CTRL2_THREE_WIRE ------------------------------ +// SVD Line: 7602 + +// SFDITEM_FIELD__SPI17Y_CTRL2_THREE_WIRE +// THREE_WIRE +// +// [Bit 15] RW (@ 0x4004600C) \nThree Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.\n0 : dis = Use four wire mode (Mono only).\n1 : en = Use three wire mode. +// +// ( (unsigned int) SPI17Y_CTRL2 ) +// THREE_WIRE +// <0=> 0: dis = Use four wire mode (Mono only). +// <1=> 1: en = Use three wire mode. +// +// +// + + +// ----------------------------- Field Item: SPI17Y_CTRL2_SS_POL -------------------------------- +// SVD Line: 7620 + +// SFDITEM_FIELD__SPI17Y_CTRL2_SS_POL +// SS_POL +// +// [Bits 23..16] RW (@ 0x4004600C) Slave Select Polarity, each Slave Select can have unique polarity. +// +// ( (unsigned char)((SPI17Y_CTRL2 >> 16) & 0xFF), ((SPI17Y_CTRL2 = (SPI17Y_CTRL2 & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) )) +// +// +// + + +// ----------------------------- Field Item: SPI17Y_CTRL2_SRPOL --------------------------------- +// SVD Line: 7648 + +// SFDITEM_FIELD__SPI17Y_CTRL2_SRPOL +// SRPOL +// +// [Bits 31..24] RW (@ 0x4004600C) Slave Ready Polarity, each Slave Ready can have unique polarity. +// +// ( (unsigned char)((SPI17Y_CTRL2 >> 24) & 0xFF), ((SPI17Y_CTRL2 = (SPI17Y_CTRL2 & ~(0xFFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 24 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: SPI17Y_CTRL2 ---------------------------------- +// SVD Line: 7518 + +// SFDITEM_REG__SPI17Y_CTRL2 +// CTRL2 +// +// [Bits 31..0] RW (@ 0x4004600C) Register for controlling SPI peripheral. +// ( (unsigned int)((SPI17Y_CTRL2 >> 0) & 0xFFFFFFFF), ((SPI17Y_CTRL2 = (SPI17Y_CTRL2 & ~(0xFFFFBF13UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFBF13) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_CTRL2_CPHA +// SFDITEM_FIELD__SPI17Y_CTRL2_CPOL +// SFDITEM_FIELD__SPI17Y_CTRL2_SCLK_INV +// SFDITEM_FIELD__SPI17Y_CTRL2_NUMBITS +// SFDITEM_FIELD__SPI17Y_CTRL2_DATA_WIDTH +// SFDITEM_FIELD__SPI17Y_CTRL2_THREE_WIRE +// SFDITEM_FIELD__SPI17Y_CTRL2_SS_POL +// SFDITEM_FIELD__SPI17Y_CTRL2_SRPOL +// +// + + +// -------------------------- Register Item Address: SPI17Y_SS_TIME ----------------------------- +// SVD Line: 7698 + +unsigned int SPI17Y_SS_TIME __AT (0x40046010); + + + +// ----------------------------- Field Item: SPI17Y_SS_TIME_PRE --------------------------------- +// SVD Line: 7704 + +// SFDITEM_FIELD__SPI17Y_SS_TIME_PRE +// PRE +// +// [Bits 7..0] RW (@ 0x40046010) Slave Select Pre delay 1. +// +// ( (unsigned char)((SPI17Y_SS_TIME >> 0) & 0xFF), ((SPI17Y_SS_TIME = (SPI17Y_SS_TIME & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Field Item: SPI17Y_SS_TIME_POST -------------------------------- +// SVD Line: 7717 + +// SFDITEM_FIELD__SPI17Y_SS_TIME_POST +// POST +// +// [Bits 15..8] RW (@ 0x40046010) Slave Select Post delay 2. +// +// ( (unsigned char)((SPI17Y_SS_TIME >> 8) & 0xFF), ((SPI17Y_SS_TIME = (SPI17Y_SS_TIME & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) +// +// +// + + +// ---------------------------- Field Item: SPI17Y_SS_TIME_INACT -------------------------------- +// SVD Line: 7730 + +// SFDITEM_FIELD__SPI17Y_SS_TIME_INACT +// INACT +// +// [Bits 23..16] RW (@ 0x40046010) Slave Select Inactive delay. +// +// ( (unsigned char)((SPI17Y_SS_TIME >> 16) & 0xFF), ((SPI17Y_SS_TIME = (SPI17Y_SS_TIME & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) )) +// +// +// + + +// ----------------------------- Register RTree: SPI17Y_SS_TIME --------------------------------- +// SVD Line: 7698 + +// SFDITEM_REG__SPI17Y_SS_TIME +// SS_TIME +// +// [Bits 31..0] RW (@ 0x40046010) Register for controlling SPI peripheral/Slave Select Timing. +// ( (unsigned int)((SPI17Y_SS_TIME >> 0) & 0xFFFFFFFF), ((SPI17Y_SS_TIME = (SPI17Y_SS_TIME & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_SS_TIME_PRE +// SFDITEM_FIELD__SPI17Y_SS_TIME_POST +// SFDITEM_FIELD__SPI17Y_SS_TIME_INACT +// +// + + +// -------------------------- Register Item Address: SPI17Y_CLK_CFG ----------------------------- +// SVD Line: 7745 + +unsigned int SPI17Y_CLK_CFG __AT (0x40046014); + + + +// ------------------------------ Field Item: SPI17Y_CLK_CFG_LO --------------------------------- +// SVD Line: 7751 + +// SFDITEM_FIELD__SPI17Y_CLK_CFG_LO +// LO +// +// [Bits 7..0] RW (@ 0x40046014) Low duty cycle control. In timer mode, reload[7:0]. +// +// ( (unsigned char)((SPI17Y_CLK_CFG >> 0) & 0xFF), ((SPI17Y_CLK_CFG = (SPI17Y_CLK_CFG & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Field Item: SPI17Y_CLK_CFG_HI --------------------------------- +// SVD Line: 7764 + +// SFDITEM_FIELD__SPI17Y_CLK_CFG_HI +// HI +// +// [Bits 15..8] RW (@ 0x40046014) High duty cycle control. In timer mode, reload[15:8]. +// +// ( (unsigned char)((SPI17Y_CLK_CFG >> 8) & 0xFF), ((SPI17Y_CLK_CFG = (SPI17Y_CLK_CFG & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) +// +// +// + + +// ---------------------------- Field Item: SPI17Y_CLK_CFG_SCALE -------------------------------- +// SVD Line: 7777 + +// SFDITEM_FIELD__SPI17Y_CLK_CFG_SCALE +// SCALE +// +// [Bits 19..16] RW (@ 0x40046014) System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. +// +// ( (unsigned char)((SPI17Y_CLK_CFG >> 16) & 0xF), ((SPI17Y_CLK_CFG = (SPI17Y_CLK_CFG & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) )) +// +// +// + + +// ----------------------------- Register RTree: SPI17Y_CLK_CFG --------------------------------- +// SVD Line: 7745 + +// SFDITEM_REG__SPI17Y_CLK_CFG +// CLK_CFG +// +// [Bits 31..0] RW (@ 0x40046014) Register for controlling SPI clock rate. +// ( (unsigned int)((SPI17Y_CLK_CFG >> 0) & 0xFFFFFFFF), ((SPI17Y_CLK_CFG = (SPI17Y_CLK_CFG & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_CLK_CFG_LO +// SFDITEM_FIELD__SPI17Y_CLK_CFG_HI +// SFDITEM_FIELD__SPI17Y_CLK_CFG_SCALE +// +// + + +// ---------------------------- Register Item Address: SPI17Y_DMA ------------------------------- +// SVD Line: 7785 + +unsigned int SPI17Y_DMA __AT (0x4004601C); + + + +// -------------------------- Field Item: SPI17Y_DMA_TX_FIFO_LEVEL ------------------------------ +// SVD Line: 7791 + +// SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_LEVEL +// TX_FIFO_LEVEL +// +// [Bits 4..0] RW (@ 0x4004601C) Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. +// +// ( (unsigned char)((SPI17Y_DMA >> 0) & 0x1F), ((SPI17Y_DMA = (SPI17Y_DMA & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) )) +// +// +// + + +// ---------------------------- Field Item: SPI17Y_DMA_TX_FIFO_EN ------------------------------- +// SVD Line: 7797 + +// SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_EN +// TX_FIFO_EN +// +// [Bit 6] RW (@ 0x4004601C) \nTransmit FIFO enabled for SPI transactions.\n0 : dis = Transmit FIFO is not enabled.\n1 : en = Transmit FIFO is enabled. +// +// ( (unsigned int) SPI17Y_DMA ) +// TX_FIFO_EN +// <0=> 0: dis = Transmit FIFO is not enabled. +// <1=> 1: en = Transmit FIFO is enabled. +// +// +// + + +// -------------------------- Field Item: SPI17Y_DMA_TX_FIFO_CLEAR ------------------------------ +// SVD Line: 7815 + +// SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_CLEAR +// TX_FIFO_CLEAR +// +// [Bit 7] RW (@ 0x4004601C) \nClear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. .\n0 : Reserved - do not use\n1 : CLEAR = Clear the Transmit FIFO, clears any pending TX FIFO status. +// +// ( (unsigned int) SPI17Y_DMA ) +// TX_FIFO_CLEAR +// <0=> 0: +// <1=> 1: CLEAR = Clear the Transmit FIFO, clears any pending TX FIFO status. +// +// +// + + +// --------------------------- Field Item: SPI17Y_DMA_TX_FIFO_CNT ------------------------------- +// SVD Line: 7830 + +// SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_CNT +// TX_FIFO_CNT +// +// [Bits 13..8] RO (@ 0x4004601C) Count of entries in TX FIFO. +// +// ( (unsigned char)((SPI17Y_DMA >> 8) & 0x3F) ) +// +// +// + + +// ---------------------------- Field Item: SPI17Y_DMA_TX_DMA_EN -------------------------------- +// SVD Line: 7837 + +// SFDITEM_FIELD__SPI17Y_DMA_TX_DMA_EN +// TX_DMA_EN +// +// [Bit 15] RW (@ 0x4004601C) \nTX DMA Enable.\n0 : DIS = TX DMA requests are disabled, andy pending DMA requests are cleared.\n1 : en = TX DMA requests are enabled. +// +// ( (unsigned int) SPI17Y_DMA ) +// TX_DMA_EN +// <0=> 0: DIS = TX DMA requests are disabled, andy pending DMA requests are cleared. +// <1=> 1: en = TX DMA requests are enabled. +// +// +// + + +// -------------------------- Field Item: SPI17Y_DMA_RX_FIFO_LEVEL ------------------------------ +// SVD Line: 7855 + +// SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_LEVEL +// RX_FIFO_LEVEL +// +// [Bits 20..16] RW (@ 0x4004601C) Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. +// +// ( (unsigned char)((SPI17Y_DMA >> 16) & 0x1F), ((SPI17Y_DMA = (SPI17Y_DMA & ~(0x1FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 16 ) ) )) +// +// +// + + +// ---------------------------- Field Item: SPI17Y_DMA_RX_FIFO_EN ------------------------------- +// SVD Line: 7861 + +// SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_EN +// RX_FIFO_EN +// +// [Bit 22] RW (@ 0x4004601C) \nReceive FIFO enabled for SPI transactions.\n0 : DIS = Receive FIFO is not enabled.\n1 : en = Receive FIFO is enabled. +// +// ( (unsigned int) SPI17Y_DMA ) +// RX_FIFO_EN +// <0=> 0: DIS = Receive FIFO is not enabled. +// <1=> 1: en = Receive FIFO is enabled. +// +// +// + + +// -------------------------- Field Item: SPI17Y_DMA_RX_FIFO_CLEAR ------------------------------ +// SVD Line: 7879 + +// SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_CLEAR +// RX_FIFO_CLEAR +// +// [Bit 23] RW (@ 0x4004601C) \nClear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.\n0 : Reserved - do not use\n1 : CLEAR = Clear the Receive FIFO, clears any pending RX FIFO status. +// +// ( (unsigned int) SPI17Y_DMA ) +// RX_FIFO_CLEAR +// <0=> 0: +// <1=> 1: CLEAR = Clear the Receive FIFO, clears any pending RX FIFO status. +// +// +// + + +// --------------------------- Field Item: SPI17Y_DMA_RX_FIFO_CNT ------------------------------- +// SVD Line: 7892 + +// SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_CNT +// RX_FIFO_CNT +// +// [Bits 29..24] RO (@ 0x4004601C) Count of entries in RX FIFO. +// +// ( (unsigned char)((SPI17Y_DMA >> 24) & 0x3F) ) +// +// +// + + +// ---------------------------- Field Item: SPI17Y_DMA_RX_DMA_EN -------------------------------- +// SVD Line: 7899 + +// SFDITEM_FIELD__SPI17Y_DMA_RX_DMA_EN +// RX_DMA_EN +// +// [Bit 31] RW (@ 0x4004601C) \nRX DMA Enable.\n0 : dis = RX DMA requests are disabled, any pending DMA requests are cleared.\n1 : en = RX DMA requests are enabled. +// +// ( (unsigned int) SPI17Y_DMA ) +// RX_DMA_EN +// <0=> 0: dis = RX DMA requests are disabled, any pending DMA requests are cleared. +// <1=> 1: en = RX DMA requests are enabled. +// +// +// + + +// ------------------------------- Register RTree: SPI17Y_DMA ----------------------------------- +// SVD Line: 7785 + +// SFDITEM_REG__SPI17Y_DMA +// DMA +// +// [Bits 31..0] RW (@ 0x4004601C) Register for controlling DMA. +// ( (unsigned int)((SPI17Y_DMA >> 0) & 0xFFFFFFFF), ((SPI17Y_DMA = (SPI17Y_DMA & ~(0x80DF80DFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80DF80DF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_LEVEL +// SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_EN +// SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_CLEAR +// SFDITEM_FIELD__SPI17Y_DMA_TX_FIFO_CNT +// SFDITEM_FIELD__SPI17Y_DMA_TX_DMA_EN +// SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_LEVEL +// SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_EN +// SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_CLEAR +// SFDITEM_FIELD__SPI17Y_DMA_RX_FIFO_CNT +// SFDITEM_FIELD__SPI17Y_DMA_RX_DMA_EN +// +// + + +// -------------------------- Register Item Address: SPI17Y_INT_FL ------------------------------ +// SVD Line: 7919 + +unsigned int SPI17Y_INT_FL __AT (0x40046020); + + + +// --------------------------- Field Item: SPI17Y_INT_FL_TX_THRESH ------------------------------ +// SVD Line: 7925 + +// SFDITEM_FIELD__SPI17Y_INT_FL_TX_THRESH +// TX_THRESH +// +// [Bit 0] RW (@ 0x40046020) \nTX FIFO Threshold Crossed.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// TX_THRESH +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// --------------------------- Field Item: SPI17Y_INT_FL_TX_EMPTY ------------------------------- +// SVD Line: 7938 + +// SFDITEM_FIELD__SPI17Y_INT_FL_TX_EMPTY +// TX_EMPTY +// +// [Bit 1] RW (@ 0x40046020) \nTX FIFO Empty.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// TX_EMPTY +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// --------------------------- Field Item: SPI17Y_INT_FL_RX_THRESH ------------------------------ +// SVD Line: 7951 + +// SFDITEM_FIELD__SPI17Y_INT_FL_RX_THRESH +// RX_THRESH +// +// [Bit 2] RW (@ 0x40046020) \nRX FIFO Threshold Crossed.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// RX_THRESH +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_FL_RX_FULL ------------------------------- +// SVD Line: 7964 + +// SFDITEM_FIELD__SPI17Y_INT_FL_RX_FULL +// RX_FULL +// +// [Bit 3] RW (@ 0x40046020) \nRX FIFO FULL.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// RX_FULL +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ------------------------------ Field Item: SPI17Y_INT_FL_SSA --------------------------------- +// SVD Line: 7977 + +// SFDITEM_FIELD__SPI17Y_INT_FL_SSA +// SSA +// +// [Bit 4] RW (@ 0x40046020) \nSlave Select Asserted.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// SSA +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ------------------------------ Field Item: SPI17Y_INT_FL_SSD --------------------------------- +// SVD Line: 7990 + +// SFDITEM_FIELD__SPI17Y_INT_FL_SSD +// SSD +// +// [Bit 5] RW (@ 0x40046020) \nSlave Select Deasserted.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// SSD +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ----------------------------- Field Item: SPI17Y_INT_FL_FAULT -------------------------------- +// SVD Line: 8003 + +// SFDITEM_FIELD__SPI17Y_INT_FL_FAULT +// FAULT +// +// [Bit 8] RW (@ 0x40046020) \nMulti-Master Mode Fault.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// FAULT +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ----------------------------- Field Item: SPI17Y_INT_FL_ABORT -------------------------------- +// SVD Line: 8016 + +// SFDITEM_FIELD__SPI17Y_INT_FL_ABORT +// ABORT +// +// [Bit 9] RW (@ 0x40046020) \nSlave Abort Detected.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// ABORT +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_FL_M_DONE -------------------------------- +// SVD Line: 8029 + +// SFDITEM_FIELD__SPI17Y_INT_FL_M_DONE +// M_DONE +// +// [Bit 11] RW (@ 0x40046020) \nMaster Done, set when SPI Master has completed any transactions.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// M_DONE +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_FL_TX_OVR -------------------------------- +// SVD Line: 8042 + +// SFDITEM_FIELD__SPI17Y_INT_FL_TX_OVR +// TX_OVR +// +// [Bit 12] RW (@ 0x40046020) \nTransmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// TX_OVR +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_FL_TX_UND -------------------------------- +// SVD Line: 8055 + +// SFDITEM_FIELD__SPI17Y_INT_FL_TX_UND +// TX_UND +// +// [Bit 13] RW (@ 0x40046020) \nTransmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// TX_UND +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_FL_RX_OVR -------------------------------- +// SVD Line: 8068 + +// SFDITEM_FIELD__SPI17Y_INT_FL_RX_OVR +// RX_OVR +// +// [Bit 14] RW (@ 0x40046020) \nReceive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// RX_OVR +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_FL_RX_UND -------------------------------- +// SVD Line: 8081 + +// SFDITEM_FIELD__SPI17Y_INT_FL_RX_UND +// RX_UND +// +// [Bit 15] RW (@ 0x40046020) \nReceive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_INT_FL ) +// RX_UND +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ------------------------------ Register RTree: SPI17Y_INT_FL --------------------------------- +// SVD Line: 7919 + +// SFDITEM_REG__SPI17Y_INT_FL +// INT_FL +// +// [Bits 31..0] RW (@ 0x40046020) Register for reading and clearing interrupt flags. All bits are write 1 to clear. +// ( (unsigned int)((SPI17Y_INT_FL >> 0) & 0xFFFFFFFF), ((SPI17Y_INT_FL = (SPI17Y_INT_FL & ~(0xFB3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB3F) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_INT_FL_TX_THRESH +// SFDITEM_FIELD__SPI17Y_INT_FL_TX_EMPTY +// SFDITEM_FIELD__SPI17Y_INT_FL_RX_THRESH +// SFDITEM_FIELD__SPI17Y_INT_FL_RX_FULL +// SFDITEM_FIELD__SPI17Y_INT_FL_SSA +// SFDITEM_FIELD__SPI17Y_INT_FL_SSD +// SFDITEM_FIELD__SPI17Y_INT_FL_FAULT +// SFDITEM_FIELD__SPI17Y_INT_FL_ABORT +// SFDITEM_FIELD__SPI17Y_INT_FL_M_DONE +// SFDITEM_FIELD__SPI17Y_INT_FL_TX_OVR +// SFDITEM_FIELD__SPI17Y_INT_FL_TX_UND +// SFDITEM_FIELD__SPI17Y_INT_FL_RX_OVR +// SFDITEM_FIELD__SPI17Y_INT_FL_RX_UND +// +// + + +// -------------------------- Register Item Address: SPI17Y_INT_EN ------------------------------ +// SVD Line: 8096 + +unsigned int SPI17Y_INT_EN __AT (0x40046024); + + + +// --------------------------- Field Item: SPI17Y_INT_EN_TX_THRESH ------------------------------ +// SVD Line: 8102 + +// SFDITEM_FIELD__SPI17Y_INT_EN_TX_THRESH +// TX_THRESH +// +// [Bit 0] RW (@ 0x40046024) \nTX FIFO Threshold interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// TX_THRESH +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// --------------------------- Field Item: SPI17Y_INT_EN_TX_EMPTY ------------------------------- +// SVD Line: 8120 + +// SFDITEM_FIELD__SPI17Y_INT_EN_TX_EMPTY +// TX_EMPTY +// +// [Bit 1] RW (@ 0x40046024) \nTX FIFO Empty interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// TX_EMPTY +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// --------------------------- Field Item: SPI17Y_INT_EN_RX_THRESH ------------------------------ +// SVD Line: 8138 + +// SFDITEM_FIELD__SPI17Y_INT_EN_RX_THRESH +// RX_THRESH +// +// [Bit 2] RW (@ 0x40046024) \nRX FIFO Threshold Crossed interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// RX_THRESH +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_EN_RX_FULL ------------------------------- +// SVD Line: 8156 + +// SFDITEM_FIELD__SPI17Y_INT_EN_RX_FULL +// RX_FULL +// +// [Bit 3] RW (@ 0x40046024) \nRX FIFO FULL interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// RX_FULL +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ------------------------------ Field Item: SPI17Y_INT_EN_SSA --------------------------------- +// SVD Line: 8174 + +// SFDITEM_FIELD__SPI17Y_INT_EN_SSA +// SSA +// +// [Bit 4] RW (@ 0x40046024) \nSlave Select Asserted interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// SSA +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ------------------------------ Field Item: SPI17Y_INT_EN_SSD --------------------------------- +// SVD Line: 8192 + +// SFDITEM_FIELD__SPI17Y_INT_EN_SSD +// SSD +// +// [Bit 5] RW (@ 0x40046024) \nSlave Select Deasserted interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// SSD +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ----------------------------- Field Item: SPI17Y_INT_EN_FAULT -------------------------------- +// SVD Line: 8210 + +// SFDITEM_FIELD__SPI17Y_INT_EN_FAULT +// FAULT +// +// [Bit 8] RW (@ 0x40046024) \nMulti-Master Mode Fault interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// FAULT +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ----------------------------- Field Item: SPI17Y_INT_EN_ABORT -------------------------------- +// SVD Line: 8228 + +// SFDITEM_FIELD__SPI17Y_INT_EN_ABORT +// ABORT +// +// [Bit 9] RW (@ 0x40046024) \nSlave Abort Detected interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// ABORT +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_EN_M_DONE -------------------------------- +// SVD Line: 8246 + +// SFDITEM_FIELD__SPI17Y_INT_EN_M_DONE +// M_DONE +// +// [Bit 11] RW (@ 0x40046024) \nMaster Done interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// M_DONE +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_EN_TX_OVR -------------------------------- +// SVD Line: 8264 + +// SFDITEM_FIELD__SPI17Y_INT_EN_TX_OVR +// TX_OVR +// +// [Bit 12] RW (@ 0x40046024) \nTransmit FIFO Overrun interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// TX_OVR +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_EN_TX_UND -------------------------------- +// SVD Line: 8282 + +// SFDITEM_FIELD__SPI17Y_INT_EN_TX_UND +// TX_UND +// +// [Bit 13] RW (@ 0x40046024) \nTransmit FIFO Underrun interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// TX_UND +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_EN_RX_OVR -------------------------------- +// SVD Line: 8300 + +// SFDITEM_FIELD__SPI17Y_INT_EN_RX_OVR +// RX_OVR +// +// [Bit 14] RW (@ 0x40046024) \nReceive FIFO Overrun interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// RX_OVR +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ---------------------------- Field Item: SPI17Y_INT_EN_RX_UND -------------------------------- +// SVD Line: 8318 + +// SFDITEM_FIELD__SPI17Y_INT_EN_RX_UND +// RX_UND +// +// [Bit 15] RW (@ 0x40046024) \nReceive FIFO Underrun interrupt enable.\n0 : dis = Interrupt is disabled.\n1 : en = Interrupt is enabled. +// +// ( (unsigned int) SPI17Y_INT_EN ) +// RX_UND +// <0=> 0: dis = Interrupt is disabled. +// <1=> 1: en = Interrupt is enabled. +// +// +// + + +// ------------------------------ Register RTree: SPI17Y_INT_EN --------------------------------- +// SVD Line: 8096 + +// SFDITEM_REG__SPI17Y_INT_EN +// INT_EN +// +// [Bits 31..0] RW (@ 0x40046024) Register for enabling interrupts. +// ( (unsigned int)((SPI17Y_INT_EN >> 0) & 0xFFFFFFFF), ((SPI17Y_INT_EN = (SPI17Y_INT_EN & ~(0xFB3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFB3F) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_INT_EN_TX_THRESH +// SFDITEM_FIELD__SPI17Y_INT_EN_TX_EMPTY +// SFDITEM_FIELD__SPI17Y_INT_EN_RX_THRESH +// SFDITEM_FIELD__SPI17Y_INT_EN_RX_FULL +// SFDITEM_FIELD__SPI17Y_INT_EN_SSA +// SFDITEM_FIELD__SPI17Y_INT_EN_SSD +// SFDITEM_FIELD__SPI17Y_INT_EN_FAULT +// SFDITEM_FIELD__SPI17Y_INT_EN_ABORT +// SFDITEM_FIELD__SPI17Y_INT_EN_M_DONE +// SFDITEM_FIELD__SPI17Y_INT_EN_TX_OVR +// SFDITEM_FIELD__SPI17Y_INT_EN_TX_UND +// SFDITEM_FIELD__SPI17Y_INT_EN_RX_OVR +// SFDITEM_FIELD__SPI17Y_INT_EN_RX_UND +// +// + + +// -------------------------- Register Item Address: SPI17Y_WAKE_FL ----------------------------- +// SVD Line: 8338 + +unsigned int SPI17Y_WAKE_FL __AT (0x40046028); + + + +// -------------------------- Field Item: SPI17Y_WAKE_FL_TX_THRESH ------------------------------ +// SVD Line: 8344 + +// SFDITEM_FIELD__SPI17Y_WAKE_FL_TX_THRESH +// TX_THRESH +// +// [Bit 0] RW (@ 0x40046028) \nWake on TX FIFO Threshold Crossed.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_WAKE_FL ) +// TX_THRESH +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// --------------------------- Field Item: SPI17Y_WAKE_FL_TX_EMPTY ------------------------------ +// SVD Line: 8357 + +// SFDITEM_FIELD__SPI17Y_WAKE_FL_TX_EMPTY +// TX_EMPTY +// +// [Bit 1] RW (@ 0x40046028) \nWake on TX FIFO Empty.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_WAKE_FL ) +// TX_EMPTY +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// -------------------------- Field Item: SPI17Y_WAKE_FL_RX_THRESH ------------------------------ +// SVD Line: 8370 + +// SFDITEM_FIELD__SPI17Y_WAKE_FL_RX_THRESH +// RX_THRESH +// +// [Bit 2] RW (@ 0x40046028) \nWake on RX FIFO Threshold Crossed.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_WAKE_FL ) +// RX_THRESH +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// --------------------------- Field Item: SPI17Y_WAKE_FL_RX_FULL ------------------------------- +// SVD Line: 8383 + +// SFDITEM_FIELD__SPI17Y_WAKE_FL_RX_FULL +// RX_FULL +// +// [Bit 3] RW (@ 0x40046028) \nWake on RX FIFO Full.\n0 : Reserved - do not use\n1 : clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// ( (unsigned int) SPI17Y_WAKE_FL ) +// RX_FULL +// <0=> 0: +// <1=> 1: clear = Flag is set when value read is 1. Write 1 to clear this flag. +// +// +// + + +// ----------------------------- Register RTree: SPI17Y_WAKE_FL --------------------------------- +// SVD Line: 8338 + +// SFDITEM_REG__SPI17Y_WAKE_FL +// WAKE_FL +// +// [Bits 31..0] RW (@ 0x40046028) Register for wake up flags. All bits in this register are write 1 to clear. +// ( (unsigned int)((SPI17Y_WAKE_FL >> 0) & 0xFFFFFFFF), ((SPI17Y_WAKE_FL = (SPI17Y_WAKE_FL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_WAKE_FL_TX_THRESH +// SFDITEM_FIELD__SPI17Y_WAKE_FL_TX_EMPTY +// SFDITEM_FIELD__SPI17Y_WAKE_FL_RX_THRESH +// SFDITEM_FIELD__SPI17Y_WAKE_FL_RX_FULL +// +// + + +// -------------------------- Register Item Address: SPI17Y_WAKE_EN ----------------------------- +// SVD Line: 8398 + +unsigned int SPI17Y_WAKE_EN __AT (0x4004602C); + + + +// -------------------------- Field Item: SPI17Y_WAKE_EN_TX_THRESH ------------------------------ +// SVD Line: 8404 + +// SFDITEM_FIELD__SPI17Y_WAKE_EN_TX_THRESH +// TX_THRESH +// +// [Bit 0] RW (@ 0x4004602C) \nWake on TX FIFO Threshold Crossed Enable.\n0 : dis = Wakeup source disabled.\n1 : en = Wakeup source enabled. +// +// ( (unsigned int) SPI17Y_WAKE_EN ) +// TX_THRESH +// <0=> 0: dis = Wakeup source disabled. +// <1=> 1: en = Wakeup source enabled. +// +// +// + + +// --------------------------- Field Item: SPI17Y_WAKE_EN_TX_EMPTY ------------------------------ +// SVD Line: 8422 + +// SFDITEM_FIELD__SPI17Y_WAKE_EN_TX_EMPTY +// TX_EMPTY +// +// [Bit 1] RW (@ 0x4004602C) \nWake on TX FIFO Empty Enable.\n0 : dis = Wakeup source disabled.\n1 : en = Wakeup source enabled. +// +// ( (unsigned int) SPI17Y_WAKE_EN ) +// TX_EMPTY +// <0=> 0: dis = Wakeup source disabled. +// <1=> 1: en = Wakeup source enabled. +// +// +// + + +// -------------------------- Field Item: SPI17Y_WAKE_EN_RX_THRESH ------------------------------ +// SVD Line: 8440 + +// SFDITEM_FIELD__SPI17Y_WAKE_EN_RX_THRESH +// RX_THRESH +// +// [Bit 2] RW (@ 0x4004602C) \nWake on RX FIFO Threshold Crossed Enable.\n0 : dis = Wakeup source disabled.\n1 : en = Wakeup source enabled. +// +// ( (unsigned int) SPI17Y_WAKE_EN ) +// RX_THRESH +// <0=> 0: dis = Wakeup source disabled. +// <1=> 1: en = Wakeup source enabled. +// +// +// + + +// --------------------------- Field Item: SPI17Y_WAKE_EN_RX_FULL ------------------------------- +// SVD Line: 8458 + +// SFDITEM_FIELD__SPI17Y_WAKE_EN_RX_FULL +// RX_FULL +// +// [Bit 3] RW (@ 0x4004602C) \nWake on RX FIFO Full Enable.\n0 : dis = Wakeup source disabled.\n1 : en = Wakeup source enabled. +// +// ( (unsigned int) SPI17Y_WAKE_EN ) +// RX_FULL +// <0=> 0: dis = Wakeup source disabled. +// <1=> 1: en = Wakeup source enabled. +// +// +// + + +// ----------------------------- Register RTree: SPI17Y_WAKE_EN --------------------------------- +// SVD Line: 8398 + +// SFDITEM_REG__SPI17Y_WAKE_EN +// WAKE_EN +// +// [Bits 31..0] RW (@ 0x4004602C) Register for wake up enable. +// ( (unsigned int)((SPI17Y_WAKE_EN >> 0) & 0xFFFFFFFF), ((SPI17Y_WAKE_EN = (SPI17Y_WAKE_EN & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) )) +// SFDITEM_FIELD__SPI17Y_WAKE_EN_TX_THRESH +// SFDITEM_FIELD__SPI17Y_WAKE_EN_TX_EMPTY +// SFDITEM_FIELD__SPI17Y_WAKE_EN_RX_THRESH +// SFDITEM_FIELD__SPI17Y_WAKE_EN_RX_FULL +// +// + + +// --------------------------- Register Item Address: SPI17Y_STAT ------------------------------- +// SVD Line: 8478 + +unsigned int SPI17Y_STAT __AT (0x40046030); + + + +// ------------------------------ Field Item: SPI17Y_STAT_BUSY ---------------------------------- +// SVD Line: 8484 + +// SFDITEM_FIELD__SPI17Y_STAT_BUSY +// BUSY +// +// [Bit 0] RO (@ 0x40046030) \nSPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.\n0 : not = SPI not active.\n1 : active = SPI active. +// +// ( (unsigned int) SPI17Y_STAT ) +// BUSY +// <0=> 0: not = SPI not active. +// <1=> 1: active = SPI active. +// +// +// + + +// ------------------------------- Register RTree: SPI17Y_STAT ---------------------------------- +// SVD Line: 8478 + +// SFDITEM_REG__SPI17Y_STAT +// STAT +// +// [Bits 31..0] RO (@ 0x40046030) SPI Status register. +// ( (unsigned int)((SPI17Y_STAT >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__SPI17Y_STAT_BUSY +// +// + + +// --------------------------------- Peripheral View: SPI17Y ------------------------------------ +// SVD Line: 7312 + +// SPI17Y +// SPI17Y +// SFDITEM_REG__SPI17Y_DATA32 +// SFDITEM_REG__SPI17Y_DATA16 +// SFDITEM_REG__SPI17Y_DATA8 +// SFDITEM_REG__SPI17Y_CTRL0 +// SFDITEM_REG__SPI17Y_CTRL1 +// SFDITEM_REG__SPI17Y_CTRL2 +// SFDITEM_REG__SPI17Y_SS_TIME +// SFDITEM_REG__SPI17Y_CLK_CFG +// SFDITEM_REG__SPI17Y_DMA +// SFDITEM_REG__SPI17Y_INT_FL +// SFDITEM_REG__SPI17Y_INT_EN +// SFDITEM_REG__SPI17Y_WAKE_FL +// SFDITEM_REG__SPI17Y_WAKE_EN +// SFDITEM_REG__SPI17Y_STAT +// +// + + +// -------------------------- Register Item Address: SPIMSS_DATA16 ------------------------------ +// SVD Line: 8518 + +unsigned short SPIMSS_DATA16 __AT (0x40018000); + + + +// ----------------------------- Field Item: SPIMSS_DATA16_DATA --------------------------------- +// SVD Line: 8525 + +// SFDITEM_FIELD__SPIMSS_DATA16_DATA +// DATA +// +// [Bits 15..0] RW (@ 0x40018000) SPI data. +// +// ( (unsigned short)((SPIMSS_DATA16 >> 0) & 0xFFFF), ((SPIMSS_DATA16 = (SPIMSS_DATA16 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: SPIMSS_DATA16 --------------------------------- +// SVD Line: 8518 + +// SFDITEM_REG__SPIMSS_DATA16 +// DATA16 +// +// [Bits 15..0] RW (@ 0x40018000) SPI 16-bit Data Access +// ( (unsigned short)((SPIMSS_DATA16 >> 0) & 0xFFFF), ((SPIMSS_DATA16 = (SPIMSS_DATA16 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_DATA16_DATA +// +// + + +// ----------------- Register Array Item Address: SPIMSS_DATA8_DATA8_DATA80 --------------------- +// SVD Line: 8533 + +unsigned char SPIMSS_DATA8_DATA8_DATA80 __AT (0x40018000); + + + +// ----------------------- Field Item: SPIMSS_DATA8_DATA8_DATA80_DATA --------------------------- +// SVD Line: 8543 + +// SFDITEM_FIELD__SPIMSS_DATA8_DATA8_DATA80_DATA +// DATA +// +// [Bits 7..0] RW (@ 0x40018000) SPI data. +// +// ( (unsigned char)((SPIMSS_DATA8_DATA8_DATA80 >> 0) & 0xFF), ((SPIMSS_DATA8_DATA8_DATA80 = (SPIMSS_DATA8_DATA8_DATA80 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// --------------------- Register Array RTree: SPIMSS_DATA8_DATA8_DATA80 ------------------------ +// SVD Line: 8533 + +// SFDITEM_REG__SPIMSS_DATA8_DATA8_DATA80 +// [0] +// +// [Bits 7..0] RW (@ 0x40018000) SPI Data 8-bit access +// ( (unsigned char)((SPIMSS_DATA8_DATA8_DATA80 >> 0) & 0xFF), ((SPIMSS_DATA8_DATA8_DATA80 = (SPIMSS_DATA8_DATA8_DATA80 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_DATA8_DATA8_DATA80_DATA +// +// + + +// ----------------- Register Array Item Address: SPIMSS_DATA8_DATA8_DATA81 --------------------- +// SVD Line: 8533 + +unsigned char SPIMSS_DATA8_DATA8_DATA81 __AT (0x40018001); + + + +// ----------------------- Field Item: SPIMSS_DATA8_DATA8_DATA81_DATA --------------------------- +// SVD Line: 8543 + +// SFDITEM_FIELD__SPIMSS_DATA8_DATA8_DATA81_DATA +// DATA +// +// [Bits 7..0] RW (@ 0x40018001) SPI data. +// +// ( (unsigned char)((SPIMSS_DATA8_DATA8_DATA81 >> 0) & 0xFF), ((SPIMSS_DATA8_DATA8_DATA81 = (SPIMSS_DATA8_DATA8_DATA81 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// --------------------- Register Array RTree: SPIMSS_DATA8_DATA8_DATA81 ------------------------ +// SVD Line: 8533 + +// SFDITEM_REG__SPIMSS_DATA8_DATA8_DATA81 +// [1] +// +// [Bits 7..0] RW (@ 0x40018001) SPI Data 8-bit access +// ( (unsigned char)((SPIMSS_DATA8_DATA8_DATA81 >> 0) & 0xFF), ((SPIMSS_DATA8_DATA8_DATA81 = (SPIMSS_DATA8_DATA8_DATA81 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_DATA8_DATA8_DATA81_DATA +// +// + + +// --------------------------- Register Array ITree: SPIMSS_DATA8 ------------------------------- +// SVD Line: 8533 + +// SFDITEM_REG__SPIMSS_DATA8 +// DATA8 +// SPI Data 8-bit access +// SFDITEM_REG__SPIMSS_DATA8_DATA8_DATA80 +// SFDITEM_REG__SPIMSS_DATA8_DATA8_DATA81 +// +// + + +// --------------------------- Register Item Address: SPIMSS_CTRL ------------------------------- +// SVD Line: 8551 + +unsigned int SPIMSS_CTRL __AT (0x40018004); + + + +// ------------------------------ Field Item: SPIMSS_CTRL_SPIEN --------------------------------- +// SVD Line: 8556 + +// SFDITEM_FIELD__SPIMSS_CTRL_SPIEN +// SPIEN +// +// [Bit 0] RW (@ 0x40018004) \nSPI Enable.\n0 : disable = disable\n1 : enable = enable +// +// ( (unsigned int) SPIMSS_CTRL ) +// SPIEN +// <0=> 0: disable = disable +// <1=> 1: enable = enable +// +// +// + + +// ------------------------------ Field Item: SPIMSS_CTRL_MMEN ---------------------------------- +// SVD Line: 8573 + +// SFDITEM_FIELD__SPIMSS_CTRL_MMEN +// MMEN +// +// [Bit 1] RW (@ 0x40018004) \nSPI Master Mode Enable.\n0 : slave = slave\n1 : master = master +// +// ( (unsigned int) SPIMSS_CTRL ) +// MMEN +// <0=> 0: slave = slave +// <1=> 1: master = master +// +// +// + + +// ------------------------------- Field Item: SPIMSS_CTRL_WOR ---------------------------------- +// SVD Line: 8590 + +// SFDITEM_FIELD__SPIMSS_CTRL_WOR +// WOR +// +// [Bit 2] RW (@ 0x40018004) \nWired OR (open drain) Enable.\n0 : disable = disable\n1 : enable = enable +// +// ( (unsigned int) SPIMSS_CTRL ) +// WOR +// <0=> 0: disable = disable +// <1=> 1: enable = enable +// +// +// + + +// ----------------------------- Field Item: SPIMSS_CTRL_CLKPOL --------------------------------- +// SVD Line: 8607 + +// SFDITEM_FIELD__SPIMSS_CTRL_CLKPOL +// CLKPOL +// +// [Bit 3] RW (@ 0x40018004) \nClock Polarity.\n0 : idleLo = SCLK idles Low (0) after character transmission/reception.\n1 : idleHi = SCLK idles High (1) after character transmission/reception. +// +// ( (unsigned int) SPIMSS_CTRL ) +// CLKPOL +// <0=> 0: idleLo = SCLK idles Low (0) after character transmission/reception. +// <1=> 1: idleHi = SCLK idles High (1) after character transmission/reception. +// +// +// + + +// ------------------------------ Field Item: SPIMSS_CTRL_PHASE --------------------------------- +// SVD Line: 8626 + +// SFDITEM_FIELD__SPIMSS_CTRL_PHASE +// PHASE +// +// [Bit 4] RW (@ 0x40018004) \nPhase Select.\n0 : activeEdge = Transmit on active edge of SCLK.\n1 : inactiveEdge = Transmit on inactive edge of SCLK. +// +// ( (unsigned int) SPIMSS_CTRL ) +// PHASE +// <0=> 0: activeEdge = Transmit on active edge of SCLK. +// <1=> 1: inactiveEdge = Transmit on inactive edge of SCLK. +// +// +// + + +// ------------------------------ Field Item: SPIMSS_CTRL_BIRQ ---------------------------------- +// SVD Line: 8645 + +// SFDITEM_FIELD__SPIMSS_CTRL_BIRQ +// BIRQ +// +// [Bit 5] RW (@ 0x40018004) \nBaud Rate Generator Timer Interrupt Request.\n0 : disable = disable\n1 : enable = enable +// +// ( (unsigned int) SPIMSS_CTRL ) +// BIRQ +// <0=> 0: disable = disable +// <1=> 1: enable = enable +// +// +// + + +// ------------------------------- Field Item: SPIMSS_CTRL_STR ---------------------------------- +// SVD Line: 8662 + +// SFDITEM_FIELD__SPIMSS_CTRL_STR +// STR +// +// [Bit 6] RW (@ 0x40018004) \nStart SPI Interrupt.\n0 : complete = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) SPIMSS_CTRL ) +// STR +// <0=> 0: complete = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// ------------------------------ Field Item: SPIMSS_CTRL_IRQE ---------------------------------- +// SVD Line: 8681 + +// SFDITEM_FIELD__SPIMSS_CTRL_IRQE +// IRQE +// +// [Bit 7] RW (@ 0x40018004) \nInterrupt Request Enable.\n0 : disable = disable\n1 : enable = enable +// +// ( (unsigned int) SPIMSS_CTRL ) +// IRQE +// <0=> 0: disable = disable +// <1=> 1: enable = enable +// +// +// + + +// ------------------------------- Register RTree: SPIMSS_CTRL ---------------------------------- +// SVD Line: 8551 + +// SFDITEM_REG__SPIMSS_CTRL +// CTRL +// +// [Bits 31..0] RW (@ 0x40018004) SPI Control Register. +// ( (unsigned int)((SPIMSS_CTRL >> 0) & 0xFFFFFFFF), ((SPIMSS_CTRL = (SPIMSS_CTRL & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_CTRL_SPIEN +// SFDITEM_FIELD__SPIMSS_CTRL_MMEN +// SFDITEM_FIELD__SPIMSS_CTRL_WOR +// SFDITEM_FIELD__SPIMSS_CTRL_CLKPOL +// SFDITEM_FIELD__SPIMSS_CTRL_PHASE +// SFDITEM_FIELD__SPIMSS_CTRL_BIRQ +// SFDITEM_FIELD__SPIMSS_CTRL_STR +// SFDITEM_FIELD__SPIMSS_CTRL_IRQE +// +// + + +// -------------------------- Register Item Address: SPIMSS_STATUS ------------------------------ +// SVD Line: 8700 + +unsigned int SPIMSS_STATUS __AT (0x40018008); + + + +// ----------------------------- Field Item: SPIMSS_STATUS_SLAS --------------------------------- +// SVD Line: 8706 + +// SFDITEM_FIELD__SPIMSS_STATUS_SLAS +// SLAS +// +// [Bit 0] RO (@ 0x40018008) \nSlave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.\n0 : selected = selected\n1 : notSelected = notSelected +// +// ( (unsigned int) SPIMSS_STATUS ) +// SLAS +// <0=> 0: selected = selected +// <1=> 1: notSelected = notSelected +// +// +// + + +// ----------------------------- Field Item: SPIMSS_STATUS_TXST --------------------------------- +// SVD Line: 8724 + +// SFDITEM_FIELD__SPIMSS_STATUS_TXST +// TXST +// +// [Bit 1] RO (@ 0x40018008) \nTransmit Status.\n0 : idle = idle\n1 : busy = busy +// +// ( (unsigned int) SPIMSS_STATUS ) +// TXST +// <0=> 0: idle = idle +// <1=> 1: busy = busy +// +// +// + + +// ----------------------------- Field Item: SPIMSS_STATUS_TUND --------------------------------- +// SVD Line: 8742 + +// SFDITEM_FIELD__SPIMSS_STATUS_TUND +// TUND +// +// [Bit 2] RW (@ 0x40018008) \nTransmit Underrun.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SPIMSS_STATUS ) +// TUND +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SPIMSS_STATUS_ROVR --------------------------------- +// SVD Line: 8762 + +// SFDITEM_FIELD__SPIMSS_STATUS_ROVR +// ROVR +// +// [Bit 3] RW (@ 0x40018008) \nReceive Overrun.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SPIMSS_STATUS ) +// ROVR +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SPIMSS_STATUS_ABT --------------------------------- +// SVD Line: 8781 + +// SFDITEM_FIELD__SPIMSS_STATUS_ABT +// ABT +// +// [Bit 4] RW (@ 0x40018008) \nSlave Mode Transaction Abort.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SPIMSS_STATUS ) +// ABT +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SPIMSS_STATUS_COL --------------------------------- +// SVD Line: 8800 + +// SFDITEM_FIELD__SPIMSS_STATUS_COL +// COL +// +// [Bit 5] RW (@ 0x40018008) \nCollision.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SPIMSS_STATUS ) +// COL +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ----------------------------- Field Item: SPIMSS_STATUS_TOVR --------------------------------- +// SVD Line: 8819 + +// SFDITEM_FIELD__SPIMSS_STATUS_TOVR +// TOVR +// +// [Bit 6] RW (@ 0x40018008) \nTransmit Overrun.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) SPIMSS_STATUS ) +// TOVR +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// ------------------------------ Field Item: SPIMSS_STATUS_IRQ --------------------------------- +// SVD Line: 8838 + +// SFDITEM_FIELD__SPIMSS_STATUS_IRQ +// IRQ +// +// [Bit 7] RW (@ 0x40018008) \nSPI Interrupt Request.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) SPIMSS_STATUS ) +// IRQ +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ------------------------------ Register RTree: SPIMSS_STATUS --------------------------------- +// SVD Line: 8700 + +// SFDITEM_REG__SPIMSS_STATUS +// STATUS +// +// [Bits 31..0] RW (@ 0x40018008) SPI Status Register. +// ( (unsigned int)((SPIMSS_STATUS >> 0) & 0xFFFFFFFF), ((SPIMSS_STATUS = (SPIMSS_STATUS & ~(0xFCUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFC) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_STATUS_SLAS +// SFDITEM_FIELD__SPIMSS_STATUS_TXST +// SFDITEM_FIELD__SPIMSS_STATUS_TUND +// SFDITEM_FIELD__SPIMSS_STATUS_ROVR +// SFDITEM_FIELD__SPIMSS_STATUS_ABT +// SFDITEM_FIELD__SPIMSS_STATUS_COL +// SFDITEM_FIELD__SPIMSS_STATUS_TOVR +// SFDITEM_FIELD__SPIMSS_STATUS_IRQ +// +// + + +// ---------------------------- Register Item Address: SPIMSS_MOD ------------------------------- +// SVD Line: 8860 + +unsigned int SPIMSS_MOD __AT (0x4001800C); + + + +// ------------------------------- Field Item: SPIMSS_MOD_SSV ----------------------------------- +// SVD Line: 8865 + +// SFDITEM_FIELD__SPIMSS_MOD_SSV +// SSV +// +// [Bit 0] RW (@ 0x4001800C) \nSlave Select Value.\n0 : lo = The SSEL pin will be driven low.\n1 : hi = The SSEL pin will be driven high. +// +// ( (unsigned int) SPIMSS_MOD ) +// SSV +// <0=> 0: lo = The SSEL pin will be driven low. +// <1=> 1: hi = The SSEL pin will be driven high. +// +// +// + + +// ------------------------------- Field Item: SPIMSS_MOD_SSIO ---------------------------------- +// SVD Line: 8884 + +// SFDITEM_FIELD__SPIMSS_MOD_SSIO +// SSIO +// +// [Bit 1] RW (@ 0x4001800C) \nSlave Select I/O.\n0 : input = input\n1 : output = output +// +// ( (unsigned int) SPIMSS_MOD ) +// SSIO +// <0=> 0: input = input +// <1=> 1: output = output +// +// +// + + +// ----------------------------- Field Item: SPIMSS_MOD_NUMBITS --------------------------------- +// SVD Line: 8901 + +// SFDITEM_FIELD__SPIMSS_MOD_NUMBITS +// NUMBITS +// +// [Bits 5..2] RW (@ 0x4001800C) \nNUMBITS\n0 : bits16 = bits16\n1 : bits1 = bits1\n2 : bits2 = bits2\n3 : bits3 = bits3\n4 : bits4 = bits4\n5 : bits5 = bits5\n6 : bits6 = bits6\n7 : bits7 = bits7\n8 : bits8 = bits8\n9 : bits9 = bits9\n10 : bits10 = bits10\n11 : bits11 = bits11\n12 : bits12 = bits12\n13 : bits13 = bits13\n14 : bits14 = bits14\n15 : bits15 = bits15 +// +// ( (unsigned int) SPIMSS_MOD ) +// NUMBITS +// <0=> 0: bits16 = bits16 +// <1=> 1: bits1 = bits1 +// <2=> 2: bits2 = bits2 +// <3=> 3: bits3 = bits3 +// <4=> 4: bits4 = bits4 +// <5=> 5: bits5 = bits5 +// <6=> 6: bits6 = bits6 +// <7=> 7: bits7 = bits7 +// <8=> 8: bits8 = bits8 +// <9=> 9: bits9 = bits9 +// <10=> 10: bits10 = bits10 +// <11=> 11: bits11 = bits11 +// <12=> 12: bits12 = bits12 +// <13=> 13: bits13 = bits13 +// <14=> 14: bits14 = bits14 +// <15=> 15: bits15 = bits15 +// +// +// + + +// ------------------------------ Field Item: SPIMSS_MOD_TX_LJ ---------------------------------- +// SVD Line: 8973 + +// SFDITEM_FIELD__SPIMSS_MOD_TX_LJ +// TX_LJ +// +// [Bit 7] RW (@ 0x4001800C) \nTransmit Left Justify.\n0 : disable = disable\n1 : enable = enable +// +// ( (unsigned int) SPIMSS_MOD ) +// TX_LJ +// <0=> 0: disable = disable +// <1=> 1: enable = enable +// +// +// + + +// ------------------------------- Field Item: SPIMSS_MOD_SSL1 ---------------------------------- +// SVD Line: 8990 + +// SFDITEM_FIELD__SPIMSS_MOD_SSL1 +// SSL1 +// +// [Bit 8] RW (@ 0x4001800C) \nSlave Select 1. If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit.\n0 : hi = High.\n1 : lo = Low. +// +// ( (unsigned int) SPIMSS_MOD ) +// SSL1 +// <0=> 0: hi = High. +// <1=> 1: lo = Low. +// +// +// + + +// ------------------------------- Field Item: SPIMSS_MOD_SSL2 ---------------------------------- +// SVD Line: 9009 + +// SFDITEM_FIELD__SPIMSS_MOD_SSL2 +// SSL2 +// +// [Bit 9] RW (@ 0x4001800C) \nSlave Select 2. If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit.\n0 : hi = High.\n1 : lo = Low. +// +// ( (unsigned int) SPIMSS_MOD ) +// SSL2 +// <0=> 0: hi = High. +// <1=> 1: lo = Low. +// +// +// + + +// ------------------------------- Field Item: SPIMSS_MOD_SSL3 ---------------------------------- +// SVD Line: 9028 + +// SFDITEM_FIELD__SPIMSS_MOD_SSL3 +// SSL3 +// +// [Bit 10] RW (@ 0x4001800C) \nSlave Select 3. If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit.\n0 : hi = High.\n1 : lo = Low. +// +// ( (unsigned int) SPIMSS_MOD ) +// SSL3 +// <0=> 0: hi = High. +// <1=> 1: lo = Low. +// +// +// + + +// ------------------------------- Register RTree: SPIMSS_MOD ----------------------------------- +// SVD Line: 8860 + +// SFDITEM_REG__SPIMSS_MOD +// MOD +// +// [Bits 31..0] RW (@ 0x4001800C) SPI Mode Register. +// ( (unsigned int)((SPIMSS_MOD >> 0) & 0xFFFFFFFF), ((SPIMSS_MOD = (SPIMSS_MOD & ~(0x7BFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7BF) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_MOD_SSV +// SFDITEM_FIELD__SPIMSS_MOD_SSIO +// SFDITEM_FIELD__SPIMSS_MOD_NUMBITS +// SFDITEM_FIELD__SPIMSS_MOD_TX_LJ +// SFDITEM_FIELD__SPIMSS_MOD_SSL1 +// SFDITEM_FIELD__SPIMSS_MOD_SSL2 +// SFDITEM_FIELD__SPIMSS_MOD_SSL3 +// +// + + +// ---------------------------- Register Item Address: SPIMSS_BRG ------------------------------- +// SVD Line: 9049 + +unsigned int SPIMSS_BRG __AT (0x40018014); + + + +// ------------------------------- Field Item: SPIMSS_BRG_BRG ----------------------------------- +// SVD Line: 9055 + +// SFDITEM_FIELD__SPIMSS_BRG_BRG +// BRG +// +// [Bits 15..0] RW (@ 0x40018014) Baud Rate Reload Value. +// +// ( (unsigned short)((SPIMSS_BRG >> 0) & 0xFFFF), ((SPIMSS_BRG = (SPIMSS_BRG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: SPIMSS_BRG ----------------------------------- +// SVD Line: 9049 + +// SFDITEM_REG__SPIMSS_BRG +// BRG +// +// [Bits 31..0] RW (@ 0x40018014) Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4). +// ( (unsigned int)((SPIMSS_BRG >> 0) & 0xFFFFFFFF), ((SPIMSS_BRG = (SPIMSS_BRG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_BRG_BRG +// +// + + +// ---------------------------- Register Item Address: SPIMSS_DMA ------------------------------- +// SVD Line: 9063 + +unsigned int SPIMSS_DMA __AT (0x40018018); + + + +// -------------------------- Field Item: SPIMSS_DMA_TX_FIFO_LEVEL ------------------------------ +// SVD Line: 9069 + +// SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_LEVEL +// TX_FIFO_LEVEL +// +// [Bits 2..0] RW (@ 0x40018018) \nTransmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.\n0 : entry1 = entry1\n1 : entries2 = entries2\n2 : entries3 = entries3\n3 : entries4 = entries4\n4 : entries5 = entries5\n5 : entries6 = entries6\n6 : entries7 = entries7\n7 : entries8 = entries8 +// +// ( (unsigned int) SPIMSS_DMA ) +// TX_FIFO_LEVEL +// <0=> 0: entry1 = entry1 +// <1=> 1: entries2 = entries2 +// <2=> 2: entries3 = entries3 +// <3=> 3: entries4 = entries4 +// <4=> 4: entries5 = entries5 +// <5=> 5: entries6 = entries6 +// <6=> 6: entries7 = entries7 +// <7=> 7: entries8 = entries8 +// +// +// + + +// -------------------------- Field Item: SPIMSS_DMA_TX_FIFO_CLEAR ------------------------------ +// SVD Line: 9110 + +// SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_CLEAR +// TX_FIFO_CLEAR +// +// [Bit 4] WO (@ 0x40018018) \nTransmit FIFO Clear.\n0 : complete = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) SPIMSS_DMA ) +// TX_FIFO_CLEAR +// <0=> 0: complete = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// --------------------------- Field Item: SPIMSS_DMA_TX_FIFO_CNT ------------------------------- +// SVD Line: 9130 + +// SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_CNT +// TX_FIFO_CNT +// +// [Bits 11..8] RO (@ 0x40018018) Transmit FIFO Count. +// +// ( (unsigned char)((SPIMSS_DMA >> 8) & 0xF) ) +// +// +// + + +// ---------------------------- Field Item: SPIMSS_DMA_TX_DMA_EN -------------------------------- +// SVD Line: 9137 + +// SFDITEM_FIELD__SPIMSS_DMA_TX_DMA_EN +// TX_DMA_EN +// +// [Bit 15] RW (@ 0x40018018) \nTransmit DMA Enable.\n0 : disable = disable\n1 : enable = enable +// +// ( (unsigned int) SPIMSS_DMA ) +// TX_DMA_EN +// <0=> 0: disable = disable +// <1=> 1: enable = enable +// +// +// + + +// -------------------------- Field Item: SPIMSS_DMA_RX_FIFO_LEVEL ------------------------------ +// SVD Line: 9154 + +// SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_LEVEL +// RX_FIFO_LEVEL +// +// [Bits 18..16] RW (@ 0x40018018) \nReceive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.\n0 : entry1 = entry1\n1 : entries2 = entries2\n2 : entries3 = entries3\n3 : entries4 = entries4\n4 : entries5 = entries5\n5 : entries6 = entries6\n6 : entries7 = entries7\n7 : entries8 = entries8 +// +// ( (unsigned int) SPIMSS_DMA ) +// RX_FIFO_LEVEL +// <0=> 0: entry1 = entry1 +// <1=> 1: entries2 = entries2 +// <2=> 2: entries3 = entries3 +// <3=> 3: entries4 = entries4 +// <4=> 4: entries5 = entries5 +// <5=> 5: entries6 = entries6 +// <6=> 6: entries7 = entries7 +// <7=> 7: entries8 = entries8 +// +// +// + + +// -------------------------- Field Item: SPIMSS_DMA_RX_FIFO_CLEAR ------------------------------ +// SVD Line: 9195 + +// SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_CLEAR +// RX_FIFO_CLEAR +// +// [Bit 20] RW (@ 0x40018018) \nReceive FIFO Clear.\n0 : complete = No operation/complete.\n1 : start = Start operation. +// +// ( (unsigned int) SPIMSS_DMA ) +// RX_FIFO_CLEAR +// <0=> 0: complete = No operation/complete. +// <1=> 1: start = Start operation. +// +// +// + + +// --------------------------- Field Item: SPIMSS_DMA_RX_FIFO_CNT ------------------------------- +// SVD Line: 9214 + +// SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_CNT +// RX_FIFO_CNT +// +// [Bits 27..24] RO (@ 0x40018018) Receive FIFO Count. +// +// ( (unsigned char)((SPIMSS_DMA >> 24) & 0xF) ) +// +// +// + + +// ---------------------------- Field Item: SPIMSS_DMA_RX_DMA_EN -------------------------------- +// SVD Line: 9221 + +// SFDITEM_FIELD__SPIMSS_DMA_RX_DMA_EN +// RX_DMA_EN +// +// [Bit 31] RW (@ 0x40018018) \nReceive DMA Enable.\n0 : disable = disable\n1 : enable = enable +// +// ( (unsigned int) SPIMSS_DMA ) +// RX_DMA_EN +// <0=> 0: disable = disable +// <1=> 1: enable = enable +// +// +// + + +// ------------------------------- Register RTree: SPIMSS_DMA ----------------------------------- +// SVD Line: 9063 + +// SFDITEM_REG__SPIMSS_DMA +// DMA +// +// [Bits 31..0] RW (@ 0x40018018) SPI DMA Register. +// ( (unsigned int)((SPIMSS_DMA >> 0) & 0xFFFFFFFF), ((SPIMSS_DMA = (SPIMSS_DMA & ~(0x80178017UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80178017) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_LEVEL +// SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_CLEAR +// SFDITEM_FIELD__SPIMSS_DMA_TX_FIFO_CNT +// SFDITEM_FIELD__SPIMSS_DMA_TX_DMA_EN +// SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_LEVEL +// SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_CLEAR +// SFDITEM_FIELD__SPIMSS_DMA_RX_FIFO_CNT +// SFDITEM_FIELD__SPIMSS_DMA_RX_DMA_EN +// +// + + +// ------------------------- Register Item Address: SPIMSS_I2S_CTRL ----------------------------- +// SVD Line: 9240 + +unsigned int SPIMSS_I2S_CTRL __AT (0x4001801C); + + + +// --------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_EN ------------------------------- +// SVD Line: 9245 + +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_EN +// I2S_EN +// +// [Bit 0] RW (@ 0x4001801C) \nI2S Mode Enable.\n0 : disable = disable\n1 : enable = enable +// +// ( (unsigned int) SPIMSS_I2S_CTRL ) +// I2S_EN +// <0=> 0: disable = disable +// <1=> 1: enable = enable +// +// +// + + +// -------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_MUTE ------------------------------ +// SVD Line: 9262 + +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_MUTE +// I2S_MUTE +// +// [Bit 1] RW (@ 0x4001801C) \nI2S Mute transmit.\n0 : normal = Normal Transmit.\n1 : replaced = Transmit data is replaced with 0. +// +// ( (unsigned int) SPIMSS_I2S_CTRL ) +// I2S_MUTE +// <0=> 0: normal = Normal Transmit. +// <1=> 1: replaced = Transmit data is replaced with 0. +// +// +// + + +// -------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_PAUSE ----------------------------- +// SVD Line: 9280 + +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_PAUSE +// I2S_PAUSE +// +// [Bit 2] RW (@ 0x4001801C) \nI2S Pause transmit/receive.\n0 : normal = Normal Transmit.\n1 : halt = Halt transmit and receive FIFO and DMA access, transmit 0's. +// +// ( (unsigned int) SPIMSS_I2S_CTRL ) +// I2S_PAUSE +// <0=> 0: normal = Normal Transmit. +// <1=> 1: halt = Halt transmit and receive FIFO and DMA access, transmit 0's. +// +// +// + + +// -------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_MONO ------------------------------ +// SVD Line: 9298 + +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_MONO +// I2S_MONO +// +// [Bit 3] RW (@ 0x4001801C) \nI2S Monophonic Audio Mode.\n0 : stereophonic = Stereophonic audio.\n1 : monophonic = Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored. +// +// ( (unsigned int) SPIMSS_I2S_CTRL ) +// I2S_MONO +// <0=> 0: stereophonic = Stereophonic audio. +// <1=> 1: monophonic = Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored. +// +// +// + + +// --------------------------- Field Item: SPIMSS_I2S_CTRL_I2S_LJ ------------------------------- +// SVD Line: 9316 + +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_LJ +// I2S_LJ +// +// [Bit 4] RW (@ 0x4001801C) \nI2S Left Justify.\n0 : normal = Normal I2S audio protocol.\n1 : replaced = Audio data is synchronized with SSEL. +// +// ( (unsigned int) SPIMSS_I2S_CTRL ) +// I2S_LJ +// <0=> 0: normal = Normal I2S audio protocol. +// <1=> 1: replaced = Audio data is synchronized with SSEL. +// +// +// + + +// ----------------------------- Register RTree: SPIMSS_I2S_CTRL -------------------------------- +// SVD Line: 9240 + +// SFDITEM_REG__SPIMSS_I2S_CTRL +// I2S_CTRL +// +// [Bits 31..0] RW (@ 0x4001801C) I2S Control Register. +// ( (unsigned int)((SPIMSS_I2S_CTRL >> 0) & 0xFFFFFFFF), ((SPIMSS_I2S_CTRL = (SPIMSS_I2S_CTRL & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) )) +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_EN +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_MUTE +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_PAUSE +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_MONO +// SFDITEM_FIELD__SPIMSS_I2S_CTRL_I2S_LJ +// +// + + +// --------------------------------- Peripheral View: SPIMSS ------------------------------------ +// SVD Line: 8507 + +// SPIMSS +// SPIMSS +// SFDITEM_REG__SPIMSS_DATA16 +// SFDITEM_REG__SPIMSS_DATA8 +// SFDITEM_REG__SPIMSS_CTRL +// SFDITEM_REG__SPIMSS_STATUS +// SFDITEM_REG__SPIMSS_MOD +// SFDITEM_REG__SPIMSS_BRG +// SFDITEM_REG__SPIMSS_DMA +// SFDITEM_REG__SPIMSS_I2S_CTRL +// +// + + +// ----------------------------- Register Item Address: TMR0_CNT -------------------------------- +// SVD Line: 9355 + +unsigned int TMR0_CNT __AT (0x40010000); + + + +// --------------------------------- Register Item: TMR0_CNT ------------------------------------ +// SVD Line: 9355 + +// SFDITEM_REG__TMR0_CNT +// CNT +// [Bits 31..0] RW (@ 0x40010000) Count. This register stores the current timer count. +// +// ( (unsigned int)((TMR0_CNT >> 0) & 0xFFFFFFFF), ((TMR0_CNT = (TMR0_CNT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: TMR0_CMP -------------------------------- +// SVD Line: 9361 + +unsigned int TMR0_CMP __AT (0x40010004); + + + +// --------------------------------- Register Item: TMR0_CMP ------------------------------------ +// SVD Line: 9361 + +// SFDITEM_REG__TMR0_CMP +// CMP +// [Bits 31..0] RW (@ 0x40010004) Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. +// +// ( (unsigned int)((TMR0_CMP >> 0) & 0xFFFFFFFF), ((TMR0_CMP = (TMR0_CMP & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: TMR0_PWM -------------------------------- +// SVD Line: 9367 + +unsigned int TMR0_PWM __AT (0x40010008); + + + +// --------------------------------- Register Item: TMR0_PWM ------------------------------------ +// SVD Line: 9367 + +// SFDITEM_REG__TMR0_PWM +// PWM +// [Bits 31..0] RW (@ 0x40010008) PWM. This register stores the value that is compared to the current timer count. +// +// ( (unsigned int)((TMR0_PWM >> 0) & 0xFFFFFFFF), ((TMR0_PWM = (TMR0_PWM & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register Item Address: TMR0_INTR -------------------------------- +// SVD Line: 9372 + +unsigned int TMR0_INTR __AT (0x4001000C); + + + +// ------------------------------ Field Item: TMR0_INTR_IRQ_CLR --------------------------------- +// SVD Line: 9378 + +// SFDITEM_FIELD__TMR0_INTR_IRQ_CLR +// IRQ_CLR +// +// [Bit 0] RW (@ 0x4001000C) Clear Interrupt. +// +// ( (unsigned int) TMR0_INTR ) +// IRQ_CLR +// +// +// + + +// -------------------------------- Register RTree: TMR0_INTR ----------------------------------- +// SVD Line: 9372 + +// SFDITEM_REG__TMR0_INTR +// INTR +// +// [Bits 31..0] RW (@ 0x4001000C) Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. +// ( (unsigned int)((TMR0_INTR >> 0) & 0xFFFFFFFF), ((TMR0_INTR = (TMR0_INTR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) +// SFDITEM_FIELD__TMR0_INTR_IRQ_CLR +// +// + + +// ----------------------------- Register Item Address: TMR0_CN --------------------------------- +// SVD Line: 9386 + +unsigned int TMR0_CN __AT (0x40010010); + + + +// -------------------------------- Field Item: TMR0_CN_TMODE ----------------------------------- +// SVD Line: 9391 + +// SFDITEM_FIELD__TMR0_CN_TMODE +// TMODE +// +// [Bits 2..0] RW (@ 0x40010010) \nTimer Mode.\n0 : oneShot = One Shot Mode.\n1 : continuous = Continuous Mode.\n2 : counter = Counter Mode.\n3 : pwm = PWM Mode.\n4 : capture = Capture Mode.\n5 : compare = Compare Mode.\n6 : gated = Gated Mode.\n7 : captureCompare = Capture/Compare Mode. +// +// ( (unsigned int) TMR0_CN ) +// TMODE +// <0=> 0: oneShot = One Shot Mode. +// <1=> 1: continuous = Continuous Mode. +// <2=> 2: counter = Counter Mode. +// <3=> 3: pwm = PWM Mode. +// <4=> 4: capture = Capture Mode. +// <5=> 5: compare = Compare Mode. +// <6=> 6: gated = Gated Mode. +// <7=> 7: captureCompare = Capture/Compare Mode. +// +// +// + + +// -------------------------------- Field Item: TMR0_CN_PRES ------------------------------------ +// SVD Line: 9439 + +// SFDITEM_FIELD__TMR0_CN_PRES +// PRES +// +// [Bits 5..3] RW (@ 0x40010010) \nPrescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].\n0 : div1 = Divide by 1.\n1 : div2 = Divide by 2.\n2 : div4 = Divide by 4.\n3 : div8 = Divide by 8.\n4 : div16 = Divide by 16.\n5 : div32 = Divide by 32.\n6 : div64 = Divide by 64.\n7 : div128 = Divide by 128. +// +// ( (unsigned int) TMR0_CN ) +// PRES +// <0=> 0: div1 = Divide by 1. +// <1=> 1: div2 = Divide by 2. +// <2=> 2: div4 = Divide by 4. +// <3=> 3: div8 = Divide by 8. +// <4=> 4: div16 = Divide by 16. +// <5=> 5: div32 = Divide by 32. +// <6=> 6: div64 = Divide by 64. +// <7=> 7: div128 = Divide by 128. +// +// +// + + +// -------------------------------- Field Item: TMR0_CN_TPOL ------------------------------------ +// SVD Line: 9487 + +// SFDITEM_FIELD__TMR0_CN_TPOL +// TPOL +// +// [Bit 6] RW (@ 0x40010010) \nTimer input/output polarity bit.\n0 : activeHi = Active High.\n1 : activeLo = Active Low. +// +// ( (unsigned int) TMR0_CN ) +// TPOL +// <0=> 0: activeHi = Active High. +// <1=> 1: activeLo = Active Low. +// +// +// + + +// --------------------------------- Field Item: TMR0_CN_TEN ------------------------------------ +// SVD Line: 9505 + +// SFDITEM_FIELD__TMR0_CN_TEN +// TEN +// +// [Bit 7] RW (@ 0x40010010) \nTimer Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR0_CN ) +// TEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Field Item: TMR0_CN_PRES3 ----------------------------------- +// SVD Line: 9523 + +// SFDITEM_FIELD__TMR0_CN_PRES3 +// PRES3 +// +// [Bit 8] RW (@ 0x40010010) MSB of prescaler value. +// +// ( (unsigned int) TMR0_CN ) +// PRES3 +// +// +// + + +// ------------------------------- Field Item: TMR0_CN_PWMSYNC ---------------------------------- +// SVD Line: 9529 + +// SFDITEM_FIELD__TMR0_CN_PWMSYNC +// PWMSYNC +// +// [Bit 9] RW (@ 0x40010010) \nTimer PWM Synchronization Mode Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR0_CN ) +// PWMSYNC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR0_CN_NOLHPOL ---------------------------------- +// SVD Line: 9547 + +// SFDITEM_FIELD__TMR0_CN_NOLHPOL +// NOLHPOL +// +// [Bit 10] RW (@ 0x40010010) \nTimer PWM output 0A polarity bit.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR0_CN ) +// NOLHPOL +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR0_CN_NOLLPOL ---------------------------------- +// SVD Line: 9565 + +// SFDITEM_FIELD__TMR0_CN_NOLLPOL +// NOLLPOL +// +// [Bit 11] RW (@ 0x40010010) \nTimer PWM output 0A' polarity bit.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR0_CN ) +// NOLLPOL +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR0_CN_PWMCKBD ---------------------------------- +// SVD Line: 9583 + +// SFDITEM_FIELD__TMR0_CN_PWMCKBD +// PWMCKBD +// +// [Bit 12] RW (@ 0x40010010) \nTimer PWM output 0A Mode Disable.\n0 : en = Enable.\n1 : dis = Disable. +// +// ( (unsigned int) TMR0_CN ) +// PWMCKBD +// <0=> 0: en = Enable. +// <1=> 1: dis = Disable. +// +// +// + + +// --------------------------------- Register RTree: TMR0_CN ------------------------------------ +// SVD Line: 9386 + +// SFDITEM_REG__TMR0_CN +// CN +// +// [Bits 31..0] RW (@ 0x40010010) Timer Control Register. +// ( (unsigned int)((TMR0_CN >> 0) & 0xFFFFFFFF), ((TMR0_CN = (TMR0_CN & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) +// SFDITEM_FIELD__TMR0_CN_TMODE +// SFDITEM_FIELD__TMR0_CN_PRES +// SFDITEM_FIELD__TMR0_CN_TPOL +// SFDITEM_FIELD__TMR0_CN_TEN +// SFDITEM_FIELD__TMR0_CN_PRES3 +// SFDITEM_FIELD__TMR0_CN_PWMSYNC +// SFDITEM_FIELD__TMR0_CN_NOLHPOL +// SFDITEM_FIELD__TMR0_CN_NOLLPOL +// SFDITEM_FIELD__TMR0_CN_PWMCKBD +// +// + + +// --------------------------- Register Item Address: TMR0_NOLCMP ------------------------------- +// SVD Line: 9603 + +unsigned int TMR0_NOLCMP __AT (0x40010014); + + + +// ----------------------------- Field Item: TMR0_NOLCMP_NOLLCMP -------------------------------- +// SVD Line: 9608 + +// SFDITEM_FIELD__TMR0_NOLCMP_NOLLCMP +// NOLLCMP +// +// [Bits 7..0] RW (@ 0x40010014) Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. +// +// ( (unsigned char)((TMR0_NOLCMP >> 0) & 0xFF), ((TMR0_NOLCMP = (TMR0_NOLCMP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Field Item: TMR0_NOLCMP_NOLHCMP -------------------------------- +// SVD Line: 9614 + +// SFDITEM_FIELD__TMR0_NOLCMP_NOLHCMP +// NOLHCMP +// +// [Bits 15..8] RW (@ 0x40010014) Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. +// +// ( (unsigned char)((TMR0_NOLCMP >> 8) & 0xFF), ((TMR0_NOLCMP = (TMR0_NOLCMP & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: TMR0_NOLCMP ---------------------------------- +// SVD Line: 9603 + +// SFDITEM_REG__TMR0_NOLCMP +// NOLCMP +// +// [Bits 31..0] RW (@ 0x40010014) Timer Non-Overlapping Compare Register. +// ( (unsigned int)((TMR0_NOLCMP >> 0) & 0xFFFFFFFF), ((TMR0_NOLCMP = (TMR0_NOLCMP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__TMR0_NOLCMP_NOLLCMP +// SFDITEM_FIELD__TMR0_NOLCMP_NOLHCMP +// +// + + +// ---------------------------------- Peripheral View: TMR0 ------------------------------------- +// SVD Line: 9339 + +// TMR0 +// TMR0 +// SFDITEM_REG__TMR0_CNT +// SFDITEM_REG__TMR0_CMP +// SFDITEM_REG__TMR0_PWM +// SFDITEM_REG__TMR0_INTR +// SFDITEM_REG__TMR0_CN +// SFDITEM_REG__TMR0_NOLCMP +// +// + + +// ----------------------------- Register Item Address: TMR1_CNT -------------------------------- +// SVD Line: 9355 + +unsigned int TMR1_CNT __AT (0x40011000); + + + +// --------------------------------- Register Item: TMR1_CNT ------------------------------------ +// SVD Line: 9355 + +// SFDITEM_REG__TMR1_CNT +// CNT +// [Bits 31..0] RW (@ 0x40011000) Count. This register stores the current timer count. +// +// ( (unsigned int)((TMR1_CNT >> 0) & 0xFFFFFFFF), ((TMR1_CNT = (TMR1_CNT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: TMR1_CMP -------------------------------- +// SVD Line: 9361 + +unsigned int TMR1_CMP __AT (0x40011004); + + + +// --------------------------------- Register Item: TMR1_CMP ------------------------------------ +// SVD Line: 9361 + +// SFDITEM_REG__TMR1_CMP +// CMP +// [Bits 31..0] RW (@ 0x40011004) Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. +// +// ( (unsigned int)((TMR1_CMP >> 0) & 0xFFFFFFFF), ((TMR1_CMP = (TMR1_CMP & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: TMR1_PWM -------------------------------- +// SVD Line: 9367 + +unsigned int TMR1_PWM __AT (0x40011008); + + + +// --------------------------------- Register Item: TMR1_PWM ------------------------------------ +// SVD Line: 9367 + +// SFDITEM_REG__TMR1_PWM +// PWM +// [Bits 31..0] RW (@ 0x40011008) PWM. This register stores the value that is compared to the current timer count. +// +// ( (unsigned int)((TMR1_PWM >> 0) & 0xFFFFFFFF), ((TMR1_PWM = (TMR1_PWM & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register Item Address: TMR1_INTR -------------------------------- +// SVD Line: 9372 + +unsigned int TMR1_INTR __AT (0x4001100C); + + + +// ------------------------------ Field Item: TMR1_INTR_IRQ_CLR --------------------------------- +// SVD Line: 9378 + +// SFDITEM_FIELD__TMR1_INTR_IRQ_CLR +// IRQ_CLR +// +// [Bit 0] RW (@ 0x4001100C) Clear Interrupt. +// +// ( (unsigned int) TMR1_INTR ) +// IRQ_CLR +// +// +// + + +// -------------------------------- Register RTree: TMR1_INTR ----------------------------------- +// SVD Line: 9372 + +// SFDITEM_REG__TMR1_INTR +// INTR +// +// [Bits 31..0] RW (@ 0x4001100C) Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. +// ( (unsigned int)((TMR1_INTR >> 0) & 0xFFFFFFFF), ((TMR1_INTR = (TMR1_INTR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) +// SFDITEM_FIELD__TMR1_INTR_IRQ_CLR +// +// + + +// ----------------------------- Register Item Address: TMR1_CN --------------------------------- +// SVD Line: 9386 + +unsigned int TMR1_CN __AT (0x40011010); + + + +// -------------------------------- Field Item: TMR1_CN_TMODE ----------------------------------- +// SVD Line: 9391 + +// SFDITEM_FIELD__TMR1_CN_TMODE +// TMODE +// +// [Bits 2..0] RW (@ 0x40011010) \nTimer Mode.\n0 : oneShot = One Shot Mode.\n1 : continuous = Continuous Mode.\n2 : counter = Counter Mode.\n3 : pwm = PWM Mode.\n4 : capture = Capture Mode.\n5 : compare = Compare Mode.\n6 : gated = Gated Mode.\n7 : captureCompare = Capture/Compare Mode. +// +// ( (unsigned int) TMR1_CN ) +// TMODE +// <0=> 0: oneShot = One Shot Mode. +// <1=> 1: continuous = Continuous Mode. +// <2=> 2: counter = Counter Mode. +// <3=> 3: pwm = PWM Mode. +// <4=> 4: capture = Capture Mode. +// <5=> 5: compare = Compare Mode. +// <6=> 6: gated = Gated Mode. +// <7=> 7: captureCompare = Capture/Compare Mode. +// +// +// + + +// -------------------------------- Field Item: TMR1_CN_PRES ------------------------------------ +// SVD Line: 9439 + +// SFDITEM_FIELD__TMR1_CN_PRES +// PRES +// +// [Bits 5..3] RW (@ 0x40011010) \nPrescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].\n0 : div1 = Divide by 1.\n1 : div2 = Divide by 2.\n2 : div4 = Divide by 4.\n3 : div8 = Divide by 8.\n4 : div16 = Divide by 16.\n5 : div32 = Divide by 32.\n6 : div64 = Divide by 64.\n7 : div128 = Divide by 128. +// +// ( (unsigned int) TMR1_CN ) +// PRES +// <0=> 0: div1 = Divide by 1. +// <1=> 1: div2 = Divide by 2. +// <2=> 2: div4 = Divide by 4. +// <3=> 3: div8 = Divide by 8. +// <4=> 4: div16 = Divide by 16. +// <5=> 5: div32 = Divide by 32. +// <6=> 6: div64 = Divide by 64. +// <7=> 7: div128 = Divide by 128. +// +// +// + + +// -------------------------------- Field Item: TMR1_CN_TPOL ------------------------------------ +// SVD Line: 9487 + +// SFDITEM_FIELD__TMR1_CN_TPOL +// TPOL +// +// [Bit 6] RW (@ 0x40011010) \nTimer input/output polarity bit.\n0 : activeHi = Active High.\n1 : activeLo = Active Low. +// +// ( (unsigned int) TMR1_CN ) +// TPOL +// <0=> 0: activeHi = Active High. +// <1=> 1: activeLo = Active Low. +// +// +// + + +// --------------------------------- Field Item: TMR1_CN_TEN ------------------------------------ +// SVD Line: 9505 + +// SFDITEM_FIELD__TMR1_CN_TEN +// TEN +// +// [Bit 7] RW (@ 0x40011010) \nTimer Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR1_CN ) +// TEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Field Item: TMR1_CN_PRES3 ----------------------------------- +// SVD Line: 9523 + +// SFDITEM_FIELD__TMR1_CN_PRES3 +// PRES3 +// +// [Bit 8] RW (@ 0x40011010) MSB of prescaler value. +// +// ( (unsigned int) TMR1_CN ) +// PRES3 +// +// +// + + +// ------------------------------- Field Item: TMR1_CN_PWMSYNC ---------------------------------- +// SVD Line: 9529 + +// SFDITEM_FIELD__TMR1_CN_PWMSYNC +// PWMSYNC +// +// [Bit 9] RW (@ 0x40011010) \nTimer PWM Synchronization Mode Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR1_CN ) +// PWMSYNC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR1_CN_NOLHPOL ---------------------------------- +// SVD Line: 9547 + +// SFDITEM_FIELD__TMR1_CN_NOLHPOL +// NOLHPOL +// +// [Bit 10] RW (@ 0x40011010) \nTimer PWM output 0A polarity bit.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR1_CN ) +// NOLHPOL +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR1_CN_NOLLPOL ---------------------------------- +// SVD Line: 9565 + +// SFDITEM_FIELD__TMR1_CN_NOLLPOL +// NOLLPOL +// +// [Bit 11] RW (@ 0x40011010) \nTimer PWM output 0A' polarity bit.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR1_CN ) +// NOLLPOL +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR1_CN_PWMCKBD ---------------------------------- +// SVD Line: 9583 + +// SFDITEM_FIELD__TMR1_CN_PWMCKBD +// PWMCKBD +// +// [Bit 12] RW (@ 0x40011010) \nTimer PWM output 0A Mode Disable.\n0 : en = Enable.\n1 : dis = Disable. +// +// ( (unsigned int) TMR1_CN ) +// PWMCKBD +// <0=> 0: en = Enable. +// <1=> 1: dis = Disable. +// +// +// + + +// --------------------------------- Register RTree: TMR1_CN ------------------------------------ +// SVD Line: 9386 + +// SFDITEM_REG__TMR1_CN +// CN +// +// [Bits 31..0] RW (@ 0x40011010) Timer Control Register. +// ( (unsigned int)((TMR1_CN >> 0) & 0xFFFFFFFF), ((TMR1_CN = (TMR1_CN & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) +// SFDITEM_FIELD__TMR1_CN_TMODE +// SFDITEM_FIELD__TMR1_CN_PRES +// SFDITEM_FIELD__TMR1_CN_TPOL +// SFDITEM_FIELD__TMR1_CN_TEN +// SFDITEM_FIELD__TMR1_CN_PRES3 +// SFDITEM_FIELD__TMR1_CN_PWMSYNC +// SFDITEM_FIELD__TMR1_CN_NOLHPOL +// SFDITEM_FIELD__TMR1_CN_NOLLPOL +// SFDITEM_FIELD__TMR1_CN_PWMCKBD +// +// + + +// --------------------------- Register Item Address: TMR1_NOLCMP ------------------------------- +// SVD Line: 9603 + +unsigned int TMR1_NOLCMP __AT (0x40011014); + + + +// ----------------------------- Field Item: TMR1_NOLCMP_NOLLCMP -------------------------------- +// SVD Line: 9608 + +// SFDITEM_FIELD__TMR1_NOLCMP_NOLLCMP +// NOLLCMP +// +// [Bits 7..0] RW (@ 0x40011014) Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. +// +// ( (unsigned char)((TMR1_NOLCMP >> 0) & 0xFF), ((TMR1_NOLCMP = (TMR1_NOLCMP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Field Item: TMR1_NOLCMP_NOLHCMP -------------------------------- +// SVD Line: 9614 + +// SFDITEM_FIELD__TMR1_NOLCMP_NOLHCMP +// NOLHCMP +// +// [Bits 15..8] RW (@ 0x40011014) Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. +// +// ( (unsigned char)((TMR1_NOLCMP >> 8) & 0xFF), ((TMR1_NOLCMP = (TMR1_NOLCMP & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: TMR1_NOLCMP ---------------------------------- +// SVD Line: 9603 + +// SFDITEM_REG__TMR1_NOLCMP +// NOLCMP +// +// [Bits 31..0] RW (@ 0x40011014) Timer Non-Overlapping Compare Register. +// ( (unsigned int)((TMR1_NOLCMP >> 0) & 0xFFFFFFFF), ((TMR1_NOLCMP = (TMR1_NOLCMP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__TMR1_NOLCMP_NOLLCMP +// SFDITEM_FIELD__TMR1_NOLCMP_NOLHCMP +// +// + + +// ---------------------------------- Peripheral View: TMR1 ------------------------------------- +// SVD Line: 9625 + +// TMR1 +// TMR1 +// SFDITEM_REG__TMR1_CNT +// SFDITEM_REG__TMR1_CMP +// SFDITEM_REG__TMR1_PWM +// SFDITEM_REG__TMR1_INTR +// SFDITEM_REG__TMR1_CN +// SFDITEM_REG__TMR1_NOLCMP +// +// + + +// ----------------------------- Register Item Address: TMR2_CNT -------------------------------- +// SVD Line: 9355 + +unsigned int TMR2_CNT __AT (0x40012000); + + + +// --------------------------------- Register Item: TMR2_CNT ------------------------------------ +// SVD Line: 9355 + +// SFDITEM_REG__TMR2_CNT +// CNT +// [Bits 31..0] RW (@ 0x40012000) Count. This register stores the current timer count. +// +// ( (unsigned int)((TMR2_CNT >> 0) & 0xFFFFFFFF), ((TMR2_CNT = (TMR2_CNT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: TMR2_CMP -------------------------------- +// SVD Line: 9361 + +unsigned int TMR2_CMP __AT (0x40012004); + + + +// --------------------------------- Register Item: TMR2_CMP ------------------------------------ +// SVD Line: 9361 + +// SFDITEM_REG__TMR2_CMP +// CMP +// [Bits 31..0] RW (@ 0x40012004) Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. +// +// ( (unsigned int)((TMR2_CMP >> 0) & 0xFFFFFFFF), ((TMR2_CMP = (TMR2_CMP & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Register Item Address: TMR2_PWM -------------------------------- +// SVD Line: 9367 + +unsigned int TMR2_PWM __AT (0x40012008); + + + +// --------------------------------- Register Item: TMR2_PWM ------------------------------------ +// SVD Line: 9367 + +// SFDITEM_REG__TMR2_PWM +// PWM +// [Bits 31..0] RW (@ 0x40012008) PWM. This register stores the value that is compared to the current timer count. +// +// ( (unsigned int)((TMR2_PWM >> 0) & 0xFFFFFFFF), ((TMR2_PWM = (TMR2_PWM & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) )) +// +// +// + + +// ---------------------------- Register Item Address: TMR2_INTR -------------------------------- +// SVD Line: 9372 + +unsigned int TMR2_INTR __AT (0x4001200C); + + + +// ------------------------------ Field Item: TMR2_INTR_IRQ_CLR --------------------------------- +// SVD Line: 9378 + +// SFDITEM_FIELD__TMR2_INTR_IRQ_CLR +// IRQ_CLR +// +// [Bit 0] RW (@ 0x4001200C) Clear Interrupt. +// +// ( (unsigned int) TMR2_INTR ) +// IRQ_CLR +// +// +// + + +// -------------------------------- Register RTree: TMR2_INTR ----------------------------------- +// SVD Line: 9372 + +// SFDITEM_REG__TMR2_INTR +// INTR +// +// [Bits 31..0] RW (@ 0x4001200C) Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. +// ( (unsigned int)((TMR2_INTR >> 0) & 0xFFFFFFFF), ((TMR2_INTR = (TMR2_INTR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) )) +// SFDITEM_FIELD__TMR2_INTR_IRQ_CLR +// +// + + +// ----------------------------- Register Item Address: TMR2_CN --------------------------------- +// SVD Line: 9386 + +unsigned int TMR2_CN __AT (0x40012010); + + + +// -------------------------------- Field Item: TMR2_CN_TMODE ----------------------------------- +// SVD Line: 9391 + +// SFDITEM_FIELD__TMR2_CN_TMODE +// TMODE +// +// [Bits 2..0] RW (@ 0x40012010) \nTimer Mode.\n0 : oneShot = One Shot Mode.\n1 : continuous = Continuous Mode.\n2 : counter = Counter Mode.\n3 : pwm = PWM Mode.\n4 : capture = Capture Mode.\n5 : compare = Compare Mode.\n6 : gated = Gated Mode.\n7 : captureCompare = Capture/Compare Mode. +// +// ( (unsigned int) TMR2_CN ) +// TMODE +// <0=> 0: oneShot = One Shot Mode. +// <1=> 1: continuous = Continuous Mode. +// <2=> 2: counter = Counter Mode. +// <3=> 3: pwm = PWM Mode. +// <4=> 4: capture = Capture Mode. +// <5=> 5: compare = Compare Mode. +// <6=> 6: gated = Gated Mode. +// <7=> 7: captureCompare = Capture/Compare Mode. +// +// +// + + +// -------------------------------- Field Item: TMR2_CN_PRES ------------------------------------ +// SVD Line: 9439 + +// SFDITEM_FIELD__TMR2_CN_PRES +// PRES +// +// [Bits 5..3] RW (@ 0x40012010) \nPrescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].\n0 : div1 = Divide by 1.\n1 : div2 = Divide by 2.\n2 : div4 = Divide by 4.\n3 : div8 = Divide by 8.\n4 : div16 = Divide by 16.\n5 : div32 = Divide by 32.\n6 : div64 = Divide by 64.\n7 : div128 = Divide by 128. +// +// ( (unsigned int) TMR2_CN ) +// PRES +// <0=> 0: div1 = Divide by 1. +// <1=> 1: div2 = Divide by 2. +// <2=> 2: div4 = Divide by 4. +// <3=> 3: div8 = Divide by 8. +// <4=> 4: div16 = Divide by 16. +// <5=> 5: div32 = Divide by 32. +// <6=> 6: div64 = Divide by 64. +// <7=> 7: div128 = Divide by 128. +// +// +// + + +// -------------------------------- Field Item: TMR2_CN_TPOL ------------------------------------ +// SVD Line: 9487 + +// SFDITEM_FIELD__TMR2_CN_TPOL +// TPOL +// +// [Bit 6] RW (@ 0x40012010) \nTimer input/output polarity bit.\n0 : activeHi = Active High.\n1 : activeLo = Active Low. +// +// ( (unsigned int) TMR2_CN ) +// TPOL +// <0=> 0: activeHi = Active High. +// <1=> 1: activeLo = Active Low. +// +// +// + + +// --------------------------------- Field Item: TMR2_CN_TEN ------------------------------------ +// SVD Line: 9505 + +// SFDITEM_FIELD__TMR2_CN_TEN +// TEN +// +// [Bit 7] RW (@ 0x40012010) \nTimer Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR2_CN ) +// TEN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// -------------------------------- Field Item: TMR2_CN_PRES3 ----------------------------------- +// SVD Line: 9523 + +// SFDITEM_FIELD__TMR2_CN_PRES3 +// PRES3 +// +// [Bit 8] RW (@ 0x40012010) MSB of prescaler value. +// +// ( (unsigned int) TMR2_CN ) +// PRES3 +// +// +// + + +// ------------------------------- Field Item: TMR2_CN_PWMSYNC ---------------------------------- +// SVD Line: 9529 + +// SFDITEM_FIELD__TMR2_CN_PWMSYNC +// PWMSYNC +// +// [Bit 9] RW (@ 0x40012010) \nTimer PWM Synchronization Mode Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR2_CN ) +// PWMSYNC +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR2_CN_NOLHPOL ---------------------------------- +// SVD Line: 9547 + +// SFDITEM_FIELD__TMR2_CN_NOLHPOL +// NOLHPOL +// +// [Bit 10] RW (@ 0x40012010) \nTimer PWM output 0A polarity bit.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR2_CN ) +// NOLHPOL +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR2_CN_NOLLPOL ---------------------------------- +// SVD Line: 9565 + +// SFDITEM_FIELD__TMR2_CN_NOLLPOL +// NOLLPOL +// +// [Bit 11] RW (@ 0x40012010) \nTimer PWM output 0A' polarity bit.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) TMR2_CN ) +// NOLLPOL +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------- Field Item: TMR2_CN_PWMCKBD ---------------------------------- +// SVD Line: 9583 + +// SFDITEM_FIELD__TMR2_CN_PWMCKBD +// PWMCKBD +// +// [Bit 12] RW (@ 0x40012010) \nTimer PWM output 0A Mode Disable.\n0 : en = Enable.\n1 : dis = Disable. +// +// ( (unsigned int) TMR2_CN ) +// PWMCKBD +// <0=> 0: en = Enable. +// <1=> 1: dis = Disable. +// +// +// + + +// --------------------------------- Register RTree: TMR2_CN ------------------------------------ +// SVD Line: 9386 + +// SFDITEM_REG__TMR2_CN +// CN +// +// [Bits 31..0] RW (@ 0x40012010) Timer Control Register. +// ( (unsigned int)((TMR2_CN >> 0) & 0xFFFFFFFF), ((TMR2_CN = (TMR2_CN & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) )) +// SFDITEM_FIELD__TMR2_CN_TMODE +// SFDITEM_FIELD__TMR2_CN_PRES +// SFDITEM_FIELD__TMR2_CN_TPOL +// SFDITEM_FIELD__TMR2_CN_TEN +// SFDITEM_FIELD__TMR2_CN_PRES3 +// SFDITEM_FIELD__TMR2_CN_PWMSYNC +// SFDITEM_FIELD__TMR2_CN_NOLHPOL +// SFDITEM_FIELD__TMR2_CN_NOLLPOL +// SFDITEM_FIELD__TMR2_CN_PWMCKBD +// +// + + +// --------------------------- Register Item Address: TMR2_NOLCMP ------------------------------- +// SVD Line: 9603 + +unsigned int TMR2_NOLCMP __AT (0x40012014); + + + +// ----------------------------- Field Item: TMR2_NOLCMP_NOLLCMP -------------------------------- +// SVD Line: 9608 + +// SFDITEM_FIELD__TMR2_NOLCMP_NOLLCMP +// NOLLCMP +// +// [Bits 7..0] RW (@ 0x40012014) Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. +// +// ( (unsigned char)((TMR2_NOLCMP >> 0) & 0xFF), ((TMR2_NOLCMP = (TMR2_NOLCMP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Field Item: TMR2_NOLCMP_NOLHCMP -------------------------------- +// SVD Line: 9614 + +// SFDITEM_FIELD__TMR2_NOLCMP_NOLHCMP +// NOLHCMP +// +// [Bits 15..8] RW (@ 0x40012014) Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. +// +// ( (unsigned char)((TMR2_NOLCMP >> 8) & 0xFF), ((TMR2_NOLCMP = (TMR2_NOLCMP & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: TMR2_NOLCMP ---------------------------------- +// SVD Line: 9603 + +// SFDITEM_REG__TMR2_NOLCMP +// NOLCMP +// +// [Bits 31..0] RW (@ 0x40012014) Timer Non-Overlapping Compare Register. +// ( (unsigned int)((TMR2_NOLCMP >> 0) & 0xFFFFFFFF), ((TMR2_NOLCMP = (TMR2_NOLCMP & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) )) +// SFDITEM_FIELD__TMR2_NOLCMP_NOLLCMP +// SFDITEM_FIELD__TMR2_NOLCMP_NOLHCMP +// +// + + +// ---------------------------------- Peripheral View: TMR2 ------------------------------------- +// SVD Line: 9636 + +// TMR2 +// TMR2 +// SFDITEM_REG__TMR2_CNT +// SFDITEM_REG__TMR2_CMP +// SFDITEM_REG__TMR2_PWM +// SFDITEM_REG__TMR2_INTR +// SFDITEM_REG__TMR2_CN +// SFDITEM_REG__TMR2_NOLCMP +// +// + + +// ---------------------------- Register Item Address: UART0_CTRL ------------------------------- +// SVD Line: 9662 + +unsigned int UART0_CTRL __AT (0x40042000); + + + +// ------------------------------ Field Item: UART0_CTRL_ENABLE --------------------------------- +// SVD Line: 9668 + +// SFDITEM_FIELD__UART0_CTRL_ENABLE +// ENABLE +// +// [Bit 0] RW (@ 0x40042000) \nUART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.\n0 : dis = UART disabled. FIFOs are flushed. Clock is gated off for power savings.\n1 : en = UART enabled. +// +// ( (unsigned int) UART0_CTRL ) +// ENABLE +// <0=> 0: dis = UART disabled. FIFOs are flushed. Clock is gated off for power savings. +// <1=> 1: en = UART enabled. +// +// +// + + +// ---------------------------- Field Item: UART0_CTRL_PARITY_EN -------------------------------- +// SVD Line: 9686 + +// SFDITEM_FIELD__UART0_CTRL_PARITY_EN +// PARITY_EN +// +// [Bit 1] RW (@ 0x40042000) \nEnable/disable Parity bit (9th character).\n0 : dis = No Parity\n1 : en = Parity enabled as 9th bit +// +// ( (unsigned int) UART0_CTRL ) +// PARITY_EN +// <0=> 0: dis = No Parity +// <1=> 1: en = Parity enabled as 9th bit +// +// +// + + +// ------------------------------ Field Item: UART0_CTRL_PARITY --------------------------------- +// SVD Line: 9704 + +// SFDITEM_FIELD__UART0_CTRL_PARITY +// PARITY +// +// [Bits 3..2] RW (@ 0x40042000) \nWhen PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1; Space parity = always 0.\n0 : Even = Even parity selected.\n1 : ODD = Odd parity selected.\n2 : MARK = Mark parity selected.\n3 : SPACE = Space parity selected. +// +// ( (unsigned int) UART0_CTRL ) +// PARITY +// <0=> 0: Even = Even parity selected. +// <1=> 1: ODD = Odd parity selected. +// <2=> 2: MARK = Mark parity selected. +// <3=> 3: SPACE = Space parity selected. +// +// +// + + +// ------------------------------ Field Item: UART0_CTRL_PARMD ---------------------------------- +// SVD Line: 9733 + +// SFDITEM_FIELD__UART0_CTRL_PARMD +// PARMD +// +// [Bit 4] RW (@ 0x40042000) \nSelects parity based on 1s or 0s count (when PARITY_EN=1).\n0 : 1 = Parity calculation is based on number of 1s in frame.\n1 : 0 = Parity calculation is based on number of 0s in frame. +// +// ( (unsigned int) UART0_CTRL ) +// PARMD +// <0=> 0: 1 = Parity calculation is based on number of 1s in frame. +// <1=> 1: 0 = Parity calculation is based on number of 0s in frame. +// +// +// + + +// ----------------------------- Field Item: UART0_CTRL_TX_FLUSH -------------------------------- +// SVD Line: 9751 + +// SFDITEM_FIELD__UART0_CTRL_TX_FLUSH +// TX_FLUSH +// +// [Bit 5] RW (@ 0x40042000) Flushes the TX FIFO buffer. +// +// ( (unsigned int) UART0_CTRL ) +// TX_FLUSH +// +// +// + + +// ----------------------------- Field Item: UART0_CTRL_RX_FLUSH -------------------------------- +// SVD Line: 9757 + +// SFDITEM_FIELD__UART0_CTRL_RX_FLUSH +// RX_FLUSH +// +// [Bit 6] RW (@ 0x40042000) Flushes the RX FIFO buffer. +// +// ( (unsigned int) UART0_CTRL ) +// RX_FLUSH +// +// +// + + +// ------------------------------ Field Item: UART0_CTRL_BITACC --------------------------------- +// SVD Line: 9763 + +// SFDITEM_FIELD__UART0_CTRL_BITACC +// BITACC +// +// [Bit 7] RW (@ 0x40042000) \nIf set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.\n0 : FRAME = Frame accuracy.\n1 : BIT = Bit accuracy. +// +// ( (unsigned int) UART0_CTRL ) +// BITACC +// <0=> 0: FRAME = Frame accuracy. +// <1=> 1: BIT = Bit accuracy. +// +// +// + + +// ---------------------------- Field Item: UART0_CTRL_CHAR_SIZE -------------------------------- +// SVD Line: 9781 + +// SFDITEM_FIELD__UART0_CTRL_CHAR_SIZE +// CHAR_SIZE +// +// [Bits 9..8] RW (@ 0x40042000) \nSelects UART character size.\n0 : 5 = 5 bits.\n1 : 6 = 6 bits.\n2 : 7 = 7 bits.\n3 : 8 = 8 bits. +// +// ( (unsigned int) UART0_CTRL ) +// CHAR_SIZE +// <0=> 0: 5 = 5 bits. +// <1=> 1: 6 = 6 bits. +// <2=> 2: 7 = 7 bits. +// <3=> 3: 8 = 8 bits. +// +// +// + + +// ----------------------------- Field Item: UART0_CTRL_STOPBITS -------------------------------- +// SVD Line: 9809 + +// SFDITEM_FIELD__UART0_CTRL_STOPBITS +// STOPBITS +// +// [Bit 10] RW (@ 0x40042000) \nSelects the number of stop bits that will be generated.\n0 : 1 = 1 stop bit.\n1 : 1_5 = 1.5 stop bits. +// +// ( (unsigned int) UART0_CTRL ) +// STOPBITS +// <0=> 0: 1 = 1 stop bit. +// <1=> 1: 1_5 = 1.5 stop bits. +// +// +// + + +// ---------------------------- Field Item: UART0_CTRL_FLOW_CTRL -------------------------------- +// SVD Line: 9827 + +// SFDITEM_FIELD__UART0_CTRL_FLOW_CTRL +// FLOW_CTRL +// +// [Bit 11] RW (@ 0x40042000) \nEnables/disables hardware flow control.\n0 : dis = HW Flow Control disabled\n1 : en = HW Flow Control with RTS/CTS enabled +// +// ( (unsigned int) UART0_CTRL ) +// FLOW_CTRL +// <0=> 0: dis = HW Flow Control disabled +// <1=> 1: en = HW Flow Control with RTS/CTS enabled +// +// +// + + +// ----------------------------- Field Item: UART0_CTRL_FLOW_POL -------------------------------- +// SVD Line: 9845 + +// SFDITEM_FIELD__UART0_CTRL_FLOW_POL +// FLOW_POL +// +// [Bit 12] RW (@ 0x40042000) \nRTS/CTS polarity.\n0 : 0 = RTS/CTS asserted is logic 0.\n1 : 1 = RTS/CTS asserted is logic 1. +// +// ( (unsigned int) UART0_CTRL ) +// FLOW_POL +// <0=> 0: 0 = RTS/CTS asserted is logic 0. +// <1=> 1: 1 = RTS/CTS asserted is logic 1. +// +// +// + + +// ---------------------------- Field Item: UART0_CTRL_NULL_MODEM ------------------------------- +// SVD Line: 9863 + +// SFDITEM_FIELD__UART0_CTRL_NULL_MODEM +// NULL_MODEM +// +// [Bit 13] RW (@ 0x40042000) \nNULL Modem Support (RTS/CTS and TXD/RXD swap).\n0 : DIS = Direct convention.\n1 : EN = Null Modem Mode. +// +// ( (unsigned int) UART0_CTRL ) +// NULL_MODEM +// <0=> 0: DIS = Direct convention. +// <1=> 1: EN = Null Modem Mode. +// +// +// + + +// ------------------------------ Field Item: UART0_CTRL_BREAK ---------------------------------- +// SVD Line: 9881 + +// SFDITEM_FIELD__UART0_CTRL_BREAK +// BREAK +// +// [Bit 14] RW (@ 0x40042000) \nBreak control bit. It causes a break condition to be transmitted to receiving UART.\n0 : DIS = Break characters are not generated.\n1 : EN = Break characters are sent(all the bits are at '0' including start/parity/stop). +// +// ( (unsigned int) UART0_CTRL ) +// BREAK +// <0=> 0: DIS = Break characters are not generated. +// <1=> 1: EN = Break characters are sent(all the bits are at '0' including start/parity/stop). +// +// +// + + +// ------------------------------ Field Item: UART0_CTRL_CLKSEL --------------------------------- +// SVD Line: 9899 + +// SFDITEM_FIELD__UART0_CTRL_CLKSEL +// CLKSEL +// +// [Bit 15] RW (@ 0x40042000) \nBaud Rate Clock Source Select. Selects the baud rate clock.\n0 : SYSTEM = System clock.\n1 : ALTERNATE = Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. +// +// ( (unsigned int) UART0_CTRL ) +// CLKSEL +// <0=> 0: SYSTEM = System clock. +// <1=> 1: ALTERNATE = Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. +// +// +// + + +// ------------------------------ Field Item: UART0_CTRL_RX_TO ---------------------------------- +// SVD Line: 9917 + +// SFDITEM_FIELD__UART0_CTRL_RX_TO +// RX_TO +// +// [Bits 23..16] RW (@ 0x40042000) RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read. +// +// ( (unsigned char)((UART0_CTRL >> 16) & 0xFF), ((UART0_CTRL = (UART0_CTRL & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: UART0_CTRL ----------------------------------- +// SVD Line: 9662 + +// SFDITEM_REG__UART0_CTRL +// CTRL +// +// [Bits 31..0] RW (@ 0x40042000) Control Register. +// ( (unsigned int)((UART0_CTRL >> 0) & 0xFFFFFFFF), ((UART0_CTRL = (UART0_CTRL & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__UART0_CTRL_ENABLE +// SFDITEM_FIELD__UART0_CTRL_PARITY_EN +// SFDITEM_FIELD__UART0_CTRL_PARITY +// SFDITEM_FIELD__UART0_CTRL_PARMD +// SFDITEM_FIELD__UART0_CTRL_TX_FLUSH +// SFDITEM_FIELD__UART0_CTRL_RX_FLUSH +// SFDITEM_FIELD__UART0_CTRL_BITACC +// SFDITEM_FIELD__UART0_CTRL_CHAR_SIZE +// SFDITEM_FIELD__UART0_CTRL_STOPBITS +// SFDITEM_FIELD__UART0_CTRL_FLOW_CTRL +// SFDITEM_FIELD__UART0_CTRL_FLOW_POL +// SFDITEM_FIELD__UART0_CTRL_NULL_MODEM +// SFDITEM_FIELD__UART0_CTRL_BREAK +// SFDITEM_FIELD__UART0_CTRL_CLKSEL +// SFDITEM_FIELD__UART0_CTRL_RX_TO +// +// + + +// ------------------------ Register Item Address: UART0_THRESH_CTRL ---------------------------- +// SVD Line: 9926 + +unsigned int UART0_THRESH_CTRL __AT (0x40042004); + + + +// ---------------------- Field Item: UART0_THRESH_CTRL_RX_FIFO_THRESH -------------------------- +// SVD Line: 9932 + +// SFDITEM_FIELD__UART0_THRESH_CTRL_RX_FIFO_THRESH +// RX_FIFO_THRESH +// +// [Bits 5..0] RW (@ 0x40042004) RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. +// +// ( (unsigned char)((UART0_THRESH_CTRL >> 0) & 0x3F), ((UART0_THRESH_CTRL = (UART0_THRESH_CTRL & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) )) +// +// +// + + +// ---------------------- Field Item: UART0_THRESH_CTRL_TX_FIFO_THRESH -------------------------- +// SVD Line: 9938 + +// SFDITEM_FIELD__UART0_THRESH_CTRL_TX_FIFO_THRESH +// TX_FIFO_THRESH +// +// [Bits 13..8] RW (@ 0x40042004) TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. +// +// ( (unsigned char)((UART0_THRESH_CTRL >> 8) & 0x3F), ((UART0_THRESH_CTRL = (UART0_THRESH_CTRL & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) )) +// +// +// + + +// ---------------------- Field Item: UART0_THRESH_CTRL_RTS_FIFO_THRESH ------------------------- +// SVD Line: 9944 + +// SFDITEM_FIELD__UART0_THRESH_CTRL_RTS_FIFO_THRESH +// RTS_FIFO_THRESH +// +// [Bits 21..16] RW (@ 0x40042004) RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. +// +// ( (unsigned char)((UART0_THRESH_CTRL >> 16) & 0x3F), ((UART0_THRESH_CTRL = (UART0_THRESH_CTRL & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: UART0_THRESH_CTRL ------------------------------- +// SVD Line: 9926 + +// SFDITEM_REG__UART0_THRESH_CTRL +// THRESH_CTRL +// +// [Bits 31..0] RW (@ 0x40042004) Threshold Control register. +// ( (unsigned int)((UART0_THRESH_CTRL >> 0) & 0xFFFFFFFF), ((UART0_THRESH_CTRL = (UART0_THRESH_CTRL & ~(0x3F3F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F3F) << 0 ) ) )) +// SFDITEM_FIELD__UART0_THRESH_CTRL_RX_FIFO_THRESH +// SFDITEM_FIELD__UART0_THRESH_CTRL_TX_FIFO_THRESH +// SFDITEM_FIELD__UART0_THRESH_CTRL_RTS_FIFO_THRESH +// +// + + +// --------------------------- Register Item Address: UART0_STATUS ------------------------------ +// SVD Line: 9952 + +unsigned int UART0_STATUS __AT (0x40042008); + + + +// ---------------------------- Field Item: UART0_STATUS_TX_BUSY -------------------------------- +// SVD Line: 9959 + +// SFDITEM_FIELD__UART0_STATUS_TX_BUSY +// TX_BUSY +// +// [Bit 0] RO (@ 0x40042008) Read-only flag indicating the UART transmit status. +// +// ( (unsigned int) UART0_STATUS ) +// TX_BUSY +// +// +// + + +// ---------------------------- Field Item: UART0_STATUS_RX_BUSY -------------------------------- +// SVD Line: 9966 + +// SFDITEM_FIELD__UART0_STATUS_RX_BUSY +// RX_BUSY +// +// [Bit 1] RO (@ 0x40042008) Read-only flag indicating the UARTreceiver status. +// +// ( (unsigned int) UART0_STATUS ) +// RX_BUSY +// +// +// + + +// ----------------------------- Field Item: UART0_STATUS_PARITY -------------------------------- +// SVD Line: 9973 + +// SFDITEM_FIELD__UART0_STATUS_PARITY +// PARITY +// +// [Bit 2] RO (@ 0x40042008) 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. +// +// ( (unsigned int) UART0_STATUS ) +// PARITY +// +// +// + + +// ----------------------------- Field Item: UART0_STATUS_BREAK --------------------------------- +// SVD Line: 9980 + +// SFDITEM_FIELD__UART0_STATUS_BREAK +// BREAK +// +// [Bit 3] RO (@ 0x40042008) Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). +// +// ( (unsigned int) UART0_STATUS ) +// BREAK +// +// +// + + +// ---------------------------- Field Item: UART0_STATUS_RX_EMPTY ------------------------------- +// SVD Line: 9987 + +// SFDITEM_FIELD__UART0_STATUS_RX_EMPTY +// RX_EMPTY +// +// [Bit 4] RO (@ 0x40042008) Read-only flag indicating the RX FIFO state. +// +// ( (unsigned int) UART0_STATUS ) +// RX_EMPTY +// +// +// + + +// ---------------------------- Field Item: UART0_STATUS_RX_FULL -------------------------------- +// SVD Line: 9994 + +// SFDITEM_FIELD__UART0_STATUS_RX_FULL +// RX_FULL +// +// [Bit 5] RO (@ 0x40042008) Read-only flag indicating the RX FIFO state. +// +// ( (unsigned int) UART0_STATUS ) +// RX_FULL +// +// +// + + +// ---------------------------- Field Item: UART0_STATUS_TX_EMPTY ------------------------------- +// SVD Line: 10001 + +// SFDITEM_FIELD__UART0_STATUS_TX_EMPTY +// TX_EMPTY +// +// [Bit 6] RO (@ 0x40042008) Read-only flag indicating the TX FIFO state. +// +// ( (unsigned int) UART0_STATUS ) +// TX_EMPTY +// +// +// + + +// ---------------------------- Field Item: UART0_STATUS_TX_FULL -------------------------------- +// SVD Line: 10008 + +// SFDITEM_FIELD__UART0_STATUS_TX_FULL +// TX_FULL +// +// [Bit 7] RO (@ 0x40042008) Read-only flag indicating the TX FIFO state. +// +// ( (unsigned int) UART0_STATUS ) +// TX_FULL +// +// +// + + +// -------------------------- Field Item: UART0_STATUS_RX_FIFO_CNT ------------------------------ +// SVD Line: 10015 + +// SFDITEM_FIELD__UART0_STATUS_RX_FIFO_CNT +// RX_FIFO_CNT +// +// [Bits 13..8] RO (@ 0x40042008) Indicates the number of bytes currently in the RX FIFO. +// +// ( (unsigned char)((UART0_STATUS >> 8) & 0x3F) ) +// +// +// + + +// -------------------------- Field Item: UART0_STATUS_TX_FIFO_CNT ------------------------------ +// SVD Line: 10022 + +// SFDITEM_FIELD__UART0_STATUS_TX_FIFO_CNT +// TX_FIFO_CNT +// +// [Bits 21..16] RO (@ 0x40042008) Indicates the number of bytes currently in the TX FIFO. +// +// ( (unsigned char)((UART0_STATUS >> 16) & 0x3F) ) +// +// +// + + +// ----------------------------- Field Item: UART0_STATUS_RX_TO --------------------------------- +// SVD Line: 10029 + +// SFDITEM_FIELD__UART0_STATUS_RX_TO +// RX_TO +// +// [Bit 24] RO (@ 0x40042008) RX Timeout status. +// +// ( (unsigned int) UART0_STATUS ) +// RX_TO +// +// +// + + +// ------------------------------ Register RTree: UART0_STATUS ---------------------------------- +// SVD Line: 9952 + +// SFDITEM_REG__UART0_STATUS +// STATUS +// +// [Bits 31..0] RO (@ 0x40042008) Status Register. +// ( (unsigned int)((UART0_STATUS >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__UART0_STATUS_TX_BUSY +// SFDITEM_FIELD__UART0_STATUS_RX_BUSY +// SFDITEM_FIELD__UART0_STATUS_PARITY +// SFDITEM_FIELD__UART0_STATUS_BREAK +// SFDITEM_FIELD__UART0_STATUS_RX_EMPTY +// SFDITEM_FIELD__UART0_STATUS_RX_FULL +// SFDITEM_FIELD__UART0_STATUS_TX_EMPTY +// SFDITEM_FIELD__UART0_STATUS_TX_FULL +// SFDITEM_FIELD__UART0_STATUS_RX_FIFO_CNT +// SFDITEM_FIELD__UART0_STATUS_TX_FIFO_CNT +// SFDITEM_FIELD__UART0_STATUS_RX_TO +// +// + + +// --------------------------- Register Item Address: UART0_INT_EN ------------------------------ +// SVD Line: 10038 + +unsigned int UART0_INT_EN __AT (0x4004200C); + + + +// ------------------------- Field Item: UART0_INT_EN_RX_FRAME_ERROR ---------------------------- +// SVD Line: 10044 + +// SFDITEM_FIELD__UART0_INT_EN_RX_FRAME_ERROR +// RX_FRAME_ERROR +// +// [Bit 0] RW (@ 0x4004200C) Enable for RX Frame Error Interrupt. +// +// ( (unsigned int) UART0_INT_EN ) +// RX_FRAME_ERROR +// +// +// + + +// ------------------------ Field Item: UART0_INT_EN_RX_PARITY_ERROR ---------------------------- +// SVD Line: 10050 + +// SFDITEM_FIELD__UART0_INT_EN_RX_PARITY_ERROR +// RX_PARITY_ERROR +// +// [Bit 1] RW (@ 0x4004200C) Enable for RX Parity Error interrupt. +// +// ( (unsigned int) UART0_INT_EN ) +// RX_PARITY_ERROR +// +// +// + + +// --------------------------- Field Item: UART0_INT_EN_CTS_CHANGE ------------------------------ +// SVD Line: 10056 + +// SFDITEM_FIELD__UART0_INT_EN_CTS_CHANGE +// CTS_CHANGE +// +// [Bit 2] RW (@ 0x4004200C) Enable for CTS signal change interrupt. +// +// ( (unsigned int) UART0_INT_EN ) +// CTS_CHANGE +// +// +// + + +// --------------------------- Field Item: UART0_INT_EN_RX_OVERRUN ------------------------------ +// SVD Line: 10062 + +// SFDITEM_FIELD__UART0_INT_EN_RX_OVERRUN +// RX_OVERRUN +// +// [Bit 3] RW (@ 0x4004200C) Enable for RX FIFO OVerrun interrupt. +// +// ( (unsigned int) UART0_INT_EN ) +// RX_OVERRUN +// +// +// + + +// ------------------------- Field Item: UART0_INT_EN_RX_FIFO_THRESH ---------------------------- +// SVD Line: 10068 + +// SFDITEM_FIELD__UART0_INT_EN_RX_FIFO_THRESH +// RX_FIFO_THRESH +// +// [Bit 4] RW (@ 0x4004200C) Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. +// +// ( (unsigned int) UART0_INT_EN ) +// RX_FIFO_THRESH +// +// +// + + +// ---------------------- Field Item: UART0_INT_EN_TX_FIFO_ALMOST_EMPTY ------------------------- +// SVD Line: 10074 + +// SFDITEM_FIELD__UART0_INT_EN_TX_FIFO_ALMOST_EMPTY +// TX_FIFO_ALMOST_EMPTY +// +// [Bit 5] RW (@ 0x4004200C) Enable for interrupt when TX FIFO has only one byte remaining. +// +// ( (unsigned int) UART0_INT_EN ) +// TX_FIFO_ALMOST_EMPTY +// +// +// + + +// ------------------------- Field Item: UART0_INT_EN_TX_FIFO_THRESH ---------------------------- +// SVD Line: 10080 + +// SFDITEM_FIELD__UART0_INT_EN_TX_FIFO_THRESH +// TX_FIFO_THRESH +// +// [Bit 6] RW (@ 0x4004200C) Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. +// +// ( (unsigned int) UART0_INT_EN ) +// TX_FIFO_THRESH +// +// +// + + +// ----------------------------- Field Item: UART0_INT_EN_BREAK --------------------------------- +// SVD Line: 10086 + +// SFDITEM_FIELD__UART0_INT_EN_BREAK +// BREAK +// +// [Bit 7] RW (@ 0x4004200C) Enable for received BREAK character interrupt. +// +// ( (unsigned int) UART0_INT_EN ) +// BREAK +// +// +// + + +// --------------------------- Field Item: UART0_INT_EN_RX_TIMEOUT ------------------------------ +// SVD Line: 10092 + +// SFDITEM_FIELD__UART0_INT_EN_RX_TIMEOUT +// RX_TIMEOUT +// +// [Bit 8] RW (@ 0x4004200C) Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). +// +// ( (unsigned int) UART0_INT_EN ) +// RX_TIMEOUT +// +// +// + + +// --------------------------- Field Item: UART0_INT_EN_LAST_BREAK ------------------------------ +// SVD Line: 10098 + +// SFDITEM_FIELD__UART0_INT_EN_LAST_BREAK +// LAST_BREAK +// +// [Bit 9] RW (@ 0x4004200C) Enable for Last break character interrupt. +// +// ( (unsigned int) UART0_INT_EN ) +// LAST_BREAK +// +// +// + + +// ------------------------------ Register RTree: UART0_INT_EN ---------------------------------- +// SVD Line: 10038 + +// SFDITEM_REG__UART0_INT_EN +// INT_EN +// +// [Bits 31..0] RW (@ 0x4004200C) Interrupt Enable Register. +// ( (unsigned int)((UART0_INT_EN >> 0) & 0xFFFFFFFF), ((UART0_INT_EN = (UART0_INT_EN & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) +// SFDITEM_FIELD__UART0_INT_EN_RX_FRAME_ERROR +// SFDITEM_FIELD__UART0_INT_EN_RX_PARITY_ERROR +// SFDITEM_FIELD__UART0_INT_EN_CTS_CHANGE +// SFDITEM_FIELD__UART0_INT_EN_RX_OVERRUN +// SFDITEM_FIELD__UART0_INT_EN_RX_FIFO_THRESH +// SFDITEM_FIELD__UART0_INT_EN_TX_FIFO_ALMOST_EMPTY +// SFDITEM_FIELD__UART0_INT_EN_TX_FIFO_THRESH +// SFDITEM_FIELD__UART0_INT_EN_BREAK +// SFDITEM_FIELD__UART0_INT_EN_RX_TIMEOUT +// SFDITEM_FIELD__UART0_INT_EN_LAST_BREAK +// +// + + +// --------------------------- Register Item Address: UART0_INT_FL ------------------------------ +// SVD Line: 10106 + +unsigned int UART0_INT_FL __AT (0x40042010); + + + +// ------------------------- Field Item: UART0_INT_FL_RX_FRAME_ERROR ---------------------------- +// SVD Line: 10113 + +// SFDITEM_FIELD__UART0_INT_FL_RX_FRAME_ERROR +// RX_FRAME_ERROR +// +// [Bit 0] RW (@ 0x40042010) FLAG for RX Frame Error Interrupt. +// +// ( (unsigned int) UART0_INT_FL ) +// RX_FRAME_ERROR +// +// +// + + +// ------------------------ Field Item: UART0_INT_FL_RX_PARITY_ERROR ---------------------------- +// SVD Line: 10119 + +// SFDITEM_FIELD__UART0_INT_FL_RX_PARITY_ERROR +// RX_PARITY_ERROR +// +// [Bit 1] RW (@ 0x40042010) FLAG for RX Parity Error interrupt. +// +// ( (unsigned int) UART0_INT_FL ) +// RX_PARITY_ERROR +// +// +// + + +// --------------------------- Field Item: UART0_INT_FL_CTS_CHANGE ------------------------------ +// SVD Line: 10125 + +// SFDITEM_FIELD__UART0_INT_FL_CTS_CHANGE +// CTS_CHANGE +// +// [Bit 2] RW (@ 0x40042010) FLAG for CTS signal change interrupt. +// +// ( (unsigned int) UART0_INT_FL ) +// CTS_CHANGE +// +// +// + + +// --------------------------- Field Item: UART0_INT_FL_RX_OVERRUN ------------------------------ +// SVD Line: 10131 + +// SFDITEM_FIELD__UART0_INT_FL_RX_OVERRUN +// RX_OVERRUN +// +// [Bit 3] RW (@ 0x40042010) FLAG for RX FIFO Overrun interrupt. +// +// ( (unsigned int) UART0_INT_FL ) +// RX_OVERRUN +// +// +// + + +// ------------------------- Field Item: UART0_INT_FL_RX_FIFO_THRESH ---------------------------- +// SVD Line: 10137 + +// SFDITEM_FIELD__UART0_INT_FL_RX_FIFO_THRESH +// RX_FIFO_THRESH +// +// [Bit 4] RW (@ 0x40042010) FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. +// +// ( (unsigned int) UART0_INT_FL ) +// RX_FIFO_THRESH +// +// +// + + +// ---------------------- Field Item: UART0_INT_FL_TX_FIFO_ALMOST_EMPTY ------------------------- +// SVD Line: 10143 + +// SFDITEM_FIELD__UART0_INT_FL_TX_FIFO_ALMOST_EMPTY +// TX_FIFO_ALMOST_EMPTY +// +// [Bit 5] RW (@ 0x40042010) FLAG for interrupt when TX FIFO has only one byte remaining. +// +// ( (unsigned int) UART0_INT_FL ) +// TX_FIFO_ALMOST_EMPTY +// +// +// + + +// ------------------------- Field Item: UART0_INT_FL_TX_FIFO_THRESH ---------------------------- +// SVD Line: 10149 + +// SFDITEM_FIELD__UART0_INT_FL_TX_FIFO_THRESH +// TX_FIFO_THRESH +// +// [Bit 6] RW (@ 0x40042010) FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. +// +// ( (unsigned int) UART0_INT_FL ) +// TX_FIFO_THRESH +// +// +// + + +// ----------------------------- Field Item: UART0_INT_FL_BREAK --------------------------------- +// SVD Line: 10155 + +// SFDITEM_FIELD__UART0_INT_FL_BREAK +// BREAK +// +// [Bit 7] RW (@ 0x40042010) FLAG for received BREAK character interrupt. +// +// ( (unsigned int) UART0_INT_FL ) +// BREAK +// +// +// + + +// --------------------------- Field Item: UART0_INT_FL_RX_TIMEOUT ------------------------------ +// SVD Line: 10161 + +// SFDITEM_FIELD__UART0_INT_FL_RX_TIMEOUT +// RX_TIMEOUT +// +// [Bit 8] RW (@ 0x40042010) FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). +// +// ( (unsigned int) UART0_INT_FL ) +// RX_TIMEOUT +// +// +// + + +// --------------------------- Field Item: UART0_INT_FL_LAST_BREAK ------------------------------ +// SVD Line: 10167 + +// SFDITEM_FIELD__UART0_INT_FL_LAST_BREAK +// LAST_BREAK +// +// [Bit 9] RW (@ 0x40042010) FLAG for Last break character interrupt. +// +// ( (unsigned int) UART0_INT_FL ) +// LAST_BREAK +// +// +// + + +// ------------------------------ Register RTree: UART0_INT_FL ---------------------------------- +// SVD Line: 10106 + +// SFDITEM_REG__UART0_INT_FL +// INT_FL +// +// [Bits 31..0] RW (@ 0x40042010) Interrupt Status Flags. +// ( (unsigned int)((UART0_INT_FL >> 0) & 0xFFFFFFFF), ((UART0_INT_FL = (UART0_INT_FL & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) +// SFDITEM_FIELD__UART0_INT_FL_RX_FRAME_ERROR +// SFDITEM_FIELD__UART0_INT_FL_RX_PARITY_ERROR +// SFDITEM_FIELD__UART0_INT_FL_CTS_CHANGE +// SFDITEM_FIELD__UART0_INT_FL_RX_OVERRUN +// SFDITEM_FIELD__UART0_INT_FL_RX_FIFO_THRESH +// SFDITEM_FIELD__UART0_INT_FL_TX_FIFO_ALMOST_EMPTY +// SFDITEM_FIELD__UART0_INT_FL_TX_FIFO_THRESH +// SFDITEM_FIELD__UART0_INT_FL_BREAK +// SFDITEM_FIELD__UART0_INT_FL_RX_TIMEOUT +// SFDITEM_FIELD__UART0_INT_FL_LAST_BREAK +// +// + + +// --------------------------- Register Item Address: UART0_BAUD0 ------------------------------- +// SVD Line: 10175 + +unsigned int UART0_BAUD0 __AT (0x40042014); + + + +// ------------------------------ Field Item: UART0_BAUD0_IBAUD --------------------------------- +// SVD Line: 10181 + +// SFDITEM_FIELD__UART0_BAUD0_IBAUD +// IBAUD +// +// [Bits 11..0] RW (@ 0x40042014) Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). +// +// ( (unsigned short)((UART0_BAUD0 >> 0) & 0xFFF), ((UART0_BAUD0 = (UART0_BAUD0 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Field Item: UART0_BAUD0_FACTOR --------------------------------- +// SVD Line: 10187 + +// SFDITEM_FIELD__UART0_BAUD0_FACTOR +// FACTOR +// +// [Bits 17..16] RW (@ 0x40042014) \nFACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.\n0 : 128 = Baud Factor 128\n1 : 64 = Baud Factor 64\n2 : 32 = Baud Factor 32\n3 : 16 = Baud Factor 16 +// +// ( (unsigned int) UART0_BAUD0 ) +// FACTOR +// <0=> 0: 128 = Baud Factor 128 +// <1=> 1: 64 = Baud Factor 64 +// <2=> 2: 32 = Baud Factor 32 +// <3=> 3: 16 = Baud Factor 16 +// +// +// + + +// ------------------------------- Register RTree: UART0_BAUD0 ---------------------------------- +// SVD Line: 10175 + +// SFDITEM_REG__UART0_BAUD0 +// BAUD0 +// +// [Bits 31..0] RW (@ 0x40042014) Baud rate register. Integer portion. +// ( (unsigned int)((UART0_BAUD0 >> 0) & 0xFFFFFFFF), ((UART0_BAUD0 = (UART0_BAUD0 & ~(0x30FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30FFF) << 0 ) ) )) +// SFDITEM_FIELD__UART0_BAUD0_IBAUD +// SFDITEM_FIELD__UART0_BAUD0_FACTOR +// +// + + +// --------------------------- Register Item Address: UART0_BAUD1 ------------------------------- +// SVD Line: 10217 + +unsigned int UART0_BAUD1 __AT (0x40042018); + + + +// ------------------------------ Field Item: UART0_BAUD1_DBAUD --------------------------------- +// SVD Line: 10223 + +// SFDITEM_FIELD__UART0_BAUD1_DBAUD +// DBAUD +// +// [Bits 11..0] RW (@ 0x40042018) Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128. +// +// ( (unsigned short)((UART0_BAUD1 >> 0) & 0xFFF), ((UART0_BAUD1 = (UART0_BAUD1 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: UART0_BAUD1 ---------------------------------- +// SVD Line: 10217 + +// SFDITEM_REG__UART0_BAUD1 +// BAUD1 +// +// [Bits 31..0] RW (@ 0x40042018) Baud rate register. Decimal Setting. +// ( (unsigned int)((UART0_BAUD1 >> 0) & 0xFFFFFFFF), ((UART0_BAUD1 = (UART0_BAUD1 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) +// SFDITEM_FIELD__UART0_BAUD1_DBAUD +// +// + + +// ---------------------------- Register Item Address: UART0_FIFO ------------------------------- +// SVD Line: 10231 + +unsigned int UART0_FIFO __AT (0x4004201C); + + + +// ------------------------------- Field Item: UART0_FIFO_FIFO ---------------------------------- +// SVD Line: 10237 + +// SFDITEM_FIELD__UART0_FIFO_FIFO +// FIFO +// +// [Bits 7..0] RW (@ 0x4004201C) Load/unload location for TX and RX FIFO buffers. +// +// ( (unsigned char)((UART0_FIFO >> 0) & 0xFF), ((UART0_FIFO = (UART0_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: UART0_FIFO ----------------------------------- +// SVD Line: 10231 + +// SFDITEM_REG__UART0_FIFO +// FIFO +// +// [Bits 31..0] RW (@ 0x4004201C) FIFO Data buffer. +// ( (unsigned int)((UART0_FIFO >> 0) & 0xFFFFFFFF), ((UART0_FIFO = (UART0_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__UART0_FIFO_FIFO +// +// + + +// ---------------------------- Register Item Address: UART0_DMA -------------------------------- +// SVD Line: 10245 + +unsigned int UART0_DMA __AT (0x40042020); + + + +// ----------------------------- Field Item: UART0_DMA_TXDMA_EN --------------------------------- +// SVD Line: 10251 + +// SFDITEM_FIELD__UART0_DMA_TXDMA_EN +// TXDMA_EN +// +// [Bit 0] RW (@ 0x40042020) \nTX DMA channel enable.\n0 : dis = DMA is disabled\n1 : en = DMA is enabled +// +// ( (unsigned int) UART0_DMA ) +// TXDMA_EN +// <0=> 0: dis = DMA is disabled +// <1=> 1: en = DMA is enabled +// +// +// + + +// ----------------------------- Field Item: UART0_DMA_RXDMA_EN --------------------------------- +// SVD Line: 10269 + +// SFDITEM_FIELD__UART0_DMA_RXDMA_EN +// RXDMA_EN +// +// [Bit 1] RW (@ 0x40042020) \nRX DMA channel enable.\n0 : dis = DMA is disabled\n1 : en = DMA is enabled +// +// ( (unsigned int) UART0_DMA ) +// RXDMA_EN +// <0=> 0: dis = DMA is disabled +// <1=> 1: en = DMA is enabled +// +// +// + + +// ---------------------------- Field Item: UART0_DMA_TXDMA_LEVEL ------------------------------- +// SVD Line: 10287 + +// SFDITEM_FIELD__UART0_DMA_TXDMA_LEVEL +// TXDMA_LEVEL +// +// [Bits 13..8] RW (@ 0x40042020) TX threshold for DMA transmission. +// +// ( (unsigned char)((UART0_DMA >> 8) & 0x3F), ((UART0_DMA = (UART0_DMA & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) )) +// +// +// + + +// ---------------------------- Field Item: UART0_DMA_RXDMA_LEVEL ------------------------------- +// SVD Line: 10293 + +// SFDITEM_FIELD__UART0_DMA_RXDMA_LEVEL +// RXDMA_LEVEL +// +// [Bits 21..16] RW (@ 0x40042020) RX threshold for DMA transmission. +// +// ( (unsigned char)((UART0_DMA >> 16) & 0x3F), ((UART0_DMA = (UART0_DMA & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: UART0_DMA ----------------------------------- +// SVD Line: 10245 + +// SFDITEM_REG__UART0_DMA +// DMA +// +// [Bits 31..0] RW (@ 0x40042020) DMA Configuration. +// ( (unsigned int)((UART0_DMA >> 0) & 0xFFFFFFFF), ((UART0_DMA = (UART0_DMA & ~(0x3F3F03UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F03) << 0 ) ) )) +// SFDITEM_FIELD__UART0_DMA_TXDMA_EN +// SFDITEM_FIELD__UART0_DMA_RXDMA_EN +// SFDITEM_FIELD__UART0_DMA_TXDMA_LEVEL +// SFDITEM_FIELD__UART0_DMA_RXDMA_LEVEL +// +// + + +// -------------------------- Register Item Address: UART0_TX_FIFO ------------------------------ +// SVD Line: 10301 + +unsigned int UART0_TX_FIFO __AT (0x40042024); + + + +// ----------------------------- Field Item: UART0_TX_FIFO_DATA --------------------------------- +// SVD Line: 10307 + +// SFDITEM_FIELD__UART0_TX_FIFO_DATA +// DATA +// +// [Bits 6..0] RW (@ 0x40042024) Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned). +// +// ( (unsigned char)((UART0_TX_FIFO >> 0) & 0x7F), ((UART0_TX_FIFO = (UART0_TX_FIFO & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: UART0_TX_FIFO --------------------------------- +// SVD Line: 10301 + +// SFDITEM_REG__UART0_TX_FIFO +// TX_FIFO +// +// [Bits 31..0] RW (@ 0x40042024) Transmit FIFO Status register. +// ( (unsigned int)((UART0_TX_FIFO >> 0) & 0xFFFFFFFF), ((UART0_TX_FIFO = (UART0_TX_FIFO & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) +// SFDITEM_FIELD__UART0_TX_FIFO_DATA +// +// + + +// --------------------------------- Peripheral View: UART0 ------------------------------------- +// SVD Line: 9647 + +// UART0 +// UART0 +// SFDITEM_REG__UART0_CTRL +// SFDITEM_REG__UART0_THRESH_CTRL +// SFDITEM_REG__UART0_STATUS +// SFDITEM_REG__UART0_INT_EN +// SFDITEM_REG__UART0_INT_FL +// SFDITEM_REG__UART0_BAUD0 +// SFDITEM_REG__UART0_BAUD1 +// SFDITEM_REG__UART0_FIFO +// SFDITEM_REG__UART0_DMA +// SFDITEM_REG__UART0_TX_FIFO +// +// + + +// ---------------------------- Register Item Address: UART1_CTRL ------------------------------- +// SVD Line: 9662 + +unsigned int UART1_CTRL __AT (0x40043000); + + + +// ------------------------------ Field Item: UART1_CTRL_ENABLE --------------------------------- +// SVD Line: 9668 + +// SFDITEM_FIELD__UART1_CTRL_ENABLE +// ENABLE +// +// [Bit 0] RW (@ 0x40043000) \nUART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.\n0 : dis = UART disabled. FIFOs are flushed. Clock is gated off for power savings.\n1 : en = UART enabled. +// +// ( (unsigned int) UART1_CTRL ) +// ENABLE +// <0=> 0: dis = UART disabled. FIFOs are flushed. Clock is gated off for power savings. +// <1=> 1: en = UART enabled. +// +// +// + + +// ---------------------------- Field Item: UART1_CTRL_PARITY_EN -------------------------------- +// SVD Line: 9686 + +// SFDITEM_FIELD__UART1_CTRL_PARITY_EN +// PARITY_EN +// +// [Bit 1] RW (@ 0x40043000) \nEnable/disable Parity bit (9th character).\n0 : dis = No Parity\n1 : en = Parity enabled as 9th bit +// +// ( (unsigned int) UART1_CTRL ) +// PARITY_EN +// <0=> 0: dis = No Parity +// <1=> 1: en = Parity enabled as 9th bit +// +// +// + + +// ------------------------------ Field Item: UART1_CTRL_PARITY --------------------------------- +// SVD Line: 9704 + +// SFDITEM_FIELD__UART1_CTRL_PARITY +// PARITY +// +// [Bits 3..2] RW (@ 0x40043000) \nWhen PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1; Space parity = always 0.\n0 : Even = Even parity selected.\n1 : ODD = Odd parity selected.\n2 : MARK = Mark parity selected.\n3 : SPACE = Space parity selected. +// +// ( (unsigned int) UART1_CTRL ) +// PARITY +// <0=> 0: Even = Even parity selected. +// <1=> 1: ODD = Odd parity selected. +// <2=> 2: MARK = Mark parity selected. +// <3=> 3: SPACE = Space parity selected. +// +// +// + + +// ------------------------------ Field Item: UART1_CTRL_PARMD ---------------------------------- +// SVD Line: 9733 + +// SFDITEM_FIELD__UART1_CTRL_PARMD +// PARMD +// +// [Bit 4] RW (@ 0x40043000) \nSelects parity based on 1s or 0s count (when PARITY_EN=1).\n0 : 1 = Parity calculation is based on number of 1s in frame.\n1 : 0 = Parity calculation is based on number of 0s in frame. +// +// ( (unsigned int) UART1_CTRL ) +// PARMD +// <0=> 0: 1 = Parity calculation is based on number of 1s in frame. +// <1=> 1: 0 = Parity calculation is based on number of 0s in frame. +// +// +// + + +// ----------------------------- Field Item: UART1_CTRL_TX_FLUSH -------------------------------- +// SVD Line: 9751 + +// SFDITEM_FIELD__UART1_CTRL_TX_FLUSH +// TX_FLUSH +// +// [Bit 5] RW (@ 0x40043000) Flushes the TX FIFO buffer. +// +// ( (unsigned int) UART1_CTRL ) +// TX_FLUSH +// +// +// + + +// ----------------------------- Field Item: UART1_CTRL_RX_FLUSH -------------------------------- +// SVD Line: 9757 + +// SFDITEM_FIELD__UART1_CTRL_RX_FLUSH +// RX_FLUSH +// +// [Bit 6] RW (@ 0x40043000) Flushes the RX FIFO buffer. +// +// ( (unsigned int) UART1_CTRL ) +// RX_FLUSH +// +// +// + + +// ------------------------------ Field Item: UART1_CTRL_BITACC --------------------------------- +// SVD Line: 9763 + +// SFDITEM_FIELD__UART1_CTRL_BITACC +// BITACC +// +// [Bit 7] RW (@ 0x40043000) \nIf set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.\n0 : FRAME = Frame accuracy.\n1 : BIT = Bit accuracy. +// +// ( (unsigned int) UART1_CTRL ) +// BITACC +// <0=> 0: FRAME = Frame accuracy. +// <1=> 1: BIT = Bit accuracy. +// +// +// + + +// ---------------------------- Field Item: UART1_CTRL_CHAR_SIZE -------------------------------- +// SVD Line: 9781 + +// SFDITEM_FIELD__UART1_CTRL_CHAR_SIZE +// CHAR_SIZE +// +// [Bits 9..8] RW (@ 0x40043000) \nSelects UART character size.\n0 : 5 = 5 bits.\n1 : 6 = 6 bits.\n2 : 7 = 7 bits.\n3 : 8 = 8 bits. +// +// ( (unsigned int) UART1_CTRL ) +// CHAR_SIZE +// <0=> 0: 5 = 5 bits. +// <1=> 1: 6 = 6 bits. +// <2=> 2: 7 = 7 bits. +// <3=> 3: 8 = 8 bits. +// +// +// + + +// ----------------------------- Field Item: UART1_CTRL_STOPBITS -------------------------------- +// SVD Line: 9809 + +// SFDITEM_FIELD__UART1_CTRL_STOPBITS +// STOPBITS +// +// [Bit 10] RW (@ 0x40043000) \nSelects the number of stop bits that will be generated.\n0 : 1 = 1 stop bit.\n1 : 1_5 = 1.5 stop bits. +// +// ( (unsigned int) UART1_CTRL ) +// STOPBITS +// <0=> 0: 1 = 1 stop bit. +// <1=> 1: 1_5 = 1.5 stop bits. +// +// +// + + +// ---------------------------- Field Item: UART1_CTRL_FLOW_CTRL -------------------------------- +// SVD Line: 9827 + +// SFDITEM_FIELD__UART1_CTRL_FLOW_CTRL +// FLOW_CTRL +// +// [Bit 11] RW (@ 0x40043000) \nEnables/disables hardware flow control.\n0 : dis = HW Flow Control disabled\n1 : en = HW Flow Control with RTS/CTS enabled +// +// ( (unsigned int) UART1_CTRL ) +// FLOW_CTRL +// <0=> 0: dis = HW Flow Control disabled +// <1=> 1: en = HW Flow Control with RTS/CTS enabled +// +// +// + + +// ----------------------------- Field Item: UART1_CTRL_FLOW_POL -------------------------------- +// SVD Line: 9845 + +// SFDITEM_FIELD__UART1_CTRL_FLOW_POL +// FLOW_POL +// +// [Bit 12] RW (@ 0x40043000) \nRTS/CTS polarity.\n0 : 0 = RTS/CTS asserted is logic 0.\n1 : 1 = RTS/CTS asserted is logic 1. +// +// ( (unsigned int) UART1_CTRL ) +// FLOW_POL +// <0=> 0: 0 = RTS/CTS asserted is logic 0. +// <1=> 1: 1 = RTS/CTS asserted is logic 1. +// +// +// + + +// ---------------------------- Field Item: UART1_CTRL_NULL_MODEM ------------------------------- +// SVD Line: 9863 + +// SFDITEM_FIELD__UART1_CTRL_NULL_MODEM +// NULL_MODEM +// +// [Bit 13] RW (@ 0x40043000) \nNULL Modem Support (RTS/CTS and TXD/RXD swap).\n0 : DIS = Direct convention.\n1 : EN = Null Modem Mode. +// +// ( (unsigned int) UART1_CTRL ) +// NULL_MODEM +// <0=> 0: DIS = Direct convention. +// <1=> 1: EN = Null Modem Mode. +// +// +// + + +// ------------------------------ Field Item: UART1_CTRL_BREAK ---------------------------------- +// SVD Line: 9881 + +// SFDITEM_FIELD__UART1_CTRL_BREAK +// BREAK +// +// [Bit 14] RW (@ 0x40043000) \nBreak control bit. It causes a break condition to be transmitted to receiving UART.\n0 : DIS = Break characters are not generated.\n1 : EN = Break characters are sent(all the bits are at '0' including start/parity/stop). +// +// ( (unsigned int) UART1_CTRL ) +// BREAK +// <0=> 0: DIS = Break characters are not generated. +// <1=> 1: EN = Break characters are sent(all the bits are at '0' including start/parity/stop). +// +// +// + + +// ------------------------------ Field Item: UART1_CTRL_CLKSEL --------------------------------- +// SVD Line: 9899 + +// SFDITEM_FIELD__UART1_CTRL_CLKSEL +// CLKSEL +// +// [Bit 15] RW (@ 0x40043000) \nBaud Rate Clock Source Select. Selects the baud rate clock.\n0 : SYSTEM = System clock.\n1 : ALTERNATE = Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. +// +// ( (unsigned int) UART1_CTRL ) +// CLKSEL +// <0=> 0: SYSTEM = System clock. +// <1=> 1: ALTERNATE = Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. +// +// +// + + +// ------------------------------ Field Item: UART1_CTRL_RX_TO ---------------------------------- +// SVD Line: 9917 + +// SFDITEM_FIELD__UART1_CTRL_RX_TO +// RX_TO +// +// [Bits 23..16] RW (@ 0x40043000) RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read. +// +// ( (unsigned char)((UART1_CTRL >> 16) & 0xFF), ((UART1_CTRL = (UART1_CTRL & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: UART1_CTRL ----------------------------------- +// SVD Line: 9662 + +// SFDITEM_REG__UART1_CTRL +// CTRL +// +// [Bits 31..0] RW (@ 0x40043000) Control Register. +// ( (unsigned int)((UART1_CTRL >> 0) & 0xFFFFFFFF), ((UART1_CTRL = (UART1_CTRL & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) )) +// SFDITEM_FIELD__UART1_CTRL_ENABLE +// SFDITEM_FIELD__UART1_CTRL_PARITY_EN +// SFDITEM_FIELD__UART1_CTRL_PARITY +// SFDITEM_FIELD__UART1_CTRL_PARMD +// SFDITEM_FIELD__UART1_CTRL_TX_FLUSH +// SFDITEM_FIELD__UART1_CTRL_RX_FLUSH +// SFDITEM_FIELD__UART1_CTRL_BITACC +// SFDITEM_FIELD__UART1_CTRL_CHAR_SIZE +// SFDITEM_FIELD__UART1_CTRL_STOPBITS +// SFDITEM_FIELD__UART1_CTRL_FLOW_CTRL +// SFDITEM_FIELD__UART1_CTRL_FLOW_POL +// SFDITEM_FIELD__UART1_CTRL_NULL_MODEM +// SFDITEM_FIELD__UART1_CTRL_BREAK +// SFDITEM_FIELD__UART1_CTRL_CLKSEL +// SFDITEM_FIELD__UART1_CTRL_RX_TO +// +// + + +// ------------------------ Register Item Address: UART1_THRESH_CTRL ---------------------------- +// SVD Line: 9926 + +unsigned int UART1_THRESH_CTRL __AT (0x40043004); + + + +// ---------------------- Field Item: UART1_THRESH_CTRL_RX_FIFO_THRESH -------------------------- +// SVD Line: 9932 + +// SFDITEM_FIELD__UART1_THRESH_CTRL_RX_FIFO_THRESH +// RX_FIFO_THRESH +// +// [Bits 5..0] RW (@ 0x40043004) RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. +// +// ( (unsigned char)((UART1_THRESH_CTRL >> 0) & 0x3F), ((UART1_THRESH_CTRL = (UART1_THRESH_CTRL & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) )) +// +// +// + + +// ---------------------- Field Item: UART1_THRESH_CTRL_TX_FIFO_THRESH -------------------------- +// SVD Line: 9938 + +// SFDITEM_FIELD__UART1_THRESH_CTRL_TX_FIFO_THRESH +// TX_FIFO_THRESH +// +// [Bits 13..8] RW (@ 0x40043004) TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. +// +// ( (unsigned char)((UART1_THRESH_CTRL >> 8) & 0x3F), ((UART1_THRESH_CTRL = (UART1_THRESH_CTRL & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) )) +// +// +// + + +// ---------------------- Field Item: UART1_THRESH_CTRL_RTS_FIFO_THRESH ------------------------- +// SVD Line: 9944 + +// SFDITEM_FIELD__UART1_THRESH_CTRL_RTS_FIFO_THRESH +// RTS_FIFO_THRESH +// +// [Bits 21..16] RW (@ 0x40043004) RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. +// +// ( (unsigned char)((UART1_THRESH_CTRL >> 16) & 0x3F), ((UART1_THRESH_CTRL = (UART1_THRESH_CTRL & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) )) +// +// +// + + +// ---------------------------- Register RTree: UART1_THRESH_CTRL ------------------------------- +// SVD Line: 9926 + +// SFDITEM_REG__UART1_THRESH_CTRL +// THRESH_CTRL +// +// [Bits 31..0] RW (@ 0x40043004) Threshold Control register. +// ( (unsigned int)((UART1_THRESH_CTRL >> 0) & 0xFFFFFFFF), ((UART1_THRESH_CTRL = (UART1_THRESH_CTRL & ~(0x3F3F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F3F) << 0 ) ) )) +// SFDITEM_FIELD__UART1_THRESH_CTRL_RX_FIFO_THRESH +// SFDITEM_FIELD__UART1_THRESH_CTRL_TX_FIFO_THRESH +// SFDITEM_FIELD__UART1_THRESH_CTRL_RTS_FIFO_THRESH +// +// + + +// --------------------------- Register Item Address: UART1_STATUS ------------------------------ +// SVD Line: 9952 + +unsigned int UART1_STATUS __AT (0x40043008); + + + +// ---------------------------- Field Item: UART1_STATUS_TX_BUSY -------------------------------- +// SVD Line: 9959 + +// SFDITEM_FIELD__UART1_STATUS_TX_BUSY +// TX_BUSY +// +// [Bit 0] RO (@ 0x40043008) Read-only flag indicating the UART transmit status. +// +// ( (unsigned int) UART1_STATUS ) +// TX_BUSY +// +// +// + + +// ---------------------------- Field Item: UART1_STATUS_RX_BUSY -------------------------------- +// SVD Line: 9966 + +// SFDITEM_FIELD__UART1_STATUS_RX_BUSY +// RX_BUSY +// +// [Bit 1] RO (@ 0x40043008) Read-only flag indicating the UARTreceiver status. +// +// ( (unsigned int) UART1_STATUS ) +// RX_BUSY +// +// +// + + +// ----------------------------- Field Item: UART1_STATUS_PARITY -------------------------------- +// SVD Line: 9973 + +// SFDITEM_FIELD__UART1_STATUS_PARITY +// PARITY +// +// [Bit 2] RO (@ 0x40043008) 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. +// +// ( (unsigned int) UART1_STATUS ) +// PARITY +// +// +// + + +// ----------------------------- Field Item: UART1_STATUS_BREAK --------------------------------- +// SVD Line: 9980 + +// SFDITEM_FIELD__UART1_STATUS_BREAK +// BREAK +// +// [Bit 3] RO (@ 0x40043008) Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). +// +// ( (unsigned int) UART1_STATUS ) +// BREAK +// +// +// + + +// ---------------------------- Field Item: UART1_STATUS_RX_EMPTY ------------------------------- +// SVD Line: 9987 + +// SFDITEM_FIELD__UART1_STATUS_RX_EMPTY +// RX_EMPTY +// +// [Bit 4] RO (@ 0x40043008) Read-only flag indicating the RX FIFO state. +// +// ( (unsigned int) UART1_STATUS ) +// RX_EMPTY +// +// +// + + +// ---------------------------- Field Item: UART1_STATUS_RX_FULL -------------------------------- +// SVD Line: 9994 + +// SFDITEM_FIELD__UART1_STATUS_RX_FULL +// RX_FULL +// +// [Bit 5] RO (@ 0x40043008) Read-only flag indicating the RX FIFO state. +// +// ( (unsigned int) UART1_STATUS ) +// RX_FULL +// +// +// + + +// ---------------------------- Field Item: UART1_STATUS_TX_EMPTY ------------------------------- +// SVD Line: 10001 + +// SFDITEM_FIELD__UART1_STATUS_TX_EMPTY +// TX_EMPTY +// +// [Bit 6] RO (@ 0x40043008) Read-only flag indicating the TX FIFO state. +// +// ( (unsigned int) UART1_STATUS ) +// TX_EMPTY +// +// +// + + +// ---------------------------- Field Item: UART1_STATUS_TX_FULL -------------------------------- +// SVD Line: 10008 + +// SFDITEM_FIELD__UART1_STATUS_TX_FULL +// TX_FULL +// +// [Bit 7] RO (@ 0x40043008) Read-only flag indicating the TX FIFO state. +// +// ( (unsigned int) UART1_STATUS ) +// TX_FULL +// +// +// + + +// -------------------------- Field Item: UART1_STATUS_RX_FIFO_CNT ------------------------------ +// SVD Line: 10015 + +// SFDITEM_FIELD__UART1_STATUS_RX_FIFO_CNT +// RX_FIFO_CNT +// +// [Bits 13..8] RO (@ 0x40043008) Indicates the number of bytes currently in the RX FIFO. +// +// ( (unsigned char)((UART1_STATUS >> 8) & 0x3F) ) +// +// +// + + +// -------------------------- Field Item: UART1_STATUS_TX_FIFO_CNT ------------------------------ +// SVD Line: 10022 + +// SFDITEM_FIELD__UART1_STATUS_TX_FIFO_CNT +// TX_FIFO_CNT +// +// [Bits 21..16] RO (@ 0x40043008) Indicates the number of bytes currently in the TX FIFO. +// +// ( (unsigned char)((UART1_STATUS >> 16) & 0x3F) ) +// +// +// + + +// ----------------------------- Field Item: UART1_STATUS_RX_TO --------------------------------- +// SVD Line: 10029 + +// SFDITEM_FIELD__UART1_STATUS_RX_TO +// RX_TO +// +// [Bit 24] RO (@ 0x40043008) RX Timeout status. +// +// ( (unsigned int) UART1_STATUS ) +// RX_TO +// +// +// + + +// ------------------------------ Register RTree: UART1_STATUS ---------------------------------- +// SVD Line: 9952 + +// SFDITEM_REG__UART1_STATUS +// STATUS +// +// [Bits 31..0] RO (@ 0x40043008) Status Register. +// ( (unsigned int)((UART1_STATUS >> 0) & 0xFFFFFFFF) ) +// SFDITEM_FIELD__UART1_STATUS_TX_BUSY +// SFDITEM_FIELD__UART1_STATUS_RX_BUSY +// SFDITEM_FIELD__UART1_STATUS_PARITY +// SFDITEM_FIELD__UART1_STATUS_BREAK +// SFDITEM_FIELD__UART1_STATUS_RX_EMPTY +// SFDITEM_FIELD__UART1_STATUS_RX_FULL +// SFDITEM_FIELD__UART1_STATUS_TX_EMPTY +// SFDITEM_FIELD__UART1_STATUS_TX_FULL +// SFDITEM_FIELD__UART1_STATUS_RX_FIFO_CNT +// SFDITEM_FIELD__UART1_STATUS_TX_FIFO_CNT +// SFDITEM_FIELD__UART1_STATUS_RX_TO +// +// + + +// --------------------------- Register Item Address: UART1_INT_EN ------------------------------ +// SVD Line: 10038 + +unsigned int UART1_INT_EN __AT (0x4004300C); + + + +// ------------------------- Field Item: UART1_INT_EN_RX_FRAME_ERROR ---------------------------- +// SVD Line: 10044 + +// SFDITEM_FIELD__UART1_INT_EN_RX_FRAME_ERROR +// RX_FRAME_ERROR +// +// [Bit 0] RW (@ 0x4004300C) Enable for RX Frame Error Interrupt. +// +// ( (unsigned int) UART1_INT_EN ) +// RX_FRAME_ERROR +// +// +// + + +// ------------------------ Field Item: UART1_INT_EN_RX_PARITY_ERROR ---------------------------- +// SVD Line: 10050 + +// SFDITEM_FIELD__UART1_INT_EN_RX_PARITY_ERROR +// RX_PARITY_ERROR +// +// [Bit 1] RW (@ 0x4004300C) Enable for RX Parity Error interrupt. +// +// ( (unsigned int) UART1_INT_EN ) +// RX_PARITY_ERROR +// +// +// + + +// --------------------------- Field Item: UART1_INT_EN_CTS_CHANGE ------------------------------ +// SVD Line: 10056 + +// SFDITEM_FIELD__UART1_INT_EN_CTS_CHANGE +// CTS_CHANGE +// +// [Bit 2] RW (@ 0x4004300C) Enable for CTS signal change interrupt. +// +// ( (unsigned int) UART1_INT_EN ) +// CTS_CHANGE +// +// +// + + +// --------------------------- Field Item: UART1_INT_EN_RX_OVERRUN ------------------------------ +// SVD Line: 10062 + +// SFDITEM_FIELD__UART1_INT_EN_RX_OVERRUN +// RX_OVERRUN +// +// [Bit 3] RW (@ 0x4004300C) Enable for RX FIFO OVerrun interrupt. +// +// ( (unsigned int) UART1_INT_EN ) +// RX_OVERRUN +// +// +// + + +// ------------------------- Field Item: UART1_INT_EN_RX_FIFO_THRESH ---------------------------- +// SVD Line: 10068 + +// SFDITEM_FIELD__UART1_INT_EN_RX_FIFO_THRESH +// RX_FIFO_THRESH +// +// [Bit 4] RW (@ 0x4004300C) Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. +// +// ( (unsigned int) UART1_INT_EN ) +// RX_FIFO_THRESH +// +// +// + + +// ---------------------- Field Item: UART1_INT_EN_TX_FIFO_ALMOST_EMPTY ------------------------- +// SVD Line: 10074 + +// SFDITEM_FIELD__UART1_INT_EN_TX_FIFO_ALMOST_EMPTY +// TX_FIFO_ALMOST_EMPTY +// +// [Bit 5] RW (@ 0x4004300C) Enable for interrupt when TX FIFO has only one byte remaining. +// +// ( (unsigned int) UART1_INT_EN ) +// TX_FIFO_ALMOST_EMPTY +// +// +// + + +// ------------------------- Field Item: UART1_INT_EN_TX_FIFO_THRESH ---------------------------- +// SVD Line: 10080 + +// SFDITEM_FIELD__UART1_INT_EN_TX_FIFO_THRESH +// TX_FIFO_THRESH +// +// [Bit 6] RW (@ 0x4004300C) Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. +// +// ( (unsigned int) UART1_INT_EN ) +// TX_FIFO_THRESH +// +// +// + + +// ----------------------------- Field Item: UART1_INT_EN_BREAK --------------------------------- +// SVD Line: 10086 + +// SFDITEM_FIELD__UART1_INT_EN_BREAK +// BREAK +// +// [Bit 7] RW (@ 0x4004300C) Enable for received BREAK character interrupt. +// +// ( (unsigned int) UART1_INT_EN ) +// BREAK +// +// +// + + +// --------------------------- Field Item: UART1_INT_EN_RX_TIMEOUT ------------------------------ +// SVD Line: 10092 + +// SFDITEM_FIELD__UART1_INT_EN_RX_TIMEOUT +// RX_TIMEOUT +// +// [Bit 8] RW (@ 0x4004300C) Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). +// +// ( (unsigned int) UART1_INT_EN ) +// RX_TIMEOUT +// +// +// + + +// --------------------------- Field Item: UART1_INT_EN_LAST_BREAK ------------------------------ +// SVD Line: 10098 + +// SFDITEM_FIELD__UART1_INT_EN_LAST_BREAK +// LAST_BREAK +// +// [Bit 9] RW (@ 0x4004300C) Enable for Last break character interrupt. +// +// ( (unsigned int) UART1_INT_EN ) +// LAST_BREAK +// +// +// + + +// ------------------------------ Register RTree: UART1_INT_EN ---------------------------------- +// SVD Line: 10038 + +// SFDITEM_REG__UART1_INT_EN +// INT_EN +// +// [Bits 31..0] RW (@ 0x4004300C) Interrupt Enable Register. +// ( (unsigned int)((UART1_INT_EN >> 0) & 0xFFFFFFFF), ((UART1_INT_EN = (UART1_INT_EN & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) +// SFDITEM_FIELD__UART1_INT_EN_RX_FRAME_ERROR +// SFDITEM_FIELD__UART1_INT_EN_RX_PARITY_ERROR +// SFDITEM_FIELD__UART1_INT_EN_CTS_CHANGE +// SFDITEM_FIELD__UART1_INT_EN_RX_OVERRUN +// SFDITEM_FIELD__UART1_INT_EN_RX_FIFO_THRESH +// SFDITEM_FIELD__UART1_INT_EN_TX_FIFO_ALMOST_EMPTY +// SFDITEM_FIELD__UART1_INT_EN_TX_FIFO_THRESH +// SFDITEM_FIELD__UART1_INT_EN_BREAK +// SFDITEM_FIELD__UART1_INT_EN_RX_TIMEOUT +// SFDITEM_FIELD__UART1_INT_EN_LAST_BREAK +// +// + + +// --------------------------- Register Item Address: UART1_INT_FL ------------------------------ +// SVD Line: 10106 + +unsigned int UART1_INT_FL __AT (0x40043010); + + + +// ------------------------- Field Item: UART1_INT_FL_RX_FRAME_ERROR ---------------------------- +// SVD Line: 10113 + +// SFDITEM_FIELD__UART1_INT_FL_RX_FRAME_ERROR +// RX_FRAME_ERROR +// +// [Bit 0] RW (@ 0x40043010) FLAG for RX Frame Error Interrupt. +// +// ( (unsigned int) UART1_INT_FL ) +// RX_FRAME_ERROR +// +// +// + + +// ------------------------ Field Item: UART1_INT_FL_RX_PARITY_ERROR ---------------------------- +// SVD Line: 10119 + +// SFDITEM_FIELD__UART1_INT_FL_RX_PARITY_ERROR +// RX_PARITY_ERROR +// +// [Bit 1] RW (@ 0x40043010) FLAG for RX Parity Error interrupt. +// +// ( (unsigned int) UART1_INT_FL ) +// RX_PARITY_ERROR +// +// +// + + +// --------------------------- Field Item: UART1_INT_FL_CTS_CHANGE ------------------------------ +// SVD Line: 10125 + +// SFDITEM_FIELD__UART1_INT_FL_CTS_CHANGE +// CTS_CHANGE +// +// [Bit 2] RW (@ 0x40043010) FLAG for CTS signal change interrupt. +// +// ( (unsigned int) UART1_INT_FL ) +// CTS_CHANGE +// +// +// + + +// --------------------------- Field Item: UART1_INT_FL_RX_OVERRUN ------------------------------ +// SVD Line: 10131 + +// SFDITEM_FIELD__UART1_INT_FL_RX_OVERRUN +// RX_OVERRUN +// +// [Bit 3] RW (@ 0x40043010) FLAG for RX FIFO Overrun interrupt. +// +// ( (unsigned int) UART1_INT_FL ) +// RX_OVERRUN +// +// +// + + +// ------------------------- Field Item: UART1_INT_FL_RX_FIFO_THRESH ---------------------------- +// SVD Line: 10137 + +// SFDITEM_FIELD__UART1_INT_FL_RX_FIFO_THRESH +// RX_FIFO_THRESH +// +// [Bit 4] RW (@ 0x40043010) FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. +// +// ( (unsigned int) UART1_INT_FL ) +// RX_FIFO_THRESH +// +// +// + + +// ---------------------- Field Item: UART1_INT_FL_TX_FIFO_ALMOST_EMPTY ------------------------- +// SVD Line: 10143 + +// SFDITEM_FIELD__UART1_INT_FL_TX_FIFO_ALMOST_EMPTY +// TX_FIFO_ALMOST_EMPTY +// +// [Bit 5] RW (@ 0x40043010) FLAG for interrupt when TX FIFO has only one byte remaining. +// +// ( (unsigned int) UART1_INT_FL ) +// TX_FIFO_ALMOST_EMPTY +// +// +// + + +// ------------------------- Field Item: UART1_INT_FL_TX_FIFO_THRESH ---------------------------- +// SVD Line: 10149 + +// SFDITEM_FIELD__UART1_INT_FL_TX_FIFO_THRESH +// TX_FIFO_THRESH +// +// [Bit 6] RW (@ 0x40043010) FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. +// +// ( (unsigned int) UART1_INT_FL ) +// TX_FIFO_THRESH +// +// +// + + +// ----------------------------- Field Item: UART1_INT_FL_BREAK --------------------------------- +// SVD Line: 10155 + +// SFDITEM_FIELD__UART1_INT_FL_BREAK +// BREAK +// +// [Bit 7] RW (@ 0x40043010) FLAG for received BREAK character interrupt. +// +// ( (unsigned int) UART1_INT_FL ) +// BREAK +// +// +// + + +// --------------------------- Field Item: UART1_INT_FL_RX_TIMEOUT ------------------------------ +// SVD Line: 10161 + +// SFDITEM_FIELD__UART1_INT_FL_RX_TIMEOUT +// RX_TIMEOUT +// +// [Bit 8] RW (@ 0x40043010) FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). +// +// ( (unsigned int) UART1_INT_FL ) +// RX_TIMEOUT +// +// +// + + +// --------------------------- Field Item: UART1_INT_FL_LAST_BREAK ------------------------------ +// SVD Line: 10167 + +// SFDITEM_FIELD__UART1_INT_FL_LAST_BREAK +// LAST_BREAK +// +// [Bit 9] RW (@ 0x40043010) FLAG for Last break character interrupt. +// +// ( (unsigned int) UART1_INT_FL ) +// LAST_BREAK +// +// +// + + +// ------------------------------ Register RTree: UART1_INT_FL ---------------------------------- +// SVD Line: 10106 + +// SFDITEM_REG__UART1_INT_FL +// INT_FL +// +// [Bits 31..0] RW (@ 0x40043010) Interrupt Status Flags. +// ( (unsigned int)((UART1_INT_FL >> 0) & 0xFFFFFFFF), ((UART1_INT_FL = (UART1_INT_FL & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) )) +// SFDITEM_FIELD__UART1_INT_FL_RX_FRAME_ERROR +// SFDITEM_FIELD__UART1_INT_FL_RX_PARITY_ERROR +// SFDITEM_FIELD__UART1_INT_FL_CTS_CHANGE +// SFDITEM_FIELD__UART1_INT_FL_RX_OVERRUN +// SFDITEM_FIELD__UART1_INT_FL_RX_FIFO_THRESH +// SFDITEM_FIELD__UART1_INT_FL_TX_FIFO_ALMOST_EMPTY +// SFDITEM_FIELD__UART1_INT_FL_TX_FIFO_THRESH +// SFDITEM_FIELD__UART1_INT_FL_BREAK +// SFDITEM_FIELD__UART1_INT_FL_RX_TIMEOUT +// SFDITEM_FIELD__UART1_INT_FL_LAST_BREAK +// +// + + +// --------------------------- Register Item Address: UART1_BAUD0 ------------------------------- +// SVD Line: 10175 + +unsigned int UART1_BAUD0 __AT (0x40043014); + + + +// ------------------------------ Field Item: UART1_BAUD0_IBAUD --------------------------------- +// SVD Line: 10181 + +// SFDITEM_FIELD__UART1_BAUD0_IBAUD +// IBAUD +// +// [Bits 11..0] RW (@ 0x40043014) Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). +// +// ( (unsigned short)((UART1_BAUD0 >> 0) & 0xFFF), ((UART1_BAUD0 = (UART1_BAUD0 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) +// +// +// + + +// ----------------------------- Field Item: UART1_BAUD0_FACTOR --------------------------------- +// SVD Line: 10187 + +// SFDITEM_FIELD__UART1_BAUD0_FACTOR +// FACTOR +// +// [Bits 17..16] RW (@ 0x40043014) \nFACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.\n0 : 128 = Baud Factor 128\n1 : 64 = Baud Factor 64\n2 : 32 = Baud Factor 32\n3 : 16 = Baud Factor 16 +// +// ( (unsigned int) UART1_BAUD0 ) +// FACTOR +// <0=> 0: 128 = Baud Factor 128 +// <1=> 1: 64 = Baud Factor 64 +// <2=> 2: 32 = Baud Factor 32 +// <3=> 3: 16 = Baud Factor 16 +// +// +// + + +// ------------------------------- Register RTree: UART1_BAUD0 ---------------------------------- +// SVD Line: 10175 + +// SFDITEM_REG__UART1_BAUD0 +// BAUD0 +// +// [Bits 31..0] RW (@ 0x40043014) Baud rate register. Integer portion. +// ( (unsigned int)((UART1_BAUD0 >> 0) & 0xFFFFFFFF), ((UART1_BAUD0 = (UART1_BAUD0 & ~(0x30FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30FFF) << 0 ) ) )) +// SFDITEM_FIELD__UART1_BAUD0_IBAUD +// SFDITEM_FIELD__UART1_BAUD0_FACTOR +// +// + + +// --------------------------- Register Item Address: UART1_BAUD1 ------------------------------- +// SVD Line: 10217 + +unsigned int UART1_BAUD1 __AT (0x40043018); + + + +// ------------------------------ Field Item: UART1_BAUD1_DBAUD --------------------------------- +// SVD Line: 10223 + +// SFDITEM_FIELD__UART1_BAUD1_DBAUD +// DBAUD +// +// [Bits 11..0] RW (@ 0x40043018) Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128. +// +// ( (unsigned short)((UART1_BAUD1 >> 0) & 0xFFF), ((UART1_BAUD1 = (UART1_BAUD1 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: UART1_BAUD1 ---------------------------------- +// SVD Line: 10217 + +// SFDITEM_REG__UART1_BAUD1 +// BAUD1 +// +// [Bits 31..0] RW (@ 0x40043018) Baud rate register. Decimal Setting. +// ( (unsigned int)((UART1_BAUD1 >> 0) & 0xFFFFFFFF), ((UART1_BAUD1 = (UART1_BAUD1 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) )) +// SFDITEM_FIELD__UART1_BAUD1_DBAUD +// +// + + +// ---------------------------- Register Item Address: UART1_FIFO ------------------------------- +// SVD Line: 10231 + +unsigned int UART1_FIFO __AT (0x4004301C); + + + +// ------------------------------- Field Item: UART1_FIFO_FIFO ---------------------------------- +// SVD Line: 10237 + +// SFDITEM_FIELD__UART1_FIFO_FIFO +// FIFO +// +// [Bits 7..0] RW (@ 0x4004301C) Load/unload location for TX and RX FIFO buffers. +// +// ( (unsigned char)((UART1_FIFO >> 0) & 0xFF), ((UART1_FIFO = (UART1_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// ------------------------------- Register RTree: UART1_FIFO ----------------------------------- +// SVD Line: 10231 + +// SFDITEM_REG__UART1_FIFO +// FIFO +// +// [Bits 31..0] RW (@ 0x4004301C) FIFO Data buffer. +// ( (unsigned int)((UART1_FIFO >> 0) & 0xFFFFFFFF), ((UART1_FIFO = (UART1_FIFO & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__UART1_FIFO_FIFO +// +// + + +// ---------------------------- Register Item Address: UART1_DMA -------------------------------- +// SVD Line: 10245 + +unsigned int UART1_DMA __AT (0x40043020); + + + +// ----------------------------- Field Item: UART1_DMA_TXDMA_EN --------------------------------- +// SVD Line: 10251 + +// SFDITEM_FIELD__UART1_DMA_TXDMA_EN +// TXDMA_EN +// +// [Bit 0] RW (@ 0x40043020) \nTX DMA channel enable.\n0 : dis = DMA is disabled\n1 : en = DMA is enabled +// +// ( (unsigned int) UART1_DMA ) +// TXDMA_EN +// <0=> 0: dis = DMA is disabled +// <1=> 1: en = DMA is enabled +// +// +// + + +// ----------------------------- Field Item: UART1_DMA_RXDMA_EN --------------------------------- +// SVD Line: 10269 + +// SFDITEM_FIELD__UART1_DMA_RXDMA_EN +// RXDMA_EN +// +// [Bit 1] RW (@ 0x40043020) \nRX DMA channel enable.\n0 : dis = DMA is disabled\n1 : en = DMA is enabled +// +// ( (unsigned int) UART1_DMA ) +// RXDMA_EN +// <0=> 0: dis = DMA is disabled +// <1=> 1: en = DMA is enabled +// +// +// + + +// ---------------------------- Field Item: UART1_DMA_TXDMA_LEVEL ------------------------------- +// SVD Line: 10287 + +// SFDITEM_FIELD__UART1_DMA_TXDMA_LEVEL +// TXDMA_LEVEL +// +// [Bits 13..8] RW (@ 0x40043020) TX threshold for DMA transmission. +// +// ( (unsigned char)((UART1_DMA >> 8) & 0x3F), ((UART1_DMA = (UART1_DMA & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) )) +// +// +// + + +// ---------------------------- Field Item: UART1_DMA_RXDMA_LEVEL ------------------------------- +// SVD Line: 10293 + +// SFDITEM_FIELD__UART1_DMA_RXDMA_LEVEL +// RXDMA_LEVEL +// +// [Bits 21..16] RW (@ 0x40043020) RX threshold for DMA transmission. +// +// ( (unsigned char)((UART1_DMA >> 16) & 0x3F), ((UART1_DMA = (UART1_DMA & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: UART1_DMA ----------------------------------- +// SVD Line: 10245 + +// SFDITEM_REG__UART1_DMA +// DMA +// +// [Bits 31..0] RW (@ 0x40043020) DMA Configuration. +// ( (unsigned int)((UART1_DMA >> 0) & 0xFFFFFFFF), ((UART1_DMA = (UART1_DMA & ~(0x3F3F03UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F03) << 0 ) ) )) +// SFDITEM_FIELD__UART1_DMA_TXDMA_EN +// SFDITEM_FIELD__UART1_DMA_RXDMA_EN +// SFDITEM_FIELD__UART1_DMA_TXDMA_LEVEL +// SFDITEM_FIELD__UART1_DMA_RXDMA_LEVEL +// +// + + +// -------------------------- Register Item Address: UART1_TX_FIFO ------------------------------ +// SVD Line: 10301 + +unsigned int UART1_TX_FIFO __AT (0x40043024); + + + +// ----------------------------- Field Item: UART1_TX_FIFO_DATA --------------------------------- +// SVD Line: 10307 + +// SFDITEM_FIELD__UART1_TX_FIFO_DATA +// DATA +// +// [Bits 6..0] RW (@ 0x40043024) Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned). +// +// ( (unsigned char)((UART1_TX_FIFO >> 0) & 0x7F), ((UART1_TX_FIFO = (UART1_TX_FIFO & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) )) +// +// +// + + +// ------------------------------ Register RTree: UART1_TX_FIFO --------------------------------- +// SVD Line: 10301 + +// SFDITEM_REG__UART1_TX_FIFO +// TX_FIFO +// +// [Bits 31..0] RW (@ 0x40043024) Transmit FIFO Status register. +// ( (unsigned int)((UART1_TX_FIFO >> 0) & 0xFFFFFFFF), ((UART1_TX_FIFO = (UART1_TX_FIFO & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) )) +// SFDITEM_FIELD__UART1_TX_FIFO_DATA +// +// + + +// --------------------------------- Peripheral View: UART1 ------------------------------------- +// SVD Line: 10319 + +// UART1 +// UART1 +// SFDITEM_REG__UART1_CTRL +// SFDITEM_REG__UART1_THRESH_CTRL +// SFDITEM_REG__UART1_STATUS +// SFDITEM_REG__UART1_INT_EN +// SFDITEM_REG__UART1_INT_FL +// SFDITEM_REG__UART1_BAUD0 +// SFDITEM_REG__UART1_BAUD1 +// SFDITEM_REG__UART1_FIFO +// SFDITEM_REG__UART1_DMA +// SFDITEM_REG__UART1_TX_FIFO +// +// + + +// ---------------------------- Register Item Address: WDT0_CTRL -------------------------------- +// SVD Line: 10344 + +unsigned int WDT0_CTRL __AT (0x40003000); + + + +// ---------------------------- Field Item: WDT0_CTRL_INT_PERIOD -------------------------------- +// SVD Line: 10350 + +// SFDITEM_FIELD__WDT0_CTRL_INT_PERIOD +// INT_PERIOD +// +// [Bits 3..0] RW (@ 0x40003000) \nWatchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.\n0 : wdt2pow31 = 2**31 clock cycles.\n1 : wdt2pow30 = 2**30 clock cycles.\n2 : wdt2pow29 = 2**29 clock cycles.\n3 : wdt2pow28 = 2**28 clock cycles.\n4 : wdt2pow27 = 2^27 clock cycles.\n5 : wdt2pow26 = 2**26 clock cycles.\n6 : wdt2pow25 = 2**25 clock cycles.\n7 : wdt2pow24 = 2**24 clock cycles.\n8 : wdt2pow23 = 2**23 clock cycles.\n9 : wdt2pow22 = 2**22 clock cycles.\n10 : wdt2pow21 = 2**21 clock cycles.\n11 : wdt2pow20 = 2**20 clock cycles.\n12 : wdt2pow19 = 2**19 clock cycles.\n13 : wdt2pow18 = 2**18 clock cycles.\n14 : wdt2pow17 = 2**17 clock cycles.\n15 : wdt2pow16 = 2**16 clock cycles. +// +// ( (unsigned int) WDT0_CTRL ) +// INT_PERIOD +// <0=> 0: wdt2pow31 = 2**31 clock cycles. +// <1=> 1: wdt2pow30 = 2**30 clock cycles. +// <2=> 2: wdt2pow29 = 2**29 clock cycles. +// <3=> 3: wdt2pow28 = 2**28 clock cycles. +// <4=> 4: wdt2pow27 = 2^27 clock cycles. +// <5=> 5: wdt2pow26 = 2**26 clock cycles. +// <6=> 6: wdt2pow25 = 2**25 clock cycles. +// <7=> 7: wdt2pow24 = 2**24 clock cycles. +// <8=> 8: wdt2pow23 = 2**23 clock cycles. +// <9=> 9: wdt2pow22 = 2**22 clock cycles. +// <10=> 10: wdt2pow21 = 2**21 clock cycles. +// <11=> 11: wdt2pow20 = 2**20 clock cycles. +// <12=> 12: wdt2pow19 = 2**19 clock cycles. +// <13=> 13: wdt2pow18 = 2**18 clock cycles. +// <14=> 14: wdt2pow17 = 2**17 clock cycles. +// <15=> 15: wdt2pow16 = 2**16 clock cycles. +// +// +// + + +// ---------------------------- Field Item: WDT0_CTRL_RST_PERIOD -------------------------------- +// SVD Line: 10438 + +// SFDITEM_FIELD__WDT0_CTRL_RST_PERIOD +// RST_PERIOD +// +// [Bits 7..4] RW (@ 0x40003000) \nWatchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.\n0 : wdt2pow31 = 2**31 clock cycles.\n1 : wdt2pow30 = 2**30 clock cycles.\n2 : wdt2pow29 = 2**29 clock cycles.\n3 : wdt2pow28 = 2**28 clock cycles.\n4 : wdt2pow27 = 2^27 clock cycles.\n5 : wdt2pow26 = 2**26 clock cycles.\n6 : wdt2pow25 = 2**25 clock cycles.\n7 : wdt2pow24 = 2**24 clock cycles.\n8 : wdt2pow23 = 2**23 clock cycles.\n9 : wdt2pow22 = 2**22 clock cycles.\n10 : wdt2pow21 = 2**21 clock cycles.\n11 : wdt2pow20 = 2**20 clock cycles.\n12 : wdt2pow19 = 2**19 clock cycles.\n13 : wdt2pow18 = 2**18 clock cycles.\n14 : wdt2pow17 = 2**17 clock cycles.\n15 : wdt2pow16 = 2**16 clock cycles. +// +// ( (unsigned int) WDT0_CTRL ) +// RST_PERIOD +// <0=> 0: wdt2pow31 = 2**31 clock cycles. +// <1=> 1: wdt2pow30 = 2**30 clock cycles. +// <2=> 2: wdt2pow29 = 2**29 clock cycles. +// <3=> 3: wdt2pow28 = 2**28 clock cycles. +// <4=> 4: wdt2pow27 = 2^27 clock cycles. +// <5=> 5: wdt2pow26 = 2**26 clock cycles. +// <6=> 6: wdt2pow25 = 2**25 clock cycles. +// <7=> 7: wdt2pow24 = 2**24 clock cycles. +// <8=> 8: wdt2pow23 = 2**23 clock cycles. +// <9=> 9: wdt2pow22 = 2**22 clock cycles. +// <10=> 10: wdt2pow21 = 2**21 clock cycles. +// <11=> 11: wdt2pow20 = 2**20 clock cycles. +// <12=> 12: wdt2pow19 = 2**19 clock cycles. +// <13=> 13: wdt2pow18 = 2**18 clock cycles. +// <14=> 14: wdt2pow17 = 2**17 clock cycles. +// <15=> 15: wdt2pow16 = 2**16 clock cycles. +// +// +// + + +// ------------------------------ Field Item: WDT0_CTRL_WDT_EN ---------------------------------- +// SVD Line: 10526 + +// SFDITEM_FIELD__WDT0_CTRL_WDT_EN +// WDT_EN +// +// [Bit 8] RW (@ 0x40003000) \nWatchdog Timer Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) WDT0_CTRL ) +// WDT_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ----------------------------- Field Item: WDT0_CTRL_INT_FLAG --------------------------------- +// SVD Line: 10544 + +// SFDITEM_FIELD__WDT0_CTRL_INT_FLAG +// INT_FLAG +// +// [Bit 9] RW (@ 0x40003000) \nWatchdog Timer Interrupt Flag.\n0 : inactive = No interrupt is pending.\n1 : pending = An interrupt is pending. +// +// ( (unsigned int) WDT0_CTRL ) +// INT_FLAG +// <0=> 0: inactive = No interrupt is pending. +// <1=> 1: pending = An interrupt is pending. +// +// +// + + +// ------------------------------ Field Item: WDT0_CTRL_INT_EN ---------------------------------- +// SVD Line: 10563 + +// SFDITEM_FIELD__WDT0_CTRL_INT_EN +// INT_EN +// +// [Bit 10] RW (@ 0x40003000) \nWatchdog Timer Interrupt Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) WDT0_CTRL ) +// INT_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ------------------------------ Field Item: WDT0_CTRL_RST_EN ---------------------------------- +// SVD Line: 10581 + +// SFDITEM_FIELD__WDT0_CTRL_RST_EN +// RST_EN +// +// [Bit 11] RW (@ 0x40003000) \nWatchdog Timer Reset Enable.\n0 : dis = Disable.\n1 : en = Enable. +// +// ( (unsigned int) WDT0_CTRL ) +// RST_EN +// <0=> 0: dis = Disable. +// <1=> 1: en = Enable. +// +// +// + + +// ----------------------------- Field Item: WDT0_CTRL_RST_FLAG --------------------------------- +// SVD Line: 10599 + +// SFDITEM_FIELD__WDT0_CTRL_RST_FLAG +// RST_FLAG +// +// [Bit 31] RW (@ 0x40003000) \nWatchdog Timer Reset Flag.\n0 : noEvent = The event has not occurred.\n1 : occurred = The event has occurred. +// +// ( (unsigned int) WDT0_CTRL ) +// RST_FLAG +// <0=> 0: noEvent = The event has not occurred. +// <1=> 1: occurred = The event has occurred. +// +// +// + + +// -------------------------------- Register RTree: WDT0_CTRL ----------------------------------- +// SVD Line: 10344 + +// SFDITEM_REG__WDT0_CTRL +// CTRL +// +// [Bits 31..0] RW (@ 0x40003000) Watchdog Timer Control Register. +// ( (unsigned int)((WDT0_CTRL >> 0) & 0xFFFFFFFF), ((WDT0_CTRL = (WDT0_CTRL & ~(0x80000FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80000FFF) << 0 ) ) )) +// SFDITEM_FIELD__WDT0_CTRL_INT_PERIOD +// SFDITEM_FIELD__WDT0_CTRL_RST_PERIOD +// SFDITEM_FIELD__WDT0_CTRL_WDT_EN +// SFDITEM_FIELD__WDT0_CTRL_INT_FLAG +// SFDITEM_FIELD__WDT0_CTRL_INT_EN +// SFDITEM_FIELD__WDT0_CTRL_RST_EN +// SFDITEM_FIELD__WDT0_CTRL_RST_FLAG +// +// + + +// ----------------------------- Register Item Address: WDT0_RST -------------------------------- +// SVD Line: 10620 + +unsigned int WDT0_RST __AT (0x40003004); + + + +// ------------------------------ Field Item: WDT0_RST_WDT_RST ---------------------------------- +// SVD Line: 10626 + +// SFDITEM_FIELD__WDT0_RST_WDT_RST +// WDT_RST +// +// [Bits 7..0] WO (@ 0x40003004) Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. +// +// ( (unsigned char)((WDT0_RST >> 0) & 0x0), ((WDT0_RST = (WDT0_RST & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) )) +// +// +// + + +// -------------------------------- Register RTree: WDT0_RST ------------------------------------ +// SVD Line: 10620 + +// SFDITEM_REG__WDT0_RST +// RST +// +// [Bits 31..0] WO (@ 0x40003004) Watchdog Timer Reset Register. +// ( (unsigned int)((WDT0_RST >> 0) & 0xFFFFFFFF), ((WDT0_RST = (WDT0_RST & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) )) +// SFDITEM_FIELD__WDT0_RST_WDT_RST +// +// + + +// ---------------------------------- Peripheral View: WDT0 ------------------------------------- +// SVD Line: 10330 + +// WDT0 +// WDT0 +// SFDITEM_REG__WDT0_CTRL +// SFDITEM_REG__WDT0_RST +// +// + + +// ------------------------------ IRQ Num definition: max32660 --------------------------------- +// SVD Line: 2 + + + +// ------------------------------------------------------------------------------------------------ +// ----- Interrupt Number Definition ----- +// ------------------------------------------------------------------------------------------------ + + + +// ------------------------ ARM Cortex-M4 Specific Interrupt Numbers ---------------------------- + +// Reset_IRQ +// Reset +// Reset Vector, invoked on Power up and warm reset +// 1 +// +// +// NonMaskableInt_IRQ +// NonMaskableInt +// Non maskable Interrupt, cannot be stopped or preempted +// 2 +// +// +// HardFault_IRQ +// HardFault +// Hard Fault, all classes of Fault +// 3 +// +// +// MemoryManagement_IRQ +// MemoryManagement +// Memory Management, MPU mismatch, including Access Violation and No Match +// 4 +// +// +// BusFault_IRQ +// BusFault +// Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault +// 5 +// +// +// UsageFault_IRQ +// UsageFault +// Usage Fault, i.e. Undef Instruction, Illegal State Transition +// 6 +// +// +// SVCall_IRQ +// SVCall +// System Service Call via SVC instruction +// 11 +// +// +// DebugMonitor_IRQ +// DebugMonitor +// Debug Monitor +// 12 +// +// +// PendSV_IRQ +// PendSV +// Pendable request for system service +// 14 +// +// +// SysTick_IRQ +// SysTick +// System Tick Timer +// 15 +// +// + + +// --------------------------- max32660 Specific Interrupt Numbers ------------------------------ + +// WDT0_IRQ +// WDT0 +// WDT0 +// 17 +// +// +// RTC_IRQ +// RTC +// RTC interrupt. +// 19 +// +// +// TMR0_IRQ +// TMR0 +// TMR0 IRQ +// 21 +// +// +// TMR1_IRQ +// TMR1 +// TMR1 IRQ +// 22 +// +// +// TMR2_IRQ +// TMR2 +// TMR2 IRQ +// 23 +// +// +// I2C0_IRQ +// I2C0 +// I2C0 IRQ +// 29 +// +// +// UART0_IRQ +// UART0 +// UART0 IRQ +// 30 +// +// +// UART1_IRQ +// UART1 +// UART1 IRQ +// 31 +// +// +// SPI0_IRQ +// SPI0 +// SPI0 +// 32 +// +// +// Flash_Controller_IRQ +// Flash_Controller +// Flash Controller interrupt. +// 39 +// +// +// GPIO0_IRQ +// GPIO0 +// GPIO0 interrupt. +// 40 +// +// +// DMA0_IRQ +// DMA0 +// DMA0 +// 44 +// +// +// DMA1_IRQ +// DMA1 +// DMA1 +// 45 +// +// +// DMA2_IRQ +// DMA2 +// DMA2 +// 46 +// +// +// DMA3_IRQ +// DMA3 +// DMA3 +// 47 +// +// +// I2C1_IRQ +// I2C1 +// I2C1 IRQ +// 52 +// +// +// DMA4_IRQ +// DMA4 +// DMA4 +// 84 +// +// +// DMA5_IRQ +// DMA5 +// DMA5 +// 85 +// +// +// DMA6_IRQ +// DMA6 +// DMA6 +// 86 +// +// +// DMA7_IRQ +// DMA7 +// DMA7 +// 87 +// +// +// DMA8_IRQ +// DMA8 +// DMA8 +// 88 +// +// +// DMA9_IRQ +// DMA9 +// DMA9 +// 89 +// +// +// DMA10_IRQ +// DMA10 +// DMA10 +// 90 +// +// +// DMA11_IRQ +// DMA11 +// DMA11 +// 91 +// +// +// DMA12_IRQ +// DMA12 +// DMA12 +// 92 +// +// +// DMA13_IRQ +// DMA13 +// DMA13 +// 93 +// +// +// DMA14_IRQ +// DMA14 +// DMA14 +// 94 +// +// +// DMA15_IRQ +// DMA15 +// DMA15 +// 95 +// +// +// max32660_IRQTable +// max32660 Interrupt Table +// 3 +// Reset_IRQ +// NonMaskableInt_IRQ +// HardFault_IRQ +// MemoryManagement_IRQ +// BusFault_IRQ +// UsageFault_IRQ +// SVCall_IRQ +// DebugMonitor_IRQ +// PendSV_IRQ +// SysTick_IRQ +// WDT0_IRQ +// RTC_IRQ +// TMR0_IRQ +// TMR1_IRQ +// TMR2_IRQ +// I2C0_IRQ +// UART0_IRQ +// UART1_IRQ +// SPI0_IRQ +// Flash_Controller_IRQ +// GPIO0_IRQ +// DMA0_IRQ +// DMA1_IRQ +// DMA2_IRQ +// DMA3_IRQ +// I2C1_IRQ +// DMA4_IRQ +// DMA5_IRQ +// DMA6_IRQ +// DMA7_IRQ +// DMA8_IRQ +// DMA9_IRQ +// DMA10_IRQ +// DMA11_IRQ +// DMA12_IRQ +// DMA13_IRQ +// DMA14_IRQ +// DMA15_IRQ +// + + +// ------------------------------------- Menu: max32660 ---------------------------------------- +// SVD Line: 2 + + + +// ------------------------------- Peripheral Menu: 'max32660' ---------------------------------- + + + +// ------------------------------------------------------------------------------------------------ +// ----- Main Menu ----- +// ------------------------------------------------------------------------------------------------ + +// BBFC +// BBFC +// +// +// BBSIR +// BBSIR +// +// +// DMA +// DMA +// +// +// FLC +// FLC +// +// +// GCR +// GCR +// +// +// GPIO +// GPIO0 +// +// +// I2C +// I2C0 +// I2C1 +// +// +// ICC +// ICC0 +// ICC1 +// +// +// PWRSEQ +// PWRSEQ +// +// +// RTC +// RTC +// +// +// SIR +// SIR +// +// +// SMON +// SMON +// +// +// SPI +// SPI17Y +// SPIMSS +// +// +// Timers +// TMR0 +// TMR1 +// TMR2 +// +// +// UART +// UART0 +// UART1 +// +// +// WDT +// WDT0 +// +// diff --git a/Project/SDK/Debuggint_Info/max32660.svd b/Project/SDK/Debuggint_Info/max32660.svd new file mode 100644 index 0000000..2dd49a6 --- /dev/null +++ b/Project/SDK/Debuggint_Info/max32660.svd @@ -0,0 +1,8701 @@ + + + Maxim-Integrated + Maxim + max32660 + ARMCM4 + 1.0 + MAX32660. + + CM4 + r2p1 + little + true + true + 3 + false + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + + + SCON + System Control. + 0x00 + 0xFFFFFFFE + + + FLASH_PAGE_FLIP + Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + 4 + 1 + + + normal + Physical layout matches logical layout. + 0 + + + swapped + Bottom half mapped to logical top half and vice versa. + 1 + + + + + FPU_DIS + Floating Point Unit Disable + 5 + 1 + + + enable + enable Floating point unit + 0 + + + disable + disable floating point unit + 1 + + + + + ICC0_FLUSH + Instruction Cache Controller Flush. Write 1 to flush the internal flash cache. This bit is cleared by hardware when the flush is complete. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + SWD_DIS + Serial Wire Debug Disable + 14 + 1 + + + enable + Enable JTAG SWD + 0 + + + disable + Disable JTAG SWD + 1 + + + + + + + RST0 + Reset. + 0x04 + + + DMA + DMA Reset. + 0 + + dma_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + 1 + + dma_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + WDT0 + Watchdog Timer Reset. + 1 + 1 + + wdt_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + wdt_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + gpio0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + gpio0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 + 1 + + timer0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 + 1 + + timer1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + TIMER2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 + 1 + + timer2_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + timer2_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 + 1 + + uart0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + uart0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + uart1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + uart1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + 13 + 1 + + spi0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + spi0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 + 1 + + spi1_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + xpi1_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + I2C0 + I2C0 Reset. + 16 + 1 + + i2c0_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + i2c0_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + RTC + Real Time Clock Reset. + 17 + 1 + + rtc_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + rtc_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SOFT + Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer. + 29 + 1 + + srst_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + srst_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + PERIPH + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + prst_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + prst_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + SYSTEM + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + system_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + system_read + read + + Reset_Done + Reset Complete + 0 + + + Busy + Reset Busy + 1 + + + + + + + CLK_CTRL + Clock Control. + 0x08 + 0x00000008 + + + PSC + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + CLKSEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + HIRC + The internal 96 MHz oscillator is used for the system clock. + 0 + + + nanoRing + The nano-ring output is used for the system clock. + 3 + + + hfxIn + HFXIN is used for the system clock. + 6 + + + + + CLKRDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + X32K_EN + 32kHz Crystal Oscillator Enable. + 17 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + HIRC_EN + 60MHz High Frequency Internal Reference Clock Enable. + 18 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + X32K_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + read-only + + + not + Not Ready + 0 + + + Ready + X32K Ready + 1 + + + + + HIRC_RDY + 60MHz HIRC Ready. + 26 + 1 + + + not + Not Ready + 0 + + + ready + HIRC Ready + 1 + + + + + LIRC8K_RDY + 8kHz Low Frequency Reference Clock Ready. + 29 + 1 + + + not + Not Ready + 0 + + + ready + Clock Ready + 1 + + + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 3 + + + active + Active Mode. + 0 + + + shutdown + Shutdown Mode. + 3 + + + backup + Backup Mode. + 4 + + + + + GPIOWK_EN + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + dis + Wake Up Disable. + 0 + + + en + Wake Up Enable. + 1 + + + + + RTCWK_EN + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + dis + Wake Up Disable. + 0 + + + en + Wake Up Enable. + 1 + + + + + HFIOPD + HFIO DEEPSLEEP Auto Off. When set, the High-Frequency Internal Oscillator is automatically powered off when in DEEPSLEEP mode. + 15 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + + + PCLK_DIS0 + Peripheral Clock Disable. + 0x24 + + + GPIO0D + GPIO0 Disable. + 0 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + DMAD + DMA Disable. + 5 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + SPI0D + SPI 0 Disable. + 6 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + SPI1D + SPI 1 Disable. + 7 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + UART0D + UART 0 Disable. + 9 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + UART1D + UART 1 Disable. + 10 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + I2C0D + I2C 0 Disable. + 13 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + TIMER0D + Timer 0 Disable. + 15 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + TIMER1D + Timer 1 Disable. + 16 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + TIMER2D + Timer 2 Disable. + 17 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + I2C1D + I2C 1 Disable. + 28 + 1 + + GPIODisable + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + + + MEM_CTRL + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + RAM0_LS + System RAM 0 Light Sleep Mode. + 8 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + RAM1_LS + System RAM 1 Light Sleep Mode. + 9 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + RAM2_LS + System RAM 2 Light Sleep Mode. + 10 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + RAM3_LS + System RAM 3 Light Sleep Mode. + 11 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + ICACHE_RET + ICache RAM Light Sleep Mode. + 12 + 1 + + + active + Memory is active. + 0 + + + light_sleep + Memory is in Light Sleep mode. + 1 + + + + + + + MEM_ZCTRL + Memory Zeroize Control. + 0x2C + + + SRAM_ZERO + System RAM Block 0. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ICACHE_ZERO + Instruction Cache. + 1 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + + + SYS_STAT + System Status Register. + 0x40 + + + ICECLOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + + + RST1 + Reset 1. + 0x44 + + + I2C1 + I2C1 Reset. + 0 + 1 + + reset_write + write + + RFU + Reserved. Do not use. + 0 + + + reset + Starts reset operation. + 1 + + + + reset_read + read + + reset_done + Reset complete. + 0 + + + busy + Reset in progress. + 1 + + + + + + + PCLK_DIS1 + Peripheral Clock Disable. + 0x48 + + + FLCD + Secure Flash Controller Disable. + 3 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + ICCD + ICache Clock Disable. + 11 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + + + EVTEN + Event Enable Register. + 0x4C + + + DMAEVENT + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + RX_EVT + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + + + REV + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYS_IE + System Status Interrupt Enable + 0x54 + + + ICEULIE + Arm ICE Unlocked Interrupt Enable. Set this bit to enable a PWRSEQ IRQ if the Arm ICE is unlocked. + 0 + 1 + + + + + + + + SIR + System Initialization Registers. + 0x40000400 + read-only + + 0x00 + 0x400 + registers + + + + STATUS + System Initialization Status Register. + 0x00 + read-only + + + CFG_VALID + Configuration Valid Flag. This field is set to 1 by hardware during reset if the device configuration is valid. + 0 + 1 + read-only + + read + + invalid + config invalid + 0 + + + valid + config valid + 1 + + + + + CFG_ERR + Configuration Error Flag. This field is set by hardware during reset if an error in the device configuration is detected + 1 + 1 + read-only + + read + + valid + config valid + 0 + + + invalid + config invalid + 1 + + + + + + + ADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x04 + read-only + + + ADDR + 0 + 32 + + + + + + + + FCR + Function Control. + 0x40000800 + + 0x00 + 0x400 + registers + + + + REG0 + Register 0. + 0x00 + read-write + + + I2C0_SDA_FILTER_EN + I2C0 SDA Filter Enable + 20 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C0_SCL_FILTER_EN + I2C0 SCL Filter Enable + 21 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C1_SDA_FILTER_EN + I2C1 SDA Filter Enable + 22 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C1_SCL_FILTER_EN + I2C1 SCL Filter Enable + 23 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + + + + + + WDT0 + Watchdog Timer 0 + 0x40003000 + + 0x00 + 0x0400 + registers + + + WDT0 + 1 + + + + CTRL + Watchdog Timer Control Register. + 0x00 + 0x7FFFF000 + + + INT_PERIOD + Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 0 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_PERIOD + Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 4 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + WDT_EN + Watchdog Timer Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_FLAG + Watchdog Timer Interrupt Flag. + 9 + 1 + oneToClear + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + INT_EN + Watchdog Timer Interrupt Enable. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_EN + Watchdog Timer Reset Enable. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RST_FLAG + Watchdog Timer Reset Flag. + 31 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + RST + Watchdog Timer Reset Register. + 0x04 + write-only + + + WDT_RST + Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled. + 0 + 8 + + + seq0 + The first value to be written to reset the WDT. + 0x000000A5 + + + seq1 + The second value to be written to reset the WDT. + 0x0000005A + + + + + + + + + + RTC + Real Time Clock and Alarm. + 0x40006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + RTSS + RTC Sub-second Counter. + 0 + 8 + + + + + RAS + Time-of-day Alarm. + 0x08 + 0x00000000 + + + RAS + Time-of-day Alarm. + 0 + 20 + + + + + RSSA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + RSSA + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + RTCE + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ADE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ASE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDYE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + ALDF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + ALSF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + SQE + Square Wave Output Enable. + 8 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + FT + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + clkDiv8 + RTC Input Clock / 8. + 3 + + + + + X32KMD + 32KHz Oscillator Mode. + 11 + 2 + + + noiseImmuneMode + Always operate in Noise Immune Mode. Oscillator warm-up required. + 0 + + + quietMode + Always operate in Quiet Mode. No oscillator warm-up required. + 1 + + + quietInStopWithWarmup + Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit. + 2 + + + quietInStopNoWarmup + Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit. + 3 + + + + + WE + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + inactive + Not active + 0 + + + Pending + Active + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VBATTMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FLITER_EN + RTC Oscillator Filter Enable + 0 + 1 + + + IBIAS_SEL + RTC Oscillator 4X Bias Current Select + 1 + 1 + + + 2X + Selects 2X bias current for RTC oscillator + 0 + + + 4X + Selects 4X bias current for RTC oscillator + 1 + + + + + HYST_EN + RTC Oscillator Hysteresis Buffer Enable + 2 + 1 + + + IBIAS_EN + RTC Oscillator Bias Current Enable + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + OUT32K + RTC 32kHz Square Wave Output + 5 + 1 + + + + + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40006800 + + 0x00 + 0x800 + registers + + + + LP_CTRL + Low Power Control Register. + 0x00 + + + RAMRET_SEL0 + System RAM 0 Data retention in BACKUP mode. + 0 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL1 + System RAM 1 Data retention in BACKUP mode. + 1 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL2 + System RAM 2 Data retention in BACKUP mode. + 2 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RAMRET_SEL3 + System RAM 3 Data retention in BACKUP mode. + 3 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + OVR + Operating Voltage Range + 4 + 2 + + + 0_9V + 0.9V 24MHz + 0 + + + 1_0V + 1.0V 48MHz + 1 + + + 1_1V + 1.1V 96MHz + 2 + + + + + VCORE_DET_BYPASS + Bypass V CORE External Supply Detection + 6 + 1 + + + enabled + enable + 0 + + + Disable + disable + 1 + + + + + RETREG_EN + Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. + 8 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + FAST_WK_EN + Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. + 10 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + BG_OFF + Band Gap Disable for DEEPSLEEP and BACKUP Mode + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode(default). + 1 + + + + + VCORE_POR_DIS + V CORE POR Disable for DEEPSLEEP and BACKUP Mode + 12 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + LDO_DIS + LDO Disable + 16 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VCORE_SVM_DIS + V CORE Supply Voltage Monitor Disable + 20 + 1 + + + en + Enable if Bandgap is ON(default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIO_POR_DIS + VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods. + 25 + 1 + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + + + LP_WAKEFL + Low Power Mode Wakeup Flags for GPIO0 + 0x04 + + + WAKEST + Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode. + 0 + 14 + + + + + LPWK_EN + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + WAKEEN + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 14 + + + + + LPMEMSD + Low Power Memory Shutdown Control. + 0x40 + + + SRAM0_OFF + System RAM block 0 Shut Down. + 0 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM1_OFF + System RAM block 1 Shut Down. + 1 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM2_OFF + System RAM block 2 Shut Down. + 2 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRAM3_OFF + System RAM block 3 Shut Down. + 3 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + GPIO_EN + Mask of all of the pins on the port. + 0 + 32 + + + alternate + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT_EN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + GPIO_OUT_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUT_EN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT_EN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + GPIO_OUT + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + GPIO_OUT_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + GPIO_OUT_CLR + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + GPIO_IN + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_MOD + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + GPIO_INT_MOD + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INT_POL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + GPIO_INT_POL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + IN_EN + GPIO Port Input Enable. + 0x30 + + + GPIO_IN_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Input Disable + 0 + + + en + GPIO Input Enable + 1 + + + + + + + INT_EN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + GPIO_INT_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INT_EN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + GPIO_INT_EN_SET + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INT_EN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + GPIO_INT_EN_CLR + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INT_STAT + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + GPIO_INT_STAT + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INT_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + GPIO_WAKE_EN + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WAKE_EN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WAKE_EN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INT_DUAL_EDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + GPIO_INT_DUAL_EDGE + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PAD_CFG1 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + + + GPIO_PAD_CFG1 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + PAD_CFG2 + GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + + + GPIO_PAD_CFG2 + The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + GPIO_EN1 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + GPIO_EN2 + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DS0 + GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + PS + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + + TMR0 + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + 5 + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: + In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: + In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. + 0 + 32 + + + + + INTR + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ + Interrupt Flag for Timer A. + 0 + 1 + + + + + CN + Timer Control Register. + 0x10 + read-write + + + TMODE + Mode Select + 0 + 3 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + + + PRES + Timer Prescaler Select + 3 + 3 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + + + TPOL + Timer Polarity + 6 + 1 + + + TEN + Timer Enable + 7 + 1 + + + PRES3 + Timer Prescale Select MSB + 8 + 1 + + + PWMSYNC + PWM Synchronization Mode + 9 + 1 + + + NOLHPOL + PWM Phase A (Non-Overlapping High) Polarity + 10 + 1 + + + NOLLPOL + PWM Phase A-prime (Non-Overlapping Low) Polarity + 11 + 1 + + + PWMCKBD + PWM Phase A-Prime Output Disable + 12 + 1 + + + + + + + + TMR1 + Low-Power Configurable Timer 1 + 0x40011000 + + TMR1 + TMR1 IRQ + 6 + + + + + TMR2 + Low-Power Configurable Timer 2 + 0x40012000 + + TMR2 + TMR2 IRQ + 7 + + + + + SPIMSS + Serial Peripheral Interface. + SPIMSS + 0x40019000 + + 0x00 + 0x1000 + registers + + + + DATA + SPI 16-bit Data Access + 0x00 + 16 + read-write + + + DATA + SPI data. + 0 + 16 + + + + + CTRL + SPI Control Register. + 0x04 + + + ENABLE + SPI Enable. + 0 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + MMEN + SPI Master Mode Enable. + 1 + 1 + + slv_mst_enum + + slave + 0 + + + master + 1 + + + + + WOR + Wired OR (open drain) Enable. + 2 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + CLKPOL + Clock Polarity. + 3 + 1 + + spi_pol_enum + + idleLo + SCLK idles Low (0) after character transmission/reception. + 0 + + + idleHi + SCLK idles High (1) after character transmission/reception. + 1 + + + + + PHASE + Phase Select. + 4 + 1 + + spi_phase_enum + + activeEdge + Transmit on active edge of SCLK. + 0 + + + inactiveEdge + Transmit on inactive edge of SCLK. + 1 + + + + + BIRQ + Baud Rate Generator Timer Interrupt Request. + 5 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + STR + Start SPI Interrupt. + 6 + 1 + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + IRQE + Interrupt Request Enable. + 7 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + + + INT_FL + SPI Interrupt Flag Register. + 0x08 + 0x00000001 + + + SLAS + Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning. + 0 + 1 + read-only + + sel_enum + + selected + 0 + + + notSelected + 1 + + + + + TXST + Transmit Status. + 1 + 1 + read-only + + busy_enum + + idle + 0 + + + busy + 1 + + + + + TUND + Transmit Underrun. + 2 + 1 + oneToClear + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + ROVR + Receive Overrun. + 3 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + ABT + Slave Mode Transaction Abort. + 4 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + COL + Collision. + 5 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + TOVR + Transmit Overrun. + 6 + 1 + + event_flag_enum + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + IRQ + SPI Interrupt Request. + 7 + 1 + oneToClear + + flag_enum + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + + + MODE + SPI Mode Register. + 0x0C + + + SSV + Slave Select Value. + 0 + 1 + + lo_hi_enum + + lo + The SSEL pin will be driven low. + 0 + + + hi + The SSEL pin will be driven high. + 1 + + + + + SS_IO + Slave Select I/O. + 1 + 1 + + input_output_enum + + input + 0 + + + output + 1 + + + + + NUMBITS + 2 + 4 + + spi_bits_enum + + bits16 + 0 + + + bits1 + 1 + + + bits2 + 2 + + + bits3 + 3 + + + bits4 + 4 + + + bits5 + 5 + + + bits6 + 6 + + + bits7 + 7 + + + bits8 + 8 + + + bits9 + 9 + + + bits10 + 10 + + + bits11 + 11 + + + bits12 + 12 + + + bits13 + 13 + + + bits14 + 14 + + + bits15 + 15 + + + + + TX_LJ + Transmit Left Justify. + 7 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + + + BRG + Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4). + 0x14 + 0x0000FFFF + + + DIV + Baud Rate Reload Value. + 0 + 16 + + + + + DMA + SPI DMA Register. + 0x18 + 0x00070007 + + + TX_FIFO_LVL + Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs. + 0 + 3 + + fifo_level_enum + + entry1 + 0 + + + entries2 + 1 + + + entries3 + 2 + + + entries4 + 3 + + + entries5 + 4 + + + entries6 + 5 + + + entries7 + 6 + + + entries8 + 7 + + + + + TX_FIFO_CLR + Transmit FIFO Clear. + 4 + 1 + write-only + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + TX_FIFO_CNT + Transmit FIFO Count. + 8 + 4 + read-only + + + TX_DMA_EN + Transmit DMA Enable. + 15 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + RX_FIFO_LVL + Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request. + 16 + 3 + + fifo_level_enum + + entry1 + 0 + + + entries2 + 1 + + + entries3 + 2 + + + entries4 + 3 + + + entries5 + 4 + + + entries6 + 5 + + + entries7 + 6 + + + entries8 + 7 + + + + + RX_FIFO_CLR + Receive FIFO Clear. + 20 + 1 + + start_op_enum + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + RX_FIFO_CNT + Receive FIFO Count. + 24 + 4 + read-only + + + RX_DMA_EN + Receive DMA Enable. + 31 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + + + I2S_CTRL + I2S Control Register. + 0x1C + + + I2S_EN + I2S Mode Enable. + 0 + 1 + + dis_en_enum + + disable + 0 + + + enable + 1 + + + + + I2S_MUTE + I2S Mute transmit. + 1 + 1 + + + normal + Normal Transmit. + 0 + + + replaced + Transmit data is replaced with 0. + 1 + + + + + I2S_PAUSE + I2S Pause transmit/receive. + 2 + 1 + + + normal + Normal Transmit. + 0 + + + halt + Halt transmit and receive FIFO and DMA access, transmit 0's. + 1 + + + + + I2S_MONO + I2S Monophonic Audio Mode. + 3 + 1 + + + stereophonic + Stereophonic audio. + 0 + + + monophonic + Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored. + 1 + + + + + I2S_LJ + I2S Left Justify. + 4 + 1 + + + normal + Normal I2S audio protocol. + 0 + + + replaced + Audio data is synchronized with SSEL. + 1 + + + + + + + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + + + CTRL0 + Control Register0. + 0x00 + + + I2CEN + I2C Enable. + [0:0] + read-write + + + dis + Disable I2C. + 0 + + + en + enable I2C. + 1 + + + + + MST + Master Mode Enable. + [1:1] + read-write + + + slave_mode + Slave Mode. + 0 + + + master_mode + Master Mode. + 1 + + + + + GCEN + General Call Address Enable. + [2:2] + read-write + + + dis + Ignore Gneral Call Address. + 0 + + + en + Acknowledge general call address. + 1 + + + + + IRXM + Interactive Receive Mode. + [3:3] + read-write + + + dis + Disable Interactive Receive Mode. + 0 + + + en + Enable Interactive Receive Mode. + 1 + + + + + ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. + [4:4] + read-write + + + ack + return ACK (pulling SDA LOW). + 0 + + + nack + return NACK (leaving SDA HIGH). + 1 + + + + + SCLO + SCL Output. This bits control SCL output when SWOE =1. + [6:6] + read-write + + + drive_scl_low + Drive SCL low. + 0 + + + release_scl + Release SCL. + 1 + + + + + SDAO + SDA Output. This bits control SDA output when SWOE = 1. + [7:7] + read-write + + + drive_sda_low + Drive SDA low. + 0 + + + release_sda + Release SDA. + 1 + + + + + SCL + SCL status. This bit reflects the logic gate of SCL signal. + [8:8] + read-only + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + SWOE + Software Output Enable. + [10:10] + read-write + + + outputs_disable + I2C Outputs SCLO and SDAO disabled. + 0 + + + outputs_enable + I2C Outputs SCLO and SDAO enabled. + 1 + + + + + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only + + + write + Write. + 0 + + + read + Read. + 1 + + + + + SCL_STRD + This bit will disable slave clock stretching when set. + [12:12] + read-write + + + en + Slave clock stretching enabled. + 0 + + + dis + Slave clock stretching disabled. + 1 + + + + + SCL_PPM + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write + + + dis + Standard open-drain operation: drive low for 0, Hi-Z for 1 + 0 + + + en + Non-standard push-pull operation: drive low for 0, drive high for 1 + 1 + + + + + HSMODE + Hs-mode Enable. + 15 + 1 + + + dis + Hs-mode disabled. + 0 + + + en + Hs-mode enabled. + 1 + + + + + + + STATUS + Status Register. + 0x04 + + + BUSY + Bus Status. + [0:0] + read-only + + + idle + I2C Bus Idle. + 0 + + + busy + I2C Bus Busy. + 1 + + + + + RXE + RX empty. + [1:1] + read-only + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + RXF + RX Full. + [2:2] + read-only + + + not_full + Not Full. + 0 + + + full + Full. + 1 + + + + + TXE + TX Empty. + [3:3] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + TXF + TX Full. + [4:4] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + CKMD + Clock Mode. + [5:5] + read-only + + + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. + 0 + + + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. + 1 + + + + + STAT + Controller Status. + [11:8] + + + idle + Controller Idle. + 0 + + + mtx_addr + master Transmit address. + 1 + + + mrx_addr_ack + Master Receive address ACK. + 2 + + + mtx_ex_addr + Master Transmit extended address. + 3 + + + mrx_ex_addr + Master Receive extended address ACK. + 4 + + + srx_addr + Slave Receive address. + 5 + + + stx_addr_ack + Slave Transmit address ACK. + 6 + + + srx_ex_addr + Slave Receive extended address. + 7 + + + stx_ex_addr_ack + Slave Transmit extended address ACK. + 8 + + + tx + Transmit data (master or slave). + 9 + + + rx_ack + Receive data ACK (master or slave). + 10 + + + rx + Receive data (master or slave). + 11 + + + tx_ack + Transmit data ACK (master or slave). + 12 + + + nack + NACK stage (master or slave). + 13 + + + by_st + Bystander state (ongoing transaction but not participant- another master addressing another slave). + 15 + + + + + + + INTFL0 + Interrupt Status Register. + 0x08 + + + DONEI + Transfer Done Interrupt. + [0:0] + + INT_FL0_Done + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + IRXMI + Interactive Receive Interrupt. + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + GCI + Slave General Call Address Match Interrupt. + [2:2] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + AMI + Slave Address Match Interrupt. + [3:3] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RXTHI + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + [4:4] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. + 1 + + + + + TXTHI + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. + [5:5] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + STOPI + STOP Interrupt. + [6:6] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + ADRACKI + Address Acknowledge Interrupt. + [7:7] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ARBERI + Arbritation error Interrupt. + [8:8] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TOERI + timeout Error Interrupt. + [9:9] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADRERI + Address NACK Error Interrupt. + [10:10] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DATERI + Data NACK Error Interrupt. + [11:11] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DNRERI + Do Not Respond Error Interrupt. + [12:12] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + STRTERI + Start Error Interrupt. + [13:13] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + STOPERI + Stop Error Interrupt. + [14:14] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TXLOI + Transmit Lock Out Interrupt. + [15:15] + + + + + INTEN0 + Interrupt Enable Register. + 0x0C + read-write + + + DONEIE + Transfer Done Interrupt Enable. + [0:0] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when DONE = 1. + 1 + + + + + IRXMIE + Description not available. + [1:1] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when RX_MODE = 1. + 1 + + + + + GCIE + Slave mode general call address match received input enable. + [2:2] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when GEN_CTRL_ADDR = 1. + 1 + + + + + AMIE + Slave mode incoming address match interrupt. + [3:3] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when ADDR_MATCH = 1. + 1 + + + + + RXTHIE + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TXTHIE + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOPIE + Stop Interrupt Enable + [6:6] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when STOP = 1. + 1 + + + + + ADRACKIE + Received Address ACK from Slave Interrupt. + [7:7] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ARBERIE + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TOERIE + Timeout Error Interrupt Enable. + [9:9] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ADRERIE + Master Mode Address NACK Received Interrupt. + [10:10] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DATERIE + Master Mode Data NACK Received Interrupt. + [11:11] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DNRERIE + Slave Mode Do Not Respond Interrupt. + [12:12] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STRTERIE + Out of Sequence START condition detected interrupt. + [13:13] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOPERIE + Out of Sequence STOP condition detected interrupt. + [14:14] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TXLOIE + TX FIFO Locked Out Interrupt. + [15:15] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when TXLOIE = 1. + 1 + + + + + + + INTFL1 + Interrupt Status Register 1. + 0x10 + + + RXOFI + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TXUFI + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + + + INTEN1 + Interrupt Staus Register 1. + 0x14 + read-write + + + RXOFIE + Receiver Overflow Interrupt Enable. + [0:0] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + TXUFIE + Transmit Underflow Interrupt Enable. + [1:1] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + + + FIFOLEN + FIFO Configuration Register. + 0x18 + + + RXLEN + Receive FIFO Length. + [7:0] + read-only + + + TXLEN + Transmit FIFO Length. + [15:8] + read-only + + + + + RXCTRL0 + Receive Control Register 0. + 0x1C + + + DNR + Do Not Respond. + [0:0] + + + respond + Always respond to address match. + 0 + + + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. + 1 + + + + + RXFSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush RX_FIFO. + 1 + + + + + RXTH + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] + + + + + RXCTRL1 + Receive Control Register 1. + 0x20 + + + RXCNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] + + + RXFIFO + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only + + + + + TXCTRL0 + Transmit Control Register 0. + 0x24 + + + TXPRELD + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] + + + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + + en + HW control of I2CTXRDY enabled. + 0 + + + dis + HW control of I2CTXRDY disabled. + 1 + + + + + TXFSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush TX_FIFO. + 1 + + + + + TXTH + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + + TXCTRL1 + Transmit Control Register 1. + 0x28 + + + TXRDY + Transmit FIFO Preload Ready. + [0:0] + + + TXLAST + Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware). + [1:1] + + + hold_scl_low + Hold SCL low on TX_FIFO empty. + 0 + + + end_transaction + End transaction on TX_FIFO empty. + 1 + + + + + FLSH_GCADDR_DIS + TX FIFO Auto Flush Disable on General Call Address Match.Setting this field to 1 disables the TX FIFO Automatic Flush when a General Call Address Match occurs. + + [2:2] + + + autoflush_en + The TX FIFO is automatically flushed on a General Call Address Match. + + 0 + + + autoflush_dis + The TX FIFO is not flushed on a General Call Address Match. + 1 + + + + + FLSH_SLADDR_DIS + TX FIFO Auto Flush Disable for Slave Address Match. +Setting this field to 1 disables the TX FIFO Automatic Flush when a Slave Address +Match occurs. + [4:4] + + + autoflush_en + The TX FIFO is automatically flushed on a Slave Address Match. + 0 + + + autoflush_dis + The TX FIFO is not flushed on a Slave Address Match. + 1 + + + + + FLSH_NACK_DIS + TX FIFO Auto Flush Disable for NACK. +Setting this field to 1 disables the TX FIFO Automatic Flush when a NACK is received at the end of a slave transaction. + + [5:5] + + + autoflush_en + The TX FIFO is automatically flushed if a NACK is received at the end of a slave +transaction. + 0 + + + autoflush_dis + The TX FIFO is not flushed when a NACK is received at the end of a slave +transaction. + 1 + + + + + TXFIFO + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + + FIFO + Data Register. + 0x2C + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + + MSTR_MODE + Master Control Register. + 0x30 + + + START + Setting this bit to 1 will start a master transfer. + [0:0] + + + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] + + + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] + + + SEA + Slave Extend Address Select. + [7:7] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + CLKLO + Clock Low Register. + 0x34 + + + SCL_LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + + CLKHI + Clock high Register. + 0x38 + + + SCL_HI + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + + HS_CLK + HS-Mode Clock Control Register + 0x3C + + + HS_CLK_LO + Slave Address. + [7:0] + + + HS_CLK_HI + Slave Address. + [15:8] + + + + + TIMEOUT + Timeout Register + 0x40 + + + TO + Timeout + [15:0] + + + + + SLADDR + Slave Address Register. + 0x44 + + + SLA + Slave Address. + [9:0] + + + EA + Extended Address Select. + [15:15] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + DMA + DMA Register. + 0x48 + + + TXEN + TX channel enable. + [0:0] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RXEN + RX channel enable. + [1:1] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + I2C1 + Inter-Integrated Circuit. 1 + 0x4001E000 + + I2C1 + I2C1 IRQ + 36 + + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0 + 28 + + + DMA1 + 29 + + + DMA2 + 30 + + + DMA3 + 31 + + + + INT_EN + DMA Control Register. + 0x000 + + + CHIEN + Channel Interrupt Enable. + 0 + 4 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + INT_FL + DMA Interrupt Register. + 0x004 + read-only + + + IPEND + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. + 0 + 4 + + ch_ipend_enum + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + + + 4 + 4 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CFG + DMA Channel Configuration Register. + 0x100 + + + CHEN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQSEL + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPI0RX + SPI0 RX + 0x01 + + + SPI1RX + SPI1 RX + 0x02 + + + UART0RX + UART0 RX + 0x04 + + + UART1RX + UART1 RX + 0x05 + + + I2C0RX + I2C0 RX + 0x07 + + + I2C1RX + I2C1 RX + 0x08 + + + SPI0TX + SPI0 TX + 0x21 + + + SPI1TX + SPI1 TX + 0x22 + + + UART0TX + UART0 TX + 0x24 + + + UART1TX + UART1 TX + 0x25 + + + I2C0TX + I2C0 TX + 0x27 + + + I2C1TX + I2C1 TX + 0x28 + + + + + REQWAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOSEL + Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + PSSEL + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BRST + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + CHDIEN + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZIEN + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + STAT + DMA Channel Status Register. + 0x104 + + + CH_ST + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_ST + Count-to-Zero (CTZ) Status + 2 + 1 + oneToClear + + ctz_st_enum_rd + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + ctz_st_enum_wr + write + + Clear + Clears the interrupt flag + 1 + + + + + RLD_ST + Reload Status. + 3 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + TO_ST + Time-Out Status. + 6 + 1 + oneToClear + + read + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + write + + Clear + Clears the interrupt flag + 1 + + + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x108 + + + SRC + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x10C + + + DST + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x110 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRC_RLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x114 + + + SRC_RLD + Source Address Reload Value. + 0 + 31 + + + + + DST_RLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x118 + + + DST_RLD + Destination Address Reload Value. + 0 + 31 + + + + + CNT_RLD + DMA Channel Count Reload Register. + 0x11C + + + CNT_RLD + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + RLDEN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + + FLC + Flash Memory Control. + FLC_ + 0x40029000 + + 0x00 + 0x1000 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CTRL + Flash Control Register. + 0x08 + + + WRITE + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + MASS_ERASE + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PAGE_ERASE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + WIDTH + Data Width. This bits selects write data width. + 4 + 1 + + + size128 + 128-bit. + 0 + + + size32 + 32-bit. + 1 + + + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + BUSY + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + LVE + Low Voltage enable. + 25 + 1 + + + UNLOCK_CODE + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked. + 2 + + + locked + Flash Locked. + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ACCESS_FAIL + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONE_IE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + ACCESS_FAIL_IE + 9 + 1 + + + + + 4 + 4 + DATA + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACTRL + Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: + pflc-actrl = 0x3a7f5ca3; + pflc-actrl = 0xa1e34f20; + pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACTRL + Access control. + 0 + 32 + + + + + + + + ICC0 + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x1000 + registers + + + + CACHE_ID + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + CCHID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + MEM_SIZE + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCHSZ + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEMSZ + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CACHE_CTRL + Cache Control and Status Register. + 0x0100 + + + ENABLE + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + READY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + + + + + + UART0 + UART + 0x40042000 + + 0 + 0x1000 + registers + + + UART0 + UART0 IRQ + 14 + + + + CTRL0 + Control Register. + 0x00 + 32 + + + ENABLE + UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled. + 0 + 1 + + + dis + UART disabled. FIFOs are flushed. Clock is gated off for power savings. + 0 + + + en + UART enabled. + 1 + + + + + PARITY_EN + Enable/disable Parity bit (9th character). + 1 + 1 + + + dis + No Parity + 0 + + + en + Parity enabled as 9th bit + 1 + + + + + PARITY_MODE + When PARITY_EN=1, selects odd, even, Mark or Space parity. + Mark parity = always 1; Space parity = always 0. + 2 + 2 + + + Even + Even parity selected. + 0 + + + ODD + Odd parity selected. + 1 + + + MARK + Mark parity selected. + 2 + + + SPACE + Space parity selected. + 3 + + + + + PARITY_LVL + Selects parity based on 1s or 0s count (when PARITY_EN=1). + 4 + 1 + + + 1 + Parity calculation is based on number of 1s in frame. + 0 + + + 0 + Parity calculation is based on number of 0s in frame. + 1 + + + + + TXFLUSH + Flushes the TX FIFO buffer. + 5 + 1 + + + RXFLUSH + Flushes the RX FIFO buffer. + 6 + 1 + + + BITACC + If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation. + 7 + 1 + + + FRAME + Frame accuracy. + 0 + + + BIT + Bit accuracy. + 1 + + + + + SIZE + Selects UART character size. + 8 + 2 + + + 5 + 5 bits. + 0 + + + 6 + 6 bits. + 1 + + + 7 + 7 bits. + 2 + + + 8 + 8 bits. + 3 + + + + + STOP + Selects the number of stop bits that will be generated. + 10 + 1 + + + 1 + 1 stop bit. + 0 + + + 1_5 + 1.5 stop bits. + 1 + + + + + FLOW + Enables/disables hardware flow control. + 11 + 1 + + + en + HW Flow Control with RTS/CTS enabled + 1 + + + dis + HW Flow Control disabled + 0 + + + + + FLOWPOL + RTS/CTS polarity. + 12 + 1 + + + 0 + RTS/CTS asserted is logic 0. + 0 + + + 1 + RTS/CTS asserted is logic 1. + 1 + + + + + NULLMOD + NULL Modem Support (RTS/CTS and TXD/RXD swap). + 13 + 1 + + + DIS + Direct convention. + 0 + + + EN + Null Modem Mode. + 1 + + + + + BREAK + Break control bit. It causes a break condition to be transmitted to receiving UART. + 14 + 1 + + + DIS + Break characters are not generated. + 0 + + + EN + Break characters are sent(all the bits are at '0' including start/parity/stop). + 1 + + + + + CLK_SEL + Baud Rate Clock Source Select. Selects the baud rate clock. + 15 + 1 + + + SYSTEM + System clock. + 0 + + + ALTERNATE + Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow. + 1 + + + + + TO_CNT + RX Time Out. RX time out interrupt will occur after RXTO Uart + characters if RX-FIFO is not empty and RX FIFO has not been read. + 16 + 8 + + + + + CTRL1 + Threshold Control register. + 0x04 + 32 + + + RX_FIFO_LVL + RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set. + 0 + 6 + + + TX_FIFO_LVL + TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set. + 8 + 6 + + + RTS_FIFO_LVL + RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART. + 16 + 6 + + + + + STAT + Status Register. + 0x08 + 32 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status. + 0 + 1 + read-only + + + RX_BUSY + Read-only flag indicating the UARTreceiver status. + 1 + 1 + read-only + + + PARITY + 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3. + 2 + 1 + read-only + + + BREAK + Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits). + 3 + 1 + read-only + + + RX_EMPTY + Read-only flag indicating the RX FIFO state. + 4 + 1 + read-only + + + RX_FULL + Read-only flag indicating the RX FIFO state. + 5 + 1 + read-only + + + TX_EMPTY + Read-only flag indicating the TX FIFO state. + 6 + 1 + read-only + + + TX_FULL + Read-only flag indicating the TX FIFO state. + 7 + 1 + read-only + + + RX_NUM + Indicates the number of bytes currently in the RX FIFO. + 8 + 6 + read-only + + + TX_NUM + Indicates the number of bytes currently in the TX FIFO. + 16 + 6 + read-only + + + RX_TO + RX Timeout status. + 24 + 1 + read-only + + + + + INT_EN + Interrupt Enable Register. + 0x0C + 32 + + + RX_FRAME_ERROR + Enable for RX Frame Error Interrupt. + 0 + 1 + + + RX_PARITY_ERROR + Enable for RX Parity Error interrupt. + 1 + 1 + + + CTS + Enable for CTS signal change interrupt. + 2 + 1 + + + RX_OVERRUN + Enable for RX FIFO OVerrun interrupt. + 3 + 1 + + + RX_FIFO_LVL + Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + 4 + 1 + + + TX_FIFO_AE + Enable for interrupt when TX FIFO has only one byte remaining. + 5 + 1 + + + TX_FIFO_LVL + Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. + 6 + 1 + + + BREAK + Enable for received BREAK character interrupt. + 7 + 1 + + + RX_TO + Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). + 8 + 1 + + + LAST_BREAK + Enable for Last break character interrupt. + 9 + 1 + + + + + INT_FL + Interrupt Status Flags. + 0x10 + 32 + oneToClear + + + FRAME + FLAG for RX Frame Error Interrupt. + 0 + 1 + + + PARITY + FLAG for RX Parity Error interrupt. + 1 + 1 + + + CTS + FLAG for CTS signal change interrupt. + 2 + 1 + + + RX_OVR + FLAG for RX FIFO Overrun interrupt. + 3 + 1 + + + RX_FIFO_LVL + FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + 4 + 1 + + + TX_FIFO_AE + FLAG for interrupt when TX FIFO has only one byte remaining. + 5 + 1 + + + TX_FIFO_LVL + FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field. + 6 + 1 + + + BREAK + FLAG for received BREAK character interrupt. + 7 + 1 + + + RX_TO + FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO). + 8 + 1 + + + LAST_BREAK + FLAG for Last break character interrupt. + 9 + 1 + + + + + BAUD0 + Baud rate register. Integer portion. + 0x14 + 32 + + + IBAUD + Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency). + 0 + 12 + + + CLKDIV + FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR. + 16 + 3 + + + 128 + Baud Factor 128 + 0 + + + 64 + Baud Factor 64 + 1 + + + 32 + Baud Factor 32 + 2 + + + 16 + Baud Factor 16 + 3 + + + 8 + Baud Factor 8 + 4 + + + + + + + BAUD1 + Baud rate register. Decimal Setting. + 0x18 + 32 + + + DBAUD + Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128. + 0 + 12 + + + + + FIFO + FIFO Data buffer. + 0x1C + 32 + + + FIFO + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + + + DMA + DMA Configuration. + 0x20 + 32 + + + TXDMA_EN + TX DMA channel enable. + 0 + 1 + + + dis + DMA is disabled + 0 + + + en + DMA is enabled + 1 + + + + + RXDMA_EN + RX DMA channel enable. + 1 + 1 + + + dis + DMA is disabled + 0 + + + en + DMA is enabled + 1 + + + + + TXDMA_LVL + TX threshold for DMA transmission. + 8 + 6 + + + RXDMA_LVL + RX threshold for DMA transmission. + 16 + 6 + + + + + TXFIFO + Transmit FIFO Status register. + 0x24 + 32 + + + DATA + Reading from this field returns the next character available at the + output of the TX FIFO (if one is available, otherwise 00h is returned). + 0 + 7 + + + + + + + + UART1 + UART 1 + 0x40043000 + + UART1 + UART1 IRQ + 15 + + + + + SPI0 + SPI peripheral. + 0x400BE000 + + 0x00 + 0x1000 + registers + + + SPI0 + 56 + + + + DATA + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + SPI_EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + MM_EN + Master Mode Enable. + 1 + 1 + + + dis + SPI is Slave mode. + 0 + + + en + SPI is Master mode. + 1 + + + + + SS_IO + Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + 4 + 1 + + + output + Slave select 0 is output. + 0 + + + input + Slave Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + 1 + + + + + SS_CTRL + Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Slave Select at the end of a transaction. + 0 + + + ASSERT + SPI leaves Slave Select asserted at the end of a transaction. + 1 + + + + + SS_SEL + Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + 16 + 4 + + + SS0 + SS0 is selected. + 0x1 + + + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + SS3 + SS3 is selected. + 0x8 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CLK_PHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CLK_POL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + NUM_BITS + Number of Bits per character. + 8 + 4 + + + 0 + 16 bits per character. + 0 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + SS_POL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 1 + + + SS0_low + SS1 active low. + 0x0 + + + SS0_high + SS0 active high. + 0x1 + + + + + + + SS_TIME + Register for controlling SPI peripheral/Slave Select Timing. + 0x10 + read-write + + + SSACT1 + Slave Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + + + + SSACT2 + Slave Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + + + + SSINACT + Slave Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLK_CFG + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + SCALE + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_FIFO_LEVEL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FIFO_CLEAR + Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_FIFO_CNT + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_DMA_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_FIFO_LEVEL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FIFO_CLEAR + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_FIFO_CNT + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_DMA_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INT_FL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_LEVEL + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_LEVEL + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSA + Slave Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSD + Slave Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Slave Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + M_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OVR + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UND + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OVR + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UND + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INT_EN + Register for enabling interrupts. + 0x24 + read-write + + + TX_LEVEL + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EMPTY + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_LEVEL + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSA + Slave Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSD + Slave Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Master Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Slave Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + M_DONE + Master Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OVR + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UND + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OVR + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UND + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WAKE_FL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_LEVEL + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_LEVEL + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WAKE_EN + Register for wake up enable. + 0x2C + read-write + + + TX_LEVEL + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EMPTY + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_LEVEL + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STAT + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + + \ No newline at end of file diff --git a/Project/SDK/Device/Include/arm_common_tables.h b/Project/SDK/Device/Include/arm_common_tables.h new file mode 100644 index 0000000..fa60a62 --- /dev/null +++ b/Project/SDK/Device/Include/arm_common_tables.h @@ -0,0 +1,100 @@ +/** + * @file arm_common_tables.h + * @brief External declaration for common tables like Bitreverse, reciprocal etc. + */ + +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + + + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/Project/SDK/Device/Include/arm_const_structs.h b/Project/SDK/Device/Include/arm_const_structs.h new file mode 100644 index 0000000..8d7fac0 --- /dev/null +++ b/Project/SDK/Device/Include/arm_const_structs.h @@ -0,0 +1,85 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH + }; + + const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH + }; + +#endif diff --git a/Project/SDK/Device/Include/arm_math.h b/Project/SDK/Device/Include/arm_math.h new file mode 100644 index 0000000..65304c1 --- /dev/null +++ b/Project/SDK/Device/Include/arm_math.h @@ -0,0 +1,7306 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Copyright Notice + * + * Copyright (C) 2010-2013 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 

+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR + #define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR + #define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/Project/SDK/Device/Include/bbfc_regs.h b/Project/SDK/Device/Include/bbfc_regs.h new file mode 100644 index 0000000..3b0a1d1 --- /dev/null +++ b/Project/SDK/Device/Include/bbfc_regs.h @@ -0,0 +1,127 @@ +/** + * @file bbfc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _BBFC_REGS_H_ +#define _BBFC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup bbfc + * @defgroup bbfc_registers BBFC_Registers + * @brief Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module. + * @details Battery-Backed Function Control. + */ + +/** + * @ingroup bbfc_registers + * Structure type to access the BBFC Registers. + */ +typedef struct { + __IO uint32_t bbfcr0; /**< \b 0x00: BBFC BBFCR0 Register */ +} mxc_bbfc_regs_t; + +/* Register offsets for module BBFC */ +/** + * @ingroup bbfc_registers + * @defgroup BBFC_Register_Offsets Register Offsets + * @brief BBFC Peripheral Register Offsets from the BBFC Base Peripheral Address. + * @{ + */ + #define MXC_R_BBFC_BBFCR0 ((uint32_t)0x00000000UL) /**< Offset from BBFC Base Address: 0x0000 */ +/**@} end of group bbfc_registers */ + +/** + * @ingroup bbfc_registers + * @defgroup BBFC_BBFCR0 BBFC_BBFCR0 + * @brief Function Control Register 0. + * @{ + */ + #define MXC_F_BBFC_BBFCR0_CKPDRV_POS 0 /**< BBFCR0_CKPDRV Position */ + #define MXC_F_BBFC_BBFCR0_CKPDRV ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKPDRV_POS)) /**< BBFCR0_CKPDRV Mask */ + + #define MXC_F_BBFC_BBFCR0_CKNPDRV_POS 4 /**< BBFCR0_CKNPDRV Position */ + #define MXC_F_BBFC_BBFCR0_CKNPDRV ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKNPDRV_POS)) /**< BBFCR0_CKNPDRV Mask */ + + #define MXC_F_BBFC_BBFCR0_RDSDLLEN_POS 8 /**< BBFCR0_RDSDLLEN Position */ + #define MXC_F_BBFC_BBFCR0_RDSDLLEN ((uint32_t)(0x1UL << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS)) /**< BBFCR0_RDSDLLEN Mask */ + #define MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS ((uint32_t)0x0UL) /**< BBFCR0_RDSDLLEN_DIS Value */ + #define MXC_S_BBFC_BBFCR0_RDSDLLEN_DIS (MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_DIS Setting */ + #define MXC_V_BBFC_BBFCR0_RDSDLLEN_EN ((uint32_t)0x1UL) /**< BBFCR0_RDSDLLEN_EN Value */ + #define MXC_S_BBFC_BBFCR0_RDSDLLEN_EN (MXC_V_BBFC_BBFCR0_RDSDLLEN_EN << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_EN Setting */ + +/**@} end of group BBFC_BBFCR0_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BBFC_REGS_H_ */ diff --git a/Project/SDK/Device/Include/bbsir_regs.h b/Project/SDK/Device/Include/bbsir_regs.h new file mode 100644 index 0000000..cac7b0a --- /dev/null +++ b/Project/SDK/Device/Include/bbsir_regs.h @@ -0,0 +1,111 @@ +/** + * @file bbsir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _BBSIR_REGS_H_ +#define _BBSIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup bbsir + * @defgroup bbsir_registers BBSIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module. + * @details Battery-Backed Registers. + */ + +/** + * @ingroup bbsir_registers + * Structure type to access the BBSIR Registers. + */ +typedef struct { + __IO uint32_t rsv0; /**< \b 0x00: BBSIR RSV0 Register */ + __R uint32_t rsv_0x4; + __I uint32_t bb_sir2; /**< \b 0x08: BBSIR BB_SIR2 Register */ + __I uint32_t bb_sir3; /**< \b 0x0C: BBSIR BB_SIR3 Register */ +} mxc_bbsir_regs_t; + +/* Register offsets for module BBSIR */ +/** + * @ingroup bbsir_registers + * @defgroup BBSIR_Register_Offsets Register Offsets + * @brief BBSIR Peripheral Register Offsets from the BBSIR Base Peripheral Address. + * @{ + */ + #define MXC_R_BBSIR_RSV0 ((uint32_t)0x00000000UL) /**< Offset from BBSIR Base Address: 0x0000 */ + #define MXC_R_BBSIR_BB_SIR2 ((uint32_t)0x00000008UL) /**< Offset from BBSIR Base Address: 0x0008 */ + #define MXC_R_BBSIR_BB_SIR3 ((uint32_t)0x0000000CUL) /**< Offset from BBSIR Base Address: 0x000C */ +/**@} end of group bbsir_registers */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BBSIR_REGS_H_ */ diff --git a/Project/SDK/Device/Include/core_cm3.h b/Project/SDK/Device/Include/core_cm3.h new file mode 100644 index 0000000..122c9aa --- /dev/null +++ b/Project/SDK/Device/Include/core_cm3.h @@ -0,0 +1,1627 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Project/SDK/Device/Include/core_cm4.h b/Project/SDK/Device/Include/core_cm4.h new file mode 100644 index 0000000..d65016c --- /dev/null +++ b/Project/SDK/Device/Include/core_cm4.h @@ -0,0 +1,1772 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/Project/SDK/Device/Include/core_cm4_simd.h b/Project/SDK/Device/Include/core_cm4_simd.h new file mode 100644 index 0000000..c0a9e54 --- /dev/null +++ b/Project/SDK/Device/Include/core_cm4_simd.h @@ -0,0 +1,671 @@ +/** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.20 + * @date 25. February 2013 + ******************************************************************************/ + +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLALD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SMLSLD(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/Project/SDK/Device/Include/core_cmFunc.h b/Project/SDK/Device/Include/core_cmFunc.h new file mode 100644 index 0000000..2859b7c --- /dev/null +++ b/Project/SDK/Device/Include/core_cmFunc.h @@ -0,0 +1,633 @@ +/** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + ******************************************************************************/ + +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** @ingroup CMSIS_Core_FunctionInterface + @defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** @brief Get Control Register + + This function returns the content of the Control Register. + + @return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** @brief Set Control Register + + This function writes the given value to the Control Register. + + @param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** @brief Get IPSR Register + + This function returns the content of the IPSR Register. + + @return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** @brief Get APSR Register + + This function returns the content of the APSR Register. + + @return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** @brief Get xPSR Register + + This function returns the content of the xPSR Register. + + @return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** @brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + @return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** @brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + @param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** @brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + @return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** @brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + @param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** @brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + @return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** @brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + @param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** @brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** @brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** @brief Get Base Priority + + This function returns the current value of the Base Priority register. + + @return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** @brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + @param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** @brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + @return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** @brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + @param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** @brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + @return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** @brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + @param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** @brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** @brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** @brief Get Control Register + + This function returns the content of the Control Register. + + @return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** @brief Set Control Register + + This function writes the given value to the Control Register. + + @param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** @brief Get IPSR Register + + This function returns the content of the IPSR Register. + + @return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** @brief Get APSR Register + + This function returns the content of the APSR Register. + + @return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** @brief Get xPSR Register + + This function returns the content of the xPSR Register. + + @return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** @brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + @return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** @brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + @param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** @brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + @return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** @brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + @param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** @brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + @return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** @brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + @param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** @brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** @brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** @brief Get Base Priority + + This function returns the current value of the Base Priority register. + + @return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** @brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + @param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** @brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + @return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** @brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + @param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** @brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + @return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** @brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + @param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/Project/SDK/Device/Include/core_cmInstr.h b/Project/SDK/Device/Include/core_cmInstr.h new file mode 100644 index 0000000..d213f0e --- /dev/null +++ b/Project/SDK/Device/Include/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/Project/SDK/Device/Include/dma_regs.h b/Project/SDK/Device/Include/dma_regs.h new file mode 100644 index 0000000..e60da8e --- /dev/null +++ b/Project/SDK/Device/Include/dma_regs.h @@ -0,0 +1,470 @@ +/** + * @file dma_regs.h + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _DMA_REGS_H_ +#define _DMA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup dma + * @defgroup dma_registers DMA_Registers + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @details DMA Controller Fully programmable, chaining capable DMA channels. + */ + +/** + * @ingroup dma_registers + * Structure type to access the DMA Registers. + */ +typedef struct { + __IO uint32_t cfg; /**< \b 0x100: DMA CFG Register */ + __IO uint32_t st; /**< \b 0x104: DMA ST Register */ + __IO uint32_t src; /**< \b 0x108: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x10C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x110: DMA CNT Register */ + __IO uint32_t src_rld; /**< \b 0x114: DMA SRC_RLD Register */ + __IO uint32_t dst_rld; /**< \b 0x118: DMA DST_RLD Register */ + __IO uint32_t cnt_rld; /**< \b 0x11C: DMA CNT_RLD Register */ +} mxc_dma_ch_regs_t; + +typedef struct { + __IO uint32_t cn; /**< \b 0x000: DMA CN Register */ + __I uint32_t intr; /**< \b 0x004: DMA INTR Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ +} mxc_dma_regs_t; + +/* Register offsets for module DMA */ +/** + * @ingroup dma_registers + * @defgroup DMA_Register_Offsets Register Offsets + * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. + * @{ + */ + #define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ + #define MXC_R_DMA_ST ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: 0x0104 */ + #define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: 0x0108 */ + #define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: 0x010C */ + #define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: 0x0110 */ + #define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: 0x0114 */ + #define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: 0x0118 */ + #define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: 0x011C */ + #define MXC_R_DMA_CN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ + #define MXC_R_DMA_INTR ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ + #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ +/**@} end of group dma_registers */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CN DMA_CN + * @brief DMA Control Register. + * @{ + */ + #define MXC_F_DMA_CN_CH0_IEN_POS 0 /**< CN_CH0_IEN Position */ + #define MXC_F_DMA_CN_CH0_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) /**< CN_CH0_IEN Mask */ + #define MXC_V_DMA_CN_CH0_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH0_IEN_DIS Value */ + #define MXC_S_DMA_CN_CH0_IEN_DIS (MXC_V_DMA_CN_CH0_IEN_DIS << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_DIS Setting */ + #define MXC_V_DMA_CN_CH0_IEN_EN ((uint32_t)0x1UL) /**< CN_CH0_IEN_EN Value */ + #define MXC_S_DMA_CN_CH0_IEN_EN (MXC_V_DMA_CN_CH0_IEN_EN << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_EN Setting */ + + #define MXC_F_DMA_CN_CH1_IEN_POS 1 /**< CN_CH1_IEN Position */ + #define MXC_F_DMA_CN_CH1_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) /**< CN_CH1_IEN Mask */ + + #define MXC_F_DMA_CN_CH2_IEN_POS 2 /**< CN_CH2_IEN Position */ + #define MXC_F_DMA_CN_CH2_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) /**< CN_CH2_IEN Mask */ + + #define MXC_F_DMA_CN_CH3_IEN_POS 3 /**< CN_CH3_IEN Position */ + #define MXC_F_DMA_CN_CH3_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) /**< CN_CH3_IEN Mask */ + +/**@} end of group DMA_CN_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INTR DMA_INTR + * @brief DMA Interrupt Register. + * @{ + */ + #define MXC_F_DMA_INTR_CH0_IPEND_POS 0 /**< INTR_CH0_IPEND Position */ + #define MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) /**< INTR_CH0_IPEND Mask */ + #define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH0_IPEND_INACTIVE Value */ + #define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_INACTIVE Setting */ + #define MXC_V_DMA_INTR_CH0_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH0_IPEND_PENDING Value */ + #define MXC_S_DMA_INTR_CH0_IPEND_PENDING (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_PENDING Setting */ + + #define MXC_F_DMA_INTR_CH1_IPEND_POS 1 /**< INTR_CH1_IPEND Position */ + #define MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) /**< INTR_CH1_IPEND Mask */ + + #define MXC_F_DMA_INTR_CH2_IPEND_POS 2 /**< INTR_CH2_IPEND Position */ + #define MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) /**< INTR_CH2_IPEND Mask */ + + #define MXC_F_DMA_INTR_CH3_IPEND_POS 3 /**< INTR_CH3_IPEND Position */ + #define MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) /**< INTR_CH3_IPEND Mask */ + +/**@} end of group DMA_INTR_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CFG DMA_CFG + * @brief DMA Channel Configuration Register. + * @{ + */ + #define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */ + #define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */ + #define MXC_V_DMA_CFG_CHEN_DIS ((uint32_t)0x0UL) /**< CFG_CHEN_DIS Value */ + #define MXC_S_DMA_CFG_CHEN_DIS (MXC_V_DMA_CFG_CHEN_DIS << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_DIS Setting */ + #define MXC_V_DMA_CFG_CHEN_EN ((uint32_t)0x1UL) /**< CFG_CHEN_EN Value */ + #define MXC_S_DMA_CFG_CHEN_EN (MXC_V_DMA_CFG_CHEN_EN << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_EN Setting */ + + #define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */ + #define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */ + #define MXC_V_DMA_CFG_RLDEN_DIS ((uint32_t)0x0UL) /**< CFG_RLDEN_DIS Value */ + #define MXC_S_DMA_CFG_RLDEN_DIS (MXC_V_DMA_CFG_RLDEN_DIS << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_DIS Setting */ + #define MXC_V_DMA_CFG_RLDEN_EN ((uint32_t)0x1UL) /**< CFG_RLDEN_EN Value */ + #define MXC_S_DMA_CFG_RLDEN_EN (MXC_V_DMA_CFG_RLDEN_EN << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_EN Setting */ + + #define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */ + #define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */ + #define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */ + #define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */ + #define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */ + #define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */ + #define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */ + #define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */ + #define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */ + #define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */ + + #define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */ + #define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */ + #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */ + #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */ + #define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */ + #define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */ + + #define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */ + #define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */ + #define MXC_V_DMA_CFG_REQWAIT_DIS ((uint32_t)0x0UL) /**< CFG_REQWAIT_DIS Value */ + #define MXC_S_DMA_CFG_REQWAIT_DIS (MXC_V_DMA_CFG_REQWAIT_DIS << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_DIS Setting */ + #define MXC_V_DMA_CFG_REQWAIT_EN ((uint32_t)0x1UL) /**< CFG_REQWAIT_EN Value */ + #define MXC_S_DMA_CFG_REQWAIT_EN (MXC_V_DMA_CFG_REQWAIT_EN << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_EN Setting */ + + #define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */ + #define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */ + #define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */ + #define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */ + #define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */ + + #define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */ + #define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */ + #define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */ + #define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */ + #define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */ + #define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */ + + #define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */ + #define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */ + #define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */ + #define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */ + #define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */ + #define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */ + #define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */ + #define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */ + + #define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */ + #define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */ + #define MXC_V_DMA_CFG_SRCINC_DIS ((uint32_t)0x0UL) /**< CFG_SRCINC_DIS Value */ + #define MXC_S_DMA_CFG_SRCINC_DIS (MXC_V_DMA_CFG_SRCINC_DIS << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_DIS Setting */ + #define MXC_V_DMA_CFG_SRCINC_EN ((uint32_t)0x1UL) /**< CFG_SRCINC_EN Value */ + #define MXC_S_DMA_CFG_SRCINC_EN (MXC_V_DMA_CFG_SRCINC_EN << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_EN Setting */ + + #define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */ + #define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */ + #define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */ + #define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */ + #define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */ + #define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */ + #define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */ + #define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */ + + #define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */ + #define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */ + #define MXC_V_DMA_CFG_DSTINC_DIS ((uint32_t)0x0UL) /**< CFG_DSTINC_DIS Value */ + #define MXC_S_DMA_CFG_DSTINC_DIS (MXC_V_DMA_CFG_DSTINC_DIS << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_DIS Setting */ + #define MXC_V_DMA_CFG_DSTINC_EN ((uint32_t)0x1UL) /**< CFG_DSTINC_EN Value */ + #define MXC_S_DMA_CFG_DSTINC_EN (MXC_V_DMA_CFG_DSTINC_EN << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_EN Setting */ + + #define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */ + #define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */ + + #define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */ + #define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */ + #define MXC_V_DMA_CFG_CHDIEN_DIS ((uint32_t)0x0UL) /**< CFG_CHDIEN_DIS Value */ + #define MXC_S_DMA_CFG_CHDIEN_DIS (MXC_V_DMA_CFG_CHDIEN_DIS << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_DIS Setting */ + #define MXC_V_DMA_CFG_CHDIEN_EN ((uint32_t)0x1UL) /**< CFG_CHDIEN_EN Value */ + #define MXC_S_DMA_CFG_CHDIEN_EN (MXC_V_DMA_CFG_CHDIEN_EN << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_EN Setting */ + + #define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */ + #define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */ + #define MXC_V_DMA_CFG_CTZIEN_DIS ((uint32_t)0x0UL) /**< CFG_CTZIEN_DIS Value */ + #define MXC_S_DMA_CFG_CTZIEN_DIS (MXC_V_DMA_CFG_CTZIEN_DIS << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_DIS Setting */ + #define MXC_V_DMA_CFG_CTZIEN_EN ((uint32_t)0x1UL) /**< CFG_CTZIEN_EN Value */ + #define MXC_S_DMA_CFG_CTZIEN_EN (MXC_V_DMA_CFG_CTZIEN_EN << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_EN Setting */ + +/**@} end of group DMA_CFG_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_ST DMA_ST + * @brief DMA Channel Status Register. + * @{ + */ + #define MXC_F_DMA_ST_CH_ST_POS 0 /**< ST_CH_ST Position */ + #define MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS)) /**< ST_CH_ST Mask */ + #define MXC_V_DMA_ST_CH_ST_DIS ((uint32_t)0x0UL) /**< ST_CH_ST_DIS Value */ + #define MXC_S_DMA_ST_CH_ST_DIS (MXC_V_DMA_ST_CH_ST_DIS << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_DIS Setting */ + #define MXC_V_DMA_ST_CH_ST_EN ((uint32_t)0x1UL) /**< ST_CH_ST_EN Value */ + #define MXC_S_DMA_ST_CH_ST_EN (MXC_V_DMA_ST_CH_ST_EN << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_EN Setting */ + + #define MXC_F_DMA_ST_IPEND_POS 1 /**< ST_IPEND Position */ + #define MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS)) /**< ST_IPEND Mask */ + #define MXC_V_DMA_ST_IPEND_INACTIVE ((uint32_t)0x0UL) /**< ST_IPEND_INACTIVE Value */ + #define MXC_S_DMA_ST_IPEND_INACTIVE (MXC_V_DMA_ST_IPEND_INACTIVE << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_INACTIVE Setting */ + #define MXC_V_DMA_ST_IPEND_PENDING ((uint32_t)0x1UL) /**< ST_IPEND_PENDING Value */ + #define MXC_S_DMA_ST_IPEND_PENDING (MXC_V_DMA_ST_IPEND_PENDING << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_PENDING Setting */ + + #define MXC_F_DMA_ST_CTZ_ST_POS 2 /**< ST_CTZ_ST Position */ + #define MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS)) /**< ST_CTZ_ST Mask */ + #define MXC_V_DMA_ST_CTZ_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_CTZ_ST_NOEVENT Value */ + #define MXC_S_DMA_ST_CTZ_ST_NOEVENT (MXC_V_DMA_ST_CTZ_ST_NOEVENT << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_NOEVENT Setting */ + #define MXC_V_DMA_ST_CTZ_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_CTZ_ST_OCCURRED Value */ + #define MXC_S_DMA_ST_CTZ_ST_OCCURRED (MXC_V_DMA_ST_CTZ_ST_OCCURRED << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_OCCURRED Setting */ + #define MXC_V_DMA_ST_CTZ_ST_CLEAR ((uint32_t)0x1UL) /**< ST_CTZ_ST_CLEAR Value */ + #define MXC_S_DMA_ST_CTZ_ST_CLEAR (MXC_V_DMA_ST_CTZ_ST_CLEAR << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_CLEAR Setting */ + + #define MXC_F_DMA_ST_RLD_ST_POS 3 /**< ST_RLD_ST Position */ + #define MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS)) /**< ST_RLD_ST Mask */ + #define MXC_V_DMA_ST_RLD_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_RLD_ST_NOEVENT Value */ + #define MXC_S_DMA_ST_RLD_ST_NOEVENT (MXC_V_DMA_ST_RLD_ST_NOEVENT << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_NOEVENT Setting */ + #define MXC_V_DMA_ST_RLD_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_RLD_ST_OCCURRED Value */ + #define MXC_S_DMA_ST_RLD_ST_OCCURRED (MXC_V_DMA_ST_RLD_ST_OCCURRED << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_OCCURRED Setting */ + #define MXC_V_DMA_ST_RLD_ST_CLEAR ((uint32_t)0x1UL) /**< ST_RLD_ST_CLEAR Value */ + #define MXC_S_DMA_ST_RLD_ST_CLEAR (MXC_V_DMA_ST_RLD_ST_CLEAR << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_CLEAR Setting */ + + #define MXC_F_DMA_ST_BUS_ERR_POS 4 /**< ST_BUS_ERR Position */ + #define MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS)) /**< ST_BUS_ERR Mask */ + #define MXC_V_DMA_ST_BUS_ERR_NOEVENT ((uint32_t)0x0UL) /**< ST_BUS_ERR_NOEVENT Value */ + #define MXC_S_DMA_ST_BUS_ERR_NOEVENT (MXC_V_DMA_ST_BUS_ERR_NOEVENT << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_NOEVENT Setting */ + #define MXC_V_DMA_ST_BUS_ERR_OCCURRED ((uint32_t)0x1UL) /**< ST_BUS_ERR_OCCURRED Value */ + #define MXC_S_DMA_ST_BUS_ERR_OCCURRED (MXC_V_DMA_ST_BUS_ERR_OCCURRED << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_OCCURRED Setting */ + #define MXC_V_DMA_ST_BUS_ERR_CLEAR ((uint32_t)0x1UL) /**< ST_BUS_ERR_CLEAR Value */ + #define MXC_S_DMA_ST_BUS_ERR_CLEAR (MXC_V_DMA_ST_BUS_ERR_CLEAR << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_CLEAR Setting */ + + #define MXC_F_DMA_ST_TO_ST_POS 6 /**< ST_TO_ST Position */ + #define MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS)) /**< ST_TO_ST Mask */ + #define MXC_V_DMA_ST_TO_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_TO_ST_NOEVENT Value */ + #define MXC_S_DMA_ST_TO_ST_NOEVENT (MXC_V_DMA_ST_TO_ST_NOEVENT << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_NOEVENT Setting */ + #define MXC_V_DMA_ST_TO_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_TO_ST_OCCURRED Value */ + #define MXC_S_DMA_ST_TO_ST_OCCURRED (MXC_V_DMA_ST_TO_ST_OCCURRED << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_OCCURRED Setting */ + #define MXC_V_DMA_ST_TO_ST_CLEAR ((uint32_t)0x1UL) /**< ST_TO_ST_CLEAR Value */ + #define MXC_S_DMA_ST_TO_ST_CLEAR (MXC_V_DMA_ST_TO_ST_CLEAR << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_CLEAR Setting */ + +/**@} end of group DMA_ST_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC DMA_SRC + * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or + * 4, depending on the data width of each AHB cycle. For peripheral transfers, some + * or all of the actual address bits are fixed. If SRCINC=0, this register remains + * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the + * register is reloaded with the contents of DMA_SRC_RLD. + * @{ + */ + #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ + #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ + +/**@} end of group DMA_SRC_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST DMA_DST + * @brief Destination Device Address. For peripheral transfers, some or all of the actual + * address bits are fixed. If DSTINC=1, this register is incremented on every AHB + * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the + * data width of each AHB cycle. In the case where a count-to-zero condition occurs + * while RLDEN=1, the register is reloaded with DMA_DST_RLD. + * @{ + */ + #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ + #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ + +/**@} end of group DMA_DST_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT DMA_CNT + * @brief DMA Counter. The user loads this register with the number of bytes to transfer. + * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will + * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter + * reaches 0, a count-to-zero condition is triggered. + * @{ + */ + #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ + #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ + +/**@} end of group DMA_CNT_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC_RLD DMA_SRC_RLD + * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC + * upon a count-to-zero condition. + * @{ + */ + #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */ + #define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */ + +/**@} end of group DMA_SRC_RLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST_RLD DMA_DST_RLD + * @brief Destination Address Reload Value. The value of this register is loaded into + * DMA0_DST upon a count-to-zero condition. + * @{ + */ + #define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */ + #define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */ + +/**@} end of group DMA_DST_RLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT_RLD DMA_CNT_RLD + * @brief DMA Channel Count Reload Register. + * @{ + */ + #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */ + #define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */ + + #define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */ + #define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */ + #define MXC_V_DMA_CNT_RLD_RLDEN_DIS ((uint32_t)0x0UL) /**< CNT_RLD_RLDEN_DIS Value */ + #define MXC_S_DMA_CNT_RLD_RLDEN_DIS (MXC_V_DMA_CNT_RLD_RLDEN_DIS << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_DIS Setting */ + #define MXC_V_DMA_CNT_RLD_RLDEN_EN ((uint32_t)0x1UL) /**< CNT_RLD_RLDEN_EN Value */ + #define MXC_S_DMA_CNT_RLD_RLDEN_EN (MXC_V_DMA_CNT_RLD_RLDEN_EN << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_EN Setting */ + +/**@} end of group DMA_CNT_RLD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _DMA_REGS_H_ */ diff --git a/Project/SDK/Device/Include/flc_regs.h b/Project/SDK/Device/Include/flc_regs.h new file mode 100644 index 0000000..c0c9864 --- /dev/null +++ b/Project/SDK/Device/Include/flc_regs.h @@ -0,0 +1,264 @@ +/** + * @file flc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _FLC_REGS_H_ +#define _FLC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup flc + * @defgroup flc_registers FLC_Registers + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @details Flash Memory Control. + */ + +/** + * @ingroup flc_registers + * Structure type to access the FLC Registers. + */ +typedef struct { + __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ + __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ + __IO uint32_t cn; /**< \b 0x08: FLC CN Register */ + __R uint32_t rsv_0xc_0x23[6]; + __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ + __R uint32_t rsv_0x28_0x2f[2]; + __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ + __O uint32_t acntl; /**< \b 0x40: FLC ACNTL Register */ +} mxc_flc_regs_t; + +/* Register offsets for module FLC */ +/** + * @ingroup flc_registers + * @defgroup FLC_Register_Offsets Register Offsets + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @{ + */ + #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ + #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ + #define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ + #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ + #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ + #define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ +/**@} end of group flc_registers */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ADDR FLC_ADDR + * @brief Flash Write Address. + * @{ + */ + #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ + #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group FLC_ADDR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CLKDIV FLC_CLKDIV + * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 + * MHz clock for Flash controller. + * @{ + */ + #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ + #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group FLC_CLKDIV_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CN FLC_CN + * @brief Flash Control Register. + * @{ + */ + #define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */ + #define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */ + #define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value */ + #define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */ + #define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */ + #define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */ + + #define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */ + #define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */ + + #define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */ + #define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */ + + #define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */ + #define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */ + #define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */ + #define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */ + #define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value */ + #define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */ + + #define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */ + #define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */ + #define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */ + #define MXC_S_FLC_CN_ERASE_CODE_NOP (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */ + #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */ + #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */ + #define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */ + #define MXC_S_FLC_CN_ERASE_CODE_ERASEALL (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */ + + #define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */ + #define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */ + #define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */ + #define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */ + #define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */ + #define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */ + + #define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */ + #define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */ + #define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */ + #define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */ + #define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */ + #define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting */ + + #define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */ + #define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */ + #define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */ + #define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */ + #define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value */ + #define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */ + + #define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */ + #define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */ + #define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */ + #define MXC_S_FLC_CN_UNLOCK_UNLOCKED (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */ + #define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */ + #define MXC_S_FLC_CN_UNLOCK_LOCKED (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */ + +/**@} end of group FLC_CN_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_INTR FLC_INTR + * @brief Flash Interrupt Register. + * @{ + */ + #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ + #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ + #define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */ + #define MXC_S_FLC_INTR_DONE_INACTIVE (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */ + #define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */ + #define MXC_S_FLC_INTR_DONE_PENDING (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */ + + #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ + #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ + #define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */ + #define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */ + #define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */ + #define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */ + + #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ + #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ + #define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */ + #define MXC_S_FLC_INTR_DONEIE_DISABLE (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */ + #define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */ + #define MXC_S_FLC_INTR_DONEIE_ENABLE (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */ + + #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ + #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ + +/**@} end of group FLC_INTR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_DATA FLC_DATA + * @brief Flash Write Data. + * @{ + */ + #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ + #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group FLC_DATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ACNTL FLC_ACNTL + * @brief Access Control Register. Writing the ACNTL register with the following values in + * the order shown, allows read and write access to the system and user Information + * block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = + * 0x9608b2c1. When unlocked, a write of any word will disable access to system and + * user information block. Readback of this register is always zero. + * @{ + */ + #define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */ + #define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */ + +/**@} end of group FLC_ACNTL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FLC_REGS_H_ */ diff --git a/Project/SDK/Device/Include/gcr_regs.h b/Project/SDK/Device/Include/gcr_regs.h new file mode 100644 index 0000000..1506311 --- /dev/null +++ b/Project/SDK/Device/Include/gcr_regs.h @@ -0,0 +1,769 @@ +/** + * @file gcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _GCR_REGS_H_ +#define _GCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gcr + * @defgroup gcr_registers GCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @details Global Control Registers. + */ + +/** + * @ingroup gcr_registers + * Structure type to access the GCR Registers. + */ +typedef struct { + __IO uint32_t scon; /**< \b 0x00: GCR SCON Register */ + __IO uint32_t rstr0; /**< \b 0x04: GCR RSTR0 Register */ + __IO uint32_t clkcn; /**< \b 0x08: GCR CLKCN Register */ + __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ + __R uint32_t rsv_0x10_0x17[2]; + __IO uint32_t pckdiv; /**< \b 0x18: GCR PCKDIV Register */ + __R uint32_t rsv_0x1c_0x23[2]; + __IO uint32_t perckcn0; /**< \b 0x24: GCR PERCKCN0 Register */ + __IO uint32_t memckcn; /**< \b 0x28: GCR MEMCKCN Register */ + __IO uint32_t memzcn; /**< \b 0x2C: GCR MEMZCN Register */ + __R uint32_t rsv_0x30; + __IO uint32_t scck; /**< \b 0x34: GCR SCCK Register */ + __IO uint32_t mpri0; /**< \b 0x38: GCR MPRI0 Register */ + __IO uint32_t mpri1; /**< \b 0x3C: GCR MPRI1 Register */ + __IO uint32_t sysst; /**< \b 0x40: GCR SYSST Register */ + __IO uint32_t rstr1; /**< \b 0x44: GCR RSTR1 Register */ + __IO uint32_t perckcn1; /**< \b 0x48: GCR PERCKCN1 Register */ + __IO uint32_t evten; /**< \b 0x4C: GCR EVTEN Register */ + __I uint32_t revision; /**< \b 0x50: GCR REVISION Register */ + __IO uint32_t syssie; /**< \b 0x54: GCR SYSSIE Register */ +} mxc_gcr_regs_t; + +/* Register offsets for module GCR */ +/** + * @ingroup gcr_registers + * @defgroup GCR_Register_Offsets Register Offsets + * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. + * @{ + */ + #define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ + #define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ + #define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ + #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ + #define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: 0x0018 */ + #define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ + #define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ + #define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ + #define MXC_R_GCR_SCCK ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: 0x0034 */ + #define MXC_R_GCR_MPRI0 ((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: 0x0038 */ + #define MXC_R_GCR_MPRI1 ((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: 0x003C */ + #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ + #define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ + #define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ + #define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ + #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ + #define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ +/**@} end of group gcr_registers */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SCON GCR_SCON + * @brief System Control. + * @{ + */ + #define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */ + #define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */ + #define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */ + #define MXC_S_GCR_SCON_SBUSARB_FIX (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */ + #define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */ + #define MXC_S_GCR_SCON_SBUSARB_ROUND (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */ + + #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */ + #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */ + #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */ + #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */ + #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */ + #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */ + + #define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */ + #define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */ + #define MXC_V_GCR_SCON_FPU_DIS_ENABLE ((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */ + #define MXC_S_GCR_SCON_FPU_DIS_ENABLE (MXC_V_GCR_SCON_FPU_DIS_ENABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */ + #define MXC_V_GCR_SCON_FPU_DIS_DISABLE ((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */ + #define MXC_S_GCR_SCON_FPU_DIS_DISABLE (MXC_V_GCR_SCON_FPU_DIS_DISABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */ + + #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */ + #define MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */ + #define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */ + #define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */ + #define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */ + #define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */ + + #define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */ + #define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */ + #define MXC_V_GCR_SCON_SWD_DIS_ENABLE ((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */ + #define MXC_S_GCR_SCON_SWD_DIS_ENABLE (MXC_V_GCR_SCON_SWD_DIS_ENABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */ + #define MXC_V_GCR_SCON_SWD_DIS_DISABLE ((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */ + #define MXC_S_GCR_SCON_SWD_DIS_DISABLE (MXC_V_GCR_SCON_SWD_DIS_DISABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */ + +/**@} end of group GCR_SCON_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RSTR0 GCR_RSTR0 + * @brief Reset. + * @{ + */ + #define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */ + #define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */ + #define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */ + #define MXC_S_GCR_RSTR0_DMA_RFU (MXC_V_GCR_RSTR0_DMA_RFU << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */ + #define MXC_V_GCR_RSTR0_DMA_RESET ((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */ + #define MXC_S_GCR_RSTR0_DMA_RESET (MXC_V_GCR_RSTR0_DMA_RESET << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */ + #define MXC_V_GCR_RSTR0_DMA_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_DMA_RESET_DONE (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_DMA_BUSY ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value */ + #define MXC_S_GCR_RSTR0_DMA_BUSY (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */ + #define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */ + #define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */ + #define MXC_S_GCR_RSTR0_WDT_RFU (MXC_V_GCR_RSTR0_WDT_RFU << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */ + #define MXC_V_GCR_RSTR0_WDT_RESET ((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */ + #define MXC_S_GCR_RSTR0_WDT_RESET (MXC_V_GCR_RSTR0_WDT_RESET << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */ + #define MXC_V_GCR_RSTR0_WDT_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_WDT_RESET_DONE (MXC_V_GCR_RSTR0_WDT_RESET_DONE << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_WDT_BUSY ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value */ + #define MXC_S_GCR_RSTR0_WDT_BUSY (MXC_V_GCR_RSTR0_WDT_BUSY << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */ + #define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */ + #define MXC_V_GCR_RSTR0_GPIO0_RFU ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */ + #define MXC_S_GCR_RSTR0_GPIO0_RFU (MXC_V_GCR_RSTR0_GPIO0_RFU << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */ + #define MXC_V_GCR_RSTR0_GPIO0_RESET ((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */ + #define MXC_S_GCR_RSTR0_GPIO0_RESET (MXC_V_GCR_RSTR0_GPIO0_RESET << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */ + #define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_GPIO0_BUSY ((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */ + #define MXC_S_GCR_RSTR0_GPIO0_BUSY (MXC_V_GCR_RSTR0_GPIO0_BUSY << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */ + #define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */ + #define MXC_V_GCR_RSTR0_TIMER0_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */ + #define MXC_S_GCR_RSTR0_TIMER0_RFU (MXC_V_GCR_RSTR0_TIMER0_RFU << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */ + #define MXC_V_GCR_RSTR0_TIMER0_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */ + #define MXC_S_GCR_RSTR0_TIMER0_RESET (MXC_V_GCR_RSTR0_TIMER0_RESET << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */ + #define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE (MXC_V_GCR_RSTR0_TIMER0_RESET_DONE << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_TIMER0_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */ + #define MXC_S_GCR_RSTR0_TIMER0_BUSY (MXC_V_GCR_RSTR0_TIMER0_BUSY << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */ + #define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */ + #define MXC_V_GCR_RSTR0_TIMER1_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */ + #define MXC_S_GCR_RSTR0_TIMER1_RFU (MXC_V_GCR_RSTR0_TIMER1_RFU << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */ + #define MXC_V_GCR_RSTR0_TIMER1_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */ + #define MXC_S_GCR_RSTR0_TIMER1_RESET (MXC_V_GCR_RSTR0_TIMER1_RESET << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */ + #define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE (MXC_V_GCR_RSTR0_TIMER1_RESET_DONE << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_TIMER1_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */ + #define MXC_S_GCR_RSTR0_TIMER1_BUSY (MXC_V_GCR_RSTR0_TIMER1_BUSY << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */ + #define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */ + #define MXC_V_GCR_RSTR0_TIMER2_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */ + #define MXC_S_GCR_RSTR0_TIMER2_RFU (MXC_V_GCR_RSTR0_TIMER2_RFU << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */ + #define MXC_V_GCR_RSTR0_TIMER2_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */ + #define MXC_S_GCR_RSTR0_TIMER2_RESET (MXC_V_GCR_RSTR0_TIMER2_RESET << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */ + #define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE (MXC_V_GCR_RSTR0_TIMER2_RESET_DONE << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_TIMER2_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */ + #define MXC_S_GCR_RSTR0_TIMER2_BUSY (MXC_V_GCR_RSTR0_TIMER2_BUSY << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */ + #define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */ + #define MXC_V_GCR_RSTR0_UART0_RFU ((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */ + #define MXC_S_GCR_RSTR0_UART0_RFU (MXC_V_GCR_RSTR0_UART0_RFU << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */ + #define MXC_V_GCR_RSTR0_UART0_RESET ((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */ + #define MXC_S_GCR_RSTR0_UART0_RESET (MXC_V_GCR_RSTR0_UART0_RESET << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */ + #define MXC_V_GCR_RSTR0_UART0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_UART0_RESET_DONE (MXC_V_GCR_RSTR0_UART0_RESET_DONE << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_UART0_BUSY ((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */ + #define MXC_S_GCR_RSTR0_UART0_BUSY (MXC_V_GCR_RSTR0_UART0_BUSY << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */ + #define MXC_F_GCR_RSTR0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */ + #define MXC_V_GCR_RSTR0_UART1_RFU ((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */ + #define MXC_S_GCR_RSTR0_UART1_RFU (MXC_V_GCR_RSTR0_UART1_RFU << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */ + #define MXC_V_GCR_RSTR0_UART1_RESET ((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */ + #define MXC_S_GCR_RSTR0_UART1_RESET (MXC_V_GCR_RSTR0_UART1_RESET << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */ + #define MXC_V_GCR_RSTR0_UART1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_UART1_RESET_DONE (MXC_V_GCR_RSTR0_UART1_RESET_DONE << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_UART1_BUSY ((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */ + #define MXC_S_GCR_RSTR0_UART1_BUSY (MXC_V_GCR_RSTR0_UART1_BUSY << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */ + #define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */ + #define MXC_V_GCR_RSTR0_SPI0_RFU ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value */ + #define MXC_S_GCR_RSTR0_SPI0_RFU (MXC_V_GCR_RSTR0_SPI0_RFU << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */ + #define MXC_V_GCR_RSTR0_SPI0_RESET ((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */ + #define MXC_S_GCR_RSTR0_SPI0_RESET (MXC_V_GCR_RSTR0_SPI0_RESET << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */ + #define MXC_V_GCR_RSTR0_SPI0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_SPI0_RESET_DONE (MXC_V_GCR_RSTR0_SPI0_RESET_DONE << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_SPI0_BUSY ((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */ + #define MXC_S_GCR_RSTR0_SPI0_BUSY (MXC_V_GCR_RSTR0_SPI0_BUSY << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */ + #define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */ + #define MXC_V_GCR_RSTR0_SPI1_RFU ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value */ + #define MXC_S_GCR_RSTR0_SPI1_RFU (MXC_V_GCR_RSTR0_SPI1_RFU << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */ + #define MXC_V_GCR_RSTR0_SPI1_RESET ((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */ + #define MXC_S_GCR_RSTR0_SPI1_RESET (MXC_V_GCR_RSTR0_SPI1_RESET << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */ + #define MXC_V_GCR_RSTR0_SPI1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_SPI1_RESET_DONE (MXC_V_GCR_RSTR0_SPI1_RESET_DONE << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_SPI1_BUSY ((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */ + #define MXC_S_GCR_RSTR0_SPI1_BUSY (MXC_V_GCR_RSTR0_SPI1_BUSY << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */ + #define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */ + #define MXC_V_GCR_RSTR0_I2C0_RFU ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value */ + #define MXC_S_GCR_RSTR0_I2C0_RFU (MXC_V_GCR_RSTR0_I2C0_RFU << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */ + #define MXC_V_GCR_RSTR0_I2C0_RESET ((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */ + #define MXC_S_GCR_RSTR0_I2C0_RESET (MXC_V_GCR_RSTR0_I2C0_RESET << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */ + #define MXC_V_GCR_RSTR0_I2C0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_I2C0_RESET_DONE (MXC_V_GCR_RSTR0_I2C0_RESET_DONE << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_I2C0_BUSY ((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */ + #define MXC_S_GCR_RSTR0_I2C0_BUSY (MXC_V_GCR_RSTR0_I2C0_BUSY << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */ + #define MXC_F_GCR_RSTR0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */ + #define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */ + #define MXC_S_GCR_RSTR0_RTC_RFU (MXC_V_GCR_RSTR0_RTC_RFU << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */ + #define MXC_V_GCR_RSTR0_RTC_RESET ((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */ + #define MXC_S_GCR_RSTR0_RTC_RESET (MXC_V_GCR_RSTR0_RTC_RESET << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */ + #define MXC_V_GCR_RSTR0_RTC_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_RTC_RESET_DONE (MXC_V_GCR_RSTR0_RTC_RESET_DONE << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_RTC_BUSY ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value */ + #define MXC_S_GCR_RSTR0_RTC_BUSY (MXC_V_GCR_RSTR0_RTC_BUSY << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */ + #define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */ + #define MXC_V_GCR_RSTR0_SRST_RFU ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value */ + #define MXC_S_GCR_RSTR0_SRST_RFU (MXC_V_GCR_RSTR0_SRST_RFU << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */ + #define MXC_V_GCR_RSTR0_SRST_RESET ((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */ + #define MXC_S_GCR_RSTR0_SRST_RESET (MXC_V_GCR_RSTR0_SRST_RESET << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */ + #define MXC_V_GCR_RSTR0_SRST_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_SRST_RESET_DONE (MXC_V_GCR_RSTR0_SRST_RESET_DONE << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_SRST_BUSY ((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */ + #define MXC_S_GCR_RSTR0_SRST_BUSY (MXC_V_GCR_RSTR0_SRST_BUSY << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */ + #define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */ + #define MXC_V_GCR_RSTR0_PRST_RFU ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value */ + #define MXC_S_GCR_RSTR0_PRST_RFU (MXC_V_GCR_RSTR0_PRST_RFU << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */ + #define MXC_V_GCR_RSTR0_PRST_RESET ((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */ + #define MXC_S_GCR_RSTR0_PRST_RESET (MXC_V_GCR_RSTR0_PRST_RESET << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */ + #define MXC_V_GCR_RSTR0_PRST_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_PRST_RESET_DONE (MXC_V_GCR_RSTR0_PRST_RESET_DONE << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_PRST_BUSY ((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */ + #define MXC_S_GCR_RSTR0_PRST_BUSY (MXC_V_GCR_RSTR0_PRST_BUSY << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */ + + #define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */ + #define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */ + #define MXC_V_GCR_RSTR0_SYSTEM_RFU ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */ + #define MXC_S_GCR_RSTR0_SYSTEM_RFU (MXC_V_GCR_RSTR0_SYSTEM_RFU << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */ + #define MXC_V_GCR_RSTR0_SYSTEM_RESET ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */ + #define MXC_S_GCR_RSTR0_SYSTEM_RESET (MXC_V_GCR_RSTR0_SYSTEM_RESET << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */ + #define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */ + #define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE (MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR0_SYSTEM_BUSY ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */ + #define MXC_S_GCR_RSTR0_SYSTEM_BUSY (MXC_V_GCR_RSTR0_SYSTEM_BUSY << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */ + +/**@} end of group GCR_RSTR0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_CLKCN GCR_CLKCN + * @brief Clock Control. + * @{ + */ + #define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */ + #define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */ + #define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */ + #define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */ + #define MXC_S_GCR_CLKCN_PSC_DIV128 (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */ + + #define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */ + #define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */ + #define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */ + #define MXC_S_GCR_CLKCN_CLKSEL_HIRC (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */ + #define MXC_V_GCR_CLKCN_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */ + #define MXC_S_GCR_CLKCN_CLKSEL_NANORING (MXC_V_GCR_CLKCN_CLKSEL_NANORING << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */ + #define MXC_V_GCR_CLKCN_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */ + #define MXC_S_GCR_CLKCN_CLKSEL_HFXIN (MXC_V_GCR_CLKCN_CLKSEL_HFXIN << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */ + + #define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */ + #define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */ + #define MXC_V_GCR_CLKCN_CKRDY_BUSY ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */ + #define MXC_S_GCR_CLKCN_CKRDY_BUSY (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */ + #define MXC_V_GCR_CLKCN_CKRDY_READY ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */ + #define MXC_S_GCR_CLKCN_CKRDY_READY (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */ + + #define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */ + #define MXC_F_GCR_CLKCN_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */ + #define MXC_V_GCR_CLKCN_X32K_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */ + #define MXC_S_GCR_CLKCN_X32K_EN_DIS (MXC_V_GCR_CLKCN_X32K_EN_DIS << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */ + #define MXC_V_GCR_CLKCN_X32K_EN_EN ((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */ + #define MXC_S_GCR_CLKCN_X32K_EN_EN (MXC_V_GCR_CLKCN_X32K_EN_EN << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */ + + #define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */ + #define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */ + #define MXC_V_GCR_CLKCN_HIRC_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */ + #define MXC_S_GCR_CLKCN_HIRC_EN_DIS (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */ + #define MXC_V_GCR_CLKCN_HIRC_EN_EN ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */ + #define MXC_S_GCR_CLKCN_HIRC_EN_EN (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */ + + #define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */ + #define MXC_F_GCR_CLKCN_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */ + #define MXC_V_GCR_CLKCN_X32K_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */ + #define MXC_S_GCR_CLKCN_X32K_RDY_NOT (MXC_V_GCR_CLKCN_X32K_RDY_NOT << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */ + #define MXC_V_GCR_CLKCN_X32K_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */ + #define MXC_S_GCR_CLKCN_X32K_RDY_READY (MXC_V_GCR_CLKCN_X32K_RDY_READY << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */ + + #define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */ + #define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */ + #define MXC_V_GCR_CLKCN_HIRC_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */ + #define MXC_S_GCR_CLKCN_HIRC_RDY_NOT (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */ + #define MXC_V_GCR_CLKCN_HIRC_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */ + #define MXC_S_GCR_CLKCN_HIRC_RDY_READY (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */ + + #define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */ + #define MXC_F_GCR_CLKCN_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */ + #define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */ + #define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT (MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting */ + #define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */ + #define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY (MXC_V_GCR_CLKCN_LIRC8K_RDY_READY << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY Setting */ + +/**@} end of group GCR_CLKCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PM GCR_PM + * @brief Power Management. + * @{ + */ + #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ + #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ + #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ + #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ + #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ + #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ + #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ + #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ + + #define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */ + #define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */ + #define MXC_V_GCR_PM_GPIOWKEN_DIS ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */ + #define MXC_S_GCR_PM_GPIOWKEN_DIS (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */ + #define MXC_V_GCR_PM_GPIOWKEN_EN ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value */ + #define MXC_S_GCR_PM_GPIOWKEN_EN (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */ + + #define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */ + #define MXC_F_GCR_PM_RTCWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask */ + #define MXC_V_GCR_PM_RTCWKEN_DIS ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value */ + #define MXC_S_GCR_PM_RTCWKEN_DIS (MXC_V_GCR_PM_RTCWKEN_DIS << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_DIS Setting */ + #define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */ + #define MXC_S_GCR_PM_RTCWKEN_EN (MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */ + + #define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */ + #define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */ + #define MXC_V_GCR_PM_HIRCPD_ACTIVE ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */ + #define MXC_S_GCR_PM_HIRCPD_ACTIVE (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */ + #define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */ + #define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */ + +/**@} end of group GCR_PM_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCKDIV GCR_PCKDIV + * @brief Peripheral Clock Divider. + * @{ + */ + #define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */ + #define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */ + #define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */ + #define MXC_S_GCR_PCKDIV_AONCD_DIV_4 (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */ + #define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */ + #define MXC_S_GCR_PCKDIV_AONCD_DIV_8 (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */ + #define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */ + #define MXC_S_GCR_PCKDIV_AONCD_DIV_16 (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */ + #define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */ + #define MXC_S_GCR_PCKDIV_AONCD_DIV_32 (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */ + +/**@} end of group GCR_PCKDIV_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PERCKCN0 GCR_PERCKCN0 + * @brief Peripheral Clock Disable. + * @{ + */ + #define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */ + #define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */ + #define MXC_V_GCR_PERCKCN0_GPIO0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_GPIO0D_EN (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_GPIO0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_GPIO0D_DIS (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */ + #define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */ + #define MXC_V_GCR_PERCKCN0_DMAD_EN ((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */ + #define MXC_S_GCR_PERCKCN0_DMAD_EN (MXC_V_GCR_PERCKCN0_DMAD_EN << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */ + #define MXC_V_GCR_PERCKCN0_DMAD_DIS ((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */ + #define MXC_S_GCR_PERCKCN0_DMAD_DIS (MXC_V_GCR_PERCKCN0_DMAD_DIS << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */ + #define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */ + #define MXC_V_GCR_PERCKCN0_SPI0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_SPI0D_EN (MXC_V_GCR_PERCKCN0_SPI0D_EN << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_SPI0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_SPI0D_DIS (MXC_V_GCR_PERCKCN0_SPI0D_DIS << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */ + #define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */ + #define MXC_V_GCR_PERCKCN0_SPI1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */ + #define MXC_S_GCR_PERCKCN0_SPI1D_EN (MXC_V_GCR_PERCKCN0_SPI1D_EN << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_SPI1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_SPI1D_DIS (MXC_V_GCR_PERCKCN0_SPI1D_DIS << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */ + #define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */ + #define MXC_V_GCR_PERCKCN0_UART0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_UART0D_EN (MXC_V_GCR_PERCKCN0_UART0D_EN << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_UART0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_UART0D_DIS (MXC_V_GCR_PERCKCN0_UART0D_DIS << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */ + #define MXC_F_GCR_PERCKCN0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D Mask */ + #define MXC_V_GCR_PERCKCN0_UART1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */ + #define MXC_S_GCR_PERCKCN0_UART1D_EN (MXC_V_GCR_PERCKCN0_UART1D_EN << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_UART1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_UART1D_DIS (MXC_V_GCR_PERCKCN0_UART1D_DIS << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */ + #define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */ + #define MXC_V_GCR_PERCKCN0_I2C0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_I2C0D_EN (MXC_V_GCR_PERCKCN0_I2C0D_EN << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_I2C0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_I2C0D_DIS (MXC_V_GCR_PERCKCN0_I2C0D_DIS << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */ + #define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */ + #define MXC_V_GCR_PERCKCN0_T0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */ + #define MXC_S_GCR_PERCKCN0_T0D_EN (MXC_V_GCR_PERCKCN0_T0D_EN << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_T0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_T0D_DIS (MXC_V_GCR_PERCKCN0_T0D_DIS << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */ + #define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */ + #define MXC_V_GCR_PERCKCN0_T1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */ + #define MXC_S_GCR_PERCKCN0_T1D_EN (MXC_V_GCR_PERCKCN0_T1D_EN << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_T1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_T1D_DIS (MXC_V_GCR_PERCKCN0_T1D_DIS << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */ + #define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */ + #define MXC_V_GCR_PERCKCN0_T2D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */ + #define MXC_S_GCR_PERCKCN0_T2D_EN (MXC_V_GCR_PERCKCN0_T2D_EN << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_T2D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_T2D_DIS (MXC_V_GCR_PERCKCN0_T2D_DIS << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */ + + #define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */ + #define MXC_F_GCR_PERCKCN0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */ + #define MXC_V_GCR_PERCKCN0_I2C1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */ + #define MXC_S_GCR_PERCKCN0_I2C1D_EN (MXC_V_GCR_PERCKCN0_I2C1D_EN << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */ + #define MXC_V_GCR_PERCKCN0_I2C1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */ + #define MXC_S_GCR_PERCKCN0_I2C1D_DIS (MXC_V_GCR_PERCKCN0_I2C1D_DIS << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */ + +/**@} end of group GCR_PERCKCN0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMCKCN GCR_MEMCKCN + * @brief Memory Clock Control Register. + * @{ + */ + #define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */ + #define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */ + + #define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */ + #define MXC_F_GCR_MEMCKCN_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS Mask */ + #define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */ + + #define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */ + #define MXC_F_GCR_MEMCKCN_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */ + #define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Setting */ + + #define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */ + #define MXC_F_GCR_MEMCKCN_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */ + #define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Setting */ + + #define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */ + #define MXC_F_GCR_MEMCKCN_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */ + #define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Setting */ + + #define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */ + #define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */ + #define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */ + #define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE (MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE Setting */ + #define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */ + #define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Setting */ + +/**@} end of group GCR_MEMCKCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMZCN GCR_MEMZCN + * @brief Memory Zeroize Control. + * @{ + */ + #define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */ + #define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */ + #define MXC_V_GCR_MEMZCN_SRAM0Z_NOP ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */ + #define MXC_S_GCR_MEMZCN_SRAM0Z_NOP (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */ + #define MXC_V_GCR_MEMZCN_SRAM0Z_START ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */ + #define MXC_S_GCR_MEMZCN_SRAM0Z_START (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */ + + #define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */ + #define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */ + #define MXC_V_GCR_MEMZCN_ICACHEZ_NOP ((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */ + #define MXC_S_GCR_MEMZCN_ICACHEZ_NOP (MXC_V_GCR_MEMZCN_ICACHEZ_NOP << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */ + #define MXC_V_GCR_MEMZCN_ICACHEZ_START ((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */ + #define MXC_S_GCR_MEMZCN_ICACHEZ_START (MXC_V_GCR_MEMZCN_ICACHEZ_START << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */ + +/**@} end of group GCR_MEMZCN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSST GCR_SYSST + * @brief System Status Register. + * @{ + */ + #define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */ + #define MXC_F_GCR_SYSST_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */ + #define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */ + #define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */ + #define MXC_V_GCR_SYSST_ICECLOCK_LOCKED ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */ + #define MXC_S_GCR_SYSST_ICECLOCK_LOCKED (MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */ + + #define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */ + #define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */ + #define MXC_V_GCR_SYSST_CODEINTERR_NORM ((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */ + #define MXC_S_GCR_SYSST_CODEINTERR_NORM (MXC_V_GCR_SYSST_CODEINTERR_NORM << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting */ + #define MXC_V_GCR_SYSST_CODEINTERR_CODE ((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */ + #define MXC_S_GCR_SYSST_CODEINTERR_CODE (MXC_V_GCR_SYSST_CODEINTERR_CODE << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_CODE Setting */ + + #define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ + #define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ + #define MXC_V_GCR_SYSST_SCMEMF_NORM ((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */ + #define MXC_S_GCR_SYSST_SCMEMF_NORM (MXC_V_GCR_SYSST_SCMEMF_NORM << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */ + #define MXC_V_GCR_SYSST_SCMEMF_MEMORY ((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */ + #define MXC_S_GCR_SYSST_SCMEMF_MEMORY (MXC_V_GCR_SYSST_SCMEMF_MEMORY << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */ + +/**@} end of group GCR_SYSST_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RSTR1 GCR_RSTR1 + * @brief Reset 1. + * @{ + */ + #define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */ + #define MXC_F_GCR_RSTR1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask */ + #define MXC_V_GCR_RSTR1_I2C1_RFU ((uint32_t)0x0UL) /**< RSTR1_I2C1_RFU Value */ + #define MXC_S_GCR_RSTR1_I2C1_RFU (MXC_V_GCR_RSTR1_I2C1_RFU << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RFU Setting */ + #define MXC_V_GCR_RSTR1_I2C1_RESET ((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */ + #define MXC_S_GCR_RSTR1_I2C1_RESET (MXC_V_GCR_RSTR1_I2C1_RESET << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */ + #define MXC_V_GCR_RSTR1_I2C1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */ + #define MXC_S_GCR_RSTR1_I2C1_RESET_DONE (MXC_V_GCR_RSTR1_I2C1_RESET_DONE << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */ + #define MXC_V_GCR_RSTR1_I2C1_BUSY ((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */ + #define MXC_S_GCR_RSTR1_I2C1_BUSY (MXC_V_GCR_RSTR1_I2C1_BUSY << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */ + +/**@} end of group GCR_RSTR1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PERCKCN1 GCR_PERCKCN1 + * @brief Peripheral Clock Disable. + * @{ + */ + #define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */ + #define MXC_F_GCR_PERCKCN1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */ + #define MXC_V_GCR_PERCKCN1_FLCD_EN ((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */ + #define MXC_S_GCR_PERCKCN1_FLCD_EN (MXC_V_GCR_PERCKCN1_FLCD_EN << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */ + #define MXC_V_GCR_PERCKCN1_FLCD_DIS ((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */ + #define MXC_S_GCR_PERCKCN1_FLCD_DIS (MXC_V_GCR_PERCKCN1_FLCD_DIS << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */ + + #define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */ + #define MXC_F_GCR_PERCKCN1_ICACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */ + #define MXC_V_GCR_PERCKCN1_ICACHED_EN ((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */ + #define MXC_S_GCR_PERCKCN1_ICACHED_EN (MXC_V_GCR_PERCKCN1_ICACHED_EN << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting */ + #define MXC_V_GCR_PERCKCN1_ICACHED_DIS ((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */ + #define MXC_S_GCR_PERCKCN1_ICACHED_DIS (MXC_V_GCR_PERCKCN1_ICACHED_DIS << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting */ + +/**@} end of group GCR_PERCKCN1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_EVTEN GCR_EVTEN + * @brief Event Enable Register. + * @{ + */ + #define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */ + #define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */ + + #define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */ + #define MXC_F_GCR_EVTEN_RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */ + +/**@} end of group GCR_EVTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_REVISION GCR_REVISION + * @brief Revision Register. + * @{ + */ + #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ + #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ + +/**@} end of group GCR_REVISION_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSSIE GCR_SYSSIE + * @brief System Status Interrupt Enable Register. + * @{ + */ + #define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */ + #define MXC_F_GCR_SYSSIE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */ + #define MXC_V_GCR_SYSSIE_ICEULIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */ + #define MXC_S_GCR_SYSSIE_ICEULIE_DIS (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */ + #define MXC_V_GCR_SYSSIE_ICEULIE_EN ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */ + #define MXC_S_GCR_SYSSIE_ICEULIE_EN (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */ + + #define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */ + #define MXC_F_GCR_SYSSIE_CIEIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */ + #define MXC_V_GCR_SYSSIE_CIEIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */ + #define MXC_S_GCR_SYSSIE_CIEIE_DIS (MXC_V_GCR_SYSSIE_CIEIE_DIS << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */ + #define MXC_V_GCR_SYSSIE_CIEIE_EN ((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */ + #define MXC_S_GCR_SYSSIE_CIEIE_EN (MXC_V_GCR_SYSSIE_CIEIE_EN << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */ + + #define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */ + #define MXC_F_GCR_SYSSIE_SCMFIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */ + #define MXC_V_GCR_SYSSIE_SCMFIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */ + #define MXC_S_GCR_SYSSIE_SCMFIE_DIS (MXC_V_GCR_SYSSIE_SCMFIE_DIS << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */ + #define MXC_V_GCR_SYSSIE_SCMFIE_EN ((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */ + #define MXC_S_GCR_SYSSIE_SCMFIE_EN (MXC_V_GCR_SYSSIE_SCMFIE_EN << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */ + +/**@} end of group GCR_SYSSIE_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GCR_REGS_H_ */ diff --git a/Project/SDK/Device/Include/gpio_regs.h b/Project/SDK/Device/Include/gpio_regs.h new file mode 100644 index 0000000..d25878b --- /dev/null +++ b/Project/SDK/Device/Include/gpio_regs.h @@ -0,0 +1,663 @@ +/** + * @file gpio_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _GPIO_REGS_H_ +#define _GPIO_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gpio + * @defgroup gpio_registers GPIO_Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @details Individual I/O for each GPIO + */ + +/** + * @ingroup gpio_registers + * Structure type to access the GPIO Registers. + */ +typedef struct { + __IO uint32_t en; /**< \b 0x00: GPIO EN Register */ + __IO uint32_t en_set; /**< \b 0x04: GPIO EN_SET Register */ + __IO uint32_t en_clr; /**< \b 0x08: GPIO EN_CLR Register */ + __IO uint32_t out_en; /**< \b 0x0C: GPIO OUT_EN Register */ + __IO uint32_t out_en_set; /**< \b 0x10: GPIO OUT_EN_SET Register */ + __IO uint32_t out_en_clr; /**< \b 0x14: GPIO OUT_EN_CLR Register */ + __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ + __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ + __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ + __I uint32_t in; /**< \b 0x24: GPIO IN Register */ + __IO uint32_t int_mod; /**< \b 0x28: GPIO INT_MOD Register */ + __IO uint32_t int_pol; /**< \b 0x2C: GPIO INT_POL Register */ + __R uint32_t rsv_0x30; + __IO uint32_t int_en; /**< \b 0x34: GPIO INT_EN Register */ + __IO uint32_t int_en_set; /**< \b 0x38: GPIO INT_EN_SET Register */ + __IO uint32_t int_en_clr; /**< \b 0x3C: GPIO INT_EN_CLR Register */ + __I uint32_t int_stat; /**< \b 0x40: GPIO INT_STAT Register */ + __R uint32_t rsv_0x44; + __IO uint32_t int_clr; /**< \b 0x48: GPIO INT_CLR Register */ + __IO uint32_t wake_en; /**< \b 0x4C: GPIO WAKE_EN Register */ + __IO uint32_t wake_en_set; /**< \b 0x50: GPIO WAKE_EN_SET Register */ + __IO uint32_t wake_en_clr; /**< \b 0x54: GPIO WAKE_EN_CLR Register */ + __R uint32_t rsv_0x58; + __IO uint32_t int_dual_edge; /**< \b 0x5C: GPIO INT_DUAL_EDGE Register */ + __IO uint32_t pad_cfg1; /**< \b 0x60: GPIO PAD_CFG1 Register */ + __IO uint32_t pad_cfg2; /**< \b 0x64: GPIO PAD_CFG2 Register */ + __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ + __R uint32_t rsv_0x80_0xa7[10]; + __IO uint32_t is; /**< \b 0xA8: GPIO IS Register */ + __IO uint32_t sr; /**< \b 0xAC: GPIO SR Register */ + __IO uint32_t ds; /**< \b 0xB0: GPIO DS Register */ + __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ + __IO uint32_t ps; /**< \b 0xB8: GPIO PS Register */ + __R uint32_t rsv_0xbc; + __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ +} mxc_gpio_regs_t; + +/* Register offsets for module GPIO */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_Register_Offsets Register Offsets + * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ + #define MXC_R_GPIO_EN ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ + #define MXC_R_GPIO_EN_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ + #define MXC_R_GPIO_EN_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ + #define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ + #define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ + #define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ + #define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ + #define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ + #define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ + #define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ + #define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ + #define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ + #define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ + #define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ + #define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ + #define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ + #define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ + #define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ + #define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ + #define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ + #define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ + #define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ + #define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ + #define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ + #define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ + #define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ + #define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ + #define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ + #define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ + #define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ + #define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ + #define MXC_R_GPIO_DS ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ + #define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ + #define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ + #define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ +/**@} end of group gpio_registers */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN GPIO_EN + * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one + * GPIO pin on the associated port. + * @{ + */ + #define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */ + #define MXC_F_GPIO_EN_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */ + #define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */ + #define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */ + #define MXC_V_GPIO_EN_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */ + #define MXC_S_GPIO_EN_GPIO_EN_GPIO (MXC_V_GPIO_EN_GPIO_EN_GPIO << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */ + +/**@} end of group GPIO_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN_SET GPIO_EN_SET + * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this + * register sets the bits in the same positions in GPIO_EN to 1, without affecting + * other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */ + #define MXC_F_GPIO_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */ + +/**@} end of group GPIO_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN_CLR GPIO_EN_CLR + * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN to 0, without + * affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */ + #define MXC_F_GPIO_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */ + +/**@} end of group GPIO_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN GPIO_OUT_EN + * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one + * GPIO pin in the associated port. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */ + #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */ + #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ + #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */ + #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ + #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */ + +/**@} end of group GPIO_OUT_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET + * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits + * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, + * without affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ + #define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ + +/**@} end of group GPIO_OUT_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR + * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more + * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, + * without affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ + #define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ + +/**@} end of group GPIO_OUT_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT GPIO_OUT + * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the + * associated port. This register can be written either directly, or by using the + * GPIO_OUT_SET and GPIO_OUT_CLR registers. + * @{ + */ + #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ + #define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ + #define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ + #define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ + #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ + #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ + +/**@} end of group GPIO_OUT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_SET GPIO_OUT_SET + * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits + * in the same positions in GPIO_OUT to 1, without affecting other bits in that + * register. + * @{ + */ + #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */ + #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */ + #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ + #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */ + #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ + #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */ + +/**@} end of group GPIO_OUT_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR + * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_OUT to 0, without affecting other bits in + * that register. + * @{ + */ + #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ + #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */ + +/**@} end of group GPIO_OUT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN GPIO_IN + * @brief GPIO Input Register. Read-only register to read from the logic states of the + * GPIO pins on this port. + * @{ + */ + #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ + #define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ + +/**@} end of group GPIO_IN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_MOD GPIO_INT_MOD + * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt + * mode setting for the associated GPIO pin on this port. + * @{ + */ + #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */ + #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */ + #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ + #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */ + #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ + #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */ + +/**@} end of group GPIO_INT_MOD_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_POL GPIO_INT_POL + * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the + * interrupt polarity setting for one GPIO pin in the associated port. + * @{ + */ + #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */ + #define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */ + #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ + #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */ + #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ + #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */ + +/**@} end of group GPIO_INT_POL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN GPIO_INT_EN + * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO + * interrupt enable for the associated pin on the GPIO port. + * @{ + */ + #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */ + #define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */ + #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ + #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */ + #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ + #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */ + +/**@} end of group GPIO_INT_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET + * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets + * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits + * in that register. + * @{ + */ + #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ + #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */ + #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ + #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */ + #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ + #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */ + +/**@} end of group GPIO_INT_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR + * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting + * other bits in that register. + * @{ + */ + #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ + #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */ + #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ + #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */ + #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ + #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */ + +/**@} end of group GPIO_INT_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_STAT GPIO_INT_STAT + * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending + * interrupt status for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */ + #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */ + #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ + #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */ + #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ + #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */ + +/**@} end of group GPIO_INT_STAT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_CLR GPIO_INT_CLR + * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits + * in that register. + * @{ + */ + #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ + #define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ + +/**@} end of group GPIO_INT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN GPIO_WAKE_EN + * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup + * enable for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ + #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */ + #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ + #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */ + #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ + #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */ + +/**@} end of group GPIO_WAKE_EN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET + * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the + * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in + * that register. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ + #define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */ + +/**@} end of group GPIO_WAKE_EN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR + * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears + * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ + #define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */ + +/**@} end of group GPIO_WAKE_EN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE + * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual + * edge mode for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ + #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */ + #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ + #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */ + #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ + #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */ + +/**@} end of group GPIO_INT_DUAL_EDGE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1 + * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ + #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */ + #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ + #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */ + +/**@} end of group GPIO_PAD_CFG1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2 + * @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ + #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */ + #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ + #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */ + +/**@} end of group GPIO_PAD_CFG2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1 GPIO_EN1 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ + #define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ + #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ + #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ + #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ + #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */ + +/**@} end of group GPIO_EN1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_SET GPIO_EN1_SET + * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ + #define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ + +/**@} end of group GPIO_EN1_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR + * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ + #define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ + +/**@} end of group GPIO_EN1_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2 GPIO_EN2 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ + #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ + #define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ + #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ + #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ + #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ + #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */ + +/**@} end of group GPIO_EN2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_SET GPIO_EN2_SET + * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other + * bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ + #define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ + +/**@} end of group GPIO_EN2_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR + * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN2 to 0, without + * affecting other bits in that register. + * @{ + */ + #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ + #define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ + +/**@} end of group GPIO_EN2_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS GPIO_DS + * @brief GPIO Drive Strength Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ + #define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */ + #define MXC_F_GPIO_DS_DS ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */ + #define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */ + #define MXC_S_GPIO_DS_DS_LD (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */ + #define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */ + #define MXC_S_GPIO_DS_DS_HD (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */ + +/**@} end of group GPIO_DS_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS1 GPIO_DS1 + * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ + #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ + #define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ + +/**@} end of group GPIO_DS1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PS GPIO_PS + * @brief GPIO Pull Select Mode. + * @{ + */ + #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ + #define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */ + +/**@} end of group GPIO_PS_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_VSSEL GPIO_VSSEL + * @brief GPIO Voltage Select. + * @{ + */ + #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ + #define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ + +/**@} end of group GPIO_VSSEL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_REGS_H_ */ diff --git a/Project/SDK/Device/Include/i2c_regs.h b/Project/SDK/Device/Include/i2c_regs.h new file mode 100644 index 0000000..409a3b4 --- /dev/null +++ b/Project/SDK/Device/Include/i2c_regs.h @@ -0,0 +1,843 @@ +/** + * @file i2c_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _I2C_REGS_H_ +#define _I2C_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i2c + * @defgroup i2c_registers I2C_Registers + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + * @details Inter-Integrated Circuit. + */ + +/** + * @ingroup i2c_registers + * Structure type to access the I2C Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: I2C CTRL Register */ + __IO uint32_t status; /**< \b 0x04: I2C STATUS Register */ + __IO uint32_t int_fl0; /**< \b 0x08: I2C INT_FL0 Register */ + __IO uint32_t int_en0; /**< \b 0x0C: I2C INT_EN0 Register */ + __IO uint32_t int_fl1; /**< \b 0x10: I2C INT_FL1 Register */ + __IO uint32_t int_en1; /**< \b 0x14: I2C INT_EN1 Register */ + __IO uint32_t fifo_len; /**< \b 0x18: I2C FIFO_LEN Register */ + __IO uint32_t rx_ctrl0; /**< \b 0x1C: I2C RX_CTRL0 Register */ + __IO uint32_t rx_ctrl1; /**< \b 0x20: I2C RX_CTRL1 Register */ + __IO uint32_t tx_ctrl0; /**< \b 0x24: I2C TX_CTRL0 Register */ + __IO uint32_t tx_ctrl1; /**< \b 0x28: I2C TX_CTRL1 Register */ + __IO uint32_t fifo; /**< \b 0x2C: I2C FIFO Register */ + __IO uint32_t master_ctrl; /**< \b 0x30: I2C MASTER_CTRL Register */ + __IO uint32_t clk_lo; /**< \b 0x34: I2C CLK_LO Register */ + __IO uint32_t clk_hi; /**< \b 0x38: I2C CLK_HI Register */ + __IO uint32_t hs_clk; /**< \b 0x3C: I2C HS_CLK Register */ + __IO uint32_t timeout; /**< \b 0x40: I2C TIMEOUT Register */ + __IO uint32_t slave_addr; /**< \b 0x44: I2C SLAVE_ADDR Register */ + __IO uint32_t dma; /**< \b 0x48: I2C DMA Register */ +} mxc_i2c_regs_t; + +/* Register offsets for module I2C */ +/** + * @ingroup i2c_registers + * @defgroup I2C_Register_Offsets Register Offsets + * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. + * @{ + */ + #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ + #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ + #define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ + #define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ + #define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ + #define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ + #define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ + #define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ + #define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ + #define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ + #define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ + #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ + #define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ + #define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ + #define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ + #define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ + #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ + #define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: 0x0044 */ + #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +/**@} end of group i2c_registers */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CTRL I2C_CTRL + * @brief Control Register0. + * @{ + */ + #define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */ + #define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */ + #define MXC_V_I2C_CTRL_I2C_EN_DIS ((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */ + #define MXC_S_I2C_CTRL_I2C_EN_DIS (MXC_V_I2C_CTRL_I2C_EN_DIS << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */ + #define MXC_V_I2C_CTRL_I2C_EN_EN ((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value */ + #define MXC_S_I2C_CTRL_I2C_EN_EN (MXC_V_I2C_CTRL_I2C_EN_EN << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */ + + #define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */ + #define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */ + #define MXC_V_I2C_CTRL_MST_SLAVE_MODE ((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */ + #define MXC_S_I2C_CTRL_MST_SLAVE_MODE (MXC_V_I2C_CTRL_MST_SLAVE_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */ + #define MXC_V_I2C_CTRL_MST_MASTER_MODE ((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */ + #define MXC_S_I2C_CTRL_MST_MASTER_MODE (MXC_V_I2C_CTRL_MST_MASTER_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */ + + #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */ + #define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR Mask */ + #define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS ((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */ + #define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS (MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS Setting */ + #define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN ((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */ + #define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN (MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN Setting */ + + #define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */ + #define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */ + #define MXC_V_I2C_CTRL_RX_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */ + #define MXC_S_I2C_CTRL_RX_MODE_DIS (MXC_V_I2C_CTRL_RX_MODE_DIS << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */ + #define MXC_V_I2C_CTRL_RX_MODE_EN ((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */ + #define MXC_S_I2C_CTRL_RX_MODE_EN (MXC_V_I2C_CTRL_RX_MODE_EN << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */ + + #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */ + #define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK Mask */ + #define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK ((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */ + #define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK (MXC_V_I2C_CTRL_RX_MODE_ACK_ACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting */ + #define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK ((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */ + #define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK (MXC_V_I2C_CTRL_RX_MODE_ACK_NACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting */ + + #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ + #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ + #define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW ((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */ + #define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW (MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Setting */ + #define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL ((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */ + #define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL (MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting */ + + #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ + #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ + #define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW ((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */ + #define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW (MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Setting */ + #define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA ((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */ + #define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA (MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting */ + + #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ + #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ + + #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ + #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ + + #define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */ + #define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */ + #define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE ((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */ + #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Setting */ + #define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE ((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */ + #define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Setting */ + + #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ + #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ + #define MXC_V_I2C_CTRL_READ_WRITE ((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */ + #define MXC_S_I2C_CTRL_READ_WRITE (MXC_V_I2C_CTRL_READ_WRITE << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */ + #define MXC_V_I2C_CTRL_READ_READ ((uint32_t)0x1UL) /**< CTRL_READ_READ Value */ + #define MXC_S_I2C_CTRL_READ_READ (MXC_V_I2C_CTRL_READ_READ << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */ + + #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS 12 /**< CTRL_SCL_CLK_STRECH_DIS Position */ + #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**< CTRL_SCL_CLK_STRECH_DIS Mask */ + #define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN ((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */ + #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_EN Setting */ + #define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS ((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */ + #define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Setting */ + + #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */ + #define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE Mask */ + #define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */ + #define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS (MXC_V_I2C_CTRL_SCL_PP_MODE_DIS << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting */ + #define MXC_V_I2C_CTRL_SCL_PP_MODE_EN ((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */ + #define MXC_S_I2C_CTRL_SCL_PP_MODE_EN (MXC_V_I2C_CTRL_SCL_PP_MODE_EN << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting */ + + #define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */ + #define MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */ + #define MXC_V_I2C_CTRL_HS_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */ + #define MXC_S_I2C_CTRL_HS_MODE_DIS (MXC_V_I2C_CTRL_HS_MODE_DIS << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */ + #define MXC_V_I2C_CTRL_HS_MODE_EN ((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */ + #define MXC_S_I2C_CTRL_HS_MODE_EN (MXC_V_I2C_CTRL_HS_MODE_EN << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */ + +/**@} end of group I2C_CTRL_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_STATUS I2C_STATUS + * @brief Status Register. + * @{ + */ + #define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */ + #define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask */ + #define MXC_V_I2C_STATUS_BUS_IDLE ((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */ + #define MXC_S_I2C_STATUS_BUS_IDLE (MXC_V_I2C_STATUS_BUS_IDLE << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */ + #define MXC_V_I2C_STATUS_BUS_BUSY ((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */ + #define MXC_S_I2C_STATUS_BUS_BUSY (MXC_V_I2C_STATUS_BUS_BUSY << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */ + + #define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */ + #define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ + #define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */ + #define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY Setting */ + #define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */ + #define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting */ + + #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ + #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + #define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL ((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */ + #define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL (MXC_V_I2C_STATUS_RX_FULL_NOT_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting */ + #define MXC_V_I2C_STATUS_RX_FULL_FULL ((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */ + #define MXC_S_I2C_STATUS_RX_FULL_FULL (MXC_V_I2C_STATUS_RX_FULL_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */ + + #define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */ + #define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ + #define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */ + #define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY Setting */ + #define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */ + #define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting */ + + #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ + #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + #define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */ + #define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY (MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY Setting */ + #define MXC_V_I2C_STATUS_TX_FULL_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */ + #define MXC_S_I2C_STATUS_TX_FULL_EMPTY (MXC_V_I2C_STATUS_TX_FULL_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */ + + #define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */ + #define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */ + #define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Value */ + #define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Setting */ + #define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Value */ + #define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Setting */ + + #define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */ + #define MXC_F_I2C_STATUS_STATUS ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ + #define MXC_V_I2C_STATUS_STATUS_IDLE ((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */ + #define MXC_S_I2C_STATUS_STATUS_IDLE (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */ + #define MXC_V_I2C_STATUS_STATUS_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_MTX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_SRX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */ + #define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR Setting */ + #define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_TX ((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */ + #define MXC_S_I2C_STATUS_STATUS_TX (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */ + #define MXC_V_I2C_STATUS_STATUS_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_RX_ACK (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_RX ((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */ + #define MXC_S_I2C_STATUS_STATUS_RX (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */ + #define MXC_V_I2C_STATUS_STATUS_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */ + #define MXC_S_I2C_STATUS_STATUS_TX_ACK (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_NACK ((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */ + #define MXC_S_I2C_STATUS_STATUS_NACK (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */ + #define MXC_V_I2C_STATUS_STATUS_BY_ST ((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */ + #define MXC_S_I2C_STATUS_STATUS_BY_ST (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */ + +/**@} end of group I2C_STATUS_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INT_FL0 I2C_INT_FL0 + * @brief Interrupt Status Register. + * @{ + */ + #define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */ + #define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */ + #define MXC_V_I2C_INT_FL0_DONE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_DONE_INACTIVE (MXC_V_I2C_INT_FL0_DONE_INACTIVE << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_DONE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */ + #define MXC_S_I2C_INT_FL0_DONE_PENDING (MXC_V_I2C_INT_FL0_DONE_PENDING << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */ + #define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE Mask */ + #define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE (MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_RX_MODE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */ + #define MXC_S_I2C_INT_FL0_RX_MODE_PENDING (MXC_V_I2C_INT_FL0_RX_MODE_PENDING << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 /**< INT_FL0_GEN_CALL_ADDR Position */ + #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< INT_FL0_GEN_CALL_ADDR Mask */ + #define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING ((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */ + #define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */ + #define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH Mask */ + #define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */ + #define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING (MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */ + #define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH Mask */ + #define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */ + #define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING (MXC_V_I2C_INT_FL0_RX_THRESH_PENDING << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */ + #define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH Mask */ + #define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */ + #define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING (MXC_V_I2C_INT_FL0_TX_THRESH_PENDING << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */ + #define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */ + #define MXC_V_I2C_INT_FL0_STOP_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_STOP_INACTIVE (MXC_V_I2C_INT_FL0_STOP_INACTIVE << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_STOP_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */ + #define MXC_S_I2C_INT_FL0_STOP_PENDING (MXC_V_I2C_INT_FL0_STOP_PENDING << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */ + #define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK Mask */ + #define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */ + #define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING (MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */ + #define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */ + #define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE (MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_ARB_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_ARB_ER_PENDING (MXC_V_I2C_INT_FL0_ARB_ER_PENDING << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */ + #define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */ + #define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE (MXC_V_I2C_INT_FL0_TO_ER_INACTIVE << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_TO_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_TO_ER_PENDING (MXC_V_I2C_INT_FL0_TO_ER_PENDING << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 /**< INT_FL0_ADDR_NACK_ER Position */ + #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< INT_FL0_ADDR_NACK_ER Mask */ + #define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */ + #define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER Mask */ + #define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE (MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_DATA_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_DATA_ER_PENDING (MXC_V_I2C_INT_FL0_DATA_ER_PENDING << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 /**< INT_FL0_DO_NOT_RESP_ER Position */ + #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< INT_FL0_DO_NOT_RESP_ER Mask */ + #define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */ + #define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER Mask */ + #define MXC_V_I2C_INT_FL0_START_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_START_ER_INACTIVE (MXC_V_I2C_INT_FL0_START_ER_INACTIVE << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_START_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_START_ER_PENDING (MXC_V_I2C_INT_FL0_START_ER_PENDING << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */ + #define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER Mask */ + #define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */ + #define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE (MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL0_STOP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */ + #define MXC_S_I2C_INT_FL0_STOP_ER_PENDING (MXC_V_I2C_INT_FL0_STOP_ER_PENDING << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING Setting */ + + #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 /**< INT_FL0_TX_LOCK_OUT Position */ + #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */ + +/**@} end of group I2C_INT_FL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INT_EN0 I2C_INT_EN0 + * @brief Interrupt Enable Register. + * @{ + */ + #define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */ + #define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */ + #define MXC_V_I2C_INT_EN0_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */ + #define MXC_S_I2C_INT_EN0_DONE_DIS (MXC_V_I2C_INT_EN0_DONE_DIS << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */ + #define MXC_V_I2C_INT_EN0_DONE_EN ((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */ + #define MXC_S_I2C_INT_EN0_DONE_EN (MXC_V_I2C_INT_EN0_DONE_EN << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */ + + #define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */ + #define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE Mask */ + #define MXC_V_I2C_INT_EN0_RX_MODE_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */ + #define MXC_S_I2C_INT_EN0_RX_MODE_DIS (MXC_V_I2C_INT_EN0_RX_MODE_DIS << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */ + #define MXC_V_I2C_INT_EN0_RX_MODE_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */ + #define MXC_S_I2C_INT_EN0_RX_MODE_EN (MXC_V_I2C_INT_EN0_RX_MODE_EN << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */ + + #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS 2 /**< INT_EN0_GEN_CTRL_ADDR Position */ + #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**< INT_EN0_GEN_CTRL_ADDR Mask */ + #define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS ((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */ + #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_DIS Setting */ + #define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN ((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */ + #define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN Setting */ + + #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */ + #define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH Mask */ + #define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */ + #define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS (MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS Setting */ + #define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */ + #define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN (MXC_V_I2C_INT_EN0_ADDR_MATCH_EN << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN Setting */ + + #define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */ + #define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH Mask */ + #define MXC_V_I2C_INT_EN0_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */ + #define MXC_S_I2C_INT_EN0_RX_THRESH_DIS (MXC_V_I2C_INT_EN0_RX_THRESH_DIS << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS Setting */ + #define MXC_V_I2C_INT_EN0_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */ + #define MXC_S_I2C_INT_EN0_RX_THRESH_EN (MXC_V_I2C_INT_EN0_RX_THRESH_EN << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting */ + + #define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */ + #define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH Mask */ + #define MXC_V_I2C_INT_EN0_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */ + #define MXC_S_I2C_INT_EN0_TX_THRESH_DIS (MXC_V_I2C_INT_EN0_TX_THRESH_DIS << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS Setting */ + #define MXC_V_I2C_INT_EN0_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */ + #define MXC_S_I2C_INT_EN0_TX_THRESH_EN (MXC_V_I2C_INT_EN0_TX_THRESH_EN << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting */ + + #define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */ + #define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */ + #define MXC_V_I2C_INT_EN0_STOP_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */ + #define MXC_S_I2C_INT_EN0_STOP_DIS (MXC_V_I2C_INT_EN0_STOP_DIS << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */ + #define MXC_V_I2C_INT_EN0_STOP_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */ + #define MXC_S_I2C_INT_EN0_STOP_EN (MXC_V_I2C_INT_EN0_STOP_EN << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */ + + #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */ + #define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK Mask */ + #define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */ + #define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS (MXC_V_I2C_INT_EN0_ADDR_ACK_DIS << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting */ + #define MXC_V_I2C_INT_EN0_ADDR_ACK_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */ + #define MXC_S_I2C_INT_EN0_ADDR_ACK_EN (MXC_V_I2C_INT_EN0_ADDR_ACK_EN << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting */ + + #define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */ + #define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */ + #define MXC_V_I2C_INT_EN0_ARB_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_ARB_ER_DIS (MXC_V_I2C_INT_EN0_ARB_ER_DIS << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_ARB_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_ARB_ER_EN (MXC_V_I2C_INT_EN0_ARB_ER_EN << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */ + #define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */ + #define MXC_V_I2C_INT_EN0_TO_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_TO_ER_DIS (MXC_V_I2C_INT_EN0_TO_ER_DIS << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_TO_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_TO_ER_EN (MXC_V_I2C_INT_EN0_TO_ER_EN << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */ + #define MXC_F_I2C_INT_EN0_ADDR_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER Mask */ + #define MXC_V_I2C_INT_EN0_ADDR_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_ADDR_ER_DIS (MXC_V_I2C_INT_EN0_ADDR_ER_DIS << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_ADDR_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_ADDR_ER_EN (MXC_V_I2C_INT_EN0_ADDR_ER_EN << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */ + #define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER Mask */ + #define MXC_V_I2C_INT_EN0_DATA_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_DATA_ER_DIS (MXC_V_I2C_INT_EN0_DATA_ER_DIS << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_DATA_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_DATA_ER_EN (MXC_V_I2C_INT_EN0_DATA_ER_EN << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 /**< INT_EN0_DO_NOT_RESP_ER Position */ + #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< INT_EN0_DO_NOT_RESP_ER Mask */ + #define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */ + #define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER Mask */ + #define MXC_V_I2C_INT_EN0_START_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_START_ER_DIS (MXC_V_I2C_INT_EN0_START_ER_DIS << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_START_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_START_ER_EN (MXC_V_I2C_INT_EN0_START_ER_EN << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */ + #define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER Mask */ + #define MXC_V_I2C_INT_EN0_STOP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */ + #define MXC_S_I2C_INT_EN0_STOP_ER_DIS (MXC_V_I2C_INT_EN0_STOP_ER_DIS << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */ + #define MXC_V_I2C_INT_EN0_STOP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */ + #define MXC_S_I2C_INT_EN0_STOP_ER_EN (MXC_V_I2C_INT_EN0_STOP_ER_EN << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */ + + #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 /**< INT_EN0_TX_LOCK_OUT Position */ + #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */ + #define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */ + #define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS Setting */ + #define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */ + #define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN Setting */ + +/**@} end of group I2C_INT_EN0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INT_FL1 I2C_INT_FL1 + * @brief Interrupt Status Register 1. + * @{ + */ + #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 /**< INT_FL1_RX_OVERFLOW Position */ + #define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< INT_FL1_RX_OVERFLOW Mask */ + #define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */ + #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */ + #define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING (MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_PENDING Setting */ + + #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 /**< INT_FL1_TX_UNDERFLOW Position */ + #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */ + #define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */ + #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Setting */ + #define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */ + #define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_PENDING Setting */ + +/**@} end of group I2C_INT_FL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INT_EN1 I2C_INT_EN1 + * @brief Interrupt Staus Register 1. + * @{ + */ + #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 /**< INT_EN1_RX_OVERFLOW Position */ + #define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< INT_EN1_RX_OVERFLOW Mask */ + #define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */ + #define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS (MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS Setting */ + #define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */ + #define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN (MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN Setting */ + + #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 /**< INT_EN1_TX_UNDERFLOW Position */ + #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */ + #define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */ + #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS Setting */ + #define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */ + #define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN Setting */ + +/**@} end of group I2C_INT_EN1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFO_LEN I2C_FIFO_LEN + * @brief FIFO Configuration Register. + * @{ + */ + #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */ + #define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN Mask */ + + #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */ + #define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN Mask */ + +/**@} end of group I2C_FIFO_LEN_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0 + * @brief Receive Control Register 0. + * @{ + */ + #define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */ + #define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */ + #define MXC_V_I2C_RX_CTRL0_DNR_RESPOND ((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */ + #define MXC_S_I2C_RX_CTRL0_DNR_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */ + #define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY ((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */ + #define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY (MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Setting */ + + #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */ + #define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH Mask */ + #define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */ + #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED (MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Setting */ + #define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */ + #define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH (MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH Setting */ + + #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */ + #define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH Mask */ + +/**@} end of group I2C_RX_CTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1 + * @brief Receive Control Register 1. + * @{ + */ + #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */ + #define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT Mask */ + + #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */ + #define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO Mask */ + +/**@} end of group I2C_RX_CTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0 + * @brief Transmit Control Register 0. + * @{ + */ + #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 /**< TX_CTRL0_TX_PRELOAD Position */ + #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< TX_CTRL0_TX_PRELOAD Mask */ + + #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 /**< TX_CTRL0_TX_READY_MODE Position */ + #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */ + #define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN ((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */ + #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_EN Setting */ + #define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS ((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */ + #define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_DIS Setting */ + + #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */ + #define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */ + #define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */ + #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED (MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Setting */ + #define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */ + #define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH (MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH Setting */ + + #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */ + #define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH Mask */ + +/**@} end of group I2C_TX_CTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1 + * @brief Transmit Control Register 1. + * @{ + */ + #define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */ + #define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY Mask */ + + #define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */ + #define MXC_F_I2C_TX_CTRL1_TX_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST Mask */ + #define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW ((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */ + #define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW (MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Setting */ + #define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION ((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */ + #define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION (MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Setting */ + + #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */ + #define MXC_F_I2C_TX_CTRL1_TX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO Mask */ + +/**@} end of group I2C_TX_CTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFO I2C_FIFO + * @brief Data Register. + * @{ + */ + #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ + #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +/**@} end of group I2C_FIFO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_MASTER_CTRL I2C_MASTER_CTRL + * @brief Master Control Register. + * @{ + */ + #define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */ + #define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START Mask */ + + #define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 /**< MASTER_CTRL_RESTART Position */ + #define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< MASTER_CTRL_RESTART Mask */ + + #define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */ + #define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP Mask */ + + #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 /**< MASTER_CTRL_SL_EX_ADDR Position */ + #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< MASTER_CTRL_SL_EX_ADDR Mask */ + #define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */ + #define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Setting */ + #define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */ + #define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Setting */ + + #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS 8 /**< MASTER_CTRL_MASTER_CODE Position */ + #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**< MASTER_CTRL_MASTER_CODE Mask */ + + #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 /**< MASTER_CTRL_SCL_SPEED_UP Position */ + #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**< MASTER_CTRL_SCL_SPEED_UP Mask */ + #define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN ((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */ + #define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_EN Setting */ + #define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS ((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */ + #define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Setting */ + +/**@} end of group I2C_MASTER_CTRL_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLK_LO I2C_CLK_LO + * @brief Clock Low Register. + * @{ + */ + #define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */ + #define MXC_F_I2C_CLK_LO_CLK_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */ + +/**@} end of group I2C_CLK_LO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLK_HI I2C_CLK_HI + * @brief Clock high Register. + * @{ + */ + #define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */ + #define MXC_F_I2C_CLK_HI_CKH ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */ + +/**@} end of group I2C_CLK_HI_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_HS_CLK I2C_HS_CLK + * @brief HS-Mode Clock Control Register + * @{ + */ + #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */ + #define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */ + + #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */ + #define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */ + +/**@} end of group I2C_HS_CLK_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TIMEOUT I2C_TIMEOUT + * @brief Timeout Register + * @{ + */ + #define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ + #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ + +/**@} end of group I2C_TIMEOUT_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_SLAVE_ADDR I2C_SLAVE_ADDR + * @brief Slave Address Register. + * @{ + */ + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */ + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */ + + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */ + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_DIS Mask */ + + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */ + #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_IDX Mask */ + + #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 /**< SLAVE_ADDR_EX_ADDR Position */ + #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */ + #define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */ + #define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */ + #define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */ + #define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */ + +/**@} end of group I2C_SLAVE_ADDR_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_DMA I2C_DMA + * @brief DMA Register. + * @{ + */ + #define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ + #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ + #define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */ + #define MXC_S_I2C_DMA_TX_EN_DIS (MXC_V_I2C_DMA_TX_EN_DIS << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */ + #define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */ + #define MXC_S_I2C_DMA_TX_EN_EN (MXC_V_I2C_DMA_TX_EN_EN << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */ + + #define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ + #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ + #define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */ + #define MXC_S_I2C_DMA_RX_EN_DIS (MXC_V_I2C_DMA_RX_EN_DIS << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */ + #define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */ + #define MXC_S_I2C_DMA_RX_EN_EN (MXC_V_I2C_DMA_RX_EN_EN << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */ + +/**@} end of group I2C_DMA_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _I2C_REGS_H_ */ diff --git a/Project/SDK/Device/Include/icc_regs.h b/Project/SDK/Device/Include/icc_regs.h new file mode 100644 index 0000000..abfb9d1 --- /dev/null +++ b/Project/SDK/Device/Include/icc_regs.h @@ -0,0 +1,167 @@ +/** + * @file icc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _ICC_REGS_H_ +#define _ICC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup icc + * @defgroup icc_registers ICC_Registers + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @details Instruction Cache Controller Registers + */ + +/** + * @ingroup icc_registers + * Structure type to access the ICC Registers. + */ +typedef struct { + __I uint32_t cache_id; /**< \b 0x0000: ICC CACHE_ID Register */ + __I uint32_t memcfg; /**< \b 0x0004: ICC MEMCFG Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO uint32_t cache_ctrl; /**< \b 0x0100: ICC CACHE_CTRL Register */ + __R uint32_t rsv_0x104_0x6ff[383]; + __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ +} mxc_icc_regs_t; + +/* Register offsets for module ICC */ +/** + * @ingroup icc_registers + * @defgroup ICC_Register_Offsets Register Offsets + * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. + * @{ + */ + #define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ + #define MXC_R_ICC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ + #define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ + #define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ +/**@} end of group icc_registers */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CACHE_ID ICC_CACHE_ID + * @brief Cache ID Register. + * @{ + */ + #define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ + #define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ + + #define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ + #define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ + + #define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ + #define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ + +/**@} end of group ICC_CACHE_ID_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_MEMCFG ICC_MEMCFG + * @brief Memory Configuration Register. + * @{ + */ + #define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */ + #define MXC_F_ICC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */ + + #define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */ + #define MXC_F_ICC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */ + +/**@} end of group ICC_MEMCFG_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CACHE_CTRL ICC_CACHE_CTRL + * @brief Cache Control and Status Register. + * @{ + */ + #define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */ + #define MXC_F_ICC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */ + #define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */ + #define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS Setting */ + #define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */ + #define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN Setting */ + + #define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */ + #define MXC_F_ICC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */ + #define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */ + #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Setting */ + #define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */ + #define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_READY Setting */ + +/**@} end of group ICC_CACHE_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ICC_REGS_H_ */ diff --git a/Project/SDK/Device/Include/max32660.h b/Project/SDK/Device/Include/max32660.h new file mode 100644 index 0000000..6df6839 --- /dev/null +++ b/Project/SDK/Device/Include/max32660.h @@ -0,0 +1,403 @@ +/** + * @file max32660.h + * @brief Device-specific perhiperal header file + */ + +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +#ifndef _MAX32660_REGS_H_ +#define _MAX32660_REGS_H_ + +#ifndef TARGET_NUM +#define TARGET_NUM 32660 +#endif + +#include + +#ifndef FALSE +#define FALSE (0) +#endif + +#ifndef TRUE +#define TRUE (1) +#endif + +#if !defined (__GNUC__) +#define CMSIS_VECTAB_VIRTUAL +#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h" +#endif /* !__GNUC__ */ + +/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ +#if defined ( __GNUC__ ) /* GCC */ +#define __weak __attribute__((weak)) + +#elif defined ( __CC_ARM) /* Keil */ + +#define inline __inline +#pragma anon_unions + +#endif + +typedef enum { + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* Device-specific interrupt sources (external to ARM core) */ + /* table entry number */ + /* |||| */ + /* |||| table offset address */ + /* vvvv vvvvvv */ + + PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */ + WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */ + RSV00_IRQn, /* 0x12 0x0048 18: RSV00 */ + RTC_IRQn, /* 0x13 0x004C 19: RTC */ + RSV1_IRQn, /* 0x14 0x0050 20: RSV1 */ + TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ + TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ + TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ + RSV02_IRQn, /* 0x18 0x0060 24: RSV02 */ + RSV03_IRQn, /* 0x19 0x0064 25: RSV03 */ + RSV04_IRQn, /* 0x1A 0x0068 26: RSV04 */ + RSV05_IRQn, /* 0x1B 0x006C 27: RSV05 */ + RSV06_IRQn, /* 0x1C 0x0070 28: RSV06 */ + I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */ + UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */ + UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */ + SPI17Y_IRQn, /* 0x20 0x0080 32: SPI17Y */ + SPIMSS_IRQn, /* 0x21 0x0084 33: SPIMSS */ + RSV07_IRQn, /* 0x22 0x0088 34: RSV07 */ + RSV08_IRQn, /* 0x23 0x008C 35: RSV08 */ + RSV09_IRQn, /* 0x24 0x0090 36: RSV09 */ + RSV10_IRQn, /* 0x25 0x0094 37: RSV10 */ + RSV11_IRQn, /* 0x26 0x0098 38: RSV11 */ + FLC_IRQn, /* 0x27 0x009C 39: FLC */ + GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ + RSV12_IRQn, /* 0x29 0x00A4 41: RSV12 */ + RSV13_IRQn, /* 0x2A 0x00A8 42: RSV13 */ + RSV14_IRQn, /* 0x2B 0x00AC 43: RSV14 */ + DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ + DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ + DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ + DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ + RSV15_IRQn, /* 0x30 0x00C0 48: RSV15 */ + RSV16_IRQn, /* 0x31 0x00C4 49: RSV16 */ + RSV17_IRQn, /* 0x32 0x00C8 50: RSV17 */ + RSV18_IRQn, /* 0x33 0x00CC 51: RSV18 */ + I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */ + RSV19_IRQn, /* 0x35 0x00D4 53: RSV19 */ + RSV20_IRQn, /* 0x36 0x00D8 54: RSV20 */ + RSV21_IRQn, /* 0x37 0x00DC 55: RSV21 */ + RSV22_IRQn, /* 0x38 0x00E0 56: RSV22 */ + RSV23_IRQn, /* 0x39 0x00E4 57: RSV23 */ + RSV24_IRQn, /* 0x3A 0x00E8 58: RSV24 */ + RSV25_IRQn, /* 0x3B 0x00EC 59: RSV25 */ + RSV26_IRQn, /* 0x3C 0x00F0 60: RSV26 */ + RSV27_IRQn, /* 0x3D 0x00F4 61: RSV27 */ + RSV28_IRQn, /* 0x3E 0x00F8 62: RSV28 */ + RSV29_IRQn, /* 0x3F 0x00FC 63: RSV29 */ + RSV30_IRQn, /* 0x40 0x0100 64: RSV30 */ + RSV31_IRQn, /* 0x41 0x0104 65: RSV31 */ + RSV32_IRQn, /* 0x42 0x0108 66: RSV32 */ + RSV33_IRQn, /* 0x43 0x010C 67: RSV33 */ + RSV34_IRQn, /* 0x44 0x0110 68: RSV34 */ + RSV35_IRQn, /* 0x45 0x0114 69: RSV35 */ + GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ + MXC_IRQ_EXT_COUNT, +} IRQn_Type; + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +#include /*!< Cortex-M4 processor and core peripherals */ +#include "system_max32660.h" /*!< System Header */ + + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ + +#define MXC_FLASH_MEM_BASE 0x00000000UL +#define MXC_FLASH_PAGE_SIZE 0x00002000UL +#define MXC_FLASH_MEM_SIZE 0x00040000UL +#define MXC_INFO_MEM_BASE 0x00040000UL +#define MXC_INFO_MEM_SIZE 0x00001000UL +#define MXC_SRAM_MEM_BASE 0x20000000UL +#define MXC_SRAM_MEM_SIZE 0x00018000UL + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* + Base addresses and configuration settings for all MAX32660 peripheral modules. +*/ + +/******************************************************************************/ +/* Global control */ +#define MXC_BASE_GCR ((uint32_t)0x40000000UL) +#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR) + +/******************************************************************************/ +/* Non-battery backed SI Registers */ +#define MXC_BASE_SIR ((uint32_t)0x40000400UL) +#define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR) + +/******************************************************************************/ +/* Watchdog */ +#define MXC_BASE_WDT0 ((uint32_t)0x40003000UL) +#define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0) + +/******************************************************************************/ +/* Real Time Clock */ +#define MXC_BASE_RTC ((uint32_t)0x40006000UL) +#define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC) + +/******************************************************************************/ +/* Power Sequencer */ +#define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL) +#define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ) + + +/******************************************************************************/ +/* GPIO */ +#define MXC_CFG_GPIO_INSTANCES (1) +#define MXC_CFG_GPIO_PINS_PORT (14) + +#define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL) +#define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0) + +#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 :-1) + +#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) + +#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : 0) + +/******************************************************************************/ +/* Timer */ +#define MXC_CFG_TMR_INSTANCES (3) + +#define MXC_BASE_TMR0 ((uint32_t)0x40010000UL) +#define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0) +#define MXC_BASE_TMR1 ((uint32_t)0x40011000UL) +#define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1) +#define MXC_BASE_TMR2 ((uint32_t)0x40012000UL) +#define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2) + +#define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : 0) + +#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : 0) + +#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : 0) + +#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \ + (p) == MXC_TMR1 ? 1 : \ + (p) == MXC_TMR2 ? 2 : -1) + +/******************************************************************************/ +/* SPIMSS */ + +#define MXC_SPIMSS_INSTANCES (1) +#define MXC_SPIMSS_FIFO_DEPTH (8) + +#define MXC_BASE_SPIMSS ((uint32_t)0x40019000UL) +#define MXC_SPIMSS ((mxc_spimss_regs_t*)MXC_BASE_SPIMSS) + +#define MXC_SPIMSS_GET_IDX(p) ((p) == MXC_SPIMSS ? 0 : -1) +#define MXC_SPIMSS_GET_SPI(i) ((i) == 0 ? MXC_SPIMSS : 0) + +/******************************************************************************/ +/* I2C */ +#define MXC_I2C_INSTANCES (2) +#define MXC_I2C_FIFO_DEPTH (8) + +#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL) +#define MXC_I2C0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0) +#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL) +#define MXC_I2C1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1) + +#define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2C0_IRQn : \ + (i) == 1 ? I2C1_IRQn : 0) + +#define MXC_I2C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2C0 : \ + (i) == 1 ? MXC_BASE_I2C1 : 0) + +#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : \ + (i) == 1 ? MXC_I2C1 : 0) + +#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : \ + (p) == MXC_I2C1 ? 1 : -1) + +/******************************************************************************/ +/* DMA */ +#define MXC_DMA_CHANNELS (4) + +#define MXC_BASE_DMA ((uint32_t)0x40028000UL) +#define MXC_DMA ((mxc_dma_regs_t*)MXC_BASE_DMA) + +/******************************************************************************/ +/* FLC */ +#define MXC_BASE_FLC ((uint32_t)0x40029000UL) +#define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC) + +/******************************************************************************/ +/* Instruction Cache */ +#define MXC_BASE_ICC ((uint32_t)0x4002A000UL) +#define MXC_ICC ((mxc_icc_regs_t*)MXC_BASE_ICC) + +/******************************************************************************/ +/* UART / Serial Port Interface */ + +#define MXC_UART_INSTANCES (2) +#define MXC_UART_FIFO_DEPTH (8) + +#define MXC_BASE_UART0 ((uint32_t)0x40042000UL) +#define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0) +#define MXC_BASE_UART1 ((uint32_t)0x40043000UL) +#define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1) + +#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \ + (i) == 1 ? UART1_IRQn : 0) + +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ + (i) == 1 ? MXC_BASE_UART1 : 0) + +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ + (i) == 1 ? MXC_UART1 : 0) + +#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \ + (p) == MXC_UART1 ? 1 : -1) + +/******************************************************************************/ +/* SPI */ + + +#define MXC_SPI17Y_INSTANCES (4) +#define MXC_SPI17Y_SS_INSTANCES (1) +#define MXC_SPI17Y_FIFO_DEPTH (32) + +#define MXC_BASE_SPI17Y ((uint32_t)0x40046000UL) +#define MXC_SPI17Y ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y) + +#define MXC_SPI17Y_GET_IDX(p) ((p) == MXC_SPI17Y ? 0 : -1) + +#define MXC_SPI17Y_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI17Y : 0) + +#define MXC_SPI17Y_GET_SPI17Y(i) ((i) == 0 ? MXC_SPI17Y : 0) + +/******************************************************************************/ +/* Bit Shifting */ + +#define MXC_F_BIT_0 (1 << 0) +#define MXC_F_BIT_1 (1 << 1) +#define MXC_F_BIT_2 (1 << 2) +#define MXC_F_BIT_3 (1 << 3) +#define MXC_F_BIT_4 (1 << 4) +#define MXC_F_BIT_5 (1 << 5) +#define MXC_F_BIT_6 (1 << 6) +#define MXC_F_BIT_7 (1 << 7) +#define MXC_F_BIT_8 (1 << 8) +#define MXC_F_BIT_9 (1 << 9) +#define MXC_F_BIT_10 (1 << 10) +#define MXC_F_BIT_11 (1 << 11) +#define MXC_F_BIT_12 (1 << 12) +#define MXC_F_BIT_13 (1 << 13) +#define MXC_F_BIT_14 (1 << 14) +#define MXC_F_BIT_15 (1 << 15) +#define MXC_F_BIT_16 (1 << 16) +#define MXC_F_BIT_17 (1 << 17) +#define MXC_F_BIT_18 (1 << 18) +#define MXC_F_BIT_19 (1 << 19) +#define MXC_F_BIT_20 (1 << 20) +#define MXC_F_BIT_21 (1 << 21) +#define MXC_F_BIT_22 (1 << 22) +#define MXC_F_BIT_23 (1 << 23) +#define MXC_F_BIT_24 (1 << 24) +#define MXC_F_BIT_25 (1 << 25) +#define MXC_F_BIT_26 (1 << 26) +#define MXC_F_BIT_27 (1 << 27) +#define MXC_F_BIT_28 (1 << 28) +#define MXC_F_BIT_29 (1 << 29) +#define MXC_F_BIT_30 (1 << 30) +#define MXC_F_BIT_31 (1 << 31) + +/******************************************************************************/ +/* Bit Banding */ + +#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \ + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2)) + +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + +#define MXC_SETFIELD(reg, mask, value) (reg = (reg & ~mask) | (value & mask)) + +/******************************************************************************/ +/* SCB CPACR */ + +/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */ +#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ +#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ +#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ +#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ + +#endif /* _MAX32660_REGS_H_ */ diff --git a/Project/SDK/Device/Include/mxc_device.h b/Project/SDK/Device/Include/mxc_device.h new file mode 100644 index 0000000..26fd450 --- /dev/null +++ b/Project/SDK/Device/Include/mxc_device.h @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +/** + * @file mxc_device.h + * @brief contains device and revision specific definitions + */ + +#ifndef _MXC_DEVICE_H_ +#define _MXC_DEVICE_H_ + +#include "max32660.h" + +#ifndef TARGET + #error TARGET NOT DEFINED +#endif + +// Create a string definition for the TARGET +#define STRING_ARG(arg) #arg +#define STRING_NAME(name) STRING_ARG(name) +#define TARGET_NAME STRING_NAME(TARGET) + +// Define which revisions of the IP we are using +#ifndef TARGET_REV + #error TARGET_REV NOT DEFINED +#endif + +#if(TARGET_REV == 0x4131) + // A1 + #define MXC_PBM_REV 0 + #define MXC_TMR_REV 0 + #define MXC_UART_REV 1 +#else + +#error TARGET_REV NOT SUPPORTED + +#endif // if(TARGET_REV == ...) + +#endif /* _MXC_DEVICE_H_ */ diff --git a/Project/SDK/Device/Include/pwrseq_regs.h b/Project/SDK/Device/Include/pwrseq_regs.h new file mode 100644 index 0000000..38c2638 --- /dev/null +++ b/Project/SDK/Device/Include/pwrseq_regs.h @@ -0,0 +1,273 @@ +/** + * @file pwrseq_regs.h + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _PWRSEQ_REGS_H_ +#define _PWRSEQ_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup pwrseq + * @defgroup pwrseq_registers PWRSEQ_Registers + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @details Power Sequencer / Low Power Control Register. + */ + +/** + * @ingroup pwrseq_registers + * Structure type to access the PWRSEQ Registers. + */ +typedef struct { + __IO uint32_t lp_ctrl; /**< \b 0x00: PWRSEQ LP_CTRL Register */ + __IO uint32_t lp_wakefl; /**< \b 0x04: PWRSEQ LP_WAKEFL Register */ + __IO uint32_t lpwk_en; /**< \b 0x08: PWRSEQ LPWK_EN Register */ + __R uint32_t rsv_0xc_0x3f[13]; + __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ +} mxc_pwrseq_regs_t; + +/* Register offsets for module PWRSEQ */ +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_Register_Offsets Register Offsets + * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. + * @{ + */ + #define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ + #define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ + #define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ + #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ +/**@} end of group pwrseq_registers */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LP_CTRL PWRSEQ_LP_CTRL + * @brief Low Power Control Register. + * @{ + */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */ + #define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ + #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */ + #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */ + #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */ + #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */ + #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */ + #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_DIS Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_EN Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_EN Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_DIS Setting */ + + #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */ + #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */ + #define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_EN Setting */ + #define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */ + #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_DIS Setting */ + +/**@} end of group PWRSEQ_LP_CTRL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LP_WAKEFL PWRSEQ_LP_WAKEFL + * @brief Low Power Mode Wakeup Flags for GPIO0 + * @{ + */ + #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ + #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */ + +/**@} end of group PWRSEQ_LP_WAKEFL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWK_EN PWRSEQ_LPWK_EN + * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup + * functionality for GPIO0. + * @{ + */ + #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ + #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */ + +/**@} end of group PWRSEQ_LPWK_EN_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD + * @brief Low Power Memory Shutdown Control. + * @{ + */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL Setting */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Setting */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL Setting */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Setting */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL Setting */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Setting */ + + #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */ + #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL Setting */ + #define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */ + #define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Setting */ + +/**@} end of group PWRSEQ_LPMEMSD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _PWRSEQ_REGS_H_ */ diff --git a/Project/SDK/Device/Include/rtc_regs.h b/Project/SDK/Device/Include/rtc_regs.h new file mode 100644 index 0000000..678ed2a --- /dev/null +++ b/Project/SDK/Device/Include/rtc_regs.h @@ -0,0 +1,297 @@ +/** + * @file rtc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _RTC_REGS_H_ +#define _RTC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup rtc + * @defgroup rtc_registers RTC_Registers + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @details Real Time Clock and Alarm. + */ + +/** + * @ingroup rtc_registers + * Structure type to access the RTC Registers. + */ +typedef struct { + __IO uint32_t sec; /**< \b 0x00: RTC SEC Register */ + __IO uint32_t ssec; /**< \b 0x04: RTC SSEC Register */ + __IO uint32_t ras; /**< \b 0x08: RTC RAS Register */ + __IO uint32_t rssa; /**< \b 0x0C: RTC RSSA Register */ + __IO uint32_t ctrl; /**< \b 0x10: RTC CTRL Register */ + __IO uint32_t trim; /**< \b 0x14: RTC TRIM Register */ + __IO uint32_t oscctrl; /**< \b 0x18: RTC OSCCTRL Register */ +} mxc_rtc_regs_t; + +/* Register offsets for module RTC */ +/** + * @ingroup rtc_registers + * @defgroup RTC_Register_Offsets Register Offsets + * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. + * @{ + */ + #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ + #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ + #define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ + #define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ + #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ + #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ + #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ +/**@} end of group rtc_registers */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSEC RTC_SSEC + * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented + * when this register rolls over from 0xFF to 0x00. + * @{ + */ + #define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ + #define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ + +/**@} end of group RTC_SSEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_RAS RTC_RAS + * @brief Time-of-day Alarm. + * @{ + */ + #define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */ + #define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */ + +/**@} end of group RTC_RAS_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_RSSA RTC_RSSA + * @brief RTC sub-second alarm. This register contains the reload value for the sub- + * second alarm. + * @{ + */ + #define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ + #define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ + +/**@} end of group RTC_RSSA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_CTRL RTC_CTRL + * @brief RTC Control Register. + * @{ + */ + #define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */ + #define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */ + #define MXC_V_RTC_CTRL_RTCE_DIS ((uint32_t)0x0UL) /**< CTRL_RTCE_DIS Value */ + #define MXC_S_RTC_CTRL_RTCE_DIS (MXC_V_RTC_CTRL_RTCE_DIS << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_DIS Setting */ + #define MXC_V_RTC_CTRL_RTCE_EN ((uint32_t)0x1UL) /**< CTRL_RTCE_EN Value */ + #define MXC_S_RTC_CTRL_RTCE_EN (MXC_V_RTC_CTRL_RTCE_EN << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_EN Setting */ + + #define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ + #define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ + #define MXC_V_RTC_CTRL_ADE_DIS ((uint32_t)0x0UL) /**< CTRL_ADE_DIS Value */ + #define MXC_S_RTC_CTRL_ADE_DIS (MXC_V_RTC_CTRL_ADE_DIS << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_DIS Setting */ + #define MXC_V_RTC_CTRL_ADE_EN ((uint32_t)0x1UL) /**< CTRL_ADE_EN Value */ + #define MXC_S_RTC_CTRL_ADE_EN (MXC_V_RTC_CTRL_ADE_EN << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_EN Setting */ + + #define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ + #define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ + #define MXC_V_RTC_CTRL_ASE_DIS ((uint32_t)0x0UL) /**< CTRL_ASE_DIS Value */ + #define MXC_S_RTC_CTRL_ASE_DIS (MXC_V_RTC_CTRL_ASE_DIS << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_DIS Setting */ + #define MXC_V_RTC_CTRL_ASE_EN ((uint32_t)0x1UL) /**< CTRL_ASE_EN Value */ + #define MXC_S_RTC_CTRL_ASE_EN (MXC_V_RTC_CTRL_ASE_EN << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_EN Setting */ + + #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ + #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + #define MXC_V_RTC_CTRL_BUSY_IDLE ((uint32_t)0x0UL) /**< CTRL_BUSY_IDLE Value */ + #define MXC_S_RTC_CTRL_BUSY_IDLE (MXC_V_RTC_CTRL_BUSY_IDLE << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_IDLE Setting */ + #define MXC_V_RTC_CTRL_BUSY_BUSY ((uint32_t)0x1UL) /**< CTRL_BUSY_BUSY Value */ + #define MXC_S_RTC_CTRL_BUSY_BUSY (MXC_V_RTC_CTRL_BUSY_BUSY << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_BUSY Setting */ + + #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ + #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + #define MXC_V_RTC_CTRL_RDY_BUSY ((uint32_t)0x0UL) /**< CTRL_RDY_BUSY Value */ + #define MXC_S_RTC_CTRL_RDY_BUSY (MXC_V_RTC_CTRL_RDY_BUSY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_BUSY Setting */ + #define MXC_V_RTC_CTRL_RDY_READY ((uint32_t)0x1UL) /**< CTRL_RDY_READY Value */ + #define MXC_S_RTC_CTRL_RDY_READY (MXC_V_RTC_CTRL_RDY_READY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_READY Setting */ + + #define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ + #define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ + #define MXC_V_RTC_CTRL_RDYE_DIS ((uint32_t)0x0UL) /**< CTRL_RDYE_DIS Value */ + #define MXC_S_RTC_CTRL_RDYE_DIS (MXC_V_RTC_CTRL_RDYE_DIS << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_DIS Setting */ + #define MXC_V_RTC_CTRL_RDYE_EN ((uint32_t)0x1UL) /**< CTRL_RDYE_EN Value */ + #define MXC_S_RTC_CTRL_RDYE_EN (MXC_V_RTC_CTRL_RDYE_EN << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_EN Setting */ + + #define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ + #define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ + #define MXC_V_RTC_CTRL_ALDF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALDF_INACTIVE Value */ + #define MXC_S_RTC_CTRL_ALDF_INACTIVE (MXC_V_RTC_CTRL_ALDF_INACTIVE << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_INACTIVE Setting */ + #define MXC_V_RTC_CTRL_ALDF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALDF_PENDING Value */ + #define MXC_S_RTC_CTRL_ALDF_PENDING (MXC_V_RTC_CTRL_ALDF_PENDING << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_PENDING Setting */ + + #define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ + #define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ + #define MXC_V_RTC_CTRL_ALSF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALSF_INACTIVE Value */ + #define MXC_S_RTC_CTRL_ALSF_INACTIVE (MXC_V_RTC_CTRL_ALSF_INACTIVE << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_INACTIVE Setting */ + #define MXC_V_RTC_CTRL_ALSF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALSF_PENDING Value */ + #define MXC_S_RTC_CTRL_ALSF_PENDING (MXC_V_RTC_CTRL_ALSF_PENDING << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_PENDING Setting */ + + #define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */ + #define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */ + #define MXC_V_RTC_CTRL_SQE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_SQE_INACTIVE Value */ + #define MXC_S_RTC_CTRL_SQE_INACTIVE (MXC_V_RTC_CTRL_SQE_INACTIVE << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_INACTIVE Setting */ + #define MXC_V_RTC_CTRL_SQE_PENDING ((uint32_t)0x1UL) /**< CTRL_SQE_PENDING Value */ + #define MXC_S_RTC_CTRL_SQE_PENDING (MXC_V_RTC_CTRL_SQE_PENDING << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_PENDING Setting */ + + #define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */ + #define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */ + #define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */ + #define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */ + #define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */ + #define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */ + #define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */ + #define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */ + + #define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */ + #define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */ + #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */ + #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */ + #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */ + #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */ + + #define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */ + #define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */ + #define MXC_V_RTC_CTRL_WE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_WE_INACTIVE Value */ + #define MXC_S_RTC_CTRL_WE_INACTIVE (MXC_V_RTC_CTRL_WE_INACTIVE << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_INACTIVE Setting */ + #define MXC_V_RTC_CTRL_WE_PENDING ((uint32_t)0x1UL) /**< CTRL_WE_PENDING Value */ + #define MXC_S_RTC_CTRL_WE_PENDING (MXC_V_RTC_CTRL_WE_PENDING << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_PENDING Setting */ + +/**@} end of group RTC_CTRL_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TRIM RTC_TRIM + * @brief RTC Trim Register. + * @{ + */ + #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ + #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ + + #define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */ + #define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */ + +/**@} end of group RTC_TRIM_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_OSCCTRL RTC_OSCCTRL + * @brief RTC Oscillator Control Register. + * @{ + */ + #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */ + #define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ + #define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ + #define MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X ((uint32_t)0x0UL) /**< OSCCTRL_IBIAS_SEL_2X Value */ + #define MXC_S_RTC_OSCCTRL_IBIAS_SEL_2X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_2X Setting */ + #define MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X ((uint32_t)0x1UL) /**< OSCCTRL_IBIAS_SEL_4X Value */ + #define MXC_S_RTC_OSCCTRL_IBIAS_SEL_4X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_4X Setting */ + + #define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ + #define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ + #define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ + + #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ + #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ + + #define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */ + #define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */ + +/**@} end of group RTC_OSCCTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _RTC_REGS_H_ */ diff --git a/Project/SDK/Device/Include/sir_regs.h b/Project/SDK/Device/Include/sir_regs.h new file mode 100644 index 0000000..a48d7dc --- /dev/null +++ b/Project/SDK/Device/Include/sir_regs.h @@ -0,0 +1,255 @@ +/** + * @file sir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SIR_REGS_H_ +#define _SIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup sir + * @defgroup sir_registers SIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @details System Initialization Registers. + */ + +/** + * @ingroup sir_registers + * Structure type to access the SIR Registers. + */ +typedef struct { + __I uint32_t sistat; /**< \b 0x00: SIR SISTAT Register */ + __I uint32_t erraddr; /**< \b 0x04: SIR ERRADDR Register */ + __R uint32_t rsv_0x8_0xff[62]; + __I uint32_t fstat; /**< \b 0x100: SIR FSTAT Register */ + __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ +} mxc_sir_regs_t; + +/* Register offsets for module SIR */ +/** + * @ingroup sir_registers + * @defgroup SIR_Register_Offsets Register Offsets + * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. + * @{ + */ + #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ + #define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ + #define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: 0x0100 */ + #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ +/**@} end of group sir_registers */ + +/** + * @ingroup sir_registers + * @defgroup SIR_SISTAT SIR_SISTAT + * @brief System Initialization Status Register. + * @{ + */ + #define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */ + #define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */ + #define MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET ((uint32_t)0x0UL) /**< SISTAT_MAGIC_MAGICNOTSET Value */ + #define MXC_S_SIR_SISTAT_MAGIC_MAGICNOTSET (MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICNOTSET Setting */ + #define MXC_V_SIR_SISTAT_MAGIC_MAGICSET ((uint32_t)0x1UL) /**< SISTAT_MAGIC_MAGICSET Value */ + #define MXC_S_SIR_SISTAT_MAGIC_MAGICSET (MXC_V_SIR_SISTAT_MAGIC_MAGICSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICSET Setting */ + + #define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */ + #define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */ + #define MXC_V_SIR_SISTAT_CRCERR_NOERROR ((uint32_t)0x0UL) /**< SISTAT_CRCERR_NOERROR Value */ + #define MXC_S_SIR_SISTAT_CRCERR_NOERROR (MXC_V_SIR_SISTAT_CRCERR_NOERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_NOERROR Setting */ + #define MXC_V_SIR_SISTAT_CRCERR_ERROR ((uint32_t)0x1UL) /**< SISTAT_CRCERR_ERROR Value */ + #define MXC_S_SIR_SISTAT_CRCERR_ERROR (MXC_V_SIR_SISTAT_CRCERR_ERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_ERROR Setting */ + +/**@} end of group SIR_SISTAT_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_ERRADDR SIR_ERRADDR + * @brief Read-only field set by the SIB block if a CRC error occurs during the read of + * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals + * 1). + * @{ + */ + #define MXC_F_SIR_ERRADDR_ERRADDR_POS 0 /**< ERRADDR_ERRADDR Position */ + #define MXC_F_SIR_ERRADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ERRADDR_ERRADDR_POS)) /**< ERRADDR_ERRADDR Mask */ + +/**@} end of group SIR_ERRADDR_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_FSTAT SIR_FSTAT + * @brief funcstat register. + * @{ + */ + #define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ + #define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */ + #define MXC_V_SIR_FSTAT_FPU_NO ((uint32_t)0x0UL) /**< FSTAT_FPU_NO Value */ + #define MXC_S_SIR_FSTAT_FPU_NO (MXC_V_SIR_FSTAT_FPU_NO << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_NO Setting */ + #define MXC_V_SIR_FSTAT_FPU_YES ((uint32_t)0x1UL) /**< FSTAT_FPU_YES Value */ + #define MXC_S_SIR_FSTAT_FPU_YES (MXC_V_SIR_FSTAT_FPU_YES << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_YES Setting */ + + #define MXC_F_SIR_FSTAT_USB_POS 1 /**< FSTAT_USB Position */ + #define MXC_F_SIR_FSTAT_USB ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */ + #define MXC_V_SIR_FSTAT_USB_NO ((uint32_t)0x0UL) /**< FSTAT_USB_NO Value */ + #define MXC_S_SIR_FSTAT_USB_NO (MXC_V_SIR_FSTAT_USB_NO << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_NO Setting */ + #define MXC_V_SIR_FSTAT_USB_YES ((uint32_t)0x1UL) /**< FSTAT_USB_YES Value */ + #define MXC_S_SIR_FSTAT_USB_YES (MXC_V_SIR_FSTAT_USB_YES << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_YES Setting */ + + #define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */ + #define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */ + #define MXC_V_SIR_FSTAT_ADC_NO ((uint32_t)0x0UL) /**< FSTAT_ADC_NO Value */ + #define MXC_S_SIR_FSTAT_ADC_NO (MXC_V_SIR_FSTAT_ADC_NO << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_NO Setting */ + #define MXC_V_SIR_FSTAT_ADC_YES ((uint32_t)0x1UL) /**< FSTAT_ADC_YES Value */ + #define MXC_S_SIR_FSTAT_ADC_YES (MXC_V_SIR_FSTAT_ADC_YES << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_YES Setting */ + + #define MXC_F_SIR_FSTAT_XIP_POS 3 /**< FSTAT_XIP Position */ + #define MXC_F_SIR_FSTAT_XIP ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_XIP_POS)) /**< FSTAT_XIP Mask */ + #define MXC_V_SIR_FSTAT_XIP_NO ((uint32_t)0x0UL) /**< FSTAT_XIP_NO Value */ + #define MXC_S_SIR_FSTAT_XIP_NO (MXC_V_SIR_FSTAT_XIP_NO << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_NO Setting */ + #define MXC_V_SIR_FSTAT_XIP_YES ((uint32_t)0x1UL) /**< FSTAT_XIP_YES Value */ + #define MXC_S_SIR_FSTAT_XIP_YES (MXC_V_SIR_FSTAT_XIP_YES << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_YES Setting */ + + #define MXC_F_SIR_FSTAT_PBM_POS 4 /**< FSTAT_PBM Position */ + #define MXC_F_SIR_FSTAT_PBM ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_PBM_POS)) /**< FSTAT_PBM Mask */ + #define MXC_V_SIR_FSTAT_PBM_NO ((uint32_t)0x0UL) /**< FSTAT_PBM_NO Value */ + #define MXC_S_SIR_FSTAT_PBM_NO (MXC_V_SIR_FSTAT_PBM_NO << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_NO Setting */ + #define MXC_V_SIR_FSTAT_PBM_YES ((uint32_t)0x1UL) /**< FSTAT_PBM_YES Value */ + #define MXC_S_SIR_FSTAT_PBM_YES (MXC_V_SIR_FSTAT_PBM_YES << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_YES Setting */ + + #define MXC_F_SIR_FSTAT_HBC_POS 5 /**< FSTAT_HBC Position */ + #define MXC_F_SIR_FSTAT_HBC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_HBC_POS)) /**< FSTAT_HBC Mask */ + #define MXC_V_SIR_FSTAT_HBC_NO ((uint32_t)0x0UL) /**< FSTAT_HBC_NO Value */ + #define MXC_S_SIR_FSTAT_HBC_NO (MXC_V_SIR_FSTAT_HBC_NO << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_NO Setting */ + #define MXC_V_SIR_FSTAT_HBC_YES ((uint32_t)0x1UL) /**< FSTAT_HBC_YES Value */ + #define MXC_S_SIR_FSTAT_HBC_YES (MXC_V_SIR_FSTAT_HBC_YES << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_YES Setting */ + + #define MXC_F_SIR_FSTAT_SDHC_POS 6 /**< FSTAT_SDHC Position */ + #define MXC_F_SIR_FSTAT_SDHC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SDHC_POS)) /**< FSTAT_SDHC Mask */ + #define MXC_V_SIR_FSTAT_SDHC_NO ((uint32_t)0x0UL) /**< FSTAT_SDHC_NO Value */ + #define MXC_S_SIR_FSTAT_SDHC_NO (MXC_V_SIR_FSTAT_SDHC_NO << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_NO Setting */ + #define MXC_V_SIR_FSTAT_SDHC_YES ((uint32_t)0x1UL) /**< FSTAT_SDHC_YES Value */ + #define MXC_S_SIR_FSTAT_SDHC_YES (MXC_V_SIR_FSTAT_SDHC_YES << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_YES Setting */ + + #define MXC_F_SIR_FSTAT_SMPHR_POS 7 /**< FSTAT_SMPHR Position */ + #define MXC_F_SIR_FSTAT_SMPHR ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */ + #define MXC_V_SIR_FSTAT_SMPHR_NO ((uint32_t)0x0UL) /**< FSTAT_SMPHR_NO Value */ + #define MXC_S_SIR_FSTAT_SMPHR_NO (MXC_V_SIR_FSTAT_SMPHR_NO << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_NO Setting */ + #define MXC_V_SIR_FSTAT_SMPHR_YES ((uint32_t)0x1UL) /**< FSTAT_SMPHR_YES Value */ + #define MXC_S_SIR_FSTAT_SMPHR_YES (MXC_V_SIR_FSTAT_SMPHR_YES << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_YES Setting */ + + #define MXC_F_SIR_FSTAT_SCACHE_POS 8 /**< FSTAT_SCACHE Position */ + #define MXC_F_SIR_FSTAT_SCACHE ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SCACHE_POS)) /**< FSTAT_SCACHE Mask */ + #define MXC_V_SIR_FSTAT_SCACHE_NO ((uint32_t)0x0UL) /**< FSTAT_SCACHE_NO Value */ + #define MXC_S_SIR_FSTAT_SCACHE_NO (MXC_V_SIR_FSTAT_SCACHE_NO << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_NO Setting */ + #define MXC_V_SIR_FSTAT_SCACHE_YES ((uint32_t)0x1UL) /**< FSTAT_SCACHE_YES Value */ + #define MXC_S_SIR_FSTAT_SCACHE_YES (MXC_V_SIR_FSTAT_SCACHE_YES << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_YES Setting */ + +/**@} end of group SIR_FSTAT_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_SFSTAT SIR_SFSTAT + * @brief secfuncstat register. + * @{ + */ + #define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */ + #define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */ + #define MXC_V_SIR_SFSTAT_TRNG_NO ((uint32_t)0x0UL) /**< SFSTAT_TRNG_NO Value */ + #define MXC_S_SIR_SFSTAT_TRNG_NO (MXC_V_SIR_SFSTAT_TRNG_NO << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_NO Setting */ + #define MXC_V_SIR_SFSTAT_TRNG_YES ((uint32_t)0x1UL) /**< SFSTAT_TRNG_YES Value */ + #define MXC_S_SIR_SFSTAT_TRNG_YES (MXC_V_SIR_SFSTAT_TRNG_YES << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_YES Setting */ + + #define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */ + #define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */ + #define MXC_V_SIR_SFSTAT_AES_NO ((uint32_t)0x0UL) /**< SFSTAT_AES_NO Value */ + #define MXC_S_SIR_SFSTAT_AES_NO (MXC_V_SIR_SFSTAT_AES_NO << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_NO Setting */ + #define MXC_V_SIR_SFSTAT_AES_YES ((uint32_t)0x1UL) /**< SFSTAT_AES_YES Value */ + #define MXC_S_SIR_SFSTAT_AES_YES (MXC_V_SIR_SFSTAT_AES_YES << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_YES Setting */ + + #define MXC_F_SIR_SFSTAT_SHA_POS 4 /**< SFSTAT_SHA Position */ + #define MXC_F_SIR_SFSTAT_SHA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHA_POS)) /**< SFSTAT_SHA Mask */ + #define MXC_V_SIR_SFSTAT_SHA_NO ((uint32_t)0x0UL) /**< SFSTAT_SHA_NO Value */ + #define MXC_S_SIR_SFSTAT_SHA_NO (MXC_V_SIR_SFSTAT_SHA_NO << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_NO Setting */ + #define MXC_V_SIR_SFSTAT_SHA_YES ((uint32_t)0x1UL) /**< SFSTAT_SHA_YES Value */ + #define MXC_S_SIR_SFSTAT_SHA_YES (MXC_V_SIR_SFSTAT_SHA_YES << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_YES Setting */ + + #define MXC_F_SIR_SFSTAT_MAA_POS 5 /**< SFSTAT_MAA Position */ + #define MXC_F_SIR_SFSTAT_MAA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_MAA_POS)) /**< SFSTAT_MAA Mask */ + #define MXC_V_SIR_SFSTAT_MAA_NO ((uint32_t)0x0UL) /**< SFSTAT_MAA_NO Value */ + #define MXC_S_SIR_SFSTAT_MAA_NO (MXC_V_SIR_SFSTAT_MAA_NO << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_NO Setting */ + #define MXC_V_SIR_SFSTAT_MAA_YES ((uint32_t)0x1UL) /**< SFSTAT_MAA_YES Value */ + #define MXC_S_SIR_SFSTAT_MAA_YES (MXC_V_SIR_SFSTAT_MAA_YES << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_YES Setting */ + +/**@} end of group SIR_SFSTAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SIR_REGS_H_ */ diff --git a/Project/SDK/Device/Include/smon_regs.h b/Project/SDK/Device/Include/smon_regs.h new file mode 100644 index 0000000..82508d5 --- /dev/null +++ b/Project/SDK/Device/Include/smon_regs.h @@ -0,0 +1,628 @@ +/** + * @file smon_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SMON_REGS_H_ +#define _SMON_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup smon + * @defgroup smon_registers SMON_Registers + * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. + * @details The Security Monitor block used to monitor system threat conditions. + */ + +/** + * @ingroup smon_registers + * Structure type to access the SMON Registers. + */ +typedef struct { + __IO uint32_t extscn; /**< \b 0x00: SMON EXTSCN Register */ + __IO uint32_t intscn; /**< \b 0x04: SMON INTSCN Register */ + __IO uint32_t secalm; /**< \b 0x08: SMON SECALM Register */ + __I uint32_t secdiag; /**< \b 0x0C: SMON SECDIAG Register */ + __I uint32_t dlrtc; /**< \b 0x10: SMON DLRTC Register */ + __R uint32_t rsv_0x14_0x33[8]; + __I uint32_t secst; /**< \b 0x34: SMON SECST Register */ +} mxc_smon_regs_t; + +/* Register offsets for module SMON */ +/** + * @ingroup smon_registers + * @defgroup SMON_Register_Offsets Register Offsets + * @brief SMON Peripheral Register Offsets from the SMON Base Peripheral Address. + * @{ + */ + #define MXC_R_SMON_EXTSCN ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: 0x0000 */ + #define MXC_R_SMON_INTSCN ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: 0x0004 */ + #define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: 0x0008 */ + #define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: 0x000C */ + #define MXC_R_SMON_DLRTC ((uint32_t)0x00000010UL) /**< Offset from SMON Base Address: 0x0010 */ + #define MXC_R_SMON_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: 0x0034 */ +/**@} end of group smon_registers */ + +/** + * @ingroup smon_registers + * @defgroup SMON_EXTSCN SMON_EXTSCN + * @brief External Sensor Control Register. + * @{ + */ + #define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0 /**< EXTSCN_EXTS_EN0 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN0_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN0_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN0_DIS (MXC_V_SMON_EXTSCN_EXTS_EN0_DIS << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN0_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN0_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN0_EN (MXC_V_SMON_EXTSCN_EXTS_EN0_EN << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1 /**< EXTSCN_EXTS_EN1 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN1_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN1_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN1_DIS (MXC_V_SMON_EXTSCN_EXTS_EN1_DIS << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN1_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN1_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN1_EN (MXC_V_SMON_EXTSCN_EXTS_EN1_EN << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2 /**< EXTSCN_EXTS_EN2 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN2_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN2_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN2_DIS (MXC_V_SMON_EXTSCN_EXTS_EN2_DIS << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN2_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN2_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN2_EN (MXC_V_SMON_EXTSCN_EXTS_EN2_EN << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3 /**< EXTSCN_EXTS_EN3 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN3_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN3_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN3_DIS (MXC_V_SMON_EXTSCN_EXTS_EN3_DIS << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN3_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN3_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN3_EN (MXC_V_SMON_EXTSCN_EXTS_EN3_EN << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4 /**< EXTSCN_EXTS_EN4 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN4_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN4_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN4_DIS (MXC_V_SMON_EXTSCN_EXTS_EN4_DIS << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN4_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN4_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN4_EN (MXC_V_SMON_EXTSCN_EXTS_EN4_EN << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5 /**< EXTSCN_EXTS_EN5 Position */ + #define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */ + #define MXC_V_SMON_EXTSCN_EXTS_EN5_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN5_DIS Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN5_DIS (MXC_V_SMON_EXTSCN_EXTS_EN5_DIS << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_DIS Setting */ + #define MXC_V_SMON_EXTSCN_EXTS_EN5_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN5_EN Value */ + #define MXC_S_SMON_EXTSCN_EXTS_EN5_EN (MXC_V_SMON_EXTSCN_EXTS_EN5_EN << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_EN Setting */ + + #define MXC_F_SMON_EXTSCN_EXTCNT_POS 16 /**< EXTSCN_EXTCNT Position */ + #define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */ + + #define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21 /**< EXTSCN_EXTFRQ Position */ + #define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */ + #define MXC_V_SMON_EXTSCN_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */ + #define MXC_S_SMON_EXTSCN_EXTFRQ_RFU (MXC_V_SMON_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */ + + #define MXC_F_SMON_EXTSCN_DIVCLK_POS 24 /**< EXTSCN_DIVCLK Position */ + #define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */ + #define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */ + #define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */ + + #define MXC_F_SMON_EXTSCN_BUSY_POS 30 /**< EXTSCN_BUSY Position */ + #define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */ + #define MXC_V_SMON_EXTSCN_BUSY_IDLE ((uint32_t)0x0UL) /**< EXTSCN_BUSY_IDLE Value */ + #define MXC_S_SMON_EXTSCN_BUSY_IDLE (MXC_V_SMON_EXTSCN_BUSY_IDLE << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_IDLE Setting */ + #define MXC_V_SMON_EXTSCN_BUSY_BUSY ((uint32_t)0x1UL) /**< EXTSCN_BUSY_BUSY Value */ + #define MXC_S_SMON_EXTSCN_BUSY_BUSY (MXC_V_SMON_EXTSCN_BUSY_BUSY << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_BUSY Setting */ + + #define MXC_F_SMON_EXTSCN_LOCK_POS 31 /**< EXTSCN_LOCK Position */ + #define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */ + #define MXC_V_SMON_EXTSCN_LOCK_UNLOCKED ((uint32_t)0x0UL) /**< EXTSCN_LOCK_UNLOCKED Value */ + #define MXC_S_SMON_EXTSCN_LOCK_UNLOCKED (MXC_V_SMON_EXTSCN_LOCK_UNLOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_UNLOCKED Setting */ + #define MXC_V_SMON_EXTSCN_LOCK_LOCKED ((uint32_t)0x1UL) /**< EXTSCN_LOCK_LOCKED Value */ + #define MXC_S_SMON_EXTSCN_LOCK_LOCKED (MXC_V_SMON_EXTSCN_LOCK_LOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_LOCKED Setting */ + +/**@} end of group SMON_EXTSCN_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_INTSCN SMON_INTSCN + * @brief Internal Sensor Control Register. + * @{ + */ + #define MXC_F_SMON_INTSCN_SHIELD_EN_POS 0 /**< INTSCN_SHIELD_EN Position */ + #define MXC_F_SMON_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */ + #define MXC_V_SMON_INTSCN_SHIELD_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_SHIELD_EN_DIS Value */ + #define MXC_S_SMON_INTSCN_SHIELD_EN_DIS (MXC_V_SMON_INTSCN_SHIELD_EN_DIS << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_DIS Setting */ + #define MXC_V_SMON_INTSCN_SHIELD_EN_EN ((uint32_t)0x1UL) /**< INTSCN_SHIELD_EN_EN Value */ + #define MXC_S_SMON_INTSCN_SHIELD_EN_EN (MXC_V_SMON_INTSCN_SHIELD_EN_EN << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_EN Setting */ + + #define MXC_F_SMON_INTSCN_TEMP_EN_POS 1 /**< INTSCN_TEMP_EN Position */ + #define MXC_F_SMON_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */ + #define MXC_V_SMON_INTSCN_TEMP_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_TEMP_EN_DIS Value */ + #define MXC_S_SMON_INTSCN_TEMP_EN_DIS (MXC_V_SMON_INTSCN_TEMP_EN_DIS << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_DIS Setting */ + #define MXC_V_SMON_INTSCN_TEMP_EN_EN ((uint32_t)0x1UL) /**< INTSCN_TEMP_EN_EN Value */ + #define MXC_S_SMON_INTSCN_TEMP_EN_EN (MXC_V_SMON_INTSCN_TEMP_EN_EN << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VBAT_EN_POS 2 /**< INTSCN_VBAT_EN Position */ + #define MXC_F_SMON_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */ + #define MXC_V_SMON_INTSCN_VBAT_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_VBAT_EN_DIS Value */ + #define MXC_S_SMON_INTSCN_VBAT_EN_DIS (MXC_V_SMON_INTSCN_VBAT_EN_DIS << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VBAT_EN_EN ((uint32_t)0x1UL) /**< INTSCN_VBAT_EN_EN Value */ + #define MXC_S_SMON_INTSCN_VBAT_EN_EN (MXC_V_SMON_INTSCN_VBAT_EN_EN << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_EN Setting */ + + #define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS 16 /**< INTSCN_LOTEMP_SEL Position */ + #define MXC_F_SMON_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */ + #define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C ((uint32_t)0x0UL) /**< INTSCN_LOTEMP_SEL_NEG50C Value */ + #define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG50C (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG50C Setting */ + #define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C ((uint32_t)0x1UL) /**< INTSCN_LOTEMP_SEL_NEG30C Value */ + #define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG30C (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG30C Setting */ + + #define MXC_F_SMON_INTSCN_VCORELOEN_POS 18 /**< INTSCN_VCORELOEN Position */ + #define MXC_F_SMON_INTSCN_VCORELOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCORELOEN_POS)) /**< INTSCN_VCORELOEN Mask */ + #define MXC_V_SMON_INTSCN_VCORELOEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VCORELOEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VCORELOEN_DIS (MXC_V_SMON_INTSCN_VCORELOEN_DIS << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VCORELOEN_EN ((uint32_t)0x1UL) /**< INTSCN_VCORELOEN_EN Value */ + #define MXC_S_SMON_INTSCN_VCORELOEN_EN (MXC_V_SMON_INTSCN_VCORELOEN_EN << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VCOREHIEN_POS 19 /**< INTSCN_VCOREHIEN Position */ + #define MXC_F_SMON_INTSCN_VCOREHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCOREHIEN_POS)) /**< INTSCN_VCOREHIEN Mask */ + #define MXC_V_SMON_INTSCN_VCOREHIEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VCOREHIEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VCOREHIEN_DIS (MXC_V_SMON_INTSCN_VCOREHIEN_DIS << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VCOREHIEN_EN ((uint32_t)0x1UL) /**< INTSCN_VCOREHIEN_EN Value */ + #define MXC_S_SMON_INTSCN_VCOREHIEN_EN (MXC_V_SMON_INTSCN_VCOREHIEN_EN << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VDDLOEN_POS 20 /**< INTSCN_VDDLOEN Position */ + #define MXC_F_SMON_INTSCN_VDDLOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDLOEN_POS)) /**< INTSCN_VDDLOEN Mask */ + #define MXC_V_SMON_INTSCN_VDDLOEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VDDLOEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VDDLOEN_DIS (MXC_V_SMON_INTSCN_VDDLOEN_DIS << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VDDLOEN_EN ((uint32_t)0x1UL) /**< INTSCN_VDDLOEN_EN Value */ + #define MXC_S_SMON_INTSCN_VDDLOEN_EN (MXC_V_SMON_INTSCN_VDDLOEN_EN << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VDDHIEN_POS 21 /**< INTSCN_VDDHIEN Position */ + #define MXC_F_SMON_INTSCN_VDDHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDHIEN_POS)) /**< INTSCN_VDDHIEN Mask */ + #define MXC_V_SMON_INTSCN_VDDHIEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VDDHIEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VDDHIEN_DIS (MXC_V_SMON_INTSCN_VDDHIEN_DIS << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VDDHIEN_EN ((uint32_t)0x1UL) /**< INTSCN_VDDHIEN_EN Value */ + #define MXC_S_SMON_INTSCN_VDDHIEN_EN (MXC_V_SMON_INTSCN_VDDHIEN_EN << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_VGLEN_POS 22 /**< INTSCN_VGLEN Position */ + #define MXC_F_SMON_INTSCN_VGLEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VGLEN_POS)) /**< INTSCN_VGLEN Mask */ + #define MXC_V_SMON_INTSCN_VGLEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VGLEN_DIS Value */ + #define MXC_S_SMON_INTSCN_VGLEN_DIS (MXC_V_SMON_INTSCN_VGLEN_DIS << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_DIS Setting */ + #define MXC_V_SMON_INTSCN_VGLEN_EN ((uint32_t)0x1UL) /**< INTSCN_VGLEN_EN Value */ + #define MXC_S_SMON_INTSCN_VGLEN_EN (MXC_V_SMON_INTSCN_VGLEN_EN << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_EN Setting */ + + #define MXC_F_SMON_INTSCN_LOCK_POS 31 /**< INTSCN_LOCK Position */ + #define MXC_F_SMON_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */ + #define MXC_V_SMON_INTSCN_LOCK_UNLOCKED ((uint32_t)0x0UL) /**< INTSCN_LOCK_UNLOCKED Value */ + #define MXC_S_SMON_INTSCN_LOCK_UNLOCKED (MXC_V_SMON_INTSCN_LOCK_UNLOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_UNLOCKED Setting */ + #define MXC_V_SMON_INTSCN_LOCK_LOCKED ((uint32_t)0x1UL) /**< INTSCN_LOCK_LOCKED Value */ + #define MXC_S_SMON_INTSCN_LOCK_LOCKED (MXC_V_SMON_INTSCN_LOCK_LOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_LOCKED Setting */ + +/**@} end of group SMON_INTSCN_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_SECALM SMON_SECALM + * @brief Security Alarm Register. + * @{ + */ + #define MXC_F_SMON_SECALM_DRS_POS 0 /**< SECALM_DRS Position */ + #define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */ + #define MXC_V_SMON_SECALM_DRS_COMPLETE ((uint32_t)0x0UL) /**< SECALM_DRS_COMPLETE Value */ + #define MXC_S_SMON_SECALM_DRS_COMPLETE (MXC_V_SMON_SECALM_DRS_COMPLETE << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_COMPLETE Setting */ + #define MXC_V_SMON_SECALM_DRS_START ((uint32_t)0x1UL) /**< SECALM_DRS_START Value */ + #define MXC_S_SMON_SECALM_DRS_START (MXC_V_SMON_SECALM_DRS_START << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_START Setting */ + + #define MXC_F_SMON_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */ + #define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */ + #define MXC_V_SMON_SECALM_KEYWIPE_COMPLETE ((uint32_t)0x0UL) /**< SECALM_KEYWIPE_COMPLETE Value */ + #define MXC_S_SMON_SECALM_KEYWIPE_COMPLETE (MXC_V_SMON_SECALM_KEYWIPE_COMPLETE << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_COMPLETE Setting */ + #define MXC_V_SMON_SECALM_KEYWIPE_START ((uint32_t)0x1UL) /**< SECALM_KEYWIPE_START Value */ + #define MXC_S_SMON_SECALM_KEYWIPE_START (MXC_V_SMON_SECALM_KEYWIPE_START << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_START Setting */ + + #define MXC_F_SMON_SECALM_SHIELDF_POS 2 /**< SECALM_SHIELDF Position */ + #define MXC_F_SMON_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */ + #define MXC_V_SMON_SECALM_SHIELDF_NOEVENT ((uint32_t)0x0UL) /**< SECALM_SHIELDF_NOEVENT Value */ + #define MXC_S_SMON_SECALM_SHIELDF_NOEVENT (MXC_V_SMON_SECALM_SHIELDF_NOEVENT << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_SHIELDF_OCCURRED ((uint32_t)0x1UL) /**< SECALM_SHIELDF_OCCURRED Value */ + #define MXC_S_SMON_SECALM_SHIELDF_OCCURRED (MXC_V_SMON_SECALM_SHIELDF_OCCURRED << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_LOTEMP_POS 3 /**< SECALM_LOTEMP Position */ + #define MXC_F_SMON_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */ + #define MXC_V_SMON_SECALM_LOTEMP_NOEVENT ((uint32_t)0x0UL) /**< SECALM_LOTEMP_NOEVENT Value */ + #define MXC_S_SMON_SECALM_LOTEMP_NOEVENT (MXC_V_SMON_SECALM_LOTEMP_NOEVENT << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_LOTEMP_OCCURRED ((uint32_t)0x1UL) /**< SECALM_LOTEMP_OCCURRED Value */ + #define MXC_S_SMON_SECALM_LOTEMP_OCCURRED (MXC_V_SMON_SECALM_LOTEMP_OCCURRED << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_HITEMP_POS 4 /**< SECALM_HITEMP Position */ + #define MXC_F_SMON_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */ + #define MXC_V_SMON_SECALM_HITEMP_NOEVENT ((uint32_t)0x0UL) /**< SECALM_HITEMP_NOEVENT Value */ + #define MXC_S_SMON_SECALM_HITEMP_NOEVENT (MXC_V_SMON_SECALM_HITEMP_NOEVENT << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_HITEMP_OCCURRED ((uint32_t)0x1UL) /**< SECALM_HITEMP_OCCURRED Value */ + #define MXC_S_SMON_SECALM_HITEMP_OCCURRED (MXC_V_SMON_SECALM_HITEMP_OCCURRED << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_BATLO_POS 5 /**< SECALM_BATLO Position */ + #define MXC_F_SMON_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */ + #define MXC_V_SMON_SECALM_BATLO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_BATLO_NOEVENT Value */ + #define MXC_S_SMON_SECALM_BATLO_NOEVENT (MXC_V_SMON_SECALM_BATLO_NOEVENT << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_BATLO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_BATLO_OCCURRED Value */ + #define MXC_S_SMON_SECALM_BATLO_OCCURRED (MXC_V_SMON_SECALM_BATLO_OCCURRED << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_BATHI_POS 6 /**< SECALM_BATHI Position */ + #define MXC_F_SMON_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */ + #define MXC_V_SMON_SECALM_BATHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_BATHI_NOEVENT Value */ + #define MXC_S_SMON_SECALM_BATHI_NOEVENT (MXC_V_SMON_SECALM_BATHI_NOEVENT << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_BATHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_BATHI_OCCURRED Value */ + #define MXC_S_SMON_SECALM_BATHI_OCCURRED (MXC_V_SMON_SECALM_BATHI_OCCURRED << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTF_POS 7 /**< SECALM_EXTF Position */ + #define MXC_F_SMON_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */ + #define MXC_V_SMON_SECALM_EXTF_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTF_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTF_NOEVENT (MXC_V_SMON_SECALM_EXTF_NOEVENT << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTF_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTF_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTF_OCCURRED (MXC_V_SMON_SECALM_EXTF_OCCURRED << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VDDLO_POS 8 /**< SECALM_VDDLO Position */ + #define MXC_F_SMON_SECALM_VDDLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDLO_POS)) /**< SECALM_VDDLO Mask */ + #define MXC_V_SMON_SECALM_VDDLO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VDDLO_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VDDLO_NOEVENT (MXC_V_SMON_SECALM_VDDLO_NOEVENT << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VDDLO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VDDLO_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VDDLO_OCCURRED (MXC_V_SMON_SECALM_VDDLO_OCCURRED << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VCORELO_POS 9 /**< SECALM_VCORELO Position */ + #define MXC_F_SMON_SECALM_VCORELO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCORELO_POS)) /**< SECALM_VCORELO Mask */ + #define MXC_V_SMON_SECALM_VCORELO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VCORELO_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VCORELO_NOEVENT (MXC_V_SMON_SECALM_VCORELO_NOEVENT << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VCORELO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VCORELO_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VCORELO_OCCURRED (MXC_V_SMON_SECALM_VCORELO_OCCURRED << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VCOREHI_POS 10 /**< SECALM_VCOREHI Position */ + #define MXC_F_SMON_SECALM_VCOREHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_POS)) /**< SECALM_VCOREHI Mask */ + #define MXC_V_SMON_SECALM_VCOREHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VCOREHI_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VCOREHI_NOEVENT (MXC_V_SMON_SECALM_VCOREHI_NOEVENT << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VCOREHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VCOREHI_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VCOREHI_OCCURRED (MXC_V_SMON_SECALM_VCOREHI_OCCURRED << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VDDHI_POS 11 /**< SECALM_VDDHI Position */ + #define MXC_F_SMON_SECALM_VDDHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_POS)) /**< SECALM_VDDHI Mask */ + #define MXC_V_SMON_SECALM_VDDHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VDDHI_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VDDHI_NOEVENT (MXC_V_SMON_SECALM_VDDHI_NOEVENT << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VDDHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VDDHI_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VDDHI_OCCURRED (MXC_V_SMON_SECALM_VDDHI_OCCURRED << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_VGL_POS 12 /**< SECALM_VGL Position */ + #define MXC_F_SMON_SECALM_VGL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_POS)) /**< SECALM_VGL Mask */ + #define MXC_V_SMON_SECALM_VGL_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VGL_NOEVENT Value */ + #define MXC_S_SMON_SECALM_VGL_NOEVENT (MXC_V_SMON_SECALM_VGL_NOEVENT << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_VGL_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VGL_OCCURRED Value */ + #define MXC_S_SMON_SECALM_VGL_OCCURRED (MXC_V_SMON_SECALM_VGL_OCCURRED << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT0_POS 16 /**< SECALM_EXTSTAT0 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT0_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT0_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT0_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT0_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT1_POS 17 /**< SECALM_EXTSTAT1 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT1_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT1_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT1_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT1_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT2_POS 18 /**< SECALM_EXTSTAT2 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT2_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT2_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT2_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT2_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT3_POS 19 /**< SECALM_EXTSTAT3 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT3_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT3_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT3_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT3_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT4_POS 20 /**< SECALM_EXTSTAT4 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT4_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT4_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT4_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT4_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSTAT5_POS 21 /**< SECALM_EXTSTAT5 Position */ + #define MXC_F_SMON_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */ + #define MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT5_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSTAT5_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT5_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSTAT5_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN0_POS 24 /**< SECALM_EXTSWARN0 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN0_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN0_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN0_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN0_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN1_POS 25 /**< SECALM_EXTSWARN1 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN1_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN1_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN1_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN1_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN2_POS 26 /**< SECALM_EXTSWARN2 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN2_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN2_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN2_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN2_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN3_POS 27 /**< SECALM_EXTSWARN3 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN3_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN3_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN3_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN3_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN4_POS 28 /**< SECALM_EXTSWARN4 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN4_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN4_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN4_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN4_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_OCCURRED Setting */ + + #define MXC_F_SMON_SECALM_EXTSWARN5_POS 29 /**< SECALM_EXTSWARN5 Position */ + #define MXC_F_SMON_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */ + #define MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN5_NOEVENT Value */ + #define MXC_S_SMON_SECALM_EXTSWARN5_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_NOEVENT Setting */ + #define MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN5_OCCURRED Value */ + #define MXC_S_SMON_SECALM_EXTSWARN5_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_OCCURRED Setting */ + +/**@} end of group SMON_SECALM_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_SECDIAG SMON_SECDIAG + * @brief Security Diagnostic Register. + * @{ + */ + #define MXC_F_SMON_SECDIAG_BORF_POS 0 /**< SECDIAG_BORF Position */ + #define MXC_F_SMON_SECDIAG_BORF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BORF_POS)) /**< SECDIAG_BORF Mask */ + #define MXC_V_SMON_SECDIAG_BORF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BORF_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_BORF_NOEVENT (MXC_V_SMON_SECDIAG_BORF_NOEVENT << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_BORF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BORF_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_BORF_OCCURRED (MXC_V_SMON_SECDIAG_BORF_OCCURRED << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_SHIELDF_POS 2 /**< SECDIAG_SHIELDF Position */ + #define MXC_F_SMON_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */ + #define MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_SHIELDF_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_SHIELDF_NOEVENT (MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_SHIELDF_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_SHIELDF_OCCURRED (MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_LOTEMP_POS 3 /**< SECDIAG_LOTEMP Position */ + #define MXC_F_SMON_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */ + #define MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_LOTEMP_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_LOTEMP_NOEVENT (MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_LOTEMP_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_LOTEMP_OCCURRED (MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_HITEMP_POS 4 /**< SECDIAG_HITEMP Position */ + #define MXC_F_SMON_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */ + #define MXC_V_SMON_SECDIAG_HITEMP_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_HITEMP_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_HITEMP_NOEVENT (MXC_V_SMON_SECDIAG_HITEMP_NOEVENT << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_HITEMP_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_HITEMP_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_HITEMP_OCCURRED (MXC_V_SMON_SECDIAG_HITEMP_OCCURRED << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_BATLO_POS 5 /**< SECDIAG_BATLO Position */ + #define MXC_F_SMON_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */ + #define MXC_V_SMON_SECDIAG_BATLO_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BATLO_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_BATLO_NOEVENT (MXC_V_SMON_SECDIAG_BATLO_NOEVENT << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_BATLO_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BATLO_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_BATLO_OCCURRED (MXC_V_SMON_SECDIAG_BATLO_OCCURRED << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_BATHI_POS 6 /**< SECDIAG_BATHI Position */ + #define MXC_F_SMON_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */ + #define MXC_V_SMON_SECDIAG_BATHI_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BATHI_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_BATHI_NOEVENT (MXC_V_SMON_SECDIAG_BATHI_NOEVENT << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_BATHI_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BATHI_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_BATHI_OCCURRED (MXC_V_SMON_SECDIAG_BATHI_OCCURRED << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_DYNF_POS 7 /**< SECDIAG_DYNF Position */ + #define MXC_F_SMON_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */ + #define MXC_V_SMON_SECDIAG_DYNF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_DYNF_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_DYNF_NOEVENT (MXC_V_SMON_SECDIAG_DYNF_NOEVENT << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_DYNF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_DYNF_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_DYNF_OCCURRED (MXC_V_SMON_SECDIAG_DYNF_OCCURRED << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_AESKT_POS 8 /**< SECDIAG_AESKT Position */ + #define MXC_F_SMON_SECDIAG_AESKT ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_POS)) /**< SECDIAG_AESKT Mask */ + #define MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE ((uint32_t)0x0UL) /**< SECDIAG_AESKT_INCOMPLETE Value */ + #define MXC_S_SMON_SECDIAG_AESKT_INCOMPLETE (MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_INCOMPLETE Setting */ + #define MXC_V_SMON_SECDIAG_AESKT_COMPLETE ((uint32_t)0x1UL) /**< SECDIAG_AESKT_COMPLETE Value */ + #define MXC_S_SMON_SECDIAG_AESKT_COMPLETE (MXC_V_SMON_SECDIAG_AESKT_COMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_COMPLETE Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT0_POS 16 /**< SECDIAG_EXTSTAT0 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT0_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT0_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT0_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT0_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT1_POS 17 /**< SECDIAG_EXTSTAT1 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT1_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT1_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT1_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT1_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT2_POS 18 /**< SECDIAG_EXTSTAT2 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT2_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT2_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT2_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT2_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT3_POS 19 /**< SECDIAG_EXTSTAT3 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT3_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT3_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT3_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT3_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT4_POS 20 /**< SECDIAG_EXTSTAT4 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT4_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT4_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT4_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT4_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_OCCURRED Setting */ + + #define MXC_F_SMON_SECDIAG_EXTSTAT5_POS 21 /**< SECDIAG_EXTSTAT5 Position */ + #define MXC_F_SMON_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */ + #define MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT5_NOEVENT Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT5_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_NOEVENT Setting */ + #define MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT5_OCCURRED Value */ + #define MXC_S_SMON_SECDIAG_EXTSTAT5_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_OCCURRED Setting */ + +/**@} end of group SMON_SECDIAG_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_DLRTC SMON_DLRTC + * @brief DRS Log RTC Value. This register contains the 32 bit value in the RTC second + * register when the last DRS event occurred. + * @{ + */ + #define MXC_F_SMON_DLRTC_DLRTC_POS 0 /**< DLRTC_DLRTC Position */ + #define MXC_F_SMON_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */ + +/**@} end of group SMON_DLRTC_Register */ + +/** + * @ingroup smon_registers + * @defgroup SMON_SECST SMON_SECST + * @brief Security Monitor Status Register. + * @{ + */ + #define MXC_F_SMON_SECST_EXTSRS_POS 0 /**< SECST_EXTSRS Position */ + #define MXC_F_SMON_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */ + #define MXC_V_SMON_SECST_EXTSRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_EXTSRS_ALLOWED Value */ + #define MXC_S_SMON_SECST_EXTSRS_ALLOWED (MXC_V_SMON_SECST_EXTSRS_ALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_ALLOWED Setting */ + #define MXC_V_SMON_SECST_EXTSRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_EXTSRS_NOTALLOWED Value */ + #define MXC_S_SMON_SECST_EXTSRS_NOTALLOWED (MXC_V_SMON_SECST_EXTSRS_NOTALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_NOTALLOWED Setting */ + + #define MXC_F_SMON_SECST_INTSRS_POS 1 /**< SECST_INTSRS Position */ + #define MXC_F_SMON_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */ + #define MXC_V_SMON_SECST_INTSRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_INTSRS_ALLOWED Value */ + #define MXC_S_SMON_SECST_INTSRS_ALLOWED (MXC_V_SMON_SECST_INTSRS_ALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_ALLOWED Setting */ + #define MXC_V_SMON_SECST_INTSRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_INTSRS_NOTALLOWED Value */ + #define MXC_S_SMON_SECST_INTSRS_NOTALLOWED (MXC_V_SMON_SECST_INTSRS_NOTALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_NOTALLOWED Setting */ + + #define MXC_F_SMON_SECST_SECALRS_POS 2 /**< SECST_SECALRS Position */ + #define MXC_F_SMON_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */ + #define MXC_V_SMON_SECST_SECALRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_SECALRS_ALLOWED Value */ + #define MXC_S_SMON_SECST_SECALRS_ALLOWED (MXC_V_SMON_SECST_SECALRS_ALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_ALLOWED Setting */ + #define MXC_V_SMON_SECST_SECALRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_SECALRS_NOTALLOWED Value */ + #define MXC_S_SMON_SECST_SECALRS_NOTALLOWED (MXC_V_SMON_SECST_SECALRS_NOTALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_NOTALLOWED Setting */ + +/**@} end of group SMON_SECST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SMON_REGS_H_ */ diff --git a/Project/SDK/Device/Include/spi17y_regs.h b/Project/SDK/Device/Include/spi17y_regs.h new file mode 100644 index 0000000..9f25e1c --- /dev/null +++ b/Project/SDK/Device/Include/spi17y_regs.h @@ -0,0 +1,664 @@ +/** + * @file spi17y_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SPI17Y_REGS_H_ +#define _SPI17Y_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spi17y + * @defgroup spi17y_registers SPI17Y_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module. + * @details SPI peripheral. + */ + +/** + * @ingroup spi17y_registers + * Structure type to access the SPI17Y Registers. + */ +typedef struct { + union{ + __IO uint32_t data32; /**< \b 0x00: SPI17Y DATA32 Register */ + __IO uint16_t data16[2]; /**< \b 0x00: SPI17Y DATA16 Register */ + __IO uint8_t data8[4]; /**< \b 0x00: SPI17Y DATA8 Register */ + }; + __IO uint32_t ctrl0; /**< \b 0x04: SPI17Y CTRL0 Register */ + __IO uint32_t ctrl1; /**< \b 0x08: SPI17Y CTRL1 Register */ + __IO uint32_t ctrl2; /**< \b 0x0C: SPI17Y CTRL2 Register */ + __IO uint32_t ss_time; /**< \b 0x10: SPI17Y SS_TIME Register */ + __IO uint32_t clk_cfg; /**< \b 0x14: SPI17Y CLK_CFG Register */ + __R uint32_t rsv_0x18; + __IO uint32_t dma; /**< \b 0x1C: SPI17Y DMA Register */ + __IO uint32_t int_fl; /**< \b 0x20: SPI17Y INT_FL Register */ + __IO uint32_t int_en; /**< \b 0x24: SPI17Y INT_EN Register */ + __IO uint32_t wake_fl; /**< \b 0x28: SPI17Y WAKE_FL Register */ + __IO uint32_t wake_en; /**< \b 0x2C: SPI17Y WAKE_EN Register */ + __I uint32_t stat; /**< \b 0x30: SPI17Y STAT Register */ +} mxc_spi17y_regs_t; + +/* Register offsets for module SPI17Y */ +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_Register_Offsets Register Offsets + * @brief SPI17Y Peripheral Register Offsets from the SPI17Y Base Peripheral Address. + * @{ + */ + #define MXC_R_SPI17Y_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: 0x0000 */ + #define MXC_R_SPI17Y_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: 0x0000 */ + #define MXC_R_SPI17Y_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: 0x0000 */ + #define MXC_R_SPI17Y_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI17Y Base Address: 0x0004 */ + #define MXC_R_SPI17Y_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI17Y Base Address: 0x0008 */ + #define MXC_R_SPI17Y_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI17Y Base Address: 0x000C */ + #define MXC_R_SPI17Y_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI17Y Base Address: 0x0010 */ + #define MXC_R_SPI17Y_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI17Y Base Address: 0x0014 */ + #define MXC_R_SPI17Y_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI17Y Base Address: 0x001C */ + #define MXC_R_SPI17Y_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI17Y Base Address: 0x0020 */ + #define MXC_R_SPI17Y_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI17Y Base Address: 0x0024 */ + #define MXC_R_SPI17Y_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI17Y Base Address: 0x0028 */ + #define MXC_R_SPI17Y_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI17Y Base Address: 0x002C */ + #define MXC_R_SPI17Y_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI17Y Base Address: 0x0030 */ +/**@} end of group spi17y_registers */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_DATA32 SPI17Y_DATA32 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI17Y_DATA32_DATA_POS 0 /**< DATA32_DATA Position */ + #define MXC_F_SPI17Y_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI17Y_DATA32_DATA_POS)) /**< DATA32_DATA Mask */ + +/**@} end of group SPI17Y_DATA32_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_DATA16 SPI17Y_DATA16 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI17Y_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ + #define MXC_F_SPI17Y_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI17Y_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ + +/**@} end of group SPI17Y_DATA16_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_DATA8 SPI17Y_DATA8 + * @brief Register for reading and writing the FIFO. + * @{ + */ + #define MXC_F_SPI17Y_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ + #define MXC_F_SPI17Y_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI17Y_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ + +/**@} end of group SPI17Y_DATA8_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_CTRL0 SPI17Y_CTRL0 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI17Y_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ + #define MXC_F_SPI17Y_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ + #define MXC_V_SPI17Y_CTRL0_EN_DIS ((uint32_t)0x0UL) /**< CTRL0_EN_DIS Value */ + #define MXC_S_SPI17Y_CTRL0_EN_DIS (MXC_V_SPI17Y_CTRL0_EN_DIS << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_DIS Setting */ + #define MXC_V_SPI17Y_CTRL0_EN_EN ((uint32_t)0x1UL) /**< CTRL0_EN_EN Value */ + #define MXC_S_SPI17Y_CTRL0_EN_EN (MXC_V_SPI17Y_CTRL0_EN_EN << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_EN Setting */ + + #define MXC_F_SPI17Y_CTRL0_MASTER_POS 1 /**< CTRL0_MASTER Position */ + #define MXC_F_SPI17Y_CTRL0_MASTER ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_MASTER_POS)) /**< CTRL0_MASTER Mask */ + #define MXC_V_SPI17Y_CTRL0_MASTER_DIS ((uint32_t)0x0UL) /**< CTRL0_MASTER_DIS Value */ + #define MXC_S_SPI17Y_CTRL0_MASTER_DIS (MXC_V_SPI17Y_CTRL0_MASTER_DIS << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_DIS Setting */ + #define MXC_V_SPI17Y_CTRL0_MASTER_EN ((uint32_t)0x1UL) /**< CTRL0_MASTER_EN Value */ + #define MXC_S_SPI17Y_CTRL0_MASTER_EN (MXC_V_SPI17Y_CTRL0_MASTER_EN << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_EN Setting */ + + #define MXC_F_SPI17Y_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ + #define MXC_F_SPI17Y_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ + #define MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT ((uint32_t)0x0UL) /**< CTRL0_SS_IO_OUTPUT Value */ + #define MXC_S_SPI17Y_CTRL0_SS_IO_OUTPUT (MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_OUTPUT Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_IO_INPUT ((uint32_t)0x1UL) /**< CTRL0_SS_IO_INPUT Value */ + #define MXC_S_SPI17Y_CTRL0_SS_IO_INPUT (MXC_V_SPI17Y_CTRL0_SS_IO_INPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_INPUT Setting */ + + #define MXC_F_SPI17Y_CTRL0_START_POS 5 /**< CTRL0_START Position */ + #define MXC_F_SPI17Y_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_START_POS)) /**< CTRL0_START Mask */ + #define MXC_V_SPI17Y_CTRL0_START_START ((uint32_t)0x1UL) /**< CTRL0_START_START Value */ + #define MXC_S_SPI17Y_CTRL0_START_START (MXC_V_SPI17Y_CTRL0_START_START << MXC_F_SPI17Y_CTRL0_START_POS) /**< CTRL0_START_START Setting */ + + #define MXC_F_SPI17Y_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ + #define MXC_F_SPI17Y_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ + #define MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT ((uint32_t)0x0UL) /**< CTRL0_SS_CTRL_DEASSERT Value */ + #define MXC_S_SPI17Y_CTRL0_SS_CTRL_DEASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_DEASSERT Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT ((uint32_t)0x1UL) /**< CTRL0_SS_CTRL_ASSERT Value */ + #define MXC_S_SPI17Y_CTRL0_SS_CTRL_ASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_ASSERT Setting */ + + #define MXC_F_SPI17Y_CTRL0_SS_POS 16 /**< CTRL0_SS Position */ + #define MXC_F_SPI17Y_CTRL0_SS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL0_SS_POS)) /**< CTRL0_SS Mask */ + #define MXC_V_SPI17Y_CTRL0_SS_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SS0 Value */ + #define MXC_S_SPI17Y_CTRL0_SS_SS0 (MXC_V_SPI17Y_CTRL0_SS_SS0 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS0 Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SS1 Value */ + #define MXC_S_SPI17Y_CTRL0_SS_SS1 (MXC_V_SPI17Y_CTRL0_SS_SS1 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS1 Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SS2 Value */ + #define MXC_S_SPI17Y_CTRL0_SS_SS2 (MXC_V_SPI17Y_CTRL0_SS_SS2 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS2 Setting */ + #define MXC_V_SPI17Y_CTRL0_SS_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SS3 Value */ + #define MXC_S_SPI17Y_CTRL0_SS_SS3 (MXC_V_SPI17Y_CTRL0_SS_SS3 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS3 Setting */ + +/**@} end of group SPI17Y_CTRL0_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_CTRL1 SPI17Y_CTRL1 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ + #define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ + + #define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ + #define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ + +/**@} end of group SPI17Y_CTRL1_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_CTRL2 SPI17Y_CTRL2 + * @brief Register for controlling SPI peripheral. + * @{ + */ + #define MXC_F_SPI17Y_CTRL2_CPHA_POS 0 /**< CTRL2_CPHA Position */ + #define MXC_F_SPI17Y_CTRL2_CPHA ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */ + #define MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE ((uint32_t)0x0UL) /**< CTRL2_CPHA_RISING_EDGE Value */ + #define MXC_S_SPI17Y_CTRL2_CPHA_RISING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_RISING_EDGE Setting */ + #define MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE ((uint32_t)0x1UL) /**< CTRL2_CPHA_FALLING_EDGE Value */ + #define MXC_S_SPI17Y_CTRL2_CPHA_FALLING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_FALLING_EDGE Setting */ + + #define MXC_F_SPI17Y_CTRL2_CPOL_POS 1 /**< CTRL2_CPOL Position */ + #define MXC_F_SPI17Y_CTRL2_CPOL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */ + #define MXC_V_SPI17Y_CTRL2_CPOL_NORMAL ((uint32_t)0x0UL) /**< CTRL2_CPOL_NORMAL Value */ + #define MXC_S_SPI17Y_CTRL2_CPOL_NORMAL (MXC_V_SPI17Y_CTRL2_CPOL_NORMAL << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_NORMAL Setting */ + #define MXC_V_SPI17Y_CTRL2_CPOL_INVERTED ((uint32_t)0x1UL) /**< CTRL2_CPOL_INVERTED Value */ + #define MXC_S_SPI17Y_CTRL2_CPOL_INVERTED (MXC_V_SPI17Y_CTRL2_CPOL_INVERTED << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_INVERTED Setting */ + + #define MXC_F_SPI17Y_CTRL2_SCLK_INV_POS 4 /**< CTRL2_SCLK_INV Position */ + #define MXC_F_SPI17Y_CTRL2_SCLK_INV ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_SCLK_INV_POS)) /**< CTRL2_SCLK_INV Mask */ + + #define MXC_F_SPI17Y_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ + #define MXC_F_SPI17Y_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ + #define MXC_V_SPI17Y_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ + #define MXC_S_SPI17Y_CTRL2_NUMBITS_0 (MXC_V_SPI17Y_CTRL2_NUMBITS_0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ + + #define MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ + #define MXC_F_SPI17Y_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ + #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ + #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ + #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ + #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ + #define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ + #define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ + + #define MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ + #define MXC_F_SPI17Y_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ + #define MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS ((uint32_t)0x0UL) /**< CTRL2_THREE_WIRE_DIS Value */ + #define MXC_S_SPI17Y_CTRL2_THREE_WIRE_DIS (MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_DIS Setting */ + #define MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN ((uint32_t)0x1UL) /**< CTRL2_THREE_WIRE_EN Value */ + #define MXC_S_SPI17Y_CTRL2_THREE_WIRE_EN (MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_EN Setting */ + + #define MXC_F_SPI17Y_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ + #define MXC_F_SPI17Y_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ + #define MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */ + + #define MXC_F_SPI17Y_CTRL2_SRPOL_POS 24 /**< CTRL2_SRPOL Position */ + #define MXC_F_SPI17Y_CTRL2_SRPOL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SRPOL_POS)) /**< CTRL2_SRPOL Mask */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SRPOL_SR0_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR0_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR0_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SRPOL_SR1_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR1_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR1_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SRPOL_SR2_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR2_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR2_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SRPOL_SR3_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR3_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR3_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH ((uint32_t)0x10UL) /**< CTRL2_SRPOL_SR4_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR4_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR4_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH ((uint32_t)0x20UL) /**< CTRL2_SRPOL_SR5_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR5_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR5_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH ((uint32_t)0x40UL) /**< CTRL2_SRPOL_SR6_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR6_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR6_HIGH Setting */ + #define MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH ((uint32_t)0x80UL) /**< CTRL2_SRPOL_SR7_HIGH Value */ + #define MXC_S_SPI17Y_CTRL2_SRPOL_SR7_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR7_HIGH Setting */ + +/**@} end of group SPI17Y_CTRL2_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_SS_TIME SPI17Y_SS_TIME + * @brief Register for controlling SPI peripheral/Slave Select Timing. + * @{ + */ + #define MXC_F_SPI17Y_SS_TIME_PRE_POS 0 /**< SS_TIME_PRE Position */ + #define MXC_F_SPI17Y_SS_TIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_PRE_POS)) /**< SS_TIME_PRE Mask */ + #define MXC_V_SPI17Y_SS_TIME_PRE_256 ((uint32_t)0x0UL) /**< SS_TIME_PRE_256 Value */ + #define MXC_S_SPI17Y_SS_TIME_PRE_256 (MXC_V_SPI17Y_SS_TIME_PRE_256 << MXC_F_SPI17Y_SS_TIME_PRE_POS) /**< SS_TIME_PRE_256 Setting */ + + #define MXC_F_SPI17Y_SS_TIME_POST_POS 8 /**< SS_TIME_POST Position */ + #define MXC_F_SPI17Y_SS_TIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_POST_POS)) /**< SS_TIME_POST Mask */ + #define MXC_V_SPI17Y_SS_TIME_POST_256 ((uint32_t)0x0UL) /**< SS_TIME_POST_256 Value */ + #define MXC_S_SPI17Y_SS_TIME_POST_256 (MXC_V_SPI17Y_SS_TIME_POST_256 << MXC_F_SPI17Y_SS_TIME_POST_POS) /**< SS_TIME_POST_256 Setting */ + + #define MXC_F_SPI17Y_SS_TIME_INACT_POS 16 /**< SS_TIME_INACT Position */ + #define MXC_F_SPI17Y_SS_TIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_INACT_POS)) /**< SS_TIME_INACT Mask */ + #define MXC_V_SPI17Y_SS_TIME_INACT_256 ((uint32_t)0x0UL) /**< SS_TIME_INACT_256 Value */ + #define MXC_S_SPI17Y_SS_TIME_INACT_256 (MXC_V_SPI17Y_SS_TIME_INACT_256 << MXC_F_SPI17Y_SS_TIME_INACT_POS) /**< SS_TIME_INACT_256 Setting */ + +/**@} end of group SPI17Y_SS_TIME_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_CLK_CFG SPI17Y_CLK_CFG + * @brief Register for controlling SPI clock rate. + * @{ + */ + #define MXC_F_SPI17Y_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ + #define MXC_F_SPI17Y_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ + #define MXC_V_SPI17Y_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */ + #define MXC_S_SPI17Y_CLK_CFG_LO_DIS (MXC_V_SPI17Y_CLK_CFG_LO_DIS << MXC_F_SPI17Y_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */ + + #define MXC_F_SPI17Y_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ + #define MXC_F_SPI17Y_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ + #define MXC_V_SPI17Y_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */ + #define MXC_S_SPI17Y_CLK_CFG_HI_DIS (MXC_V_SPI17Y_CLK_CFG_HI_DIS << MXC_F_SPI17Y_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */ + + #define MXC_F_SPI17Y_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ + #define MXC_F_SPI17Y_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI17Y_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ + +/**@} end of group SPI17Y_CLK_CFG_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_DMA SPI17Y_DMA + * @brief Register for controlling DMA. + * @{ + */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ + + #define MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ + #define MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_FIFO_EN_DIS Value */ + #define MXC_S_SPI17Y_DMA_TX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_DIS Setting */ + #define MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_FIFO_EN_EN Value */ + #define MXC_S_SPI17Y_DMA_TX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_EN Setting */ + + #define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ + #define MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_CLEAR Value */ + #define MXC_S_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_CLEAR Setting */ + + #define MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ + #define MXC_F_SPI17Y_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ + + #define MXC_F_SPI17Y_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ + #define MXC_F_SPI17Y_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ + #define MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */ + #define MXC_S_SPI17Y_DMA_TX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */ + #define MXC_V_SPI17Y_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */ + #define MXC_S_SPI17Y_DMA_TX_DMA_EN_EN (MXC_V_SPI17Y_DMA_TX_DMA_EN_EN << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */ + + #define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ + #define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ + + #define MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ + #define MXC_F_SPI17Y_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ + #define MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_FIFO_EN_DIS Value */ + #define MXC_S_SPI17Y_DMA_RX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_DIS Setting */ + #define MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_FIFO_EN_EN Value */ + #define MXC_S_SPI17Y_DMA_RX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_EN Setting */ + + #define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ + #define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ + #define MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_CLEAR Value */ + #define MXC_S_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_CLEAR Setting */ + + #define MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ + #define MXC_F_SPI17Y_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ + + #define MXC_F_SPI17Y_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ + #define MXC_F_SPI17Y_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ + #define MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */ + #define MXC_S_SPI17Y_DMA_RX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */ + #define MXC_V_SPI17Y_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */ + #define MXC_S_SPI17Y_DMA_RX_DMA_EN_EN (MXC_V_SPI17Y_DMA_RX_DMA_EN_EN << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */ + +/**@} end of group SPI17Y_DMA_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_INT_FL SPI17Y_INT_FL + * @brief Register for reading and clearing interrupt flags. All bits are write 1 to + * clear. + * @{ + */ + #define MXC_F_SPI17Y_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */ + #define MXC_F_SPI17Y_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */ + #define MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_THRESH_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS) /**< INT_FL_TX_THRESH_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ + #define MXC_F_SPI17Y_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ + #define MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_EMPTY_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS) /**< INT_FL_TX_EMPTY_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */ + #define MXC_F_SPI17Y_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */ + #define MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_THRESH_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS) /**< INT_FL_RX_THRESH_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ + #define MXC_F_SPI17Y_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ + #define MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_FULL_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_INT_FL_RX_FULL_POS) /**< INT_FL_RX_FULL_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ + #define MXC_F_SPI17Y_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ + #define MXC_V_SPI17Y_INT_FL_SSA_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSA_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_SSA_CLEAR (MXC_V_SPI17Y_INT_FL_SSA_CLEAR << MXC_F_SPI17Y_INT_FL_SSA_POS) /**< INT_FL_SSA_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ + #define MXC_F_SPI17Y_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ + #define MXC_V_SPI17Y_INT_FL_SSD_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSD_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_SSD_CLEAR (MXC_V_SPI17Y_INT_FL_SSD_CLEAR << MXC_F_SPI17Y_INT_FL_SSD_POS) /**< INT_FL_SSD_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ + #define MXC_F_SPI17Y_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ + #define MXC_V_SPI17Y_INT_FL_FAULT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_FAULT_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_FAULT_CLEAR (MXC_V_SPI17Y_INT_FL_FAULT_CLEAR << MXC_F_SPI17Y_INT_FL_FAULT_POS) /**< INT_FL_FAULT_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ + #define MXC_F_SPI17Y_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ + #define MXC_V_SPI17Y_INT_FL_ABORT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_ABORT_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_ABORT_CLEAR (MXC_V_SPI17Y_INT_FL_ABORT_CLEAR << MXC_F_SPI17Y_INT_FL_ABORT_POS) /**< INT_FL_ABORT_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ + #define MXC_F_SPI17Y_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ + #define MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_M_DONE_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_M_DONE_CLEAR (MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR << MXC_F_SPI17Y_INT_FL_M_DONE_POS) /**< INT_FL_M_DONE_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ + #define MXC_F_SPI17Y_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ + #define MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_OVR_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_TX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_TX_OVR_POS) /**< INT_FL_TX_OVR_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ + #define MXC_F_SPI17Y_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ + #define MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_UND_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_TX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_TX_UND_POS) /**< INT_FL_TX_UND_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ + #define MXC_F_SPI17Y_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ + #define MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_RX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_CLEAR Setting */ + + #define MXC_F_SPI17Y_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ + #define MXC_F_SPI17Y_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ + #define MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_UND_CLEAR Value */ + #define MXC_S_SPI17Y_INT_FL_RX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_RX_UND_POS) /**< INT_FL_RX_UND_CLEAR Setting */ + +/**@} end of group SPI17Y_INT_FL_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_INT_EN SPI17Y_INT_EN + * @brief Register for enabling interrupts. + * @{ + */ + #define MXC_F_SPI17Y_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */ + #define MXC_F_SPI17Y_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */ + #define MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_THRESH_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_TX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_TX_THRESH_EN Value */ + #define MXC_S_SPI17Y_INT_EN_TX_THRESH_EN (MXC_V_SPI17Y_INT_EN_TX_THRESH_EN << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ + #define MXC_F_SPI17Y_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ + #define MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_EMPTY_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< INT_EN_TX_EMPTY_EN Value */ + #define MXC_S_SPI17Y_INT_EN_TX_EMPTY_EN (MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */ + #define MXC_F_SPI17Y_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */ + #define MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_THRESH_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_RX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_RX_THRESH_EN Value */ + #define MXC_S_SPI17Y_INT_EN_RX_THRESH_EN (MXC_V_SPI17Y_INT_EN_RX_THRESH_EN << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ + #define MXC_F_SPI17Y_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ + #define MXC_V_SPI17Y_INT_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FULL_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_RX_FULL_DIS (MXC_V_SPI17Y_INT_EN_RX_FULL_DIS << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FULL_EN Value */ + #define MXC_S_SPI17Y_INT_EN_RX_FULL_EN (MXC_V_SPI17Y_INT_EN_RX_FULL_EN << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ + #define MXC_F_SPI17Y_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ + #define MXC_V_SPI17Y_INT_EN_SSA_DIS ((uint32_t)0x0UL) /**< INT_EN_SSA_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_SSA_DIS (MXC_V_SPI17Y_INT_EN_SSA_DIS << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_SSA_EN ((uint32_t)0x1UL) /**< INT_EN_SSA_EN Value */ + #define MXC_S_SPI17Y_INT_EN_SSA_EN (MXC_V_SPI17Y_INT_EN_SSA_EN << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ + #define MXC_F_SPI17Y_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ + #define MXC_V_SPI17Y_INT_EN_SSD_DIS ((uint32_t)0x0UL) /**< INT_EN_SSD_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_SSD_DIS (MXC_V_SPI17Y_INT_EN_SSD_DIS << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_SSD_EN ((uint32_t)0x1UL) /**< INT_EN_SSD_EN Value */ + #define MXC_S_SPI17Y_INT_EN_SSD_EN (MXC_V_SPI17Y_INT_EN_SSD_EN << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ + #define MXC_F_SPI17Y_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ + #define MXC_V_SPI17Y_INT_EN_FAULT_DIS ((uint32_t)0x0UL) /**< INT_EN_FAULT_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_FAULT_DIS (MXC_V_SPI17Y_INT_EN_FAULT_DIS << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_FAULT_EN ((uint32_t)0x1UL) /**< INT_EN_FAULT_EN Value */ + #define MXC_S_SPI17Y_INT_EN_FAULT_EN (MXC_V_SPI17Y_INT_EN_FAULT_EN << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ + #define MXC_F_SPI17Y_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ + #define MXC_V_SPI17Y_INT_EN_ABORT_DIS ((uint32_t)0x0UL) /**< INT_EN_ABORT_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_ABORT_DIS (MXC_V_SPI17Y_INT_EN_ABORT_DIS << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_ABORT_EN ((uint32_t)0x1UL) /**< INT_EN_ABORT_EN Value */ + #define MXC_S_SPI17Y_INT_EN_ABORT_EN (MXC_V_SPI17Y_INT_EN_ABORT_EN << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ + #define MXC_F_SPI17Y_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ + #define MXC_V_SPI17Y_INT_EN_M_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN_M_DONE_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_M_DONE_DIS (MXC_V_SPI17Y_INT_EN_M_DONE_DIS << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_M_DONE_EN ((uint32_t)0x1UL) /**< INT_EN_M_DONE_EN Value */ + #define MXC_S_SPI17Y_INT_EN_M_DONE_EN (MXC_V_SPI17Y_INT_EN_M_DONE_EN << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ + #define MXC_F_SPI17Y_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ + #define MXC_V_SPI17Y_INT_EN_TX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_OVR_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_TX_OVR_DIS (MXC_V_SPI17Y_INT_EN_TX_OVR_DIS << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_TX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_TX_OVR_EN Value */ + #define MXC_S_SPI17Y_INT_EN_TX_OVR_EN (MXC_V_SPI17Y_INT_EN_TX_OVR_EN << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ + #define MXC_F_SPI17Y_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ + #define MXC_V_SPI17Y_INT_EN_TX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_UND_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_TX_UND_DIS (MXC_V_SPI17Y_INT_EN_TX_UND_DIS << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_TX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_TX_UND_EN Value */ + #define MXC_S_SPI17Y_INT_EN_TX_UND_EN (MXC_V_SPI17Y_INT_EN_TX_UND_EN << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ + #define MXC_F_SPI17Y_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ + #define MXC_V_SPI17Y_INT_EN_RX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_OVR_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_RX_OVR_DIS (MXC_V_SPI17Y_INT_EN_RX_OVR_DIS << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_RX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_OVR_EN Value */ + #define MXC_S_SPI17Y_INT_EN_RX_OVR_EN (MXC_V_SPI17Y_INT_EN_RX_OVR_EN << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_EN Setting */ + + #define MXC_F_SPI17Y_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ + #define MXC_F_SPI17Y_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ + #define MXC_V_SPI17Y_INT_EN_RX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_UND_DIS Value */ + #define MXC_S_SPI17Y_INT_EN_RX_UND_DIS (MXC_V_SPI17Y_INT_EN_RX_UND_DIS << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_DIS Setting */ + #define MXC_V_SPI17Y_INT_EN_RX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_RX_UND_EN Value */ + #define MXC_S_SPI17Y_INT_EN_RX_UND_EN (MXC_V_SPI17Y_INT_EN_RX_UND_EN << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_EN Setting */ + +/**@} end of group SPI17Y_INT_EN_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_WAKE_FL SPI17Y_WAKE_FL + * @brief Register for wake up flags. All bits in this register are write 1 to clear. + * @{ + */ + #define MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */ + #define MXC_F_SPI17Y_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */ + #define MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_THRESH_CLEAR Value */ + #define MXC_S_SPI17Y_WAKE_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS) /**< WAKE_FL_TX_THRESH_CLEAR Setting */ + + #define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ + #define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ + #define MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_EMPTY_CLEAR Value */ + #define MXC_S_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS) /**< WAKE_FL_TX_EMPTY_CLEAR Setting */ + + #define MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */ + #define MXC_F_SPI17Y_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */ + #define MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_THRESH_CLEAR Value */ + #define MXC_S_SPI17Y_WAKE_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS) /**< WAKE_FL_RX_THRESH_CLEAR Setting */ + + #define MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ + #define MXC_F_SPI17Y_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ + #define MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_FULL_CLEAR Value */ + #define MXC_S_SPI17Y_WAKE_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS) /**< WAKE_FL_RX_FULL_CLEAR Setting */ + +/**@} end of group SPI17Y_WAKE_FL_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_WAKE_EN SPI17Y_WAKE_EN + * @brief Register for wake up enable. + * @{ + */ + #define MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */ + #define MXC_F_SPI17Y_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */ + #define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_THRESH_DIS Value */ + #define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_DIS Setting */ + #define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_THRESH_EN Value */ + #define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_EN Setting */ + + #define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ + #define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ + #define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_EMPTY_DIS Value */ + #define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_DIS Setting */ + #define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_EMPTY_EN Value */ + #define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_EN (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_EN Setting */ + + #define MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */ + #define MXC_F_SPI17Y_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */ + #define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_THRESH_DIS Value */ + #define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_DIS Setting */ + #define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_THRESH_EN Value */ + #define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_EN Setting */ + + #define MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ + #define MXC_F_SPI17Y_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ + #define MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_FULL_DIS Value */ + #define MXC_S_SPI17Y_WAKE_EN_RX_FULL_DIS (MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_DIS Setting */ + #define MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_FULL_EN Value */ + #define MXC_S_SPI17Y_WAKE_EN_RX_FULL_EN (MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_EN Setting */ + +/**@} end of group SPI17Y_WAKE_EN_Register */ + +/** + * @ingroup spi17y_registers + * @defgroup SPI17Y_STAT SPI17Y_STAT + * @brief SPI Status register. + * @{ + */ + #define MXC_F_SPI17Y_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ + #define MXC_F_SPI17Y_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI17Y_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ + #define MXC_V_SPI17Y_STAT_BUSY_NOT ((uint32_t)0x0UL) /**< STAT_BUSY_NOT Value */ + #define MXC_S_SPI17Y_STAT_BUSY_NOT (MXC_V_SPI17Y_STAT_BUSY_NOT << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_NOT Setting */ + #define MXC_V_SPI17Y_STAT_BUSY_ACTIVE ((uint32_t)0x1UL) /**< STAT_BUSY_ACTIVE Value */ + #define MXC_S_SPI17Y_STAT_BUSY_ACTIVE (MXC_V_SPI17Y_STAT_BUSY_ACTIVE << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_ACTIVE Setting */ + +/**@} end of group SPI17Y_STAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPI17Y_REGS_H_ */ diff --git a/Project/SDK/Device/Include/spimss_regs.h b/Project/SDK/Device/Include/spimss_regs.h new file mode 100644 index 0000000..44ea80f --- /dev/null +++ b/Project/SDK/Device/Include/spimss_regs.h @@ -0,0 +1,496 @@ +/** + * @file spimss_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _SPIMSS_REGS_H_ +#define _SPIMSS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spimss + * @defgroup spimss_registers SPIMSS_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module. + * @details Serial Peripheral Interface. + */ + +/** + * @ingroup spimss_registers + * Structure type to access the SPIMSS Registers. + */ +typedef struct { + union{ + __IO uint16_t data16; /**< \b 0x00: SPIMSS DATA16 Register */ + __IO uint8_t data8[2]; /**< \b 0x00: SPIMSS DATA8 Register */ + }; + __R uint16_t rsv_0x2; + __IO uint32_t ctrl; /**< \b 0x04: SPIMSS CTRL Register */ + __IO uint32_t status; /**< \b 0x08: SPIMSS STATUS Register */ + __IO uint32_t mod; /**< \b 0x0C: SPIMSS MOD Register */ + __R uint32_t rsv_0x10; + __IO uint32_t brg; /**< \b 0x14: SPIMSS BRG Register */ + __IO uint32_t dma; /**< \b 0x18: SPIMSS DMA Register */ + __IO uint32_t i2s_ctrl; /**< \b 0x1C: SPIMSS I2S_CTRL Register */ +} mxc_spimss_regs_t; + +/* Register offsets for module SPIMSS */ +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_Register_Offsets Register Offsets + * @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address. + * @{ + */ + #define MXC_R_SPIMSS_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: 0x0000 */ + #define MXC_R_SPIMSS_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: 0x0000 */ + #define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: 0x0004 */ + #define MXC_R_SPIMSS_STATUS ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: 0x0008 */ + #define MXC_R_SPIMSS_MOD ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: 0x000C */ + #define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: 0x0014 */ + #define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: 0x0018 */ + #define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: 0x001C */ +/**@} end of group spimss_registers */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DATA16 SPIMSS_DATA16 + * @brief SPI 16-bit Data Access + * @{ + */ + #define MXC_F_SPIMSS_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ + #define MXC_F_SPIMSS_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ + +/**@} end of group SPIMSS_DATA16_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DATA8 SPIMSS_DATA8 + * @brief SPI Data 8-bit access + * @{ + */ + #define MXC_F_SPIMSS_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ + #define MXC_F_SPIMSS_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIMSS_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ + +/**@} end of group SPIMSS_DATA8_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_CTRL SPIMSS_CTRL + * @brief SPI Control Register. + * @{ + */ + #define MXC_F_SPIMSS_CTRL_SPIEN_POS 0 /**< CTRL_SPIEN Position */ + #define MXC_F_SPIMSS_CTRL_SPIEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_SPIEN_POS)) /**< CTRL_SPIEN Mask */ + #define MXC_V_SPIMSS_CTRL_SPIEN_DISABLE ((uint32_t)0x0UL) /**< CTRL_SPIEN_DISABLE Value */ + #define MXC_S_SPIMSS_CTRL_SPIEN_DISABLE (MXC_V_SPIMSS_CTRL_SPIEN_DISABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_DISABLE Setting */ + #define MXC_V_SPIMSS_CTRL_SPIEN_ENABLE ((uint32_t)0x1UL) /**< CTRL_SPIEN_ENABLE Value */ + #define MXC_S_SPIMSS_CTRL_SPIEN_ENABLE (MXC_V_SPIMSS_CTRL_SPIEN_ENABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_ENABLE Setting */ + + #define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */ + #define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */ + #define MXC_V_SPIMSS_CTRL_MMEN_SLAVE ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */ + #define MXC_S_SPIMSS_CTRL_MMEN_SLAVE (MXC_V_SPIMSS_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */ + #define MXC_V_SPIMSS_CTRL_MMEN_MASTER ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */ + #define MXC_S_SPIMSS_CTRL_MMEN_MASTER (MXC_V_SPIMSS_CTRL_MMEN_MASTER << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */ + + #define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */ + #define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */ + #define MXC_V_SPIMSS_CTRL_WOR_DISABLE ((uint32_t)0x0UL) /**< CTRL_WOR_DISABLE Value */ + #define MXC_S_SPIMSS_CTRL_WOR_DISABLE (MXC_V_SPIMSS_CTRL_WOR_DISABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_DISABLE Setting */ + #define MXC_V_SPIMSS_CTRL_WOR_ENABLE ((uint32_t)0x1UL) /**< CTRL_WOR_ENABLE Value */ + #define MXC_S_SPIMSS_CTRL_WOR_ENABLE (MXC_V_SPIMSS_CTRL_WOR_ENABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_ENABLE Setting */ + + #define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */ + #define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */ + #define MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */ + #define MXC_S_SPIMSS_CTRL_CLKPOL_IDLELO (MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */ + #define MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */ + #define MXC_S_SPIMSS_CTRL_CLKPOL_IDLEHI (MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */ + + #define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */ + #define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */ + #define MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */ + #define MXC_S_SPIMSS_CTRL_PHASE_ACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */ + #define MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */ + #define MXC_S_SPIMSS_CTRL_PHASE_INACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */ + + #define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */ + #define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */ + #define MXC_V_SPIMSS_CTRL_BIRQ_DISABLE ((uint32_t)0x0UL) /**< CTRL_BIRQ_DISABLE Value */ + #define MXC_S_SPIMSS_CTRL_BIRQ_DISABLE (MXC_V_SPIMSS_CTRL_BIRQ_DISABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DISABLE Setting */ + #define MXC_V_SPIMSS_CTRL_BIRQ_ENABLE ((uint32_t)0x1UL) /**< CTRL_BIRQ_ENABLE Value */ + #define MXC_S_SPIMSS_CTRL_BIRQ_ENABLE (MXC_V_SPIMSS_CTRL_BIRQ_ENABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_ENABLE Setting */ + + #define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */ + #define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */ + #define MXC_V_SPIMSS_CTRL_STR_COMPLETE ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */ + #define MXC_S_SPIMSS_CTRL_STR_COMPLETE (MXC_V_SPIMSS_CTRL_STR_COMPLETE << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */ + #define MXC_V_SPIMSS_CTRL_STR_START ((uint32_t)0x1UL) /**< CTRL_STR_START Value */ + #define MXC_S_SPIMSS_CTRL_STR_START (MXC_V_SPIMSS_CTRL_STR_START << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_START Setting */ + + #define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */ + #define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */ + #define MXC_V_SPIMSS_CTRL_IRQE_DISABLE ((uint32_t)0x0UL) /**< CTRL_IRQE_DISABLE Value */ + #define MXC_S_SPIMSS_CTRL_IRQE_DISABLE (MXC_V_SPIMSS_CTRL_IRQE_DISABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_DISABLE Setting */ + #define MXC_V_SPIMSS_CTRL_IRQE_ENABLE ((uint32_t)0x1UL) /**< CTRL_IRQE_ENABLE Value */ + #define MXC_S_SPIMSS_CTRL_IRQE_ENABLE (MXC_V_SPIMSS_CTRL_IRQE_ENABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_ENABLE Setting */ + +/**@} end of group SPIMSS_CTRL_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_STATUS SPIMSS_STATUS + * @brief SPI Status Register. + * @{ + */ + #define MXC_F_SPIMSS_STATUS_SLAS_POS 0 /**< STATUS_SLAS Position */ + #define MXC_F_SPIMSS_STATUS_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_SLAS_POS)) /**< STATUS_SLAS Mask */ + #define MXC_V_SPIMSS_STATUS_SLAS_SELECTED ((uint32_t)0x0UL) /**< STATUS_SLAS_SELECTED Value */ + #define MXC_S_SPIMSS_STATUS_SLAS_SELECTED (MXC_V_SPIMSS_STATUS_SLAS_SELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_SELECTED Setting */ + #define MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED ((uint32_t)0x1UL) /**< STATUS_SLAS_NOTSELECTED Value */ + #define MXC_S_SPIMSS_STATUS_SLAS_NOTSELECTED (MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_NOTSELECTED Setting */ + + #define MXC_F_SPIMSS_STATUS_TXST_POS 1 /**< STATUS_TXST Position */ + #define MXC_F_SPIMSS_STATUS_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TXST_POS)) /**< STATUS_TXST Mask */ + #define MXC_V_SPIMSS_STATUS_TXST_IDLE ((uint32_t)0x0UL) /**< STATUS_TXST_IDLE Value */ + #define MXC_S_SPIMSS_STATUS_TXST_IDLE (MXC_V_SPIMSS_STATUS_TXST_IDLE << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_IDLE Setting */ + #define MXC_V_SPIMSS_STATUS_TXST_BUSY ((uint32_t)0x1UL) /**< STATUS_TXST_BUSY Value */ + #define MXC_S_SPIMSS_STATUS_TXST_BUSY (MXC_V_SPIMSS_STATUS_TXST_BUSY << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_BUSY Setting */ + + #define MXC_F_SPIMSS_STATUS_TUND_POS 2 /**< STATUS_TUND Position */ + #define MXC_F_SPIMSS_STATUS_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TUND_POS)) /**< STATUS_TUND Mask */ + #define MXC_V_SPIMSS_STATUS_TUND_NOEVENT ((uint32_t)0x0UL) /**< STATUS_TUND_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_TUND_NOEVENT (MXC_V_SPIMSS_STATUS_TUND_NOEVENT << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_TUND_OCCURRED ((uint32_t)0x1UL) /**< STATUS_TUND_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_TUND_OCCURRED (MXC_V_SPIMSS_STATUS_TUND_OCCURRED << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_ROVR_POS 3 /**< STATUS_ROVR Position */ + #define MXC_F_SPIMSS_STATUS_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ROVR_POS)) /**< STATUS_ROVR Mask */ + #define MXC_V_SPIMSS_STATUS_ROVR_NOEVENT ((uint32_t)0x0UL) /**< STATUS_ROVR_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_ROVR_NOEVENT (MXC_V_SPIMSS_STATUS_ROVR_NOEVENT << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_ROVR_OCCURRED ((uint32_t)0x1UL) /**< STATUS_ROVR_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_ROVR_OCCURRED (MXC_V_SPIMSS_STATUS_ROVR_OCCURRED << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_ABT_POS 4 /**< STATUS_ABT Position */ + #define MXC_F_SPIMSS_STATUS_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ABT_POS)) /**< STATUS_ABT Mask */ + #define MXC_V_SPIMSS_STATUS_ABT_NOEVENT ((uint32_t)0x0UL) /**< STATUS_ABT_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_ABT_NOEVENT (MXC_V_SPIMSS_STATUS_ABT_NOEVENT << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_ABT_OCCURRED ((uint32_t)0x1UL) /**< STATUS_ABT_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_ABT_OCCURRED (MXC_V_SPIMSS_STATUS_ABT_OCCURRED << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_COL_POS 5 /**< STATUS_COL Position */ + #define MXC_F_SPIMSS_STATUS_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_COL_POS)) /**< STATUS_COL Mask */ + #define MXC_V_SPIMSS_STATUS_COL_NOEVENT ((uint32_t)0x0UL) /**< STATUS_COL_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_COL_NOEVENT (MXC_V_SPIMSS_STATUS_COL_NOEVENT << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_COL_OCCURRED ((uint32_t)0x1UL) /**< STATUS_COL_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_COL_OCCURRED (MXC_V_SPIMSS_STATUS_COL_OCCURRED << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_TOVR_POS 6 /**< STATUS_TOVR Position */ + #define MXC_F_SPIMSS_STATUS_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TOVR_POS)) /**< STATUS_TOVR Mask */ + #define MXC_V_SPIMSS_STATUS_TOVR_NOEVENT ((uint32_t)0x0UL) /**< STATUS_TOVR_NOEVENT Value */ + #define MXC_S_SPIMSS_STATUS_TOVR_NOEVENT (MXC_V_SPIMSS_STATUS_TOVR_NOEVENT << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_NOEVENT Setting */ + #define MXC_V_SPIMSS_STATUS_TOVR_OCCURRED ((uint32_t)0x1UL) /**< STATUS_TOVR_OCCURRED Value */ + #define MXC_S_SPIMSS_STATUS_TOVR_OCCURRED (MXC_V_SPIMSS_STATUS_TOVR_OCCURRED << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_OCCURRED Setting */ + + #define MXC_F_SPIMSS_STATUS_IRQ_POS 7 /**< STATUS_IRQ Position */ + #define MXC_F_SPIMSS_STATUS_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_IRQ_POS)) /**< STATUS_IRQ Mask */ + #define MXC_V_SPIMSS_STATUS_IRQ_INACTIVE ((uint32_t)0x0UL) /**< STATUS_IRQ_INACTIVE Value */ + #define MXC_S_SPIMSS_STATUS_IRQ_INACTIVE (MXC_V_SPIMSS_STATUS_IRQ_INACTIVE << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_INACTIVE Setting */ + #define MXC_V_SPIMSS_STATUS_IRQ_PENDING ((uint32_t)0x1UL) /**< STATUS_IRQ_PENDING Value */ + #define MXC_S_SPIMSS_STATUS_IRQ_PENDING (MXC_V_SPIMSS_STATUS_IRQ_PENDING << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_PENDING Setting */ + +/**@} end of group SPIMSS_STATUS_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_MOD SPIMSS_MOD + * @brief SPI Mode Register. + * @{ + */ + #define MXC_F_SPIMSS_MOD_SSV_POS 0 /**< MOD_SSV Position */ + #define MXC_F_SPIMSS_MOD_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSV_POS)) /**< MOD_SSV Mask */ + #define MXC_V_SPIMSS_MOD_SSV_LO ((uint32_t)0x0UL) /**< MOD_SSV_LO Value */ + #define MXC_S_SPIMSS_MOD_SSV_LO (MXC_V_SPIMSS_MOD_SSV_LO << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_LO Setting */ + #define MXC_V_SPIMSS_MOD_SSV_HI ((uint32_t)0x1UL) /**< MOD_SSV_HI Value */ + #define MXC_S_SPIMSS_MOD_SSV_HI (MXC_V_SPIMSS_MOD_SSV_HI << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_HI Setting */ + + #define MXC_F_SPIMSS_MOD_SSIO_POS 1 /**< MOD_SSIO Position */ + #define MXC_F_SPIMSS_MOD_SSIO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSIO_POS)) /**< MOD_SSIO Mask */ + #define MXC_V_SPIMSS_MOD_SSIO_INPUT ((uint32_t)0x0UL) /**< MOD_SSIO_INPUT Value */ + #define MXC_S_SPIMSS_MOD_SSIO_INPUT (MXC_V_SPIMSS_MOD_SSIO_INPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_INPUT Setting */ + #define MXC_V_SPIMSS_MOD_SSIO_OUTPUT ((uint32_t)0x1UL) /**< MOD_SSIO_OUTPUT Value */ + #define MXC_S_SPIMSS_MOD_SSIO_OUTPUT (MXC_V_SPIMSS_MOD_SSIO_OUTPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_OUTPUT Setting */ + + #define MXC_F_SPIMSS_MOD_NUMBITS_POS 2 /**< MOD_NUMBITS Position */ + #define MXC_F_SPIMSS_MOD_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MOD_NUMBITS_POS)) /**< MOD_NUMBITS Mask */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MOD_NUMBITS_BITS16 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS16 (MXC_V_SPIMSS_MOD_NUMBITS_BITS16 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS16 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MOD_NUMBITS_BITS1 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS1 (MXC_V_SPIMSS_MOD_NUMBITS_BITS1 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS1 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MOD_NUMBITS_BITS2 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS2 (MXC_V_SPIMSS_MOD_NUMBITS_BITS2 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS2 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MOD_NUMBITS_BITS3 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS3 (MXC_V_SPIMSS_MOD_NUMBITS_BITS3 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS3 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MOD_NUMBITS_BITS4 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS4 (MXC_V_SPIMSS_MOD_NUMBITS_BITS4 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS4 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MOD_NUMBITS_BITS5 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS5 (MXC_V_SPIMSS_MOD_NUMBITS_BITS5 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS5 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MOD_NUMBITS_BITS6 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS6 (MXC_V_SPIMSS_MOD_NUMBITS_BITS6 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS6 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MOD_NUMBITS_BITS7 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS7 (MXC_V_SPIMSS_MOD_NUMBITS_BITS7 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS7 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MOD_NUMBITS_BITS8 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS8 (MXC_V_SPIMSS_MOD_NUMBITS_BITS8 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS8 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MOD_NUMBITS_BITS9 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS9 (MXC_V_SPIMSS_MOD_NUMBITS_BITS9 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS9 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MOD_NUMBITS_BITS10 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS10 (MXC_V_SPIMSS_MOD_NUMBITS_BITS10 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS10 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MOD_NUMBITS_BITS11 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS11 (MXC_V_SPIMSS_MOD_NUMBITS_BITS11 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS11 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MOD_NUMBITS_BITS12 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS12 (MXC_V_SPIMSS_MOD_NUMBITS_BITS12 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS12 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MOD_NUMBITS_BITS13 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS13 (MXC_V_SPIMSS_MOD_NUMBITS_BITS13 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS13 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MOD_NUMBITS_BITS14 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS14 (MXC_V_SPIMSS_MOD_NUMBITS_BITS14 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS14 Setting */ + #define MXC_V_SPIMSS_MOD_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MOD_NUMBITS_BITS15 Value */ + #define MXC_S_SPIMSS_MOD_NUMBITS_BITS15 (MXC_V_SPIMSS_MOD_NUMBITS_BITS15 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS15 Setting */ + + #define MXC_F_SPIMSS_MOD_TX_LJ_POS 7 /**< MOD_TX_LJ Position */ + #define MXC_F_SPIMSS_MOD_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_TX_LJ_POS)) /**< MOD_TX_LJ Mask */ + #define MXC_V_SPIMSS_MOD_TX_LJ_DISABLE ((uint32_t)0x0UL) /**< MOD_TX_LJ_DISABLE Value */ + #define MXC_S_SPIMSS_MOD_TX_LJ_DISABLE (MXC_V_SPIMSS_MOD_TX_LJ_DISABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_DISABLE Setting */ + #define MXC_V_SPIMSS_MOD_TX_LJ_ENABLE ((uint32_t)0x1UL) /**< MOD_TX_LJ_ENABLE Value */ + #define MXC_S_SPIMSS_MOD_TX_LJ_ENABLE (MXC_V_SPIMSS_MOD_TX_LJ_ENABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_ENABLE Setting */ + + #define MXC_F_SPIMSS_MOD_SSL1_POS 8 /**< MOD_SSL1 Position */ + #define MXC_F_SPIMSS_MOD_SSL1 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL1_POS)) /**< MOD_SSL1 Mask */ + #define MXC_V_SPIMSS_MOD_SSL1_HI ((uint32_t)0x0UL) /**< MOD_SSL1_HI Value */ + #define MXC_S_SPIMSS_MOD_SSL1_HI (MXC_V_SPIMSS_MOD_SSL1_HI << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_HI Setting */ + #define MXC_V_SPIMSS_MOD_SSL1_LO ((uint32_t)0x1UL) /**< MOD_SSL1_LO Value */ + #define MXC_S_SPIMSS_MOD_SSL1_LO (MXC_V_SPIMSS_MOD_SSL1_LO << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_LO Setting */ + + #define MXC_F_SPIMSS_MOD_SSL2_POS 9 /**< MOD_SSL2 Position */ + #define MXC_F_SPIMSS_MOD_SSL2 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL2_POS)) /**< MOD_SSL2 Mask */ + #define MXC_V_SPIMSS_MOD_SSL2_HI ((uint32_t)0x0UL) /**< MOD_SSL2_HI Value */ + #define MXC_S_SPIMSS_MOD_SSL2_HI (MXC_V_SPIMSS_MOD_SSL2_HI << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_HI Setting */ + #define MXC_V_SPIMSS_MOD_SSL2_LO ((uint32_t)0x1UL) /**< MOD_SSL2_LO Value */ + #define MXC_S_SPIMSS_MOD_SSL2_LO (MXC_V_SPIMSS_MOD_SSL2_LO << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_LO Setting */ + + #define MXC_F_SPIMSS_MOD_SSL3_POS 10 /**< MOD_SSL3 Position */ + #define MXC_F_SPIMSS_MOD_SSL3 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL3_POS)) /**< MOD_SSL3 Mask */ + #define MXC_V_SPIMSS_MOD_SSL3_HI ((uint32_t)0x0UL) /**< MOD_SSL3_HI Value */ + #define MXC_S_SPIMSS_MOD_SSL3_HI (MXC_V_SPIMSS_MOD_SSL3_HI << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_HI Setting */ + #define MXC_V_SPIMSS_MOD_SSL3_LO ((uint32_t)0x1UL) /**< MOD_SSL3_LO Value */ + #define MXC_S_SPIMSS_MOD_SSL3_LO (MXC_V_SPIMSS_MOD_SSL3_LO << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_LO Setting */ + +/**@} end of group SPIMSS_MOD_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_BRG SPIMSS_BRG + * @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for + * the SPI Baud Rate Generator. The reload value must be greater than or equal to + * 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by + * 4). + * @{ + */ + #define MXC_F_SPIMSS_BRG_BRG_POS 0 /**< BRG_BRG Position */ + #define MXC_F_SPIMSS_BRG_BRG ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_BRG_POS)) /**< BRG_BRG Mask */ + +/**@} end of group SPIMSS_BRG_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_DMA SPIMSS_DMA + * @brief SPI DMA Register. + * @{ + */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Setting */ + + #define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS 4 /**< DMA_TX_FIFO_CLEAR Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE ((uint32_t)0x0UL) /**< DMA_TX_FIFO_CLEAR_COMPLETE Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_COMPLETE Setting */ + #define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_START Value */ + #define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_START (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_START Setting */ + + #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ + #define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ + + #define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ + #define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ + #define MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DISABLE Value */ + #define MXC_S_SPIMSS_DMA_TX_DMA_EN_DISABLE (MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_ENABLE Value */ + #define MXC_S_SPIMSS_DMA_TX_DMA_EN_ENABLE (MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_ENABLE Setting */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Setting */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS 20 /**< DMA_RX_FIFO_CLEAR Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE ((uint32_t)0x0UL) /**< DMA_RX_FIFO_CLEAR_COMPLETE Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_COMPLETE Setting */ + #define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_START Value */ + #define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_START (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_START Setting */ + + #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ + #define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ + + #define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ + #define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ + #define MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DISABLE Value */ + #define MXC_S_SPIMSS_DMA_RX_DMA_EN_DISABLE (MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_ENABLE Value */ + #define MXC_S_SPIMSS_DMA_RX_DMA_EN_ENABLE (MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_ENABLE Setting */ + +/**@} end of group SPIMSS_DMA_Register */ + +/** + * @ingroup spimss_registers + * @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL + * @brief I2S Control Register. + * @{ + */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DISABLE Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_DISABLE (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DISABLE Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_ENABLE Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_ENABLE (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_ENABLE Setting */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_REPLACED Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_REPLACED Setting */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_HALT Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_HALT Setting */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Setting */ + + #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */ + #define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_NORMAL Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_NORMAL Setting */ + #define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_REPLACED Value */ + #define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_REPLACED Setting */ + +/**@} end of group SPIMSS_I2S_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPIMSS_REGS_H_ */ diff --git a/Project/SDK/Device/Include/system_max32660.h b/Project/SDK/Device/Include/system_max32660.h new file mode 100644 index 0000000..1d80f6f --- /dev/null +++ b/Project/SDK/Device/Include/system_max32660.h @@ -0,0 +1,93 @@ +/** + * @file system_max32660.h + * @brief System-specific header file + */ + + +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +#ifndef _SYSTEM_MAX32660_H_ +#define _SYSTEM_MAX32660_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +#ifndef HFX_FREQ +#define HFX_FREQ 32768 +#endif + +#ifndef NANORING_FREQ +#define NANORING_FREQ 8000 +#endif + +#ifndef HIRC96_FREQ +#define HIRC96_FREQ 96000000 +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +#ifndef PeripheralClock +#define PeripheralClock (SystemCoreClock /2) /*!< Peripheral Clock Frequency */ +#endif + +/* + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/* + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MAX32660_H_ */ diff --git a/Project/SDK/Device/Include/tmr_regs.h b/Project/SDK/Device/Include/tmr_regs.h new file mode 100644 index 0000000..5f74afa --- /dev/null +++ b/Project/SDK/Device/Include/tmr_regs.h @@ -0,0 +1,233 @@ +/** + * @file tmr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _TMR_REGS_H_ +#define _TMR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup tmr + * @defgroup tmr_registers TMR_Registers + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @details 32-bit reloadable timer that can be used for timing and event counting. + */ + +/** + * @ingroup tmr_registers + * Structure type to access the TMR Registers. + */ +typedef struct { + __IO uint32_t cnt; /**< \b 0x00: TMR CNT Register */ + __IO uint32_t cmp; /**< \b 0x04: TMR CMP Register */ + __IO uint32_t pwm; /**< \b 0x08: TMR PWM Register */ + __IO uint32_t intr; /**< \b 0x0C: TMR INTR Register */ + __IO uint32_t cn; /**< \b 0x10: TMR CN Register */ + __IO uint32_t nolcmp; /**< \b 0x14: TMR NOLCMP Register */ +} mxc_tmr_regs_t; + +/* Register offsets for module TMR */ +/** + * @ingroup tmr_registers + * @defgroup TMR_Register_Offsets Register Offsets + * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. + * @{ + */ + #define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ + #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ + #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ + #define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ + #define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ + #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ +/**@} end of group tmr_registers */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_INTR TMR_INTR + * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the + * associated interrupt. + * @{ + */ + #define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */ + #define MXC_F_TMR_INTR_IRQ_CLR ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */ + +/**@} end of group TMR_INTR_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CN TMR_CN + * @brief Timer Control Register. + * @{ + */ + #define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */ + #define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */ + #define MXC_V_TMR_CN_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */ + #define MXC_S_TMR_CN_TMODE_ONESHOT (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */ + #define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */ + #define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */ + #define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */ + #define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */ + #define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */ + #define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */ + #define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */ + #define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */ + #define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */ + #define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */ + #define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */ + #define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */ + #define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */ + #define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */ + + #define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */ + #define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */ + #define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */ + #define MXC_S_TMR_CN_PRES_DIV1 (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */ + #define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */ + #define MXC_S_TMR_CN_PRES_DIV2 (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */ + #define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */ + #define MXC_S_TMR_CN_PRES_DIV4 (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */ + #define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */ + #define MXC_S_TMR_CN_PRES_DIV8 (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */ + #define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */ + #define MXC_S_TMR_CN_PRES_DIV16 (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */ + #define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */ + #define MXC_S_TMR_CN_PRES_DIV32 (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */ + #define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */ + #define MXC_S_TMR_CN_PRES_DIV64 (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */ + #define MXC_V_TMR_CN_PRES_DIV128 ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */ + #define MXC_S_TMR_CN_PRES_DIV128 (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */ + + #define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */ + #define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */ + #define MXC_V_TMR_CN_TPOL_ACTIVEHI ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */ + #define MXC_S_TMR_CN_TPOL_ACTIVEHI (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */ + #define MXC_V_TMR_CN_TPOL_ACTIVELO ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */ + #define MXC_S_TMR_CN_TPOL_ACTIVELO (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */ + + #define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */ + #define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */ + #define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */ + #define MXC_S_TMR_CN_TEN_DIS (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */ + #define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */ + #define MXC_S_TMR_CN_TEN_EN (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting */ + + #define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */ + #define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */ + + #define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */ + #define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */ + #define MXC_V_TMR_CN_PWMSYNC_DIS ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value */ + #define MXC_S_TMR_CN_PWMSYNC_DIS (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */ + #define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */ + #define MXC_S_TMR_CN_PWMSYNC_EN (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */ + + #define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */ + #define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */ + #define MXC_V_TMR_CN_NOLHPOL_DIS ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value */ + #define MXC_S_TMR_CN_NOLHPOL_DIS (MXC_V_TMR_CN_NOLHPOL_DIS << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */ + #define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */ + #define MXC_S_TMR_CN_NOLHPOL_EN (MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */ + + #define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */ + #define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */ + #define MXC_V_TMR_CN_NOLLPOL_DIS ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value */ + #define MXC_S_TMR_CN_NOLLPOL_DIS (MXC_V_TMR_CN_NOLLPOL_DIS << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */ + #define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */ + #define MXC_S_TMR_CN_NOLLPOL_EN (MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */ + + #define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */ + #define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */ + #define MXC_V_TMR_CN_PWMCKBD_DIS ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value */ + #define MXC_S_TMR_CN_PWMCKBD_DIS (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */ + #define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */ + #define MXC_S_TMR_CN_PWMCKBD_EN (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */ + +/**@} end of group TMR_CN_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_NOLCMP TMR_NOLCMP + * @brief Timer Non-Overlapping Compare Register. + * @{ + */ + #define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */ + #define MXC_F_TMR_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */ + + #define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */ + #define MXC_F_TMR_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */ + +/**@} end of group TMR_NOLCMP_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TMR_REGS_H_ */ diff --git a/Project/SDK/Device/Include/uart_regs.h b/Project/SDK/Device/Include/uart_regs.h new file mode 100644 index 0000000..aaa2f5e --- /dev/null +++ b/Project/SDK/Device/Include/uart_regs.h @@ -0,0 +1,450 @@ +/** + * @file uart_regs.h + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _UART_REGS_H_ +#define _UART_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup uart + * @defgroup uart_registers UART_Registers + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @details UART + */ + +/** + * @ingroup uart_registers + * Structure type to access the UART Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: UART CTRL Register */ + __IO uint32_t thresh_ctrl; /**< \b 0x04: UART THRESH_CTRL Register */ + __I uint32_t status; /**< \b 0x08: UART STATUS Register */ + __IO uint32_t int_en; /**< \b 0x0C: UART INT_EN Register */ + __IO uint32_t int_fl; /**< \b 0x10: UART INT_FL Register */ + __IO uint32_t baud0; /**< \b 0x14: UART BAUD0 Register */ + __IO uint32_t baud1; /**< \b 0x18: UART BAUD1 Register */ + __IO uint32_t fifo; /**< \b 0x1C: UART FIFO Register */ + __IO uint32_t dma; /**< \b 0x20: UART DMA Register */ + __IO uint32_t tx_fifo; /**< \b 0x24: UART TX_FIFO Register */ +} mxc_uart_regs_t; + +/* Register offsets for module UART */ +/** + * @ingroup uart_registers + * @defgroup UART_Register_Offsets Register Offsets + * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. + * @{ + */ + #define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ + #define MXC_R_UART_THRESH_CTRL ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ + #define MXC_R_UART_STATUS ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ + #define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ + #define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ + #define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ + #define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ + #define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ + #define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ + #define MXC_R_UART_TX_FIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: 0x0024 */ +/**@} end of group uart_registers */ + +/** + * @ingroup uart_registers + * @defgroup UART_CTRL UART_CTRL + * @brief Control Register. + * @{ + */ + #define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */ + #define MXC_F_UART_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */ + #define MXC_V_UART_CTRL_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */ + #define MXC_S_UART_CTRL_ENABLE_DIS (MXC_V_UART_CTRL_ENABLE_DIS << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */ + #define MXC_V_UART_CTRL_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value */ + #define MXC_S_UART_CTRL_ENABLE_EN (MXC_V_UART_CTRL_ENABLE_EN << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */ + + #define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */ + #define MXC_F_UART_CTRL_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */ + #define MXC_V_UART_CTRL_PARITY_EN_DIS ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */ + #define MXC_S_UART_CTRL_PARITY_EN_DIS (MXC_V_UART_CTRL_PARITY_EN_DIS << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */ + #define MXC_V_UART_CTRL_PARITY_EN_EN ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */ + #define MXC_S_UART_CTRL_PARITY_EN_EN (MXC_V_UART_CTRL_PARITY_EN_EN << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */ + + #define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */ + #define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */ + #define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */ + #define MXC_S_UART_CTRL_PARITY_EVEN (MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */ + #define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */ + #define MXC_S_UART_CTRL_PARITY_ODD (MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */ + #define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */ + #define MXC_S_UART_CTRL_PARITY_MARK (MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */ + #define MXC_V_UART_CTRL_PARITY_SPACE ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */ + #define MXC_S_UART_CTRL_PARITY_SPACE (MXC_V_UART_CTRL_PARITY_SPACE << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */ + + #define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */ + #define MXC_F_UART_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */ + #define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */ + #define MXC_S_UART_CTRL_PARMD_1 (MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */ + #define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */ + #define MXC_S_UART_CTRL_PARMD_0 (MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */ + + #define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */ + #define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ + + #define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */ + #define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ + + #define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */ + #define MXC_F_UART_CTRL_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */ + #define MXC_V_UART_CTRL_BITACC_FRAME ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */ + #define MXC_S_UART_CTRL_BITACC_FRAME (MXC_V_UART_CTRL_BITACC_FRAME << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */ + #define MXC_V_UART_CTRL_BITACC_BIT ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */ + #define MXC_S_UART_CTRL_BITACC_BIT (MXC_V_UART_CTRL_BITACC_BIT << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */ + + #define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */ + #define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ + #define MXC_V_UART_CTRL_CHAR_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */ + #define MXC_S_UART_CTRL_CHAR_SIZE_5 (MXC_V_UART_CTRL_CHAR_SIZE_5 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */ + #define MXC_V_UART_CTRL_CHAR_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */ + #define MXC_S_UART_CTRL_CHAR_SIZE_6 (MXC_V_UART_CTRL_CHAR_SIZE_6 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */ + #define MXC_V_UART_CTRL_CHAR_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */ + #define MXC_S_UART_CTRL_CHAR_SIZE_7 (MXC_V_UART_CTRL_CHAR_SIZE_7 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */ + #define MXC_V_UART_CTRL_CHAR_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */ + #define MXC_S_UART_CTRL_CHAR_SIZE_8 (MXC_V_UART_CTRL_CHAR_SIZE_8 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */ + + #define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */ + #define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ + #define MXC_V_UART_CTRL_STOPBITS_1 ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */ + #define MXC_S_UART_CTRL_STOPBITS_1 (MXC_V_UART_CTRL_STOPBITS_1 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */ + #define MXC_V_UART_CTRL_STOPBITS_1_5 ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */ + #define MXC_S_UART_CTRL_STOPBITS_1_5 (MXC_V_UART_CTRL_STOPBITS_1_5 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */ + + #define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */ + #define MXC_F_UART_CTRL_FLOW_CTRL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */ + #define MXC_V_UART_CTRL_FLOW_CTRL_EN ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */ + #define MXC_S_UART_CTRL_FLOW_CTRL_EN (MXC_V_UART_CTRL_FLOW_CTRL_EN << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */ + #define MXC_V_UART_CTRL_FLOW_CTRL_DIS ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */ + #define MXC_S_UART_CTRL_FLOW_CTRL_DIS (MXC_V_UART_CTRL_FLOW_CTRL_DIS << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */ + + #define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */ + #define MXC_F_UART_CTRL_FLOW_POL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */ + #define MXC_V_UART_CTRL_FLOW_POL_0 ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */ + #define MXC_S_UART_CTRL_FLOW_POL_0 (MXC_V_UART_CTRL_FLOW_POL_0 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */ + #define MXC_V_UART_CTRL_FLOW_POL_1 ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */ + #define MXC_S_UART_CTRL_FLOW_POL_1 (MXC_V_UART_CTRL_FLOW_POL_1 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */ + + #define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */ + #define MXC_F_UART_CTRL_NULL_MODEM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM Mask */ + #define MXC_V_UART_CTRL_NULL_MODEM_DIS ((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */ + #define MXC_S_UART_CTRL_NULL_MODEM_DIS (MXC_V_UART_CTRL_NULL_MODEM_DIS << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting */ + #define MXC_V_UART_CTRL_NULL_MODEM_EN ((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */ + #define MXC_S_UART_CTRL_NULL_MODEM_EN (MXC_V_UART_CTRL_NULL_MODEM_EN << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */ + + #define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */ + #define MXC_F_UART_CTRL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask */ + #define MXC_V_UART_CTRL_BREAK_DIS ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value */ + #define MXC_S_UART_CTRL_BREAK_DIS (MXC_V_UART_CTRL_BREAK_DIS << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */ + #define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */ + #define MXC_S_UART_CTRL_BREAK_EN (MXC_V_UART_CTRL_BREAK_EN << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */ + + #define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */ + #define MXC_F_UART_CTRL_CLKSEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ + #define MXC_V_UART_CTRL_CLKSEL_SYSTEM ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */ + #define MXC_S_UART_CTRL_CLKSEL_SYSTEM (MXC_V_UART_CTRL_CLKSEL_SYSTEM << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */ + #define MXC_V_UART_CTRL_CLKSEL_ALTERNATE ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */ + #define MXC_S_UART_CTRL_CLKSEL_ALTERNATE (MXC_V_UART_CTRL_CLKSEL_ALTERNATE << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */ + + #define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */ + #define MXC_F_UART_CTRL_RX_TO ((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */ + +/**@} end of group UART_CTRL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_THRESH_CTRL UART_THRESH_CTRL + * @brief Threshold Control register. + * @{ + */ + #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */ + #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< THRESH_CTRL_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */ + #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< THRESH_CTRL_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */ + #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< THRESH_CTRL_RTS_FIFO_THRESH Mask */ + +/**@} end of group UART_THRESH_CTRL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_STATUS UART_STATUS + * @brief Status Register. + * @{ + */ + #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ + #define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ + + #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ + #define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ + + #define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */ + #define MXC_F_UART_STATUS_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */ + + #define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */ + #define MXC_F_UART_STATUS_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */ + + #define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */ + #define MXC_F_UART_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ + + #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ + #define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + + #define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */ + #define MXC_F_UART_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ + + #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ + #define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + + #define MXC_F_UART_STATUS_RX_FIFO_CNT_POS 8 /**< STATUS_RX_FIFO_CNT Position */ + #define MXC_F_UART_STATUS_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */ + + #define MXC_F_UART_STATUS_TX_FIFO_CNT_POS 16 /**< STATUS_TX_FIFO_CNT Position */ + #define MXC_F_UART_STATUS_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */ + + #define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */ + #define MXC_F_UART_STATUS_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */ + +/**@} end of group UART_STATUS_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INT_EN UART_INT_EN + * @brief Interrupt Enable Register. + * @{ + */ + #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */ + #define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */ + + #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */ + #define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */ + + #define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */ + #define MXC_F_UART_INT_EN_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE Mask */ + + #define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */ + #define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */ + + #define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS 4 /**< INT_EN_RX_FIFO_THRESH Position */ + #define MXC_F_UART_INT_EN_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */ + #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */ + + #define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS 6 /**< INT_EN_TX_FIFO_THRESH Position */ + #define MXC_F_UART_INT_EN_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< INT_EN_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */ + #define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */ + + #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */ + #define MXC_F_UART_INT_EN_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT Mask */ + + #define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */ + #define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */ + +/**@} end of group UART_INT_EN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INT_FL UART_INT_FL + * @brief Interrupt Status Flags. + * @{ + */ + #define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS 0 /**< INT_FL_RX_FRAME_ERROR Position */ + #define MXC_F_UART_INT_FL_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */ + + #define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS 1 /**< INT_FL_RX_PARITY_ERROR Position */ + #define MXC_F_UART_INT_FL_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */ + + #define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */ + #define MXC_F_UART_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */ + + #define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */ + #define MXC_F_UART_INT_FL_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */ + + #define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS 4 /**< INT_FL_RX_FIFO_THRESH Position */ + #define MXC_F_UART_INT_FL_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */ + + #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */ + #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */ + + #define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS 6 /**< INT_FL_TX_FIFO_THRESH Position */ + #define MXC_F_UART_INT_FL_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< INT_FL_TX_FIFO_THRESH Mask */ + + #define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */ + #define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */ + + #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */ + #define MXC_F_UART_INT_FL_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT Mask */ + + #define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */ + #define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */ + +/**@} end of group UART_INT_FL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_BAUD0 UART_BAUD0 + * @brief Baud rate register. Integer portion. + * @{ + */ + #define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */ + #define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */ + + #define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */ + #define MXC_F_UART_BAUD0_FACTOR ((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */ + #define MXC_V_UART_BAUD0_FACTOR_128 ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */ + #define MXC_S_UART_BAUD0_FACTOR_128 (MXC_V_UART_BAUD0_FACTOR_128 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */ + #define MXC_V_UART_BAUD0_FACTOR_64 ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */ + #define MXC_S_UART_BAUD0_FACTOR_64 (MXC_V_UART_BAUD0_FACTOR_64 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */ + #define MXC_V_UART_BAUD0_FACTOR_32 ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */ + #define MXC_S_UART_BAUD0_FACTOR_32 (MXC_V_UART_BAUD0_FACTOR_32 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */ + #define MXC_V_UART_BAUD0_FACTOR_16 ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */ + #define MXC_S_UART_BAUD0_FACTOR_16 (MXC_V_UART_BAUD0_FACTOR_16 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */ + +/**@} end of group UART_BAUD0_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_BAUD1 UART_BAUD1 + * @brief Baud rate register. Decimal Setting. + * @{ + */ + #define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */ + #define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */ + +/**@} end of group UART_BAUD1_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_FIFO UART_FIFO + * @brief FIFO Data buffer. + * @{ + */ + #define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */ + #define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */ + +/**@} end of group UART_FIFO_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_DMA UART_DMA + * @brief DMA Configuration. + * @{ + */ + #define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */ + #define MXC_F_UART_DMA_TDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */ + #define MXC_V_UART_DMA_TDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */ + #define MXC_S_UART_DMA_TDMA_EN_DIS (MXC_V_UART_DMA_TDMA_EN_DIS << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */ + #define MXC_V_UART_DMA_TDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value */ + #define MXC_S_UART_DMA_TDMA_EN_EN (MXC_V_UART_DMA_TDMA_EN_EN << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */ + + #define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */ + #define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */ + #define MXC_V_UART_DMA_RXDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */ + #define MXC_S_UART_DMA_RXDMA_EN_DIS (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */ + #define MXC_V_UART_DMA_RXDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */ + #define MXC_S_UART_DMA_RXDMA_EN_EN (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */ + + #define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */ + #define MXC_F_UART_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */ + + #define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */ + #define MXC_F_UART_DMA_RXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */ + +/**@} end of group UART_DMA_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_TX_FIFO UART_TX_FIFO + * @brief Transmit FIFO Status register. + * @{ + */ + #define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */ + #define MXC_F_UART_TX_FIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */ + +/**@} end of group UART_TX_FIFO_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _UART_REGS_H_ */ diff --git a/Project/SDK/Device/Include/wdt_regs.h b/Project/SDK/Device/Include/wdt_regs.h new file mode 100644 index 0000000..e993307 --- /dev/null +++ b/Project/SDK/Device/Include/wdt_regs.h @@ -0,0 +1,236 @@ +/** + * @file wdt_regs.h + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + *************************************************************************** */ + +#ifndef _WDT_REGS_H_ +#define _WDT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup wdt + * @defgroup wdt_registers WDT_Registers + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @details Watchdog Timer 0 + */ + +/** + * @ingroup wdt_registers + * Structure type to access the WDT Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: WDT CTRL Register */ + __O uint32_t rst; /**< \b 0x04: WDT RST Register */ +} mxc_wdt_regs_t; + +/* Register offsets for module WDT */ +/** + * @ingroup wdt_registers + * @defgroup WDT_Register_Offsets Register Offsets + * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. + * @{ + */ + #define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ + #define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ +/**@} end of group wdt_registers */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CTRL WDT_CTRL + * @brief Watchdog Timer Control Register. + * @{ + */ + #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */ + #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */ + #define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */ + #define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */ + + #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */ + #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */ + #define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */ + #define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */ + + #define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */ + #define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */ + #define MXC_V_WDT_CTRL_WDT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */ + #define MXC_S_WDT_CTRL_WDT_EN_DIS (MXC_V_WDT_CTRL_WDT_EN_DIS << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */ + #define MXC_V_WDT_CTRL_WDT_EN_EN ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value */ + #define MXC_S_WDT_CTRL_WDT_EN_EN (MXC_V_WDT_CTRL_WDT_EN_EN << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */ + + #define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */ + #define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */ + #define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE ((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */ + #define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE (MXC_V_WDT_CTRL_INT_FLAG_INACTIVE << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting */ + #define MXC_V_WDT_CTRL_INT_FLAG_PENDING ((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */ + #define MXC_S_WDT_CTRL_INT_FLAG_PENDING (MXC_V_WDT_CTRL_INT_FLAG_PENDING << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */ + + #define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */ + #define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ + #define MXC_V_WDT_CTRL_INT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */ + #define MXC_S_WDT_CTRL_INT_EN_DIS (MXC_V_WDT_CTRL_INT_EN_DIS << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */ + #define MXC_V_WDT_CTRL_INT_EN_EN ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value */ + #define MXC_S_WDT_CTRL_INT_EN_EN (MXC_V_WDT_CTRL_INT_EN_EN << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */ + + #define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */ + #define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */ + #define MXC_V_WDT_CTRL_RST_EN_DIS ((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */ + #define MXC_S_WDT_CTRL_RST_EN_DIS (MXC_V_WDT_CTRL_RST_EN_DIS << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */ + #define MXC_V_WDT_CTRL_RST_EN_EN ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value */ + #define MXC_S_WDT_CTRL_RST_EN_EN (MXC_V_WDT_CTRL_RST_EN_EN << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */ + + #define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */ + #define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */ + #define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT ((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */ + #define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */ + #define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED ((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */ + #define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED (MXC_V_WDT_CTRL_RST_FLAG_OCCURRED << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting */ + +/**@} end of group WDT_CTRL_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_RST WDT_RST + * @brief Watchdog Timer Reset Register. + * @{ + */ + #define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */ + #define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */ + #define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */ + #define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */ + #define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */ + #define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */ + +/**@} end of group WDT_RST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_REGS_H_ */ diff --git a/Project/SDK/Device/system_max32660.c b/Project/SDK/Device/system_max32660.c new file mode 100644 index 0000000..1d404cc --- /dev/null +++ b/Project/SDK/Device/system_max32660.c @@ -0,0 +1,167 @@ +/** + * @file system_max32660.c + * @brief System-level initialization implementation file + */ + +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + ******************************************************************************/ + +#include +#include +#include +#include "max32660.h" +#include "gcr_regs.h" +#include "pwrseq_regs.h" +#include "tmr_regs.h" +#include "wdt_regs.h" +#include "mxc_sys.h" + +extern void (* const __isr_vector[])(void); +uint32_t SystemCoreClock = HIRC96_FREQ; + +__weak void SystemCoreClockUpdate(void) +{ + uint32_t base_freq, div, clk_src,ovr; + + // Get the clock source and frequency + clk_src = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL); + + if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_HFXIN) { + base_freq = HFX_FREQ; + } else { + if (clk_src == MXC_S_GCR_CLKCN_CLKSEL_NANORING) { + base_freq = NANORING_FREQ; + } else { + ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR); + if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V) { + base_freq = HIRC96_FREQ/4; + } else { + if (ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V) { + base_freq = HIRC96_FREQ/2; + } else { + base_freq = HIRC96_FREQ; + } + } + } + } + + // Get the clock divider + div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS; + + SystemCoreClock = base_freq >> div; +} + +/* This function is called before C runtime initialization and can be + * implemented by the application for early initializations. If a value other + * than '0' is returned, the C runtime initialization will be skipped. + * + * You may over-ride this function in your program by defining a custom + * PreInit(), but care should be taken to reproduce the initilization steps + * or a non-functional system may result. + */ +__weak int PreInit(void) +{ + /* Do nothing */ + return 0; +} + +/* This function can be implemented by the application to initialize the board */ +__weak int Board_Init(void) +{ + /* Do nothing */ + return 0; +} + +/* This function is called just before control is transferred to main(). + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ +__weak void SystemInit(void) +{ + /* Configure the interrupt controller to use the application vector table in */ + /* the application space */ + /* IAR & Keil must set vector table after all memory initialization. */ + SCB->VTOR = (unsigned long)__isr_vector; + + MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */ + + /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ + /* Grant full access, per "Table B3-24 CPACR bit assignments". */ + /* DDI0403D "ARMv7-M Architecture Reference Manual" */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; + __DSB(); + __ISB(); + + /* Switch system clock to HIRC */ + SYS_Clock_Select(SYS_CLOCK_HIRC, MXC_TMR0); + + /* Disable clocks to peripherals by default to reduce power */ + SYS_ClockDisable(SYS_PERIPH_CLOCK_DMA); + SYS_ClockDisable(SYS_PERIPH_CLOCK_SPI17Y); + SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS); + SYS_ClockDisable(SYS_PERIPH_CLOCK_UART0); + SYS_ClockDisable(SYS_PERIPH_CLOCK_UART1); + SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C0); + SYS_ClockDisable(SYS_PERIPH_CLOCK_T0); + SYS_ClockDisable(SYS_PERIPH_CLOCK_T1); + SYS_ClockDisable(SYS_PERIPH_CLOCK_T2); + SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C1); + + Board_Init(); +} + +#if defined ( __CC_ARM ) +/* Global variable initialization does not occur until post scatterload in Keil tools.*/ + +/* External function called after our post scatterload function implementation. */ +extern void $Super$$__main_after_scatterload(void); + +/** + * @brief Initialization function for SystemCoreClock and Board_Init. + * @details $Sub$$__main_after_scatterload is called during system startup in the Keil + * toolset. Global variable and static variable space must be set up by the compiler + * prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init + * require global memory for variable storage and are called from this function in + * the Keil tool chain. + */ +void $Sub$$__main_after_scatterload(void) +{ + SystemInit(); + $Super$$__main_after_scatterload(); +} +#endif /* __CC_ARM */ diff --git a/Project/SDK/Driver/Include/dma.h b/Project/SDK/Driver/Include/dma.h new file mode 100644 index 0000000..c9f260c --- /dev/null +++ b/Project/SDK/Driver/Include/dma.h @@ -0,0 +1,317 @@ +/** + * @file + * @brief Direct Memory Access (DMA) driver function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-07-01 11:06:19 -0500 (Mon, 01 Jul 2019) $ + * $Revision: 44383 $ + * + *************************************************************************** */ + +#ifndef _DMA_H_ +#define _DMA_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup dma Direct Memory Access (DMA) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +/** + * Enumeration for the DMA Channel's priority level. + */ +typedef enum { + DMA_PRIO_HIGH = MXC_S_DMA_CFG_PRI_HIGH, /**< High Priority */ + DMA_PRIO_MEDHIGH = MXC_S_DMA_CFG_PRI_MEDHIGH, /**< Medium High Priority */ + DMA_PRIO_MEDLOW = MXC_S_DMA_CFG_PRI_MEDLOW, /**< Medium Low Priority */ + DMA_PRIO_LOW = MXC_S_DMA_CFG_PRI_LOW, /**< Low Priority */ +} dma_priority_t; + +/** @brief DMA request select */ +typedef enum { + DMA_REQSEL_MEMTOMEM = MXC_S_DMA_CFG_REQSEL_MEMTOMEM, /**< Memory to Memory DMA Request Selection */ + DMA_REQSEL_SPI0RX = MXC_S_DMA_CFG_REQSEL_SPI0RX, /**< SPI0 Receive DMA Request Selection */ + DMA_REQSEL_SPI1RX = MXC_S_DMA_CFG_REQSEL_SPI1RX, /**< SPI1 Receive DMA Request Selection */ + DMA_REQSEL_UART0RX = MXC_S_DMA_CFG_REQSEL_UART0RX, /**< UART0 Receive DMA Request Selection */ + DMA_REQSEL_UART1RX = MXC_S_DMA_CFG_REQSEL_UART1RX, /**< UART1 Receive DMA Request Selection */ + DMA_REQSEL_I2C0RX = MXC_S_DMA_CFG_REQSEL_I2C0RX, /**< I2C0 Receive DMA Request Selection */ + DMA_REQSEL_I2C1RX = MXC_S_DMA_CFG_REQSEL_I2C1RX, /**< I2C1 Receive DMA Request Selection */ + DMA_REQSEL_SPI0TX = MXC_S_DMA_CFG_REQSEL_SPI0TX, /**< SPI0 Transmit DMA Request Selection */ + DMA_REQSEL_SPI1TX = MXC_S_DMA_CFG_REQSEL_SPI1TX, /**< SPI1 Transmit DMA Request Selection */ + DMA_REQSEL_UART0TX = MXC_S_DMA_CFG_REQSEL_UART0TX, /**< UART0 Transmit DMA Request Selection */ + DMA_REQSEL_UART1TX = MXC_S_DMA_CFG_REQSEL_UART1TX, /**< UART1 Transmit DMA Request Selection */ + DMA_REQSEL_I2C0TX = MXC_S_DMA_CFG_REQSEL_I2C0TX, /**< I2C0 Transmit DMA Request Selection */ + DMA_REQSEL_I2C1TX = MXC_S_DMA_CFG_REQSEL_I2C1TX, /**< I2C1 Transmit DMA Request Selection */ +} dma_reqsel_t; + +/** @brief Enumeration for the DMA prescaler */ +typedef enum { + DMA_PRESCALE_DISABLE = MXC_S_DMA_CFG_PSSEL_DIS, /**< Prescaler disabled */ + DMA_PRESCALE_DIV256 = MXC_S_DMA_CFG_PSSEL_DIV256, /**< Divide by 256 */ + DMA_PRESCALE_DIV64K = MXC_S_DMA_CFG_PSSEL_DIV64K, /**< Divide by 65,536 */ + DMA_PRESCALE_DIV16M = MXC_S_DMA_CFG_PSSEL_DIV16M, /**< Divide by 16,777,216 */ +} dma_prescale_t; + +/** @brief Enumeration for the DMA timeout value */ +typedef enum { + DMA_TIMEOUT_4_CLK = MXC_S_DMA_CFG_TOSEL_TO4, /**< DMA timeout of 4 clocks */ + DMA_TIMEOUT_8_CLK = MXC_S_DMA_CFG_TOSEL_TO8, /**< DMA timeout of 8 clocks */ + DMA_TIMEOUT_16_CLK = MXC_S_DMA_CFG_TOSEL_TO16, /**< DMA timeout of 16 clocks */ + DMA_TIMEOUT_32_CLK = MXC_S_DMA_CFG_TOSEL_TO32, /**< DMA timeout of 32 clocks */ + DMA_TIMEOUT_64_CLK = MXC_S_DMA_CFG_TOSEL_TO64, /**< DMA timeout of 64 clocks */ + DMA_TIMEOUT_128_CLK = MXC_S_DMA_CFG_TOSEL_TO128, /**< DMA timeout of 128 clocks */ + DMA_TIMEOUT_256_CLK = MXC_S_DMA_CFG_TOSEL_TO256, /**< DMA timeout of 256 clocks */ + DMA_TIMEOUT_512_CLK = MXC_S_DMA_CFG_TOSEL_TO512, /**< DMA timeout of 512 clocks */ +} dma_timeout_t; + +/** @brief DMA transfer data width */ +typedef enum { + /* Using the '_V_' define instead of the '_S_' since these same values will be used to + specify the DSTWD also. The API functions will shift the value the correct amount + prior to writing the cfg register. */ + DMA_WIDTH_BYTE = MXC_V_DMA_CFG_SRCWD_BYTE, /**< DMA transfer in bytes */ + DMA_WIDTH_HALFWORD = MXC_V_DMA_CFG_SRCWD_HALFWORD, /**< DMA transfer in 16-bit half-words */ + DMA_WIDTH_WORD = MXC_V_DMA_CFG_SRCWD_WORD, /**< DMA transfer in 32-bit words */ +} dma_width_t; + +/** @brief Convenience defines for options */ +#define DMA_FALSE 0 /**< Define for passing 0 to DMA functions */ +#define DMA_TRUE 1 /**< Define for passing 1 to DMA functions */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize DMA resources + * @details This initialization is required before using the DMA driver functions. + * @return #E_NO_ERROR if successful + */ +int DMA_Init(void); + + +/** + * @brief Request DMA channel + * @details Returns a handle to the first free DMA channel, which can be used via API calls + * or direct access to channel registers using the DMA_GetCHRegs(int ch) function. + * @return Non-negative channel handle (inclusive of zero). + * @return #E_NONE_AVAIL All channels in use. + * @return #E_BAD_STATE DMA is not initialized, call DMA_Init() first. + * @return #E_BUSY DMA is currently busy (locked), try again later. + */ +int DMA_AcquireChannel(void); + +/** + * @brief Release DMA channel + * @details Stops any DMA operation on the channel and returns it to the pool of free channels. + * + * @param ch channel handle to release + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int DMA_ReleaseChannel(int ch); + +/** + * @brief Configure the DMA channel + * @details Configures the channel, which was previously requested by DMA_Getchannel() + * + * @param ch The channel to configure + * @param prio The channel's priority + * @param reqsel Select the DMA request line + * @param reqwait_en The enable delay before request + * @param tosel The transfer timer timeout select + * @param pssel The transfer timer prescale select + * @param srcwd The size of the read transactions + * @param srcinc_en Enable auto-increment source pointer + * @param dstwd The size of write transactions + * @param dstinc_en Enable auto-increment destination pointer + * @param burst_size The number of bytes transferred in one transaction + * @param chdis_inten The channel disable interrupt enable + * @param ctz_inten The count-to-zero interrupt enable + * + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_ConfigChannel(int ch, + dma_priority_t prio, + dma_reqsel_t reqsel, unsigned int reqwait_en, + dma_timeout_t tosel, dma_prescale_t pssel, + dma_width_t srcwd, unsigned int srcinc_en, + dma_width_t dstwd, unsigned int dstinc_en, + unsigned int burst_size, unsigned int chdis_inten, + unsigned int ctz_inten); + +/** + * @brief Set channel source, destination, and count for transfer + * @param ch channel handle + * @param src_addr source address (*) + * @param dst_addr destination address (*) + * @param count number of bytes to transfer + * @details This function is used to set the source and destination addresses and the number + * of bytes to transfer using the channel, @p ch. + * @note Unless the channel request select is #DMA_REQSEL_MEMTOMEM, + * either src_addr or dst_addr will be ignored by the DMA engine. + * In these cases, the address is a don't-care. See the User's + * Guide for more information. + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_SetSrcDstCnt(int ch, + void *src_addr, + void *dst_addr, + unsigned int count); + +/** + * @brief Set channel reload values + * @param ch channel handle + * @param src_addr_reload source address + * @param dst_addr_reload destination address + * @param count_reload number of bytes to transfer + * @details This function will set the values which will be loaded after the + * channel count register reaches zero. After enabling, call with + * count_reload set to zero to disable reload. + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_SetReload(int ch, + void *src_addr_reload, + void *dst_addr_reload, + unsigned int count_reload); + +/** + * @brief Set channel interrupt callback + * @param ch channel handle + * @param callback Pointer to a function to call when the channel + * interrupt flag is set and interrupts are enabled or + * when DMA is shutdown by the driver. + * @details Configures the channel interrupt callback. The @p callback + * function is called for two conditions: + * -# When the channel's interrupt flag is set and DMA interrupts + * are enabled. + * -# If the driver calls the DMA_Shutdown() function. The + * callback function prototype is: + * @code + * void callback_fn(int ch, int reason); + * @endcode + * @p ch indicates the channel that generated the callback, @p + * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN + * if the DMA is being shutdown. + * + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_SetCallback(int ch, void (*callback)(int, int)); + +/** + * @brief Enable channel interrupt + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_EnableInterrupt(int ch); + +/** + * @brief Disable channel interrupt + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_DisableInterrupt(int ch); + +/** + * @brief Read channel interrupt flags + * @param ch channel handle + * @param fl flags to get + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_GetFlags(int ch, unsigned int *fl); + +/** + * @brief Clear channel interrupt flags + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_ClearFlags(int ch); + +/** + * @brief Start transfer + * @param ch channel handle + * @details Start the DMA channel transfer, assumes that DMA_SetSrcDstCnt() has been called beforehand. + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_Start(int ch); + +/** + * @brief Stop DMA transfer, irrespective of status (complete or in-progress) + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle + * @return #E_NO_ERROR otherwise + */ +int DMA_Stop(int ch); + +/** + * @brief Get a pointer to the DMA channel registers + * @param ch channel handle + * @details If direct access to DMA channel registers is required, this + * function can be used on a channel handle returned by DMA_AcquireChannel(). + * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise + */ +mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch); + +/** + * @brief Interrupt handler function + * @param ch channel handle + * @details Call this function as the ISR for each DMA channel under driver control. + * Interrupt flags for channel ch will be automatically cleared before return. + * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise + */ +void DMA_Handler(int ch); + +/**@} end of group dma */ +#ifdef __cplusplus +} +#endif + +#endif /* _DMA_H_ */ diff --git a/Project/SDK/Driver/Include/flc.h b/Project/SDK/Driver/Include/flc.h new file mode 100644 index 0000000..5859c66 --- /dev/null +++ b/Project/SDK/Driver/Include/flc.h @@ -0,0 +1,200 @@ +/** + * @file + * @brief Flash Controler driver. + * @details This driver can be used to operate on the embedded flash memory. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $ + * $Revision: 43696 $ + * + *************************************************************************** */ + +#ifndef _FLC_H_ +#define _FLC_H_ + +/* **** Includes **** */ +#include "flc_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup flc Flash Controller + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/// Bit mask that can be used to find the starting address of a page in flash +#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) + +/// Calculate the address of a page in flash from the page number +#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE)) + +/***** Function Prototypes *****/ + +/** + * @brief Initializes the flash controller for erase/write operations + * @param sys_cfg Reserved for future use. Use NULL as this parameter's value. + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int FLC_Init(const sys_cfg_flc_t *sys_cfg); + +/** + * @brief Checks if Flash controller is busy. + * @details Reading or executing from flash is not possible if flash is busy + * with an erase or write operation. + * @return If non-zero, flash operation is in progress + */ +int FLC_Busy(void); + +/** + * @brief Erases the entire flash array. + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int FLC_MassErase(void); + +/** + * @brief Erases the page of flash at the specified address. + * @param address Any address within the page to erase. + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int FLC_PageErase(uint32_t address); + +/** + * @brief Page erase from start to end address. + * @note All data within the selected pages will be erased. + * @param start Any address within the first page to erase. + * @param end Any address within the last page to erase. + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int FLC_Erase(uint32_t start, uint32_t end); + +/** + * @brief Erase from start to end address. Restoring any flash page contents outside the given range. + * @param start Starting address to erase, inclusive. + * @param end Ending address to erase, exclusive. + * @param buffer Data buffer to restore data in beginning and ending pages. + * @param length Length of given buffer. + * + * @note Buffer should be appropriate size to store all of the data remaining in the + * first and last pages. length should be greater than or equal to + * (start % MXC_FLASH_PAGE_SIZE) and ((MXC_FLASH_PAGE_SIZE - (end % MXC_FLASH_PAGE_SIZE)) % MXC_FLASH_PAGE_SIZE). + * + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int FLC_BufferErase(uint32_t start, uint32_t end, uint8_t *buffer, unsigned length); + +/** + * @brief Writes the specified 32-bit value to flash. + * @param address 32-bit aligned address in flash to write. + * @param data value to be written to flash. + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int FLC_Write32(uint32_t address, uint32_t data); + +/** + * @brief Writes the specified 128-bits of data to flash. + * @param address 128-bit aligned address in flash to write. + * @param data pointer to data to be written to flash. + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int FLC_Write128(uint32_t address, uint32_t *data); + +/** + * @brief Writes data to flash. + * @param address Address in flash to start writing from. + * @param length Number of bytes to be written. + * @param buffer Pointer to data to be written to flash. + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int FLC_Write(uint32_t address, uint32_t length, uint8_t *buffer); + +/** + * @brief Enable flash interrupts + * @param mask Interrupts to enable + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int FLC_EnableInt(uint32_t mask); + +/** + * @brief Disable flash interrupts + * @param mask Interrupts to disable + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int FLC_DisableInt(uint32_t mask); + +/** + * @brief Retrieve flash interrupt flags + * @return Mask of active flags. + */ +int FLC_GetFlags(void); + +/** + * @brief Clear flash interrupt flags + * @note Provide the bit position to clear, even if the flag is write-0-to-clear + * @param mask Mask of flags to clear + * @return #E_NO_ERROR if successful, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int FLC_ClearFlags(uint32_t mask); + +/** + * @brief Unlock info block + * + * @return #E_NO_ERROR If function is successful. + */ +int FLC_UnlockInfoBlock(void); + +/** + * @brief Lock info block + * + * @return #E_NO_ERROR If function is successful. + */ +int FLC_LockInfoBlock(void); +/**@} end of group flc */ + +#ifdef __cplusplus +} +#endif + +#endif /* _FLC_H_ */ diff --git a/Project/SDK/Driver/Include/gpio.h b/Project/SDK/Driver/Include/gpio.h new file mode 100644 index 0000000..23b9a08 --- /dev/null +++ b/Project/SDK/Driver/Include/gpio.h @@ -0,0 +1,295 @@ +/** + * @file gpio.h + * @brief General-Purpose Input/Output (GPIO) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _GPIO_H_ +#define _GPIO_H_ + +/* **** Includes **** */ +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup gpio General-Purpose Input/Output (GPIO) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ +/** + * @defgroup gpio_port_pin Port and Pin Definitions + * @ingroup gpio + * @{ + * @defgroup gpio_port Port Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define PORT_0 ((uint32_t)(0UL)) /**< Port 0 Define*/ +#define PORT_1 ((uint32_t)(1UL)) /**< Port 1 Define*/ +#define PORT_2 ((uint32_t)(2UL)) /**< Port 2 Define*/ +#define PORT_3 ((uint32_t)(3UL)) /**< Port 3 Define*/ +#define PORT_4 ((uint32_t)(4UL)) /**< Port 4 Define*/ +/**@} end of gpio_port group*/ +/** + * @defgroup gpio_pin Pin Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */ +#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */ +#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */ +#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */ +#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */ +#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */ +#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */ +#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */ +#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */ +#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */ +#define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */ +#define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */ +#define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */ +#define PIN_13 ((uint32_t)(1UL << 13)) /**< Pin 13 Define */ +#define PIN_14 ((uint32_t)(1UL << 14)) /**< Pin 14 Define */ +#define PIN_15 ((uint32_t)(1UL << 15)) /**< Pin 15 Define */ +#define PIN_16 ((uint32_t)(1UL << 16)) /**< Pin 16 Define */ +#define PIN_17 ((uint32_t)(1UL << 17)) /**< Pin 17 Define */ +#define PIN_18 ((uint32_t)(1UL << 18)) /**< Pin 18 Define */ +#define PIN_19 ((uint32_t)(1UL << 19)) /**< Pin 19 Define */ +#define PIN_20 ((uint32_t)(1UL << 20)) /**< Pin 20 Define */ +#define PIN_21 ((uint32_t)(1UL << 21)) /**< Pin 21 Define */ +#define PIN_22 ((uint32_t)(1UL << 22)) /**< Pin 22 Define */ +#define PIN_23 ((uint32_t)(1UL << 23)) /**< Pin 23 Define */ +#define PIN_24 ((uint32_t)(1UL << 24)) /**< Pin 24 Define */ +#define PIN_25 ((uint32_t)(1UL << 25)) /**< Pin 25 Define */ +#define PIN_26 ((uint32_t)(1UL << 26)) /**< Pin 26 Define */ +#define PIN_27 ((uint32_t)(1UL << 27)) /**< Pin 27 Define */ +#define PIN_28 ((uint32_t)(1UL << 28)) /**< Pin 28 Define */ +#define PIN_29 ((uint32_t)(1UL << 29)) /**< Pin 29 Define */ +#define PIN_30 ((uint32_t)(1UL << 30)) /**< Pin 30 Define */ +#define PIN_31 ((uint32_t)(1UL << 31)) /**< Pin 31 Define */ +/**@} end of gpio_pin group */ +/**@} end of gpio_port_pin group */ + +/** + * Enumeration type for the GPIO Function Type + */ +typedef enum { + GPIO_FUNC_IN, /**< GPIO Input */ + GPIO_FUNC_OUT, /**< GPIO Output */ + GPIO_FUNC_ALT1, /**< Alternate Function Selection */ + GPIO_FUNC_ALT2, /**< Alternate Function Selection */ + GPIO_FUNC_ALT3, /**< Alternate Function Selection */ + GPIO_FUNC_ALT4, /**< Alternate Function Selection */ +} gpio_func_t; + +/** + * Enumeration type for the type of GPIO pad on a given pin. + */ +typedef enum { + GPIO_PAD_NONE, /**< No pull-up or pull-down */ + GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */ + GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */ +} gpio_pad_t; + +/** + * Structure type for configuring a GPIO port. + */ +typedef struct { + uint32_t port; /**< Index of GPIO port */ + uint32_t mask; /**< Pin mask (multiple pins may be set) */ + gpio_func_t func; /**< Function type */ + gpio_pad_t pad; /**< Pad type */ +} gpio_cfg_t; + +/** + * Enumeration type for the interrupt modes. + */ +typedef enum { + GPIO_INT_LEVEL = 0, /**< Interrupt is level sensitive */ + GPIO_INT_EDGE = 1 /**< Interrupt is edge sensitive */ +} gpio_int_mode_t; + +/** + * Enumeration type for the interrupt polarity. + */ +typedef enum { + GPIO_INT_FALLING = 0, /**< Interrupt triggers on falling edge */ + GPIO_INT_HIGH = GPIO_INT_FALLING, /**< Interrupt triggers when level is high */ + GPIO_INT_RISING, /**< Interrupt triggers on rising edge */ + GPIO_INT_LOW = GPIO_INT_RISING, /**< Interrupt triggers when level is low */ + GPIO_INT_BOTH /**< Interrupt triggers on either edge */ +} gpio_int_pol_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize GPIO. + * @return #E_NO_ERROR if everything is successful. + */ +int GPIO_Init(void); + +/** + * @brief Configure GPIO pin(s). + * @param cfg Pointer to configuration structure describing the pin. + * @return #E_NO_ERROR if everything is successful. + */ +int GPIO_Config(const gpio_cfg_t *cfg); + +/** + * @brief Gets the pin(s) input state. + * @param cfg Pointer to configuration structure describing the pin. + * @return The requested pin state. + */ +uint32_t GPIO_InGet(const gpio_cfg_t *cfg); + +/** + * @brief Sets the pin(s) to a high level output. + * @param cfg Pointer to configuration structure describing the pin. + * + */ +void GPIO_OutSet(const gpio_cfg_t *cfg); + +/** + * @brief Clears the pin(s) to a low level output. + * @param cfg Pointer to configuration structure describing the pin. + * + */ +void GPIO_OutClr(const gpio_cfg_t *cfg); + +/** + * @brief Gets the pin(s) output state. + * @param cfg Pointer to configuration structure describing the pin. + * + * @return The state of the requested pin. + * + */ +uint32_t GPIO_OutGet(const gpio_cfg_t *cfg); + +/** + * @brief Write the pin(s) to a desired output level. + * @param cfg Pointer to configuration structure describing the pin. + * @param val Desired output level of the pin(s). This will be masked + * with the configuration mask. + */ +void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val); + +/** + * @brief Toggles the the pin(s) output level. + * @param cfg Pointer to configuration structure describing the pin. + * + */ +void GPIO_OutToggle(const gpio_cfg_t *cfg); + +/** + * @brief Configure GPIO interrupt(s) + * @param cfg Pointer to configuration structure describing the pin. + * @param mode Requested interrupt mode. + * @param pol Requested interrupt polarity. + * @return #E_NO_ERROR if everything is successful. + */ +int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol); + +/** + * @brief Enables the specified GPIO interrupt + * @param cfg Pointer to configuration structure describing the pin. + * + */ +void GPIO_IntEnable(const gpio_cfg_t *cfg); + +/** + * @brief Disables the specified GPIO interrupt. + * @param cfg Pointer to configuration structure describing the pin. + */ +void GPIO_IntDisable(const gpio_cfg_t *cfg); + +/** + * @brief Gets the interrupt(s) status on a GPIO pin. + * @param cfg Pointer to configuration structure describing the pin + * for which the status is being requested. + * @return The requested interrupt status. + */ +uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg); + +/** + * @brief Clears the interrupt(s) status on a GPIO pin. + * @param cfg Pointer to configuration structure describing the pin + * to clear the interrupt state of. + */ +void GPIO_IntClr(const gpio_cfg_t *cfg); + +/** + * @brief Type alias for a GPIO callback function with prototype: + * @code + void callback_fn(void *cbdata); + * @endcode + * @param cbdata A void pointer to the data type as registered when + * GPIO_RegisterCallback() was called. + */ +typedef void (*gpio_callback_fn)(void *cbdata); + +/** + * @brief Registers a callback for the interrupt on a given port and pin. + * @param cfg Pointer to configuration structure describing the pin + * @param callback A pointer to a function of type \c #gpio_callback_fn. + * @param cbdata The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs. + * + */ +void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata); + +/** + * @brief GPIO IRQ Handler. @note If a callback is registered for a given + * interrupt, the callback function will be called. + * + * @param port number of the port that generated the interrupt service routine. + * + */ +void GPIO_Handler(unsigned int port); + +/**@} end of group gpio */ + +#ifdef __cplusplus +} +#endif + +#endif /* _GPIO_H_ */ diff --git a/Project/SDK/Driver/Include/i2c.h b/Project/SDK/Driver/Include/i2c.h new file mode 100644 index 0000000..b4a4063 --- /dev/null +++ b/Project/SDK/Driver/Include/i2c.h @@ -0,0 +1,250 @@ +/** + * @file i2c.h + * @brief Inter-integrated circuit (I2C) communications interface driver. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-06-28 09:42:42 -0500 (Fri, 28 Jun 2019) $ + * $Revision: 44330 $ + * + *************************************************************************** */ + +#ifndef _I2C_H_ +#define _I2C_H_ + +#include +#include "i2c_regs.h" +#include "mxc_sys.h" + +/** + * @defgroup i2c I2C + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/// @brief I2C Speed Modes +typedef enum { + I2C_STD_MODE = 100000, //!< 100KHz Bus Speed + I2C_FAST_MODE = 400000, //!< 400KHz Bus Speed + I2C_FASTPLUS_MODE = 1000000, //!< 1MHz Bus Speed + I2C_HS_MODE = 3400000 //!< 3.4MHz Bus Speed +} i2c_speed_t; + +//State for Master +typedef enum { + I2C_STATE_READING = 0, + I2C_STATE_WRITING = 1 +} i2c_state_t; + +// @brief Enable/Disable TXFIFO Autoflush mode +typedef enum { + I2C_AUTOFLUSH_ENABLE = 0, + I2C_AUTOFLUSH_DISABLE = 1 +} i2c_autoflush_disable_t; + +// @brief I2C Transaction request. +typedef struct i2c_req i2c_req_t; +struct i2c_req { + + uint8_t addr; /**< @parblock I2C 7-bit Address left aligned, bit 7 to bit 1. + * Only supports 7-bit addressing. LSb of the given address + * will be used as the read/write bit, the @p addr will + * not be shifted. Used for both master and + * @em slave transactions. @endparblock + */ + const uint8_t *tx_data; ///< Data for mater write/slave read. + uint8_t *rx_data; ///< Data for master read/slave write. + unsigned tx_len; ///< Length of tx data. + unsigned rx_len; ///< Length of rx. + unsigned tx_num; ///< Number of tx bytes sent. + unsigned rx_num; ///< Number of rx bytes sent. + i2c_state_t state; ///< Read or Write. + + /** + * @details 0 to send a stop bit at the end of the transaction, + otherwise send a restart. Only used in master trasnactions. + */ + int restart; /**< @parblock Restart or stop bit indicator. + * @arg 0 to send a stop bit at the end of the transaction + * @arg Non-zero to send a restart at end of the transaction + * @note Only used for Master transactions. + * @endparblock + */ + i2c_autoflush_disable_t sw_autoflush_disable; ///< Enable/Disable autoflush. + + /** + * @brief Callback for asynchronous request. + * @param i2c_req_t* Pointer to the transaction request. + * @param int Error code. + */ + void (*callback)(i2c_req_t*, int); +}; + +/***** Function Prototypes *****/ + +/** + * @brief Initialize and enable I2C. + * @param i2c Pointer to I2C peripheral registers. + * @param i2cspeed desired speed (I2C mode) + * @param sys_cfg System configuration object + * @returns \c #E_NO_ERROR if everything is successful, + * @ref MXC_Error_Codes if an error occurred. + */ +int I2C_Init(mxc_i2c_regs_t * i2c, i2c_speed_t i2cspeed, const sys_cfg_i2c_t* sys_cfg); + +/** + * @brief Shutdown I2C module. + * @param i2c Pointer to the I2C registers. + * @returns #E_NO_ERROR I2C shutdown successfully, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int I2C_Shutdown(mxc_i2c_regs_t *i2c); + +/** + * @brief Master write data. Will block until transaction is complete. + * @param i2c Pointer to I2C regs. + * @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1. + * Only supports 7-bit addressing. LSb of the given address + * will be used as the read/write bit, the \p addr will + * not be shifted. Used for both master and + * @em slave transactions. @endparblock + * @param data Data to be written. + * @param len Number of bytes to Write. + * @param restart 0 to send a stop bit at the end of the transaction, + otherwise send a restart. + * @returns Bytes transacted if everything is successful, + * @ref MXC_Error_Codes if an error occurred. + */ +int I2C_MasterWrite(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* data, int len, int restart); + +/** + * @brief Master read data. Will block until transaction is complete. + * @param i2c Pointer to I2C regs. + * @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1. + * Only supports 7-bit addressing. LSb of the given address + * will be used as the read/write bit, the @p addr will + * not be shifted. Used for both master and + * @em slave transactions. @endparblock + * @param data Data to be written. + * @param len Number of bytes to Write. + * @param restart 0 to send a stop bit at the end of the transaction, + otherwise send a restart. + * @returns Bytes transacted if everything is successful, @ref MXC_Error_Codes if an error occurred. + */ +int I2C_MasterRead(mxc_i2c_regs_t *i2c, uint8_t addr, uint8_t* data, int len, int restart); + +/** + * @brief Slave read data. Will block until transaction is complete. + * @param i2c Pointer to I2C regs. + * @param addr @parblock I2C 7-bit Address left aligned, bit 7 to bit 1. + * Only supports 7-bit addressing. LSb of the given address + * will be used as the read/write bit, the @p addr will + * not be shifted. Used for both master and + * @em slave transactions. @endparblock + * @param read_data Buffer that the master will read from. + * @param read_len Number of bytes the master can read. + * @param write_data Buffer that the master will write to. + * @param write_len Number of bytes the master can write. + * @param tx_num Number of bytes transmitted by the slave. + * @param rx_num Number of bytes received by the slave. + * @param sw_autoflush_disable TX Autoflush enabled by default.Set this bit to disable autoflush manually. + * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred. + */ +int I2C_Slave(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* read_data, + int read_len, uint8_t* write_data, int write_len, int* tx_num, + int* rx_num, i2c_autoflush_disable_t sw_autoflush_disable); + +/** + * @brief Master Read and Write Asynchronous. + * @param i2c Pointer to I2C regs. + * @param req Request for an I2C transaction. + * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred. + */ +int I2C_MasterAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req); + +/** + * @brief Slave Read and Write Asynchronous. + * @param i2c Pointer to I2C regs. + * @param req Request for an I2C transaction. + * @returns #E_NO_ERROR if everything is successful, @ref MXC_Error_Codes if an error occurred. + */ +int I2C_SlaveAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req); +/** + * @brief I2C interrupt handler. + * @details This function should be called by the application from the interrupt + * handler if I2C interrupts are enabled. Alternately, this function + * can be periodically called by the application if I2C interrupts are + * disabled. + * @param i2c Base address of the I2C module. + */ +void I2C_Handler(mxc_i2c_regs_t *i2c); + +/** + * @brief Drain all of the data in the RXFIFO. + * @param i2c Pointer to I2C regs. + */ +void I2C_DrainRX(mxc_i2c_regs_t *i2c); + +/** + * @brief Drain all of the data in the TXFIFO. + * @param i2c Pointer to I2C regs. + */ +void I2C_DrainTX(mxc_i2c_regs_t *i2c); + +/** + * @brief Abort Async request based on the request you want to abort. + * @param req Pointer to I2C Transaction. + */ +int I2C_AbortAsync(i2c_req_t *req); + +/** + * @brief Enable and Set Timeout + * + * @param i2c pointer to I2C regs + * @param[in] us micro seconds to delay + * + * @return E_NO_ERROR or E_BAD_PARAM if delay is to long. + */ +int I2C_SetTimeout(mxc_i2c_regs_t *i2c, int us); + +/** + * @brief clear and disable timeout + * + * @param i2c pointer to I2C regs + */ +void I2C_ClearTimeout(mxc_i2c_regs_t *i2c); + +/**@} end of group i2c */ +#endif /* _I2C_H_ */ diff --git a/Project/SDK/Driver/Include/i2s.h b/Project/SDK/Driver/Include/i2s.h new file mode 100644 index 0000000..f7b768b --- /dev/null +++ b/Project/SDK/Driver/Include/i2s.h @@ -0,0 +1,179 @@ +/** + * @file i2s.h + * @brief I2S (Inter-Integrated Sound) driver function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + *************************************************************************** */ + +#ifndef _I2S_H_ +#define _I2S_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "dma.h" +#include "spimss_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup i2s Inter-Integrated Sound (I2S) + * @ingroup spi + * @{ + */ + +/* **** Definitions **** */ + +/** @brief I2S audio directions */ +typedef enum { + AUDIO_OUT = 1, + AUDIO_IN = 2, +} i2s_direction_t; + +/** @brief I2S Configuration Struct */ +typedef struct { + uint8_t left_justify; + uint8_t mono_audio; + i2s_direction_t audio_direction; + unsigned int sample_rate; + unsigned int start_immediately; + void *dma_src_addr; + void *dma_dst_addr; + unsigned int dma_cnt; + unsigned int dma_reload_en; +} i2s_cfg_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize I2S resources + * @param cfg I2S Configuration Struct + * @param dma_ctz_cb Optional function to be called when the DMA completes + a transfer. Set to NULL if unused. + * @param sys_cfg_i2s System configuration object + * @details This initialization is required before using the I2S driver functions. + * @return \c #E_NO_ERROR if successful + */ +int I2S_Init(const i2s_cfg_t *cfg, void (*dma_ctz_cb)(int, int), const sys_cfg_i2s_t* sys_cfg_i2s); + +/** + * @brief Release I2S + * @details De-configures the I2S protocol and stops DMA request + * @return \c #E_BAD_PARAM if DMA cannot be stopped, #E_NO_ERROR otherwise + */ +int I2S_Shutdown(void); + +/** + * @brief Mute I2S Output + * @details Sets I2S data to zero, continues sending clock and accessing DMA + * @return \c #E_NO_ERROR + */ +int I2S_Mute(void); + +/** + * @brief Unmute I2S Output + * @details Restores I2S data + * @return \c #E_NO_ERROR + */ +int I2S_Unmute(void); + +/** + * @brief Pause I2S Output + * @details Similar to mute, but stops FIFO and DMA access, clocks continue + * @return \c #E_NO_ERROR + */ +int I2S_Pause(void); + +/** + * @brief Unpause I2S Output + * @details Similar to mute, but restarts FIFO and DMA access + * @return \c #E_NO_ERROR + */ +int I2S_Unpause(void); + +/** + * @brief Stops I2S Output + * @details Similar to pause, but also halts clock + * @return \c #E_NO_ERROR + */ +int I2S_Stop(void); + +/** + * @brief Starts I2S Output + * @details Starts I2S Output, automatically called by configure if requested + * @return \c #E_NO_ERROR + */ +int I2S_Start(void); + +/** + * @brief Clears DMA Interrupt Flags + * @details Clears the DMA Interrupt flags, should be called at the end of a dma_ctz_cb + * @return \c #E_NO_ERROR + */ +int I2S_DMA_ClearFlags(void); + +/** + * @brief Set DMA Addr (Source or Dest) and bytes to transfer + * @param src_addr The address to read data from (Audio Out) + * @param dst_addr The address to write data to (Audio In) + * @param count The length of the transfer in bytes + * @details Sets the address to read/write data in memory and the length of + * the transfer. The unused addr parameter is ignored. + * @return \c #E_NO_ERROR + */ +int I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count); + +/** + * @brief Sets the DMA reload address and count + * @param src_addr The address to read data from (Audio Out) + * @param dst_addr The address to write data to (Audio In) + * @param count The length of the transfer in bytes + * @details If DMA reload is enabled, when the DMA has transfered $count bytes + * (a CTZ event occurs) the src, dst, and count registers will be + * set to these. The DMA reload flag clears after a reload occurs. + * @return \c #E_NO_ERROR + */ +int I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count); +/**@} end of group i2s */ + + +#ifdef __cplusplus +} +#endif + +#endif /* _I2S_H_ */ diff --git a/Project/SDK/Driver/Include/icc.h b/Project/SDK/Driver/Include/icc.h new file mode 100644 index 0000000..d5e4b22 --- /dev/null +++ b/Project/SDK/Driver/Include/icc.h @@ -0,0 +1,97 @@ +/** + * @file icc.h + * @brief Instruction Controller Cache(ICC) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _ICC_H_ +#define _ICC_H_ + +/* **** Includes **** */ +#include +#include "icc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup icc Internal Cache Controller (ICC) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Enumeration type for the Cache ID Register + */ +typedef enum { + ICC_CACHE_ID_RELNUM, // Identifies the RTL release version + ICC_CACHE_ID_PARTNUM, // Specifies the value of C_ID Port Number + ICC_CACHE_ID_CCHID // Specifies the value of Cache ID +} icc_cache_id_t; + +/** + * @brief Reads the data from the Cache Id Register. + * @param cid Enumeration type for Cache Id Register. + * @retval Returns the contents of Cache Id Register. + */ +int ICC_ID(icc_cache_id_t cid); + +/** + * @brief Enable the instruction cache controller. + */ +void ICC_Enable(void); + +/** + * @brief Disable the instruction cache controller. + */ +void ICC_Disable(void); + +/** + * @brief Flush the instruction cache controller. + */ +void ICC_Flush(void); + +/**@} end of group icc */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ICC_H_ */ diff --git a/Project/SDK/Driver/Include/lp.h b/Project/SDK/Driver/Include/lp.h new file mode 100644 index 0000000..7339b6f --- /dev/null +++ b/Project/SDK/Driver/Include/lp.h @@ -0,0 +1,341 @@ +/** + * @file lp.h + * @brief Low power function prototypes and data types. + */ + + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-09-26 08:48:30 -0500 (Wed, 26 Sep 2018) $ + * $Revision: 38105 $ + * + *************************************************************************** */ + +// Define to prevent redundant inclusion +#ifndef _LP_H_ +#define _LP_H_ + +/***** Includes *****/ +#include "gpio.h" +#include "pwrseq_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */ +typedef enum { + LP_OVR_0_9 = MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V, /**< Reset DMA */ + LP_OVR_1_0 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V, /**< Reset DMA */ + LP_OVR_1_1 = MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V, /**< Reset DMA */ +} lp_ovr_t; + +/** + * @brief Clears the low power wakeup flags + */ +void LP_ClearWakeStatus(void); + +/** + * @brief Enables power to RAM addresses 0x20010000-0x20017FFF. + */ +void LP_EnableSRAM3(void); + +/** + * @brief Enables power to RAM addresses 0x20008000-0x2000FFFF. + */ +void LP_EnableSRAM2(void); + +/** + * @brief Enables power to RAM addresses 0x20004000-0x20007FFF. + */ +void LP_EnableSRAM1(void); + +/** + * @brief Enables power to RAM addresses 0x20000000-0x20003FFF. + */ +void LP_EnableSRAM0(void); + +/** + * @brief Disables power to RAM addresses 0x20010000-0x20017FFF. The contents of the RAM are destroyed. + */ +void LP_DisableSRAM3(void); + +/** + * @brief Disables power to RAM addresses 0x20008000-0x2000FFFF. The contents of the RAM are destroyed. + */ +void LP_DisableSRAM2(void); + +/** + * @brief Disables power to RAM addresses 0x20004000-0x20007FFF. The contents of the RAM are destroyed. + */ +void LP_DisableSRAM1(void); + +/** + * @brief Disables power to RAM addresses 0x20000000-0x20003FFF. The contents of the RAM are destroyed. + */ +void LP_DisableSRAM0(void); + +/** + * @brief Places the instruction cache in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void LP_EnableICacheLightSleep(void); + +/** + * @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void LP_EnableSysRAM3LightSleep(void); + +/** + * @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void LP_EnableSysRAM2LightSleep(void); + +/** + * @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void LP_EnableSysRAM1LightSleep(void); + +/** + * @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in light sleep mode. Data will be unavailable for read/write operations but will be retained. + */ +void LP_EnableSysRAM0LightSleep(void); + +/** + * @brief Places the instruction cache in active mode. + */ +void LP_DisableICacheLightSleep(void); + +/** + * @brief Places addresses 0x20010000 to 0x20017FFF of the RAM in active mode. + */ +void LP_DisableSysRAM3LightSleep(void); + +/** + * @brief Places addresses 0x20008000 to 0x2000FFFF of the RAM in active mode. + */ +void LP_DisableSysRAM2LightSleep(void); + +/** + * @brief Places addresses 0x20004000 to 0x20007FFF of the RAM in active mode. + */ +void LP_DisableSysRAM1LightSleep(void); + +/** + * @brief Places addresses 0x20000000 to 0x20003FFF of the RAM in active mode. + */ +void LP_DisableSysRAM0LightSleep(void); + +/** + * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. + * Call this function multiple times to enable pins on multiple ports. This function does not configure + * the GPIO pins nor does it setup their interrupt functionality. + * @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the + * structure are used. The func and pad fields are ignored. + */ +void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins); + +/** + * @brief Disables the selected GPIO port and its selected pins as a wake up source. + * Call this function multiple times to disable pins on multiple ports. + * @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the + * structure are used. The func and pad fields are ignored. + */ +void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins); + +/** + * @brief Enables the RTC alarm to wake up the device from any low power mode. + */ +void LP_EnableRTCAlarmWakeup(void); + +/** + * @brief Disables the RTC alarm from waking up the device. + */ +void LP_DisableRTCAlarmWakeup(void); + +/** + * @brief Places the device into SLEEP mode. This function returns once any interrupt occurs. + * @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again + */ +void LP_EnterSleepMode(void); + +/** + * @brief Places the device into DEEPSLEEP mode. This function returns once an RTC or external interrupt occur. + * @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again +*/ +void LP_EnterDeepSleepMode(void); + +/** + * @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns. + * Instead, the device will restart once an RTC or external interrupt occur. + * @note LP_ClearWakeStatus should be called before this function, to avoid immediately waking up again + */ +void LP_EnterBackupMode(void); + +/** + * @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns. + * Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur. + */ +void LP_EnterShutDownMode(void); + +/** + * @brief Set operating voltage and change the clock to match the new voltage. + * @param system reset configuration struct + */ +void LP_SetOperatingVoltage(lp_ovr_t ovr); + +/** + * @brief Enables Data Retention to RAM addresses 0x20000000-0x20003FFF. + */ +void LP_EnableSRamRet0(void); + +/** + * @brief Disables Data Retention to RAM addresses 0x20000000-0x20003FFF. + */ +void LP_DisableSRamRet0(void); + +/** + * @brief Enables Data Retention to RAM addresses 0x20004000-0x20007FFF. + */ +void LP_EnableSRamRet1(void); + +/** + * @brief Disables Data Retention to RAM addresses 0x20004000-0x20007FFF. + */ +void LP_DisableSRamRet1(void); + +/** + * @brief Enables Data Retention to RAM addresses 0x20008000-0x2000FFFF. + */ +void LP_EnableSRamRet2(void); + +/** + * @brief Disables Data Retention to RAM addresses 0x20008000-0x2000FFFF. + */ +void LP_DisableSRamRet2(void); + +/** + * @brief Enables Data Retention to RAM addresses 0x20010000-0x20017FFF. + */ +void LP_EnableSRamRet3(void); + +/** + * @brief Disables Data Retention to RAM addresses 0x20010000-0x20017FFF. + */ +void LP_DisableSRamRet3(void); + +/** + * @brief Enables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time. + */ +void LP_EnableBlockDetect(void); + +/** + * @brief Disables Bypassing the hardware detection of an external supply on V CORE enables a faster wakeup time + */ +void LP_DisableBlockDetect(void); + +/** + * @brief RAM Retention Regulator Enable for BACKUP Mode + */ +void LP_EnableRamRetReg(void); + +/** + * @brief RAM Retention Regulator Disabels for BACKUP Mode + */ +void LP_DisableRamRetReg(void); + +/** + * @brief Enables Fast wake up from deepsleep + */ +void LP_EnableFastWk(void); + +/** + * @brief Disables Fast wake up from deepsleep + */ +void LP_DisableFastWk(void); + +/** + * @brief Turns on band gap during deepsleep and backup mode. + */ +void LP_EnableBandGap(void); + +/** + * @brief Turns off band gap during deepsleep and backup mode. + */ +void LP_DisableBandGap(void); + +/** + * @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode + */ +void LP_EnableVCorePORSignal(void); + +/** + * @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode + */ +void LP_DisableVCorePORSignal(void); + +/** + * @brief Enables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode + */ +void LP_EnableLDO(void); + +/** + * @brief Disables signal for power on reset when the device is int DEEPSLEEP or BACKUP mode + */ +void LP_DisableLDO(void); + +/** + * @brief Enables V CORE Supply Voltage Monitor + */ +void LP_EnableVCoreSVM(void); + +/** + * @brief Disables V CORE Supply Voltage Monitor + */ +void LP_DisableVCoreSVM(void); + + +/** + * @brief Enables VDDIO Power-On-Reset Monitor + */ +void LP_EnableVDDIOPorMonitor(void); + +/** + * @brief Disables VDDIO Power-On-Reset Monitor + */ +void LP_DisableVDDIOPorMonitor(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* _LP_H_ */ diff --git a/Project/SDK/Driver/Include/mxc_assert.h b/Project/SDK/Driver/Include/mxc_assert.h new file mode 100644 index 0000000..3e227ea --- /dev/null +++ b/Project/SDK/Driver/Include/mxc_assert.h @@ -0,0 +1,113 @@ +/** + * @file + * @brief Assertion checks for debugging. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ + * $Revision: 36818 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_ASSERT_H_ +#define _MXC_ASSERT_H_ + +/* **** Includes **** */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup mxc_assertions Assertion Checks for Debugging + * @brief Assertion checks for debugging. + * @{ + */ +/* **** Definitions **** */ +/** + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +///@cond +#ifdef MXC_ASSERT_ENABLE +/** + * Macro that checks the expression for true and generates an assertion. + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT(expr) \ +if (!(expr)) \ +{ \ + mxc_assert(#expr, __FILE__, __LINE__); \ +} +/** + * Macro that generates an assertion with the message "FAIL". + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__); +#else +#define MXC_ASSERT(expr) +#define MXC_ASSERT_FAIL() +#endif +///@endcond +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Assert an error when the given expression fails during debugging. + * @param expr String with the expression that failed the assertion. + * @param file File containing the failed assertion. + * @param line Line number for the failed assertion. + * @note This is defined as a weak function and can be overridden at the + * application layer to print the debugging information. + * @code + * printf("%s, file: %s, line %d\n", expr, file, line); + * @endcode + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +void mxc_assert(const char *expr, const char *file, int line); + +/**@} end of group MXC_Assertions*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_ASSERT_H_ */ diff --git a/Project/SDK/Driver/Include/mxc_config.h b/Project/SDK/Driver/Include/mxc_config.h new file mode 100644 index 0000000..ca85378 --- /dev/null +++ b/Project/SDK/Driver/Include/mxc_config.h @@ -0,0 +1,53 @@ +/** + * @file mxc_config.h + * @brief Top-level include file for device configuration. + */ + +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ + * $Revision: 36818 $ + * + ******************************************************************************/ + +#ifndef _MXC_CONFIG_H +#define _MXC_CONFIG_H + +#if !defined __GNUC__ +#include "RTE_Components.h" +#endif /* not __GNUC__ */ + +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_pins.h" + +#endif /* _CONFIG_H */ diff --git a/Project/SDK/Driver/Include/mxc_delay.h b/Project/SDK/Driver/Include/mxc_delay.h new file mode 100644 index 0000000..927e38b --- /dev/null +++ b/Project/SDK/Driver/Include/mxc_delay.h @@ -0,0 +1,124 @@ +/** + * @file + * @brief Asynchronous delay routines based on the SysTick Timer. +*/ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-11-05 09:52:05 -0600 (Mon, 05 Nov 2018) $ + * $Revision: 38934 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _DELAY_H_ +#define _DELAY_H_ + +/** + * @defgroup MXC_delay Delay Utility Functions + * @ingroup devicelibs + * @brief Asynchronous delay routines based on the SysTick Timer + * @{ + */ + +/***** Definitions *****/ +/** + * Macro used to specify a microsecond timing parameter in seconds. + * \code + * x = SEC(3) // 3 seconds -> x = 3,000,000 + * \endcode + */ +#define MXC_DELAY_SEC(s) (((unsigned long)s) * 1000000UL) +/** + * Macro used to specify a microsecond timing parameter in milliseconds. + * \code + * x = MSEC(3) // 3ms -> x = 3,000 + * \endcode + */ +#define MXC_DELAY_MSEC(ms) (ms * 1000UL) +/** + * Macro used to specify a microsecond timing parameter. + * \code + * x = USEC(3) // 3us -> x = 3 + * \endcode + */ +#define MXC_DELAY_USEC(us) (us) + +/***** Function Prototypes *****/ + +/** + * @brief Blocks and delays for the specified number of microseconds. + * @details Uses the SysTick to create the requested delay. If the SysTick is + * running, the current settings will be used. If the SysTick is not + * running, it will be started. + * @param us microseconds to delay + * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int mxc_delay(unsigned long us); + +/** + * @brief Starts a non-blocking delay for the specified number of + * microseconds. + * @details Uses the SysTick to time the requested delay. If the SysTick is + * running, the current settings will be used. If the SysTick is not + * running, it will be started. + * @note mxc_delay_handler() must be called from the SysTick interrupt service + * routine or at a rate greater than the SysTick overflow rate. + * @param us microseconds to delay + * @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another + * delay request. + */ +int mxc_delay_start(unsigned long us); + +/** + * @brief Returns the status of a non-blocking delay request + * @pre Start the asynchronous delay by calling mxc_delay_start(). + * @return #E_BUSY until the requested delay time has expired. + */ +int mxc_delay_check(void); + +/** + * @brief Stops an asynchronous delay previously started. + * @pre Start the asynchronous delay by calling mxc_delay_start(). + */ +void mxc_delay_stop(void); + +/** + * @brief Processes the delay interrupt. + * @details This function must be called from the SysTick IRQ or polled at a + * rate greater than the SysTick overflow rate. + */ +void mxc_delay_handler(void); + +/**@} end of group MXC_delay */ + +#endif /* _DELAY_H_ */ diff --git a/Project/SDK/Driver/Include/mxc_errors.h b/Project/SDK/Driver/Include/mxc_errors.h new file mode 100644 index 0000000..49e871a --- /dev/null +++ b/Project/SDK/Driver/Include/mxc_errors.h @@ -0,0 +1,94 @@ +/** + * @file + * @brief List of common error return codes for Maxim Integrated libraries. +*/ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ + * $Revision: 36818 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_ERRORS_H_ +#define _MXC_ERRORS_H_ + +/** + * @ingroup syscfg + * @defgroup MXC_Error_Codes Error Codes + * @brief A list of common error codes used by the API. + * @note A Negative Error Convention is used to avoid conflict with + * positive, Non-Error, returns. + * @{ + */ + +/** No Error */ +#define E_NO_ERROR 0 +/** No Error, success */ +#define E_SUCCESS 0 +/** Pointer is NULL */ +#define E_NULL_PTR -1 +/** No such device */ +#define E_NO_DEVICE -2 +/** Parameter not acceptable */ +#define E_BAD_PARAM -3 +/** Value not valid or allowed */ +#define E_INVALID -4 +/** Module not initialized */ +#define E_UNINITIALIZED -5 +/** Busy now, try again later */ +#define E_BUSY -6 +/** Operation not allowed in current state */ +#define E_BAD_STATE -7 +/** Generic error */ +#define E_UNKNOWN -8 +/** General communications error */ +#define E_COMM_ERR -9 +/** Operation timed out */ +#define E_TIME_OUT -10 +/** Expected response did not occur */ +#define E_NO_RESPONSE -11 +/** Operations resulted in unexpected overflow */ +#define E_OVERFLOW -12 +/** Operations resulted in unexpected underflow */ +#define E_UNDERFLOW -13 +/** Data or resource not available at this time */ +#define E_NONE_AVAIL -14 +/** Event was shutdown */ +#define E_SHUTDOWN -15 +/** Event was aborted */ +#define E_ABORT -16 +/** The requested operation is not supported */ +#define E_NOT_SUPPORTED -17 +/**@} end of MXC_Error_Codes group */ + +#endif /* _MXC_ERRORS_H_ */ diff --git a/Project/SDK/Driver/Include/mxc_lock.h b/Project/SDK/Driver/Include/mxc_lock.h new file mode 100644 index 0000000..5667d79 --- /dev/null +++ b/Project/SDK/Driver/Include/mxc_lock.h @@ -0,0 +1,94 @@ +/** + * @file + * @brief Exclusive access lock utility functions. +*/ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ + * $Revision: 36818 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_LOCK_H_ +#define _MXC_LOCK_H_ + +/* **** Includes **** */ +#include "mxc_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup mxc_lock_utilities Exclusive Access Locks + * @brief Lock functions to obtain and release a variable for exclusive + * access. These functions are marked interrupt safe if they are + * interrupt safe. + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Attempts to acquire the lock. + * @details This in an interrupt safe function that can be used as a mutex. + * The lock variable must remain in scope until the lock is + * released. Will not block if another thread has already acquired + * the lock. + * @param lock Pointer to variable that is used for the lock. + * @param value Value to be place in the lock. Can not be 0. + * + * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken. + */ +int mxc_get_lock(uint32_t *lock, uint32_t value); + +/** + * @brief Free the given lock. + * @param[in,out] lock Pointer to the variable used for the lock. When the lock + * is free, the value pointed to by @p lock is set to zero. + */ +void mxc_free_lock(uint32_t *lock); + +/**@} end of group mxc_lock_utilities */ + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_LOCK_H_ */ diff --git a/Project/SDK/Driver/Include/mxc_pins.h b/Project/SDK/Driver/Include/mxc_pins.h new file mode 100644 index 0000000..1c324e1 --- /dev/null +++ b/Project/SDK/Driver/Include/mxc_pins.h @@ -0,0 +1,91 @@ + /** + * @file mxc_pins.h + * @brief This file contains constant pin configurations for the peripherals. + */ + +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ + * $Revision: 36818 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_PINS_H_ +#define _MXC_PINS_H_ + +/* **** Includes **** */ +#include "gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* **** Global Variables **** */ + +// Predefined GPIO Configurations + +/***** @brief TIMER pins *****/ +extern const gpio_cfg_t gpio_cfg_tmr0; + +/***** @brief UART pins *****/ +extern const gpio_cfg_t gpio_cfg_uart0rtscts; +extern const gpio_cfg_t gpio_cfg_uart0a; +extern const gpio_cfg_t gpio_cfg_uart1rtscts; +extern const gpio_cfg_t gpio_cfg_uart1a; +extern const gpio_cfg_t gpio_cfg_uart1b; +extern const gpio_cfg_t gpio_cfg_uart1c; +extern const gpio_cfg_t gpio_cfg_uart2; + +/***** @brief I2C pins *****/ +extern const gpio_cfg_t gpio_cfg_i2c0; +extern const gpio_cfg_t gpio_cfg_i2c1; + +/***** @brief SPI/I2S pins *****/ +extern const gpio_cfg_t gpio_cfg_spi17y; // SPI0A +extern const gpio_cfg_t gpio_cfg_spimss1a; // SPI1A +extern const gpio_cfg_t gpio_cfg_spimss1b; // SPI1B +extern const gpio_cfg_t gpio_cfg_i2s1a; // same port as SPI1A +extern const gpio_cfg_t gpio_cfg_i2s1b; // same port as SPI1B + +/***** @brief SWD pins *****/ +extern const gpio_cfg_t gpio_cfg_swd; + +/***** @brief RTC pins *****/ +extern const gpio_cfg_t gpio_cfg_rtc; + +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_PINS_H_ */ + diff --git a/Project/SDK/Driver/Include/mxc_sys.h b/Project/SDK/Driver/Include/mxc_sys.h new file mode 100644 index 0000000..4394297 --- /dev/null +++ b/Project/SDK/Driver/Include/mxc_sys.h @@ -0,0 +1,450 @@ +/** + * @file + * @brief System level header file. + */ + +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-04-15 09:35:40 -0500 (Mon, 15 Apr 2019) $ + * $Revision: 42499 $ + * + ******************************************************************************/ + +#ifndef _MXC_SYS_H_ +#define _MXC_SYS_H_ + +#include "mxc_config.h" +#include "uart_regs.h" +#include "i2c_regs.h" +#include "gcr_regs.h" +#include "tmr_regs.h" +#include "icc_regs.h" +#include "spi17y_regs.h" +#include "spimss_regs.h" +#include "gpio.h" +#include "flc_regs.h" +#include "dma.h" +#include "wdt_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif +#if defined ( __CC_ARM ) /* Suppressing the warning: "enum value is out of range of int" for Keil */ +#pragma push +#pragma diag_suppress 66 +#endif /* __CC_ARM */ + +/** @brief System reset0 enumeration. Used in SYS_PeriphReset0 function */ +typedef enum { + SYS_RESET0_DMA = MXC_F_GCR_RSTR0_DMA, /**< Reset DMA */ + SYS_RESET0_WDT = MXC_F_GCR_RSTR0_WDT, /**< Reset WDT */ + SYS_RESET0_GPIO0 = MXC_F_GCR_RSTR0_GPIO0, /**< Reset GPIO0 */ + SYS_RESET0_TIMER0 = MXC_F_GCR_RSTR0_TIMER0, /**< Reset TIMER0 */ + SYS_RESET0_TIMER1 = MXC_F_GCR_RSTR0_TIMER1, /**< Reset TIMER1 */ + SYS_RESET0_TIMER2 = MXC_F_GCR_RSTR0_TIMER2, /**< Reset TIMER2 */ + SYS_RESET0_UART0 = MXC_F_GCR_RSTR0_UART0, /**< Reset UART0 */ + SYS_RESET0_UART1 = MXC_F_GCR_RSTR0_UART1, /**< Reset UART1 */ + SYS_RESET0_SPI0 = MXC_F_GCR_RSTR0_SPI0, /**< Reset SPI0 */ + SYS_RESET0_SPI1 = MXC_F_GCR_RSTR0_SPI1, /**< Reset SPI1 */ + SYS_RESET0_I2C0 = MXC_F_GCR_RSTR0_I2C0, /**< Reset I2C0 */ + SYS_RESET0_RTC = MXC_F_GCR_RSTR0_RTC, /**< Reset RTC */ + SYS_RESET0_SRST = MXC_F_GCR_RSTR0_SRST, /**< Soft reset */ + SYS_RESET0_PRST = MXC_F_GCR_RSTR0_PRST, /**< Peripheral reset */ + SYS_RESET0_SYSTEM = MXC_F_GCR_RSTR0_SYSTEM, /**< System reset */ +} sys_reset0_t; + +/** @brief System reset1 enumeration. Used in SYS_PeriphReset1 function */ +typedef enum { + SYS_RESET1_I2C1 = MXC_F_GCR_RSTR1_I2C1, /**< Reset I2C1 */ +} sys_reset1_t; + +/** @brief System clock disable enumeration. Used in SYS_ClockDisable and SYS_ClockEnable functions */ +typedef enum { + SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PERCKCN0_GPIO0D, /**< Disable MXC_F_GCR_PERCKCN0_GPIO0D clock */ + SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PERCKCN0_DMAD, /**< Disable MXC_F_GCR_PERCKCN0_DMAD clock */ + SYS_PERIPH_CLOCK_SPI17Y = MXC_F_GCR_PERCKCN0_SPI0D, /**< Disable MXC_F_GCR_PERCKCN0_SPI0D clock */ + SYS_PERIPH_CLOCK_SPIMSS = MXC_F_GCR_PERCKCN0_SPI1D, /**< Disable MXC_F_GCR_PERCKCN0_SPI1D clock */ + SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PERCKCN0_UART0D, /**< Disable MXC_F_GCR_PERCKCN0_UART0D clock */ + SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PERCKCN0_UART1D, /**< Disable MXC_F_GCR_PERCKCN0_UART1D clock */ + SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PERCKCN0_I2C0D, /**< Disable MXC_F_GCR_PERCKCN0_I2C0D clock */ + SYS_PERIPH_CLOCK_T0 = MXC_F_GCR_PERCKCN0_T0D, /**< Disable MXC_F_GCR_PERCKCN0_T0D clock */ + SYS_PERIPH_CLOCK_T1 = MXC_F_GCR_PERCKCN0_T1D, /**< Disable MXC_F_GCR_PERCKCN0_T1D clock */ + SYS_PERIPH_CLOCK_T2 = MXC_F_GCR_PERCKCN0_T2D, /**< Disable MXC_F_GCR_PERCKCN0_T2D clock */ + SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PERCKCN0_I2C1D, /**< Disable MXC_F_GCR_PERCKCN0_I2C1D clock */ +} sys_periph_clock_t; + +/** @brief Clock source */ +typedef enum { + SYS_CLOCK_NANORING = MXC_V_GCR_CLKCN_CLKSEL_NANORING, /**< 8KHz nanoring on MAX32660 */ + SYS_CLOCK_HFXIN = MXC_V_GCR_CLKCN_CLKSEL_HFXIN, /**< 32KHz on MAX32660 */ + SYS_CLOCK_HFXIN_DIGITAL = 0x9, /**< External Clock Input*/ + SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC, /**< High Frequency Internal Oscillator */ +} sys_system_clock_t; + +typedef void* sys_cfg_t; + +typedef sys_cfg_t sys_cfg_i2c_t; +typedef sys_cfg_t sys_cfg_flc_t; +typedef sys_cfg_t sys_cfg_wdt_t; + +/** @brief Map control */ +typedef enum { + MAP_A, + MAP_B, + MAP_C, +} sys_map_t; + +/** @brief UART Flow control */ +typedef enum { + UART_FLOW_DISABLE, + UART_FLOW_ENABLE, +} sys_uart_flow_t; + +/** @brief UART system configuration object */ +typedef struct { + sys_map_t map; + sys_uart_flow_t flow_flag; +} sys_cfg_uart_t; + +/** @brief SPI17Y system configuration object */ +typedef struct { + sys_map_t map; +} sys_cfg_spi17y_t; + +/** @brief SPIMSS system configuration object */ +typedef struct { + sys_map_t map; +} sys_cfg_spimss_t; + +/** @brief I2S system configuration object */ +typedef struct { + sys_map_t map; + dma_reqsel_t dma_reqsel_tx; + dma_reqsel_t dma_reqsel_rx; +} sys_cfg_i2s_t; + +/** @brief TIMER system configuration object */ +typedef struct { + int out_en; +} sys_cfg_tmr_t; + +/** @brief Real Time Clock system configuration object */ +typedef struct { + mxc_tmr_regs_t* tmr; +} sys_cfg_rtc_t; + + +/** @brief Pulse Train System Configuration Object */ +typedef gpio_cfg_t sys_cfg_pt_t; + +#if defined ( __CC_ARM ) /* Restore the warning: "enum is out of int range" for Keil */ +#pragma pop +#endif /* __CC_ARM */ +/***** Function Prototypes *****/ +/** + * @brief Selects the system clock and enables it once ready + * @param clock Enumeration for desired clock. + * @param tmr Optional tmr pointer for timeout. NULL if undesired. + * + * @returns #E_NO_ERROR is clock is succesfully selected + */ +int SYS_Clock_Select(sys_system_clock_t clock, mxc_tmr_regs_t* tmr); + +/** + * @brief Enables the selected peripheral clock. + * @param clock Enumeration for desired clock. + */ +void SYS_ClockEnable(sys_periph_clock_t clock); + +/** + * @brief Disables the selected peripheral clock. + * @param clock Enumeration for desired clock. + */ +void SYS_ClockDisable(sys_periph_clock_t clock); + +/** + * @brief Enables the external 32k oscillator. + * @param sys_cfg system configuration object + * + * @returns #E_NO_ERROR is successful, appropriate error otherwise + */ +int SYS_ClockEnable_X32K(sys_cfg_rtc_t *sys_cfg); + +/** + * @brief Disables the external 32k oscillator. + * + * @returns #E_NO_ERROR is successful, appropriate error otherwise + */ +int SYS_ClockDisable_X32K(void); + +/** + * @brief System level initialization for UART module. + * @param uart Pointer to UART module registers + * @param sys_cfg System configuration object + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_UART_Init(mxc_uart_regs_t *uart, const sys_cfg_uart_t* sys_cfg); + +/** + * @brief System level shutdown for UART module + * @param uart Pointer to UART module registers + * + * @return #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_UART_Shutdown(mxc_uart_regs_t *uart); + +/** + * @brief System level initialization for I2C module. + * @param i2c Pointer to I2C module registers + * @param sys_cfg System configuration object + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_I2C_Init(mxc_i2c_regs_t *i2c, const sys_cfg_i2c_t* sys_cfg); + +/** + * @brief System level Shutdown for I2C module. + * @param i2c Pointer to I2C module registers + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_I2C_Shutdown(mxc_i2c_regs_t *i2c); + +/** + * @brief Init DMA system settings + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_DMA_Init(void); + +/** + * @brief Shutdown DMA system specific settings + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_DMA_Shutdown(void); + +/** + * @brief Get the frequency of the I2C module source clock + * @param spim Unused, pointer to I2C module registers + * + * @returns frequency in Hz + */ +unsigned SYS_I2C_GetFreq(mxc_i2c_regs_t *i2c); + +/** + * @brief Get the frequency of the Timer module source clock. + * @params tmr Unused, pointer to timer module registers + * + * @returns frequency in Hz + */ +unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr); + +/** + * @brief Reset the peripherals and/or CPU in the rstr0 register. + * @param Enumeration for what to reset. Can reset multiple items at once. + */ +void SYS_Reset0(sys_reset0_t reset); + +/** + * @brief Reset the peripherals and/or CPU in the rstr1 register. + * @param Enumeration for what to reset. Can reset multiple items at once. + */ +void SYS_Reset1(sys_reset1_t reset); + +/** + * @brief Clear Cache and Line buffer. + */ +void SYS_Flash_Operation(void); + +/** + * @brief Init TMR system settings + * @param tmr Pointer to timer module registers + * @param sys_cfg System configuration object + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t* sys_cfg); + +/** + * @brief Init flash system settings + * @param sys_cfg System configuration object + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg); + +/** + * @brief Shutdown flash system specific settings + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_FLC_Shutdown(void); + +/** + * @brief System level initialization for SPI17Y module. + * @param spi pointer to spi module registers + * @param sys_cfg System configuration object + * + * @returns E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_SPI17Y_Init( mxc_spi17y_regs_t *spi, const sys_cfg_spi17y_t* sys_cfg); + +/** + * @brief System level shutdown for SPI17Y module + * @param pointer to spi module registers + * + * @returns E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi); + +/** + * @brief System level initialization for SPIMSS module. + * @param spi pointer to spi module registers + * @param sys_cfg System configuration object + * + * @returns E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_SPIMSS_Init(mxc_spimss_regs_t *spi, const sys_cfg_spimss_t* sys_cfg); + +/** + * @brief System level shutdown for SPIMSS module + * @param pointer to spi module registers + * + * @returns E_NO_ERROR if everything is successful + */ +int SYS_SPIMSS_Shutdown(mxc_spimss_regs_t *spi); + +/** + * @brief Shutdown Timer system specific settings + * @param tmr pointer to timer module registers + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_TMR_Shutdown(mxc_tmr_regs_t *tmr); + +/** + * @brief System level initialization for I2S Module + * @param sys_cfg System configuration object + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_I2S_Init(const sys_cfg_i2s_t* sys_cfg); + +/** + * @brief System level shutdown of I2S module + * + * @returns #E_NO_ERROR if everything is successful + */ +int SYS_I2S_Shutdown(void); + +/** + * @brief Get the frequency of the I2S module source clock + * @param spimss Pointer to I2S module registers + * + * @returns frequency in Hz + */ +int SYS_I2S_GetFreq(mxc_spimss_regs_t *spimss); + +/** + * @brief Init system settings for RTC square wave output. + * @param sys_cfg System configuration object + * + * @returns #E_NO_ERROR if successful, appropriate error otherwise + */ +int SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg); + + +/** + * @brief System Tick Configuration Helper + * + * The function enables selection of the external clock source for + * the System Tick Timer. It initializes the System Timer and its + * interrupt, and starts the System Tick Timer. Counter is in free + * running mode to generate periodic interrupts. + * + * @param ticks Number of ticks between two interrupts. + * @param clk_src Selects between default SystemClock or External Clock. + * - 0 Use external clock source + * @param tmr Optional tmr pointer for timeout. NULL if undesired. + * - 1 SystemClock + * + * @return #E_NO_ERROR Function succeeded, of #E_INVALID if an invalid value is requested + */ +int SYS_SysTick_Config(uint32_t ticks, int clk_src, mxc_tmr_regs_t* tmr); + +/** + * @brief Disable System Tick timer + */ +void SYS_SysTick_Disable(void); + +/** + * @brief Delay a requested number of SysTick Timer Ticks. + * @param ticks Number of System Ticks to delay. + * @note This delay function is based on the clock used for the SysTick + * timer if the SysTick timer is enabled. If the SysTick timer is + * not enabled, the current SysTick registers are saved and the + * timer will use the SystemClock as the source for the delay. The + * delay is measured in clock ticks and is not based on the SysTick + * interval. + * + * @return #E_NO_ERROR if everything is successful + */ +int SYS_SysTick_Delay(uint32_t ticks); + +/** + * @brief Get the frequency of the SysTick Timer + * + * @return frequency in Hz + */ +uint32_t SYS_SysTick_GetFreq(void); + +/** + * @brief Delay a requested number of microseconds. + * @param us Number of microseconds to delay. + * @note Calls SYS_SysTick_Delay(). + */ +void SYS_SysTick_DelayUs(uint32_t us); + +/** + * @brief Init WDT system settings + * @param wdt watchdog registers + * @param sys_cfg System configuration object + */ +int SYS_WDT_Init(mxc_wdt_regs_t* wdt, const sys_cfg_wdt_t* sys_cfg); +#ifdef __cplusplus +} +#endif + +#endif /* _MXC_SYS_H_*/ + diff --git a/Project/SDK/Driver/Include/nvic_table.h b/Project/SDK/Driver/Include/nvic_table.h new file mode 100644 index 0000000..b4a8df7 --- /dev/null +++ b/Project/SDK/Driver/Include/nvic_table.h @@ -0,0 +1,89 @@ +/** + * @file nvic_table.h + * @brief Interrupt vector table manipulation functions. + */ + +/******************************************************************************* + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2020-04-20 15:48:35 -0500 (Mon, 20 Apr 2020) $ + * $Revision: 53144 $ + * + ******************************************************************************/ + +#ifndef _NVIC_TABLE_H +#define _NVIC_TABLE_H + +#include "mxc_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup nvic NVIC Table + * @brief functions handling the nvic table. + * @{ + */ +/** + * @brief Set an IRQ hander callback function. If the IRQ table is in + * flash, this will copy it to RAM and set NVIC to RAM based table. + * + * @param irqn ARM external IRQ number + * @param irq_callback Function to be called at IRQ context + * + */ +void NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void)); + +/** + * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table. + * + */ +void NVIC_SetRAM(void); + +/** + * @brief Get Interrupt Vector + * @details Reads an interrupt vector from interrupt vector table. The + * interrupt number can be positive to specify a device specific + * interrupt, or negative to specify a processor exception. + * @param[in] IRQn Interrupt number. + * @return Address of interrupt handler function + */ +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +/**@} end of group nvic */ + +#ifdef __cplusplus +} +#endif + +#endif /* _NVIC_TABLE_H */ diff --git a/Project/SDK/Driver/Include/rtc.h b/Project/SDK/Driver/Include/rtc.h new file mode 100644 index 0000000..dcfae03 --- /dev/null +++ b/Project/SDK/Driver/Include/rtc.h @@ -0,0 +1,242 @@ +/** + * @file + * @brief Real Time Clock (RTC) functions and prototypes. + */ + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + * $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $ + * $Revision: 47429 $ + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _RTC_H_ +#define _RTC_H_ + +/* **** Includes **** */ +#include +#include "mxc_config.h" +#include "rtc_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup rtc RTC + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +typedef enum { + SQUARE_WAVE_DISABLED, /**< Sq. wave output disabled */ + SQUARE_WAVE_ENABLED, /**< Sq. wave output enabled */ +} rtc_sqwave_en_t; + +typedef enum { + F_1HZ = MXC_S_RTC_CTRL_FT_FREQ1HZ, /**< 1Hz (Compensated) */ + F_512HZ = MXC_S_RTC_CTRL_FT_FREQ512HZ, /**< 512Hz (Compensated) */ + F_4KHZ = MXC_S_RTC_CTRL_FT_FREQ4KHZ, /**< 4Khz */ + F_32KHZ = 32, /**< 32Khz */ +} rtc_freq_sel_t; + +typedef enum { + NOISE_IMMUNE_MODE = MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE, + QUIET_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETMODE, + QUIET_STOP_WARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP, + QUIET_STOP_NOWARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP, +} rtc_osc_mode_t; + +/** + *@brief Enables Time-of-Day's Alarm Interrupt + *@param rtc pointer to the rtc register structure + *@return #E_SUCCESS=pass + *@return #E_BAD_STATE=fail + *@return #E_BUSY=Fail + */ +int RTC_EnableTimeofdayInterrupt(mxc_rtc_regs_t *rtc); + +/** + *@brief Disable Time-of-Day's Alarm Interrupt + *@param rtc pointer to the rtc register structure + *@return #E_SUCCESS=pass + *@return #E_BAD_STATE=fail + *@return #E_BUSY=Fail + */ +int RTC_DisableTimeofdayInterrupt(mxc_rtc_regs_t *rtc); + +/** + *@brief Enables Sub-Second's Alarm Interrupt + *@param rtc pointer to the rtc register structure + *@return #E_SUCCESS=pass + *@return #E_BAD_STATE=fail + *@return #E_BUSY=Fail + */ +int RTC_EnableSubsecondInterrupt(mxc_rtc_regs_t *rtc); + +/** + *@brief Disable Sub-Second's Alarm Interrupt + *@param rtc pointer to the rtc register structure + *@return #E_SUCCESS=pass + *@return #E_BAD_STATE=fail + *@return #E_BUSY=Fail + */ +int RTC_DisableSubsecondInterrupt(mxc_rtc_regs_t *rtc); + +/** + *@brief Set Time-of-Day alarm value and enable Interrupt + *@param rtc pointer to the rtc register structure + *@param ras 20-bit value 0-0xFFFFF + *@return #E_SUCCESS=pass + *@return #E_BAD_STATE=fail + *@return #E_BUSY=Fail + */ +int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras); + +/** + *@brief Set Sub-Second alarm value and enable interrupt, + *@brief this is to be called after the init_rtc() function + *@param rtc pointer to the rtc register structure + *@param rssa 32-bit value 0-0xFFFFFFFF + *@return #E_SUCCESS=pass + *@return #E_BAD_STATE=fail + *@return #E_BUSY=Fail + */ +int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa); + +/** + *@brief Enable/Start the Real Time Clock + *@param rtc pointer to the rtc register structure + *@return #E_SUCCESS=Pass + *@return #E_BUSY=Fail + */ +int RTC_EnableRTCE(mxc_rtc_regs_t *rtc); + +/** + *@brief Disable/Stop the Real Time Clock + *@param rtc pointer to the rtc register structure + *@return #E_SUCCESS=Pass + *@return #E_BUSY=Fail + */ +int RTC_DisableRTCE(mxc_rtc_regs_t *rtc); + +/** + * @brief Initialize the sec and ssec registers and enable RTC + * @param rtc pointer to the rtc register structure + * @param sec set the RTC Sec counter (32-bit) + * @param ssec set the RTC Sub-second counter (8-bit) + * @param sys_cfg The system configuration + * @return #E_SUCCESS=pass + * @return #E_BAD_STATE=fail + */ +int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint8_t ssec, sys_cfg_rtc_t *sys_cfg); + +/** + * @brief Allow generation of Square Wave on the SQW pin + * @param rtc pointer to the rtc register structure + * @param sqe Enable/Disable square wave output + * @param ft Frequency output selection + * @param x32kmd 32KHz Oscillator mode + * @param sys_cfg The system configuration + * @return #E_SUCCESS=Pass + * @return #E_BUSY=Fail + */ +int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft, + rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg); + +/** + *@brief Set Trim register value + *@param rtc pointer to the rtc register structure + *@param trm set the RTC Trim (8-bit, +/- 127) + *@return #E_SUCCESS=Pass + *@return #E_BUSY=Fail + */ +int RTC_Trim(mxc_rtc_regs_t *rtc, int8_t trm); + +/** + *@brief Check if BUSY bit is 0. + *@return #E_SUCCESS=Pass + *@return #E_BUSY=Fail + */ +int RTC_CheckBusy(void); + +/** + *@brief Gets Interrupt flags. + *@return Interrupts flags that have not been cleared + */ +int RTC_GetFlags(void); + +/** + *@brief Clear Interrupt flag. + *@param flags the flags that need to be cleared + */ +int RTC_ClearFlags(int flags); + +/** + *@brief Get SubSecond + *@return Returns subsecond value + */ +int RTC_GetSubSecond(void); + +/** + * @brief Get Second + * @return returns Second value + */ +int RTC_GetSecond(void); + +/** + * @brief Read seconds, then subseconds, and finally seconds. If RTC ready flag ever gets cleared during this sequence, + the RTC is in the middle of updating the counts and the user should come back later and try again. If the first + read of the seconds register doesn't match the next read, then a subsecond overflow condition has happened and + another attempt to read the counts should be made. + * @param sec variable that will be changed to hold second value + * @param subsec variable that will be changed to hold Subsecond value + * @return #E_NO_ERROR=Pass + * @return #E_BUSY=Fail + */ +int RTC_GetTime(uint32_t* sec, uint32_t* subsec); + +/** + *@brief Check if RTC is already running + */ +int RTC_IsEnabled(void); + +#ifdef __cplusplus +} +#endif +/**@} end of group rtc */ + +#endif /* _RTC_H_ */ diff --git a/Project/SDK/Driver/Include/spi.h b/Project/SDK/Driver/Include/spi.h new file mode 100644 index 0000000..2672f50 --- /dev/null +++ b/Project/SDK/Driver/Include/spi.h @@ -0,0 +1,259 @@ + /** + * @file spi.h + * @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-11-07 14:48:15 -0600 (Wed, 07 Nov 2018) $ + * $Revision: 39010 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _SPI_H_ +#define _SPI_H_ + +/* **** Includes **** */ +#include "spi17y_regs.h" +#include "spimss_regs.h" +#include "spimss.h" +#include "spi17y.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup spi SPI + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +/** + * @brief Enums assigning numbers to SPI + */ +typedef enum { + SPI0A, // SPI17Y (0A) + SPI1A, // SPIMSS (1A) + SPI1B, // SPIMSS (1B) +}spi_type; + + +/** + * @brief Renaming the SPI address names + */ +#define MXC_SPI0 MXC_SPI17Y // SPI0A +#define MXC_SPI1 MXC_SPIMSS // SPI1A & SPI1B + + +/** + * @brief Renaming Interrupt SPI Interrupt sources + */ +#define SPI0_IRQn SPI17Y_IRQn // SPI0A +#define SPI1_IRQn SPIMSS_IRQn // SPI1A & SPI1B + + +/** + * @brief Renaming SPI Width + */ +#define SPI0_WIDTH_1 SPI17Y_WIDTH_1 /**< 1 Data Line. */ +#define SPI0_WIDTH_2 SPI17Y_WIDTH_2 /**< 2 Data Lines (x2). */ +#define SPI0_WIDTH_4 SPI17Y_WIDTH_4 /**< 4 Data Lines (x4). */ + +/** + * @brief Renaming SPI Polarity + */ +#define SPI_POL_LOW SPI17Y_POL_LOW /**< Slave Select polarity Low. */ +#define SPI_POL_HIGH SPI17Y_POL_HIGH /**< Slave Select polarity High. */ + +/** + * @brief Structure type representing a SPI Master Transaction request. + */ +typedef struct spi_req spi_req_t; + +/** + * @brief Callback function type used in asynchronous SPI Master communication requests. + * @details The function declaration for the SPI Master callback is: + * @code + * void callback(spi_req_t * req, int error_code); + * @endcode + * | | | + * | -----: | :----------------------------------------- | + * | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. | + * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. | + * @note Callback will execute in interrupt context + * @addtogroup spi_async + */ +typedef void (*spi_callback_fn)(void * req, int error_code); + +/** + * @brief Structure definition for an SPI Master Transaction request. + * @note When using this structure for an asynchronous operation, the + * structure must remain allocated until the callback is completed. + * @addtogroup spi_async + */ +struct spi_req { + uint8_t ssel; /**< Slave select line to use. (Master only) */ + uint8_t deass; /**< Non-zero to de-assert slave select after transaction. (Master only)*/ + spi17y_sspol_t ssel_pol; /**< Slave select line polarity. */ + const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ + void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ + spi17y_width_t width; /**< Number of data lines to use, see #spi17y_width_t. */ + unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ + unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ + unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ + unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ + spi_callback_fn callback; /**< Callback function if desired, NULL otherwise */ +}; + + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the spi. + * @param spi_name spi module to initialize. + * @param mode SPI mode for clock phase and polarity. + * @param freq Desired clock frequency. + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI_Init(spi_type spi_name, unsigned mode, unsigned freq); + +/** + * @brief Asynchronously read/write SPI Master data + * + * @param spi_name SPI instance being used + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI_MasterTransAsync(spi_type spi_name, spi_req_t *req); + +/** + * @brief Execute a master transaction. + * @param spi_name SPI instance being used + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI_MasterTrans(spi_type spi_name, spi_req_t *req); + +/** + * @brief Asynchronously read/write SPI Slave data + * @param spi_name SPI instance being used + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI_SlaveTransAsync(spi_type spi_name, spi_req_t *req); + +/** + * @brief Execute a slave transaction. + * @param spi_name SPI instance being used + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI_SlaveTrans(spi_type spi_name, spi_req_t *req); + +/** + * @brief Shutdown SPI module. + * @param spi_name SPI instance being used + * + * @return #E_NO_ERROR if successful, appropriate error otherwise + */ +int SPI_Shutdown(spi_type spi_name); + + +/** + * @brief Aborts an Asynchronous request + * @param spi_name SPI instance being used + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI_AbortAsync(spi_type spi_name, spi_req_t *req); + +/** + * @brief Execute SPI transaction based on interrupt handler + * @param spi_name SPI instance being used + * + * @return #E_NO_ERROR if successful, + * @return #E_BAD_PARAM otherwise + */ +int SPI_Handler(spi_type spi_name); + +/** + * @brief Enable SPI + * @param spi_name Pointer to spi module. + * + * @return #E_NO_ERROR if successful, appropriate error otherwise + */ +int SPI_Enable(spi_type spi_name); + +/** + * @brief Disable SPI + * @param spi_name Pointer to spi module. + * + * @return #E_NO_ERROR if successful, appropriate error otherwise + */ +int SPI_Disable(spi_type spi_name); + +/** + * @brief Clear the TX and RX FIFO + * @param spi_name Pointer to spi module. + * + * @return #E_NO_ERROR if successful, appropriate error otherwise + */ +int SPI_Clear_fifo(spi_type spi_name); + +//------------------------------------------------------------------------------------------- +/**@} end of group spi */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPI_H_ */ + + + diff --git a/Project/SDK/Driver/Include/spi17y.h b/Project/SDK/Driver/Include/spi17y.h new file mode 100644 index 0000000..530def8 --- /dev/null +++ b/Project/SDK/Driver/Include/spi17y.h @@ -0,0 +1,242 @@ +/** + * @file spi17y.h + * @brief Serial Peripheral Interface (SPI17Y) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _SPI17Y_H_ +#define _SPI17Y_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "spi17y_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup spi17y SPI17Y + * @ingroup spi + * @{ + */ + +/* **** Definitions **** */ + +/** + * Enumeration type for setting the number data lines to use for communication. + */ +typedef enum { + SPI17Y_WIDTH_1 = 0, /**< 1 Data Line. */ + SPI17Y_WIDTH_2 = 1, /**< 2 Data Lines (x2). */ + SPI17Y_WIDTH_4 = 2 /**< 4 Data Lines (x4). */ +} spi17y_width_t; + +/** + * Enumeration type for setting the polarity of ss lines. + */ +typedef enum { + SPI17Y_POL_LOW = 0, /**< Polarity Low. */ + SPI17Y_POL_HIGH = 1 /**< Polarity High. */ +} spi17y_sspol_t; + +/** + * Structure type representing a SPI17Y Master Transaction request. + */ +typedef struct spi17y_req spi17y_req_t; + + +/** + * @brief Callback function type used in asynchronous SPI Master communication requests. + * @details The function declaration for the SPI Master callback is: + * @code + * void callback(spi17y_req_t * req, int error_code); + * @endcode + * | | | + * | -----: | :----------------------------------------- | + * | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. | + * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. | + * @note Callback will execute in interrupt context + * @addtogroup spi_async + */ +typedef void (*spi17y_callback_fn)(spi17y_req_t * req, int error_code); + +/** + * @brief Structure definition for an SPI Master Transaction request. + * @note When using this structure for an asynchronous operation, the + * structure must remain allocated until the callback is completed. + * @addtogroup spi_async + */ +struct spi17y_req { + uint8_t ssel; /**< Slave select line to use. (Master only, ignored in slave mode) */ + uint8_t deass; /**< Non-zero to de-assert slave select after transaction. (Master only, ignored in slave mode)*/ + spi17y_sspol_t ssel_pol; /**< Slave select line polarity. */ + const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ + void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ + spi17y_width_t width; /**< Number of data lines to use, see #spi17y_width_t. */ + unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ + unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ + unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ + unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ + spi17y_callback_fn callback; /**< Callback function if desired, NULL otherwise */ +}; + + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the spi. + * @param spi Pointer to spi module to initialize. + * @param mode SPI mode for clock phase and polarity. + * @param freq Desired clock frequency. + * @param sys_cfg System configuration object + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI17Y_Init(mxc_spi17y_regs_t *spi, unsigned int mode, unsigned int freq, const sys_cfg_spi17y_t* sys_cfg); + +/** + * @brief Shutdown SPI module. + * @param spi Pointer to SPI regs. + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI17Y_Shutdown(mxc_spi17y_regs_t *spi); + +/** + * @brief Processing function for asynchronous SPI operations. + * This function must be called either from the SPI interrupt + * handler or periodically. + * + * @param spi Pointer to spi module. + */ +void SPI17Y_Handler(mxc_spi17y_regs_t *spi); + +/** + * @brief Execute a master transaction. + * This function will block until the transaction is complete. + * @param spi Pointer to spi module. + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI17Y_MasterTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req); + +/** + * @brief Execute a slave transaction. + * This function will block until the transaction is complete. + * @param spi Pointer to spi module. + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI17Y_SlaveTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req); + +/** + * @brief Asynchronously read/write SPI Master data + * + * @param spi Pointer to spi module + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI17Y_MasterTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req); + +/** + * @brief Asynchronously read/write SPI Slave data + * + * @param spi Pointer to spi module + * @param req Pointer to spi request + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI17Y_SlaveTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req); + +/** + * @brief Aborts an Asynchronous request + * + * @param req Pointer to spi request + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPI17Y_AbortAsync(spi17y_req_t *req); + +/** + * @brief Enable SPI + * @param spi Pointer to spi module. + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +void SPI17Y_Enable(mxc_spi17y_regs_t* spi); + +/** + * @brief Disable SPI. Any pending asynchronous transactions will not + * complete and their callbacks will not be executed. + * @param spi Pointer to spi module. + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +void SPI17Y_Disable(mxc_spi17y_regs_t* spi); + +/** + * @brief Clear the TX and RX FIFO + * @param spi Pointer to spi module. + * + * @return #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +void SPI17Y_Clear_fifo(mxc_spi17y_regs_t* spi); + + +/**@} end of group spi17y */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPI17Y_H_ */ diff --git a/Project/SDK/Driver/Include/spimss.h b/Project/SDK/Driver/Include/spimss.h new file mode 100644 index 0000000..e693360 --- /dev/null +++ b/Project/SDK/Driver/Include/spimss.h @@ -0,0 +1,197 @@ +/** + * @file spimss.h + * @brief Serial Peripheral Interface (SPIMSS) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _SPIMSS_H_ +#define _SPIMSS_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_sys.h" +#include "spimss_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup spimss SPIMSS + * @ingroup spi + * @{ + */ + +/* **** Definitions **** */ + + +/** + * @brief Enumeration type for setting the number data lines to use for communication. + */ +typedef enum { // ONLY FOR COMPATIBILITY FOR CONSOLIDATION WITH SPY17, NOT USED OR NEEDED + DUMMY_1, /**< NOT USED */ + DUMMY_2, /**< NOT USED */ + DUMMY_3, /**< NOT USED */ +} spimss_width_t; + +/** + * @brief Structure type representing a SPI Master Transaction request. + */ +typedef struct spimss_req spimss_req_t; + +/** + * @brief Callback function type used in asynchronous SPI Master communication requests. + * @details The function declaration for the SPI Master callback is: + * @code + * void callback(spi_req_t * req, int error_code); + * @endcode + * | | | + * | -----: | :----------------------------------------- | + * | \p req | Pointer to a #spi_req object representing the active SPI Master active transaction. | + * | \p error_code | An error code if the active transaction had a failure or #E_NO_ERROR if successful. | + * @note Callback will execute in interrupt context + * @addtogroup spi_async + */ +typedef void (*spimss_callback_fn)(spimss_req_t * req, int error_code); + +/** + * @brief Structure definition for an SPI Master Transaction request. + * @note When using this structure for an asynchronous operation, the + * structure must remain allocated until the callback is completed. + * @addtogroup spi_async + */ +struct spimss_req { + uint8_t ssel; /**< Not Used*/ + uint8_t deass; /**< Not Used*/ + const void *tx_data; /**< Pointer to a buffer to transmit data from. NULL if undesired. */ + void *rx_data; /**< Pointer to a buffer to store data received. NULL if undesired.*/ + spimss_width_t width; /**< Not Used */ + unsigned len; /**< Number of transfer units to send from the \p tx_data buffer. */ + unsigned bits; /**< Number of bits in transfer unit (e.g. 8 for byte, 16 for short) */ + unsigned rx_num; /**< Number of bytes actually read into the \p rx_data buffer. */ + unsigned tx_num; /**< Number of bytes actually sent from the \p tx_data buffer */ + spimss_callback_fn callback; /**< Callback function if desired, NULL otherwise */ +}; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the spi. + * @param spi Pointer to spi module to initialize. + * @param mode SPI mode for clock phase and polarity. + * @param freq Desired clock frequency. + * @param sys_cfg System configuration object + * + * @return \c #E_NO_ERROR if successful, appropriate error otherwise + */ +int SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_cfg_spimss_t* sys_cfg); + +/** + * @brief Shutdown SPI module. + * @param spi Pointer to SPI regs. + * + * @return \c #E_NO_ERROR if successful, appropriate error otherwise + */ +int SPIMSS_Shutdown(mxc_spimss_regs_t *spi); + +/** + * @brief Execute a master transaction. + * @param spi Pointer to spi module. + * @param req Pointer to spi request + * + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, spimss_req_t *req); + +/** + * @brief Execute SPI transaction based on interrupt handler + * @param spi The spi + * + */ +void SPIMSS_Handler(mxc_spimss_regs_t *spi); + +/** + * @brief Execute a slave transaction. + * @param spi Pointer to spi module. + * @param req Pointer to spi request + * + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, spimss_req_t *req); + +/** + * @brief Asynchronously read/write SPI Master data + * + * @param spi Pointer to spi module + * @param req Pointer to spi request + * + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req); + +/** + * @brief Asynchronously read/write SPI Slave data + * + * @param spi Pointer to spi module + * @param req Pointer to spi request + * + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req); + +/** + * @brief Aborts an Asynchronous request + * + * @param req Pointer to spi request + * @return \c #E_NO_ERROR if successful, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int SPIMSS_AbortAsync(spimss_req_t *req); + +/**@} end of group spimss */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SPIMSS_H_ */ diff --git a/Project/SDK/Driver/Include/tmr.h b/Project/SDK/Driver/Include/tmr.h new file mode 100644 index 0000000..c47fd12 --- /dev/null +++ b/Project/SDK/Driver/Include/tmr.h @@ -0,0 +1,265 @@ +/** + * @file tmr.h + * @brief Timer (TMR) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-09-11 14:32:22 -0500 (Wed, 11 Sep 2019) $ + * $Revision: 46047 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _TMR_H_ +#define _TMR_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "tmr_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup tmr Timer (TMR) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Timer prescaler values + */ +typedef enum { + TMR_PRES_1 = MXC_S_TMR_CN_PRES_DIV1, /// Divide input clock by 1 + TMR_PRES_2 = MXC_S_TMR_CN_PRES_DIV2, /// Divide input clock by 2 + TMR_PRES_4 = MXC_S_TMR_CN_PRES_DIV4, /// Divide input clock by 4 + TMR_PRES_8 = MXC_S_TMR_CN_PRES_DIV8, /// Divide input clock by 8 + TMR_PRES_16 = MXC_S_TMR_CN_PRES_DIV16, /// Divide input clock by 16 + TMR_PRES_32 = MXC_S_TMR_CN_PRES_DIV32, /// Divide input clock by 32 + TMR_PRES_64 = MXC_S_TMR_CN_PRES_DIV64, /// Divide input clock by 64 + TMR_PRES_128 = MXC_S_TMR_CN_PRES_DIV128, /// Divide input clock by 128 + TMR_PRES_256 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV1, /// Divide input clock by 256 + TMR_PRES_512 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV2, /// Divide input clock by 512 + TMR_PRES_1024 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV4, /// Divide input clock by 1024 + TMR_PRES_2048 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV8, /// Divide input clock by 2048 + TMR_PRES_4096 = MXC_F_TMR_CN_PRES3 | MXC_S_TMR_CN_PRES_DIV16 /// Divide input clock by 4096 +} tmr_pres_t; + +/** + * @brief Timer modes + */ +typedef enum { + TMR_MODE_ONESHOT = MXC_V_TMR_CN_TMODE_ONESHOT, /// Timer Mode ONESHOT + TMR_MODE_CONTINUOUS = MXC_V_TMR_CN_TMODE_CONTINUOUS, /// Timer Mode CONTINUOUS + TMR_MODE_COUNTER = MXC_V_TMR_CN_TMODE_COUNTER, /// Timer Mode COUNTER + TMR_MODE_PWM = MXC_V_TMR_CN_TMODE_PWM, /// Timer Mode PWM + TMR_MODE_CAPTURE = MXC_V_TMR_CN_TMODE_CAPTURE, /// Timer Mode CAPTURE + TMR_MODE_COMPARE = MXC_V_TMR_CN_TMODE_COMPARE, /// Timer Mode COMPARE + TMR_MODE_GATED = MXC_V_TMR_CN_TMODE_GATED, /// Timer Mode GATED + TMR_MODE_CAPTURE_COMPARE = MXC_V_TMR_CN_TMODE_CAPTURECOMPARE /// Timer Mode CAPTURECOMPARE +} tmr_mode_t; + +/** + * @brief Timer units of time enumeration + */ +typedef enum { + TMR_UNIT_NANOSEC = 0, /**< Nanosecond Unit Indicator. */ + TMR_UNIT_MICROSEC, /**< Microsecond Unit Indicator. */ + TMR_UNIT_MILLISEC, /**< Millisecond Unit Indicator. */ + TMR_UNIT_SEC, /**< Second Unit Indicator. */ +} tmr_unit_t; + +/** + * @brief Timer Configuration + */ +typedef struct { + tmr_mode_t mode; /// Desired timer mode + uint32_t cmp_cnt; /// Compare register value in timer ticks + unsigned pol; /// Polarity (0 or 1) +} tmr_cfg_t; + +/** + * @brief Timer PWM Configuration + */ +typedef struct { + unsigned pol; /// PWM polarity (0 or 1) + uint32_t per_cnt; /// PWM period in timer ticks + uint32_t duty_cnt; /// PWM duty in timer ticks +} tmr_pwm_cfg_t; + +/* **** Definitions **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize timer module clock. + * @param tmr Pointer to timer module to initialize. + * @param pres Prescaler value. + * @param sys_cfg System configuration object + * @return #E_NO_ERROR if successful, error code otherwise. + */ +int TMR_Init(mxc_tmr_regs_t *tmr, tmr_pres_t pres, const sys_cfg_tmr_t* sys_cfg); + +/** + * @brief Shutdown timer module clock. + * @param tmr Pointer to timer module to initialize. + * @return #E_NO_ERROR if successful, error code otherwise. + */ +int TMR_Shutdown(mxc_tmr_regs_t *tmr); + +/** + * @brief Enable the timer. + * @param tmr Pointer to timer module to initialize. + */ +void TMR_Enable(mxc_tmr_regs_t* tmr); + +/** + * @brief Disable the timer. + * @param tmr Pointer to timer module to initialize. + */ +void TMR_Disable(mxc_tmr_regs_t* tmr); + +/** + * @brief Configure the timer. + * @param tmr Pointer to timer module to initialize. + * @param cfg Pointer to timer configuration struct. + * @return #E_NO_ERROR if successful. + */ +int TMR_Config(mxc_tmr_regs_t *tmr, const tmr_cfg_t *cfg); + +/** + * @brief Configure the timer for PWM operation. + * @param tmr Pointer to timer module to initialize. + * @param cfg Pointer to timer PWM configuration struct. + * @note Can cause a glitch if the Timer is currently running. + * @return #E_BAD_PARAM if duty_cnt > per_cnt. + */ +int TMR_PWMConfig(mxc_tmr_regs_t *tmr, const tmr_pwm_cfg_t *cfg); + +/** + * @brief Set the timer duty cycle. + * @param tmr Pointer to timer module to initialize + * @param duty New duty cycle count + * @note Will block until safe to change the duty count. + * @return #E_BAD_PARAM if duty_cnt > per_cnt. + */ +int TMR_PWMSetDuty(mxc_tmr_regs_t *tmr, uint32_t duty); + +/** + * @brief Set the timer period. + * @param tmr Pointer to timer module to initialize. + * @param per New period count. + * @note Will block until safe to change the period count. + * @return #E_BAD_PARAM if duty_cnt > per_cnt. + */ +int TMR_PWMSetPeriod(mxc_tmr_regs_t* tmr, uint32_t per); + +/** + * @brief Get the timer compare count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the current compare count. + */ +uint32_t TMR_GetCompare(mxc_tmr_regs_t* tmr); + +/** + * @brief Get the timer capture count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the most recent capture count. + */ +uint32_t TMR_GetCapture(mxc_tmr_regs_t* tmr); + +/** + * @brief Get the timer count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the current count. + */ +uint32_t TMR_GetCount(mxc_tmr_regs_t* tmr); + +/** + * @brief Clear the timer interrupt. + * @param tmr Pointer to timer module to initialize. + */ +void TMR_IntClear(mxc_tmr_regs_t* tmr); + +/** + * @brief Get the timer interrupt status. + * @param tmr Pointer to timer module to initialize. + * @return Returns the interrupt status. 1 if interrupt has occurred. + */ +uint32_t TMR_IntStatus(mxc_tmr_regs_t* tmr); + +/** + * @brief Set the timer compare count. + * @param tmr Pointer to timer module to initialize. + * @param cmp_cnt New compare count. + * @note This function does not protect against output glitches in PWM mode. + * Use TMR_PWMSetPeriod when in PWM mode. + */ +void TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); + +/** + * @brief Set the timer count. + * @param tmr Pointer to timer module to initialize. + * @param cnt New count. + */ +void TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt); + +/** + * @brief Convert real time to timer ticks. + * @param tmr Pointer to timer module to initialize. + * @param time Number of units of time. + * @param units Which units of time you want to convert. + * @param ticks Pointer to store the number of ticks calculated. + * @return #E_NO_ERROR if successful, error code otherwise. + */ +int TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks); + +/** + * @brief Convert timer ticks to real time. + * @param tmr Pointer to timer module to initialize. + * @param ticks Number of ticks. + * @param time Pointer to store number of units of time. + * @param units Pointer to store the units that time represents. + * @return #E_NO_ERROR if successful, error code otherwise. + */ +int TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units); + +/**@} end of group tmr */ + +#ifdef __cplusplus +} +#endif + +#endif /* _TMR_H_ */ diff --git a/Project/SDK/Driver/Include/tmr_utils.h b/Project/SDK/Driver/Include/tmr_utils.h new file mode 100644 index 0000000..30fbcf8 --- /dev/null +++ b/Project/SDK/Driver/Include/tmr_utils.h @@ -0,0 +1,146 @@ +/** + * @file tmr_utils.h + * @brief Timer utility function declarations + */ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $ + * $Revision: 38560 $ + * + **************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _TMR_UTILS_H +#define _TMR_UTILS_H + +/***** Includes *****/ +#include "mxc_config.h" +#include "tmr_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup tmr + * @defgroup tmr_utils Timer Utility Functions + * @{ + */ + +/* **** Definitions **** */ + +/** @def Macro to convert the parameter \p s from seconds to micro-seconds. */ +#define SEC(s) (((unsigned long)s) * 1000000UL) + +/** @def Macro to convert the parameter \p ms from milli-seconds to micro-seconds. */ +#define MSEC(ms) (ms * 1000UL) + +/** @def Macro to convert the parameter \p us to micro-seconds. */ +#define USEC(us) (us) + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Delays for the specified number of microseconds. + * @param tmr Which Timer instance to use + * @param us Number of microseconds to delay. + * @param sys_cfg System configuration object, identical to TMR_Init() + */ +void TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg); + +/** + * @brief Start the timeout time for the specified number of microseconds. + * @param tmr Which Timer instance to use + * @param us Number of microseconds in the timeout. + * @param sys_cfg System configuration object, identical to TMR_Init() + */ +void TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg); + +/** + * @brief Check if the timeout has occurred. + * @param tmr Which Timer instance to use + * @return #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has. + */ +int TMR_TO_Check(mxc_tmr_regs_t *tmr); + +/** + * @brief Stops the timer for the timeout. + * @param tmr Which Timer instance to use + */ +void TMR_TO_Stop(mxc_tmr_regs_t *tmr); + +/** + * @brief Clears the timeout flag. + * @param tmr Which Timer instance to use + */ +void TMR_TO_Clear(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the number of microseconds elapsed since TMR_TO_Start(). + * @param tmr Which Timer instance to use + * @return Number of microseconds since TMR_TO_Start(). + */ +unsigned int TMR_TO_Elapsed(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the number of microseconds remaining in the timeout. + * @param tmr Which Timer instance to use + * @return Number of microseconds until timeout. + */ +unsigned int TMR_TO_Remaining(mxc_tmr_regs_t *tmr); + +/** + * @brief Start the stopwatch. + * @note This function does not handle overflows + * @param tmr Which Timer to use + * @param sys_cfg System configuration object, identical to TMR_Init() + */ +void TMR_SW_Start(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *sys_cfg); + +/** + * @brief Stop the stopwatch and return the number of microseconds that + * have elapsed. + * @note This function does not handle overflows + * @param tmr Which Timer instance to use + * @return Number of microseconds since TMR_SW_Start(). + */ +unsigned int TMR_SW_Stop(mxc_tmr_regs_t *tmr); + +/**@} end of defgroup tmr_utils*/ +#ifdef __cplusplus +} +#endif + +#endif /* _TMR_UTILS_H */ diff --git a/Project/SDK/Driver/Include/uart.h b/Project/SDK/Driver/Include/uart.h new file mode 100644 index 0000000..9283201 --- /dev/null +++ b/Project/SDK/Driver/Include/uart.h @@ -0,0 +1,364 @@ +/** + * @file + * @brief This files defines the driver API including definitions, data types + * and function prototypes. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $ + * $Revision: 47429 $ + * + *************************************************************************** */ + + +#ifndef _UART_H_ +#define _UART_H_ + +/***** Includes *****/ +#include +#include "uart_regs.h" +#include "mxc_sys.h" + +/***** Definitions *****/ + +/** + * @brief Alternate clock rate. (7.3728MHz) */ +#define UART_ALTERNATE_CLOCK_HZ 7372800 +/** + * @defgroup uart UART + * @ingroup periphlibs + * @{ + */ +/** + * @brief Parity settings type */ +typedef enum { + UART_PARITY_DISABLE = 0, /**< Parity disabled */ + UART_PARITY_EVEN_0 = (MXC_F_UART_CTRL_PARITY_EN | + MXC_S_UART_CTRL_PARITY_EVEN | + MXC_F_UART_CTRL_PARMD), /**< Use for even parity 0 */ + UART_PARITY_EVEN_1 = (MXC_F_UART_CTRL_PARITY_EN | + MXC_S_UART_CTRL_PARITY_EVEN), /**< Use for even parity 1 */ + UART_PARITY_EVEN = UART_PARITY_EVEN_1, /**< Conventional even parity */ + UART_PARITY_ODD_0 = (MXC_F_UART_CTRL_PARITY_EN | + MXC_S_UART_CTRL_PARITY_ODD | + MXC_F_UART_CTRL_PARMD), /**< Use for odd parity 0 */ + UART_PARITY_ODD_1 = (MXC_F_UART_CTRL_PARITY_EN | + MXC_S_UART_CTRL_PARITY_ODD), /**< Use for odd parity 1 */ + UART_PARITY_ODD = UART_PARITY_ODD_1, /**< Conventional odd parity */ + UART_PARITY_MARK_0 = (MXC_F_UART_CTRL_PARITY_EN | + MXC_S_UART_CTRL_PARITY_MARK | + MXC_F_UART_CTRL_PARMD), /**< Use for mark parity 0 */ + UART_PARITY_MARK_1 = (MXC_F_UART_CTRL_PARITY_EN | + MXC_S_UART_CTRL_PARITY_MARK), /**< Use for mark parity 1 */ + UART_PARITY_MARK = UART_PARITY_MARK_1, /**< Conventional mark parity */ + UART_PARITY_SPACE_0 = (MXC_F_UART_CTRL_PARITY_EN | + MXC_S_UART_CTRL_PARITY_SPACE | + MXC_F_UART_CTRL_PARMD), /**< Use for space parity 0 */ + UART_PARITY_SPACE_1 = (MXC_F_UART_CTRL_PARITY_EN | + MXC_S_UART_CTRL_PARITY_SPACE), /**< Use for space parity 1 */ + UART_PARITY_SPACE = UART_PARITY_SPACE_1, /**< Conventional space parity */ +} uart_parity_t; + +/** + * @brief Message size settings */ +typedef enum { + UART_DATA_SIZE_5_BITS = MXC_S_UART_CTRL_CHAR_SIZE_5, /**< Data Size 5 Bits */ + UART_DATA_SIZE_6_BITS = MXC_S_UART_CTRL_CHAR_SIZE_6, /**< Data Size 6 Bits */ + UART_DATA_SIZE_7_BITS = MXC_S_UART_CTRL_CHAR_SIZE_7, /**< Data Size 7 Bits */ + UART_DATA_SIZE_8_BITS = MXC_S_UART_CTRL_CHAR_SIZE_8, /**< Data Size 8 Bits */ +} uart_size_t; + +/** + * @brief Stop bit settings */ +typedef enum { + UART_STOP_1 = 0, /**< UART Stop 1 clock cycle */ + UART_STOP_1P5 = MXC_F_UART_CTRL_STOPBITS, /**< UART Stop 1.5 clock cycle */ + UART_STOP_2 = MXC_F_UART_CTRL_STOPBITS, /**< UART Stop 2 clock cycle */ +} uart_stop_t; + +/** + * @brief Flow control */ +typedef enum { + UART_FLOW_CTRL_DIS = 0, /**< RTS/CTS flow is disabled */ + UART_FLOW_CTRL_EN = MXC_F_UART_CTRL_FLOW_CTRL, /**< RTS/CTS flow is enabled */ +} uart_flow_ctrl_t; + +/** + * @brief Flow control Polarity */ +typedef enum { + UART_FLOW_POL_DIS = 0, /**< RTS/CTS asserted is low */ + UART_FLOW_POL_EN = MXC_F_UART_CTRL_FLOW_POL, /**< RTS/CTS asserted is high */ +} uart_flow_pol_t; + +#if (TARGET != 32660) +/** + * @brief Clock Source Select */ +typedef enum { + UART_CLKSEL_SYSTEM = 0, /**< Peripheral clock will be used as the bit rate clock */ + UART_CLKSEL_ALTERNATE = MXC_F_UART_CTRL_CLKSEL, /**< Use the device's alternate UART bit rate clock. */ +} uart_clksel_t; +#endif + +/** + * @brief UART configuration type. */ +typedef struct { + uart_parity_t parity; /** Configure parity checking */ + uart_size_t size; /** Configure character size */ + uart_stop_t stop; /** Configure the number of stop bits to use */ + uart_flow_ctrl_t flow; /** Configure hardware flow control */ + uart_flow_pol_t pol; /** Configure hardware flow control */ + uint32_t baud; /** Configure baud rate */ +#if (TARGET != 32660) + uart_clksel_t clksel; /** Configure hardware clock source */ +#endif +} uart_cfg_t; + +/** + * @brief Non-blocking UART transaction request. */ +typedef struct uart_req uart_req_t; +struct uart_req { + uint8_t *data; /** Data buffer for characters */ + int len; /** Length of characters in data to send or receive */ + int num; /** Number of characters actually sent or received */ + + /** + * @brief Callback for asynchronous request. + * + * @param uart_req_t* Pointer to the transaction request. + * @param int Error code. + * + */ + void(*callback)(uart_req_t*, int); +}; + + +/***** Functions Prototypes *****/ + + +/** + * @brief Initialize and enable UART module. + * @param uart Pointer to the UART registers. + * @param cfg Pointer to UART configuration. + * @param sys_cfg Pointer to system configuration object + * @returns #E_NO_ERROR UART initialized successfully, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t* sys_cfg); + +/** + * @brief Shutdown UART module. + * @param uart Pointer to the UART registers. + * @returns #E_NO_ERROR UART shutdown successfully, @ref MXC_Error_Codes "error" if + * unsuccessful. + */ +int UART_Shutdown(mxc_uart_regs_t *uart); + +/** + * @brief UART interrupt handler. + * @details This function should be called by the application from the + * interrupt handler if UART interrupts are enabled. Alternately, + * this function can be periodically called by the application if + * UART interrupts are disabled. It is only necessary to call this + * when using asynchronous functions. + * + * @param uart Pointer to the UART registers. + */ +void UART_Handler(mxc_uart_regs_t *uart); + +/** + * @brief Read UART data, blocking until transaction is complete. + * + * @param uart Pointer to the UART registers. + * @param data Pointer to buffer to save the data read. + * @param len Number of bytes to read. + * @param num Pointer to store the number of bytes actually read, pass NULL if not needed. + * + * @return Number of bytes read, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int UART_Read(mxc_uart_regs_t *uart, uint8_t *data, int len, int *num); + +/** + * @brief Write UART data. This function blocks until the write transaction + * is complete. + * @param uart Pointer to the UART registers. + * @param data Pointer to buffer for write data. + * @param len Number of bytes to write. + * @note This function will return once data has been put into FIFO, not necessarily + * transmitted. + * @return Number of bytes written if successful, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int UART_Write(mxc_uart_regs_t *uart, const uint8_t *data, int len); + +/** + * @brief Asynchronously read UART data. + * + * @param uart Pointer to the UART registers. + * @param req Pointer to request for a UART transaction, see #uart_req. + * @note Request struct must remain allocated until callback function specified in 'req' is called. + * + * @return #E_NO_ERROR Asynchronous read successfully started, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req); + +/** + * @brief Asynchronously write/transmit UART data. + * + * @param uart Pointer to the UART registers. + * @param req Request for a UART transaction, see #uart_req. + * @note Request struct must remain allocated until callback function specified in 'req' is called. + * + * @return #E_NO_ERROR Asynchronous write successfully started, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req); + +/** + * @brief Read a single byte from the UART. + * @note This function will block until a character is available. + * + * @param uart Pointer to the UART registers. + * @return The byte read. + */ +uint8_t UART_ReadByte(mxc_uart_regs_t *uart); + +/** + * @brief Write one byte at a time to the UART. + * @note This function will block until the character has been placed in the transmit FIFO. + * It may return before the character is actually transmitted. + * + * @param uart Pointer to the UART registers. + * @param data The byte to write. + */ +void UART_WriteByte(mxc_uart_regs_t *uart, uint8_t data); + +/** + * @brief Check to see if the UART is busy. + * + * @param uart Pointer to the UART registers. + * + * @return #E_NO_ERROR if the UART is idle, #E_BUSY if the UART is in use. + */ +int UART_Busy(mxc_uart_regs_t *uart); + +/** + * @brief Prepare the UART for entry into a Low-Power mode (DEEPSLEEP/BACKUP). + * @details Checks for any ongoing transactions. Disables interrupts if the + * UART is idle. + * + * @param uart Pointer to the UART registers. + * @return #E_NO_ERROR UART is ready to enter Low-Power modes (DEEPSLEEP/BACKUP). + * @return #E_BUSY UART is active and busy and not ready to enter a + * Low-Power mode (DEEPSLEEP/BACKUP). + * + */ +int UART_PrepForSleep(mxc_uart_regs_t *uart); + +/** + * @brief Abort asynchronous request. + * + * @param req Pointer to the request to abort. See #uart_req. + * + * @return #E_NO_ERROR if the asynchronous request aborted successfully started, @ref + * MXC_Error_Codes "error" if unsuccessful. + */ +int UART_AbortAsync(uart_req_t *req); + +/** + * @brief Returns the number of bytes still pending transmission in the UART TX FIFO. + * + * @param uart Pointer to the UART registers. + * + * @return Number of unused bytes in the TX FIFO. + */ +unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart); + +/** + * @brief Returns the number of bytes available to be read from the RX FIFO. + * + * @param uart Pointer to the UART registers. + * + * @return The number of bytes available to read in the RX FIFO. + */ +unsigned UART_NumReadAvail(mxc_uart_regs_t *uart); + +/** + * @brief Clears the specified interrupt flags. + * + * @param uart Pointer to the UART registers. + * @param mask Mask of the UART interrupts to clear, see + * @ref UART_INT_FL Register. + */ +void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask); + +/** + * @brief Get the UART interrupt flags. + * + * @param uart Pointer to the UART registers. + * + * @return Mask of active flags. + */ +unsigned UART_GetFlags(mxc_uart_regs_t *uart); + +/** + * @brief Enables the UART. + * @note This function does not change the existing UART configuration. + * + * @param uart Pointer to the UART registers. + */ +void UART_Enable(mxc_uart_regs_t *uart); + +/** + * @brief Disables the UART. + * @note This function does not change the existing UART configuration. + * + * @param uart Pointer to the UART registers. + */ +void UART_Disable(mxc_uart_regs_t *uart); + +/** + * @brief Drains/empties and data in the RX FIFO, discarding any bytes not yet consumed. + * + * @param uart Pointer to the UART registers. + */ +void UART_DrainRX(mxc_uart_regs_t *uart); + +/** + * @brief Drains/empties any data in the TX FIFO, discarding any bytes not yet transmitted. + * + * @param uart Pointer to the UART registers. + */ +void UART_DrainTX(mxc_uart_regs_t *uart); + +/**@} end of group uart */ + +#endif /* _UART_H_ */ diff --git a/Project/SDK/Driver/Include/wdt.h b/Project/SDK/Driver/Include/wdt.h new file mode 100644 index 0000000..068cef2 --- /dev/null +++ b/Project/SDK/Driver/Include/wdt.h @@ -0,0 +1,166 @@ +/** + * @file wdt.h + * @brief Watchdog timer (WDT) function prototypes and data types. + */ + +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2020-04-20 15:06:58 -0500 (Mon, 20 Apr 2020) $ + * $Revision: 53142 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _WDT_H_ +#define _WDT_H_ + +/* **** Includes **** */ +#include +#include "mxc_config.h" +#include "mxc_sys.h" +#include "wdt_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup wdt Watchdog Timer (WDT) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +/** @brief Watchdog period enumeration. + Used to configure the period of the watchdog interrupt */ +typedef enum { + WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31, /**< Period 2^31 */ + WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30, /**< Period 2^30 */ + WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29, /**< Period 2^29 */ + WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28, /**< Period 2^28 */ + WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27, /**< Period 2^27 */ + WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26, /**< Period 2^26 */ + WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25, /**< Period 2^25 */ + WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24, /**< Period 2^24 */ + WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23, /**< Period 2^23 */ + WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22, /**< Period 2^22 */ + WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21, /**< Period 2^21 */ + WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20, /**< Period 2^20 */ + WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19, /**< Period 2^19 */ + WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18, /**< Period 2^18 */ + WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17, /**< Period 2^17 */ + WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16, /**< Period 2^16 */ +} wdt_period_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the Watchdog Timer + * @param wdt Pointer to the watchdog registers + * @param sys_cfg The system configuration object + */ +int WDT_Init(mxc_wdt_regs_t* wdt, sys_cfg_wdt_t sys_cfg); +/** + * @brief Set the period of the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + * @param period Enumeration of the desired watchdog period. + */ +void WDT_SetIntPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period); + +/** + * @brief Set the period of the watchdog reset. + * @param wdt Pointer to watchdog registers. + * @param period Enumeration of the desired watchdog period. + */ +void WDT_SetResetPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period); + +/** + * @brief Enable the watchdog timer. + * @param wdt Pointer to watchdog registers. + * @param enable 1 to enable the timer, 0 to disable. + */ +void WDT_Enable(mxc_wdt_regs_t* wdt, int enable); + +/** + * @brief Enable the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + * @param enable 1 to enable the interrupt, 0 to disable. + */ +void WDT_EnableInt(mxc_wdt_regs_t* wdt, int enable); + +/** + * @brief Enable the watchdog reset. + * @param wdt Pointer to watchdog registers. + * @param enable 1 to enable the reset, 0 to disable. + */ +void WDT_EnableReset(mxc_wdt_regs_t* wdt, int enable); + +/** + * @brief Reset the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void WDT_ResetTimer(mxc_wdt_regs_t* wdt); + +/** + * @brief Get the status of the reset flag. + * @param wdt Pointer to watchdog registers. + * @returns 1 if the previous reset was caused by the watchdog, 0 otherwise. + */ +int WDT_GetResetFlag(mxc_wdt_regs_t* wdt); + +/** + * @brief Clears the reset flag. + * @param wdt Pointer to watchdog registers. + */ +void WDT_ClearResetFlag(mxc_wdt_regs_t* wdt); + +/** + * @brief Get the status of the interrupt flag. + * @param wdt Pointer to watchdog registers. + * @returns 1 if the interrupt is pending, 0 otherwise. + */ +int WDT_GetIntFlag(mxc_wdt_regs_t* wdt); + +/** + * @brief Clears the interrupt flag. + * @param wdt Pointer to watchdog registers. + */ +void WDT_ClearIntFlag(mxc_wdt_regs_t* wdt); + +/**@} end of group wdt */ + +#ifdef __cplusplus +} +#endif + +#endif /* _WDT_H_ */ diff --git a/Project/SDK/Driver/Source/dma.c b/Project/SDK/Driver/Source/dma.c new file mode 100644 index 0000000..51aac68 --- /dev/null +++ b/Project/SDK/Driver/Source/dma.c @@ -0,0 +1,374 @@ +/* ***************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-07-01 11:06:19 -0500 (Mon, 01 Jul 2019) $ + * $Revision: 44383 $ + * + **************************************************************************** */ + +#include +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "dma.h" + +/* + * Structure type + */ +typedef struct { + unsigned int valid; /* Flag to invalidate this resource */ + unsigned int instance; /* Hardware instance of this DMA controller */ + unsigned int id; /* Channel ID, which matches the index into the underlying hardware */ + mxc_dma_ch_regs_t *regs; /* Pointer to the registers for this channel */ + void (*cb)(int, int); /* Pointer to a callback function type */ +} dma_channel_t; + +#define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) + +/* DMA driver must be initialized once before use, and may not be initialized again without shutdown, as it is a shared resource */ +static unsigned int dma_initialized = 0; + +static dma_channel_t dma_resource[MXC_DMA_CHANNELS]; + +static uint32_t dma_lock; + +/* Initialize DMA to known state */ +int DMA_Init(void) +{ + int i; + + if (dma_initialized) { + return E_BAD_STATE; + } + + /* Initialize any system-level DMA settings */ + SYS_DMA_Init(); + + /* Initialize mutex */ + mxc_free_lock(&dma_lock); + if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } + + /* Ensure all channels are disabled at start, clear flags, init handles */ + MXC_DMA->cn = 0; + for (i = 0; i < MXC_DMA_CHANNELS; i++) { + dma_resource[i].valid = 0; + dma_resource[i].instance = 0; + dma_resource[i].id = i; + dma_resource[i].regs = (mxc_dma_ch_regs_t *)&MXC_DMA->ch[i]; + dma_resource[i].regs->cfg = 0; + dma_resource[i].regs->st = dma_resource[i].regs->st; + + dma_resource[i].cb = NULL; + } + dma_initialized++; + mxc_free_lock(&dma_lock); + + return E_NO_ERROR; +} + +/* Shut down DMA in an orderly manner, informing clients that their requests did not complete */ +int DMA_Shutdown(void) +{ + int i; + + if (!dma_initialized) { + /* Never initialized, so shutdown is not appropriate */ + return E_BUSY; + } + + if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } + + /* Prevent any new resource allocation by this API */ + dma_initialized = 0; + /* Disable interrupts, preventing future callbacks */ + MXC_DMA->cn = 0; + + /* For each channel: + * - invalidate the handles held by clients + * - stop any transfer in progress + */ + for (i = 0; i < MXC_DMA_CHANNELS; i++) { + dma_resource[i].regs->cfg = 0; + if (dma_resource[i].valid) { + dma_resource[i].valid = 0; + if (dma_resource[i].cb != NULL) { + dma_resource[i].cb(i, E_SHUTDOWN); + } + } + } + + /* Disable any system-level DMA settings */ + SYS_DMA_Shutdown(); + + mxc_free_lock(&dma_lock); + + return E_NO_ERROR; +} + +/* Request DMA channel */ +/* Once "owned", this channel may be used directly via the DMA_GetCHRegs(ch) pointer, or */ +/* configured via the API functions */ +int DMA_AcquireChannel(void) +{ + int i, channel; + + /* Check for initialization */ + if (!dma_initialized) { + return E_BAD_STATE; + } + + /* If DMA is locked return busy */ + if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } + + /* Default is no channel available */ + channel = E_NONE_AVAIL; + if (dma_initialized) { + for (i = 0; i < MXC_DMA_CHANNELS; i++) { + if (!dma_resource[i].valid) { + /* Found one */ + channel = i; + dma_resource[i].valid = 1; + dma_resource[i].regs->cfg = 0; + dma_resource[i].regs->cnt_rld = 0; /* Used by DMA_Start() to conditionally set RLDEN */ + break; + } + } + } + mxc_free_lock(&dma_lock); + + return channel; +} + +/* Release DMA channel */ +/* Callbacks will not be called */ +int DMA_ReleaseChannel(int ch) +{ + if (CHECK_HANDLE(ch)) { + if (mxc_get_lock(&dma_lock, 1) != E_NO_ERROR) { + return E_BUSY; + } + dma_resource[ch].valid = 0; + dma_resource[ch].regs->cfg = 0; + dma_resource[ch].regs->st = dma_resource[ch].regs->st; + mxc_free_lock(&dma_lock); + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* Channel configuration */ +int DMA_ConfigChannel(int ch, + dma_priority_t prio, + dma_reqsel_t reqsel, unsigned int reqwait_en, + dma_timeout_t tosel, dma_prescale_t pssel, + dma_width_t srcwd, unsigned int srcinc_en, + dma_width_t dstwd, unsigned int dstinc_en, + unsigned int burst_size, unsigned int chdis_inten, + unsigned int ctz_inten) +{ + if (CHECK_HANDLE(ch) && (burst_size > 0)) { + /* Designed to be safe, not speedy. Should not be called often */ + dma_resource[ch].regs->cfg = + ((reqwait_en ? MXC_F_DMA_CFG_REQWAIT : 0) | + (srcinc_en ? MXC_F_DMA_CFG_SRCINC : 0) | + (dstinc_en ? MXC_F_DMA_CFG_DSTINC : 0) | + (chdis_inten ? MXC_F_DMA_CFG_CHDIEN : 0) | + (ctz_inten ? MXC_F_DMA_CFG_CTZIEN : 0) | + prio |reqsel | tosel | pssel | + (srcwd << MXC_F_DMA_CFG_SRCWD_POS) | + (dstwd << MXC_F_DMA_CFG_DSTWD_POS) | + (((burst_size - 1) << MXC_F_DMA_CFG_BRST_POS) & MXC_F_DMA_CFG_BRST)); + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* + * DMA request selects for peripherals will override either src_addr or dst_addr. + * In these cases, the overridden address is a don't care and may be 0. + */ +int DMA_SetSrcDstCnt(int ch, + void *src_addr, + void *dst_addr, + unsigned int count) +{ + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->src = (unsigned int)src_addr; + dma_resource[ch].regs->dst = (unsigned int)dst_addr; + dma_resource[ch].regs->cnt = count; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* Must set en_reload == 1 to have any effect */ +int DMA_SetReload(int ch, + void *src_addr_reload, + void *dst_addr_reload, + unsigned int count_reload) +{ + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->src_rld = (unsigned int)src_addr_reload; + dma_resource[ch].regs->dst_rld = (unsigned int)dst_addr_reload; + if (dma_resource[ch].regs->cfg & MXC_F_DMA_CFG_CHEN) { + /* If channel is already running, set RLDEN to enable next reload */ + dma_resource[ch].regs->cnt_rld = MXC_F_DMA_CNT_RLD_RLDEN | count_reload; + } else { + /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */ + dma_resource[ch].regs->cnt_rld = count_reload; + } + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int DMA_SetCallback(int ch, void (*callback)(int, int)) +{ + if (CHECK_HANDLE(ch)) { + /* Callback for interrupt handler, no checking is done, as NULL is valid for (none) */ + dma_resource[ch].cb = callback; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* Interrupt enable/disable */ +int DMA_EnableInterrupt(int ch) +{ + if (CHECK_HANDLE(ch)) { + MXC_DMA->cn |= (1 << ch); + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int DMA_DisableInterrupt(int ch) +{ + if (CHECK_HANDLE(ch)) { + MXC_DMA->cn &= ~(1 << ch); + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* Channel interrupt flags */ +int DMA_GetFlags(int ch, unsigned int *fl) +{ + if (CHECK_HANDLE(ch) && fl) { + *fl = dma_resource[ch].regs->st; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int DMA_ClearFlags(int ch) +{ + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->st = dma_resource[ch].regs->st; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* Start channel */ +int DMA_Start(int ch) +{ + if (CHECK_HANDLE(ch)) { + DMA_ClearFlags(ch); + if (dma_resource[ch].regs->cnt_rld) { + dma_resource[ch].regs->cfg |= (MXC_F_DMA_CFG_CHEN | MXC_F_DMA_CFG_RLDEN); + } else { + dma_resource[ch].regs->cfg |= MXC_F_DMA_CFG_CHEN; + } + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* Stop channel */ +int DMA_Stop(int ch) +{ + if (CHECK_HANDLE(ch)) { + dma_resource[ch].regs->cfg &= ~MXC_F_DMA_CFG_CHEN; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* Get pointer to registers, for advanced users */ +mxc_dma_ch_regs_t *DMA_GetCHRegs(int ch) +{ + if (CHECK_HANDLE(ch)) { + return dma_resource[ch].regs; + } else { + return NULL; + } +} + +/* */ +void DMA_Handler(int ch) +{ + /* Do callback, if enabled */ + if (dma_resource[ch].cb != NULL) { + dma_resource[ch].cb(ch, E_NO_ERROR); + } + DMA_ClearFlags(ch); +} diff --git a/Project/SDK/Driver/Source/flc.c b/Project/SDK/Driver/Source/flc.c new file mode 100644 index 0000000..1b554fe --- /dev/null +++ b/Project/SDK/Driver/Source/flc.c @@ -0,0 +1,579 @@ +/** + * @file flc.h + * @brief Flash Controler driver. + * @details This driver can be used to operate on the embedded flash memory. + */ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $ + * $Revision: 43696 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_config.h" +#include "mxc_sys.h" +#include "flc.h" +#include "flc_regs.h" + + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +// ***************************************************************************** +#if defined (__ICCARM__) +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +static int prepare_flc(void) +{ + // Set flash clock divider to generate a 1MHz clock from the APB clock + MXC_FLC->clkdiv = SystemCoreClock / 1000000; + + /* Check if the flash controller is busy */ + if (FLC_Busy()) { + return E_BUSY; + } + + /* Clear stale errors */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { + MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; + } + + /* Unlock flash */ + MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_UNLOCK) | MXC_S_FLC_CN_UNLOCK_UNLOCKED; + + return E_NO_ERROR; +} + +// ***************************************************************************** +#if defined (__ICCARM__) +// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM. +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_Init(const sys_cfg_flc_t *sys_cfg) +{ + SYS_FLC_Init(sys_cfg); + + return E_NO_ERROR; +} + +// ***************************************************************************** +#if defined (__ICCARM__) +// IAR memory section declaration for the in-system flash programming functions to be loaded in RAM. +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_Busy(void) +{ + return (MXC_FLC->cn & (MXC_F_FLC_CN_WR | MXC_F_FLC_CN_ME | MXC_F_FLC_CN_PGE)); +} + +// ***************************************************************************** +#if defined (__ICCARM__) +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_MassErase(void) +{ + int err; + + if ((err = prepare_flc()) != E_NO_ERROR) + return err; + + /* Write mass erase code */ + MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) | MXC_S_FLC_CN_ERASE_CODE_ERASEALL; + + /* Issue mass erase command */ + MXC_FLC->cn |= MXC_F_FLC_CN_ME; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + /* Lock flash */ + MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK; + + /* Check access violations */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { + MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; + return E_BAD_STATE; + } + + SYS_Flash_Operation(); + + return E_NO_ERROR; +} + +// ***************************************************************************** +#if defined (__ICCARM__) +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_PageErase(uint32_t address) +{ + int err; + + if ((err = prepare_flc()) != E_NO_ERROR) + return err; + + // Align address on page boundary + address = address - (address % MXC_FLASH_PAGE_SIZE); + + /* Write page erase code */ + MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_ERASE_CODE) | MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE; + /* Issue page erase command */ + MXC_FLC->addr = address; + MXC_FLC->cn |= MXC_F_FLC_CN_PGE; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + + /* Lock flash */ + MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK; + + /* Check access violations */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { + MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; + return E_BAD_STATE; + } + + SYS_Flash_Operation(); + + return E_NO_ERROR; +} + +// ***************************************************************************** +#if defined (__ICCARM__) +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_Erase(uint32_t start, uint32_t end) +{ + int retval; + uint32_t addr; + + // Align start and end on page boundaries + start = start - (start % MXC_FLASH_PAGE_SIZE); + end = end - (end % MXC_FLASH_PAGE_SIZE); + + for (addr = start; addr <= end; addr += MXC_FLASH_PAGE_SIZE) { + retval = FLC_PageErase(addr); + if (retval != E_NO_ERROR) { + return retval; + } + } + + return E_NO_ERROR; +} + +// ***************************************************************************** +#if defined (__ICCARM__) +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_BufferErase(uint32_t start, uint32_t end, uint8_t *buffer, unsigned length) +{ + int retval; + uint32_t start_align, start_len, end_align, end_len; + + // Align start and end on page boundaries, calculate length of data to buffer + start_align = start - (start % MXC_FLASH_PAGE_SIZE); + start_len = (start % MXC_FLASH_PAGE_SIZE); + end_align = end - (end % MXC_FLASH_PAGE_SIZE); + end_len = ((MXC_FLASH_PAGE_SIZE - (end % MXC_FLASH_PAGE_SIZE)) % MXC_FLASH_PAGE_SIZE); + + // Make sure the length of buffer is sufficient + if ((length < start_len) || (length < end_len)) { + return E_BAD_PARAM; + } + + + // Start and end address are in the same page + if (start_align == end_align) { + if (length < (start_len + end_len)) { + return E_BAD_PARAM; + } + + // Buffer first page data and last page data, erase and write + memcpy(buffer, (void*)start_align, start_len); + memcpy(&buffer[start_len], (void*)end, end_len); + retval = FLC_PageErase(start_align); + if (retval != E_NO_ERROR) { + return retval; + } + + retval = FLC_Write(start_align, start_len, buffer); + if (retval != E_NO_ERROR) { + return retval; + } + retval = FLC_Write(end, end_len, &buffer[start_len]); + if (retval != E_NO_ERROR) { + return retval; + } + + return E_NO_ERROR; + } + + // Buffer, erase, and write the data in the first page + memcpy(buffer, (void*)start_align, start_len); + retval = FLC_PageErase(start_align); + if (retval != E_NO_ERROR) { + return retval; + } + + retval = FLC_Write(start_align, start_len, buffer); + if (retval != E_NO_ERROR) { + return retval; + } + + // Buffer, erase, and write the data in the last page + memcpy(buffer, (void*)end, end_len); + retval = FLC_PageErase(end_align); + if (retval != E_NO_ERROR) { + return retval; + } + + retval = FLC_Write(end, end_len, buffer); + if (retval != E_NO_ERROR) { + return retval; + } + + // Erase the remaining pages + if (start_align != end_align) { + return FLC_Erase((start_align + MXC_FLASH_PAGE_SIZE), (end_align - MXC_FLASH_PAGE_SIZE)); + } + + return E_NO_ERROR; +} + +// ***************************************************************************** +#if defined (__ICCARM__) +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_Write32(uint32_t address, uint32_t data) +{ + int err; + + // Address checked if it is byte addressable + if (address & 0x3) { + return E_BAD_PARAM; + } + + if ((err = prepare_flc()) != E_NO_ERROR) + return err; + + // write in 32-bit units + MXC_FLC->cn |= MXC_F_FLC_CN_WDTH; + MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST; + + // write the data + MXC_FLC->addr = address; + MXC_FLC->data[0] = data; + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + + /* Wait until flash operation is complete */ + while (FLC_Busy()) {} + + /* Lock flash */ + MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK; + + /* Check access violations */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { + MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; + return E_BAD_STATE; + } + + SYS_Flash_Operation(); + + return E_NO_ERROR; +} + +// ***************************************************************************** +#if defined (__ICCARM__) +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_Write128(uint32_t address, uint32_t *data) +{ + int err; + + // Address checked if it is word addressable + if (address & 0xF) { + return E_BAD_PARAM; + } + + if ((err = prepare_flc()) != E_NO_ERROR) + return err; + + // write 128-bits + MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH; + + // write the data + MXC_FLC->addr = address; + memcpy((void*)&MXC_FLC->data[0], data, 16); + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + + /* Lock flash */ + MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK; + + /* Check access violations */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { + MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; + return E_BAD_STATE; + } + + SYS_Flash_Operation(); + + return E_NO_ERROR; +} + +// ***************************************************************************** +#if defined (__ICCARM__) +#pragma section=".flashprog" +#endif +#if defined ( __GNUC__ ) +__attribute__ ((section(".flashprog"))) +#endif +int FLC_Write(uint32_t address, uint32_t length, uint8_t *buffer) +{ + int err; + uint32_t bytes_written; + uint8_t current_data[4]; + + if ((err = prepare_flc()) != E_NO_ERROR) + return err; + + // write in 32-bit units until we are 128-bit aligned + MXC_FLC->cn &= ~MXC_F_FLC_CN_BRST; + MXC_FLC->cn |= MXC_F_FLC_CN_WDTH; + + // Align the address and read/write if we have to + if (address & 0x3) { + + // Figure out how many bytes we have to write to round up the address + bytes_written = 4 - (address & 0x3); + + // Save the data currently in the flash + memcpy(current_data, (void*)(address & (~0x3)), 4); + + // Modify current_data to insert the data from buffer + memcpy(¤t_data[4-bytes_written], buffer, bytes_written); + + // Write the modified data + MXC_FLC->addr = address - (address % 4); + memcpy((void*)&MXC_FLC->data[0], ¤t_data, 4); + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + + address += bytes_written; + length -= bytes_written; + buffer += bytes_written; + } + + while ( (length >= 4) && ((address & 0xF) != 0) ) { + MXC_FLC->addr = address; + memcpy((void*)&MXC_FLC->data[0], buffer, 4); + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + + address += 4; + length -= 4; + buffer += 4; + } + + if (length >= 16) { + + // write in 128-bit bursts while we can + MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH; + + while (length >= 16) { + MXC_FLC->addr = address; + memcpy((void*)&MXC_FLC->data[0], buffer, 16); + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + + address += 16; + length -= 16; + buffer += 16; + } + + // Return to 32-bit writes. + MXC_FLC->cn |= MXC_F_FLC_CN_WDTH; + } + + while (length >= 4) { + MXC_FLC->addr = address; + memcpy((void*)&MXC_FLC->data[0], buffer, 4); + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + + address += 4; + length -= 4; + buffer += 4; + } + + if (length > 0) { + // Save the data currently in the flash + memcpy(current_data, (void*)(address), 4); + + // Modify current_data to insert the data from buffer + memcpy(current_data, buffer, length); + + MXC_FLC->addr = address; + memcpy((void*)&MXC_FLC->data[0], current_data, 4); + MXC_FLC->cn |= MXC_F_FLC_CN_WR; + + /* Wait until flash operation is complete */ + while (FLC_Busy()); + } + + /* Lock flash */ + MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK; + + /* Check access violations */ + if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) { + MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF; + return E_BAD_STATE; + } + + SYS_Flash_Operation(); + + return E_NO_ERROR; +} + +int FLC_EnableInt(uint32_t mask) +{ + uint32_t tmp; + + mask &= (MXC_F_FLC_INTR_DONEIE | MXC_F_FLC_INTR_AFIE); + if (!mask) { + /* No bits set? Wasn't something we can enable. */ + return E_BAD_PARAM; + } + + /* Careful with access_fail bit, as it is W0C */ + tmp = MXC_FLC->intr | MXC_F_FLC_INTR_AF; + /* Don't lose done flag */ + tmp &= ~(MXC_F_FLC_INTR_DONE); + /* Apply enables and write back */ + MXC_FLC->intr = (tmp | mask); + + return E_NO_ERROR; +} + +int FLC_DisableInt(uint32_t mask) +{ + uint32_t tmp; + + mask &= (MXC_F_FLC_INTR_DONEIE | MXC_F_FLC_INTR_AFIE); + if (!mask) { + /* No bits set? Wasn't something we can disable. */ + return E_BAD_PARAM; + } + + /* Careful with access_fail bit, as it is W0C */ + tmp = MXC_FLC->intr | MXC_F_FLC_INTR_AF; + /* Don't lose done flag */ + tmp &= ~(MXC_F_FLC_INTR_DONE); + /* Apply disables and write back */ + MXC_FLC->intr = (tmp & ~mask); + + return E_NO_ERROR; +} + +int FLC_GetFlags(void) +{ + return (MXC_FLC->intr & (MXC_F_FLC_INTR_DONE | MXC_F_FLC_INTR_AF)); +} + +int FLC_ClearFlags(uint32_t mask) +{ + mask &= (MXC_F_FLC_INTR_DONE | MXC_F_FLC_INTR_AF); + if (!mask) { + /* No bits set? Wasn't something we can clear. */ + return E_BAD_PARAM; + } + + // Both bits are write zero clear + MXC_FLC->intr ^= mask; + + return E_NO_ERROR; +} + +int FLC_UnlockInfoBlock() +{ + MXC_FLC->acntl = 0x3a7f5ca3; + MXC_FLC->acntl = 0xa1e34f20; + MXC_FLC->acntl = 0x9608b2c1; + return E_NO_ERROR; +} + +int FLC_LockInfoBlock() +{ + MXC_FLC->acntl = 0xDEADBEEF; + return E_NO_ERROR; +} diff --git a/Project/SDK/Driver/Source/gpio.c b/Project/SDK/Driver/Source/gpio.c new file mode 100644 index 0000000..0960481 --- /dev/null +++ b/Project/SDK/Driver/Source/gpio.c @@ -0,0 +1,312 @@ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_assert.h" +#include "gpio.h" +#include + +/* **** Definitions **** */ + +/* **** Globals **** */ + +static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *); +static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT]; + +/* **** Functions **** */ + +int GPIO_Init(void) +{ + int i; + int j; + + // Initialize call back arrays + for(i = 0; i < MXC_CFG_GPIO_INSTANCES; i++) { + for(j = 0; j < MXC_CFG_GPIO_PINS_PORT; j++) { + callback[i][j] = NULL; + } + } + return E_NO_ERROR; +} + +/* ************************************************************************** */ +/* + * GPIO_EN2 | GPIO_EN1 | GPIO_EN | Function + * --------------|---------------------|---------------------|---------------------- + * 0 | 0 | 0 | Alternative 1 + * 0 | 1 | 0 | Alternative 2 + * 1 | 0 | 0 | Alternative 3 + * 1 | 1 | 0 | Alternative 4 + * 0 | 0 | 1 | GPIO (default) +*/ + +int GPIO_Config(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + // Set the GPIO type + switch (cfg->func) { + case GPIO_FUNC_IN: + gpio->out_en_clr = cfg->mask; + gpio->en_set = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; + break; + case GPIO_FUNC_OUT: + gpio->out_en_set = cfg->mask; + gpio->en_set = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; + break; + case GPIO_FUNC_ALT1: + gpio->en_clr = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_clr = cfg->mask; + break; + case GPIO_FUNC_ALT2: + gpio->en_clr = cfg->mask; + gpio->en1_set = cfg->mask; + gpio->en2_clr = cfg->mask; + break; + case GPIO_FUNC_ALT3: +#if TARGET==32660 + gpio->en_set = cfg->mask; + gpio->en1_set = cfg->mask; +#else + gpio->en_clr = cfg->mask; + gpio->en1_clr = cfg->mask; + gpio->en2_set = cfg->mask; +#endif + break; + case GPIO_FUNC_ALT4: + gpio->en_clr = cfg->mask; + gpio->en1_set = cfg->mask; + gpio->en2_set = cfg->mask; + break; + default: + return E_BAD_PARAM; + } + + // Configure the pad + switch (cfg->pad) { + case GPIO_PAD_NONE: + gpio->pad_cfg1 &= ~cfg->mask; + gpio->pad_cfg2 &= ~cfg->mask; +#if TARGET==32660 + gpio->ps &= ~cfg->mask; +#endif + break; + case GPIO_PAD_PULL_UP: + gpio->pad_cfg1 |= cfg->mask; + gpio->pad_cfg2 &= ~cfg->mask; +#if TARGET==32660 + gpio->ps |= cfg->mask; +#endif + break; + case GPIO_PAD_PULL_DOWN: + gpio->pad_cfg1 &= ~cfg->mask; + gpio->pad_cfg2 |= cfg->mask; +#if TARGET==32660 + gpio->ps &= ~cfg->mask; +#endif + break; + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +uint32_t GPIO_InGet(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + return (gpio->in & cfg->mask); +} + +/* ************************************************************************** */ +void GPIO_OutSet(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + gpio->out_set = cfg->mask; +} + +/* ************************************************************************** */ +void GPIO_OutClr(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + gpio->out_clr = cfg->mask; +} + +/* ************************************************************************** */ +uint32_t GPIO_OutGet(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + return (gpio->out & cfg->mask); +} + +/* ************************************************************************** */ +void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + gpio->out = (gpio->out & ~cfg->mask) | (val & cfg->mask); +} + +/* ************************************************************************** */ +void GPIO_OutToggle(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + gpio->out ^= cfg->mask; +} + +/* ************************************************************************** */ +int GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode, gpio_int_pol_t pol) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + switch (mode) { + case GPIO_INT_LEVEL: + gpio->int_mod &= ~cfg->mask; + break; + case GPIO_INT_EDGE: + gpio->int_mod |= cfg->mask; + break; + default: + return E_BAD_PARAM; + } + + switch (pol) { + case GPIO_INT_FALLING: /* GPIO_INT_HIGH */ + gpio->int_pol &= ~cfg->mask; + gpio->int_dual_edge &= ~cfg->mask; + break; + case GPIO_INT_RISING: /* GPIO_INT_LOW */ + gpio->int_pol |= cfg->mask; + gpio->int_dual_edge &= ~cfg->mask; + break; + case GPIO_INT_BOTH: + gpio->int_dual_edge |= cfg->mask; + break; + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void GPIO_IntEnable(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + gpio->int_en_set = cfg->mask; +} + +/* ************************************************************************** */ +void GPIO_IntDisable(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + gpio->int_en_clr = cfg->mask; +} + +/* ************************************************************************** */ +uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + return (gpio->int_stat & cfg->mask); +} + +/* ************************************************************************** */ +void GPIO_IntClr(const gpio_cfg_t *cfg) +{ + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(cfg->port); + + gpio->int_clr = cfg->mask; +} + +/* ************************************************************************** */ +void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn func, void *cbdata) +{ + uint32_t mask; + unsigned int pin; + + mask = cfg->mask; + pin = 0; + + while (mask) { + if (mask & 1) { + callback[cfg->port][pin] = func; + cbparam[cfg->port][pin] = cbdata; + } + pin++; + mask >>= 1; + } +} + +/* ************************************************************************** */ +void GPIO_Handler(unsigned int port) +{ + uint32_t stat; + unsigned int pin; + + MXC_ASSERT(port < MXC_CFG_GPIO_INSTANCES); + + mxc_gpio_regs_t *gpio = MXC_GPIO_GET_GPIO(port); + + stat = gpio->int_stat; + gpio->int_clr = stat; + + pin = 0; + + while (stat) { + if (stat & 1) { + if(callback[port][pin]) { + callback[port][pin](cbparam[port][pin]); + } + } + pin++; + stat >>= 1; + } +} diff --git a/Project/SDK/Driver/Source/i2c.c b/Project/SDK/Driver/Source/i2c.c new file mode 100644 index 0000000..e89797e --- /dev/null +++ b/Project/SDK/Driver/Source/i2c.c @@ -0,0 +1,1068 @@ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2020-02-03 10:33:50 -0600 (Mon, 03 Feb 2020) $ + * $Revision: 51326 $ + * + *************************************************************************** */ + + +#include +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "i2c.h" +#include +#include "mxc_delay.h" + +/* **** Definitions **** */ +#define I2C_ERROR (MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | MXC_F_I2C_INT_FL0_ADDR_NACK_ER | \ + MXC_F_I2C_INT_FL0_DATA_ER | MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \ + MXC_F_I2C_INT_FL0_STOP_ER) +#define MASTER 1 +#define SLAVE 0 + +/* For high speed mode, if the I2C bus capacitance is greater than 100pF, set this value to ((capacitance - 100) / 3). + Otherwise leave it at 0. */ +#define HS_SCALE_FACTOR (0) + +#define T_LOW_MIN (160 + (160 * HS_SCALE_FACTOR / 100)) /* tLOW minimum in nanoseconds */ +#define T_HIGH_MIN (60 + (60 * HS_SCALE_FACTOR / 100)) /* tHIGH minimum in nanoseconds */ +#define T_R_MAX_HS (40 + (40 * HS_SCALE_FACTOR / 100)) /* tR maximum for high speed mode in nanoseconds */ +#define T_F_MAX_HS (40 + (40 * HS_SCALE_FACTOR / 100)) /* tF maximum for high speed mode in nanoseconds */ +#define T_AF_MIN (10 + (10 * HS_SCALE_FACTOR / 100)) /* tAF minimun in nanoseconds */ + +/* **** Variable Declaration **** */ + +// Saves the state of the non-blocking requests +typedef struct { + i2c_req_t *req; + i2c_state_t state; + uint8_t num_wr; // keep track of number of bytes loaded in the fifo during slave transmit +} i2c_req_state_t; +static i2c_req_state_t states[MXC_I2C_INSTANCES]; + +/* **** Function Prototypes **** */ +static void I2C_MasterHandler(mxc_i2c_regs_t *i2c); +static void I2C_SlaveHandler(mxc_i2c_regs_t *i2c); +static void I2C_FreeCallback(int i2c_num, int error); +static void I2C_Recover(mxc_i2c_regs_t *i2c); + +/* ************************************************************************** */ +static int I2C_Setspeed(mxc_i2c_regs_t * i2c, i2c_speed_t i2cspeed) +{ + uint32_t ticks, ticks_lo, ticks_hi; + + if (i2cspeed == I2C_HS_MODE) { + + uint32_t sys_freq, tPCLK, targBusFreq, tSCLmin, cklMin, ckhMin, ckh_cklMin; + + /* Compute dividers for high speed mode. */ + sys_freq = SYS_I2C_GetFreq(i2c); + MXC_ASSERT(sys_freq >= 1000); + + tPCLK = 1000000 / (sys_freq / 1000); + MXC_ASSERT(tPCLK > 0) + + targBusFreq = i2cspeed - ((i2cspeed/2) * HS_SCALE_FACTOR / 100); + if(targBusFreq < 1000) { + return E_BAD_PARAM; + } + + tSCLmin = 1000000 / (targBusFreq / 1000); + cklMin = ((T_LOW_MIN + T_F_MAX_HS + (tPCLK - 1) - T_AF_MIN) / tPCLK) - 1; + ckhMin = ((T_HIGH_MIN + T_R_MAX_HS + (tPCLK - 1) - T_AF_MIN) / tPCLK) - 1; + ckh_cklMin = ((tSCLmin + (tPCLK - 1)) / tPCLK) - 2; + + ticks_lo = (cklMin > (ckh_cklMin - ckhMin)) ? (cklMin) : (ckh_cklMin - ckhMin); + ticks_hi = ckhMin; + + if((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >> MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) || + (ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >> MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) { + return E_BAD_PARAM; + } + + /* Write results to destination registers. */ + i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) | (ticks_hi << + MXC_F_I2C_HS_CLK_HS_CLK_HI_POS); + + /* Still need to load dividers for the preamble that each high-speed transaction starts with. + Switch setting to fast mode and fall out of if statement. */ + i2cspeed = I2C_FAST_MODE; + } + + /* Get the number of periph clocks needed to achieve selected speed. */ + ticks = SYS_I2C_GetFreq(i2c) / i2cspeed; + + /* For a 50% duty cycle, half the ticks will be spent high and half will be low. */ + ticks_hi = (ticks >> 1) - 1; + ticks_lo = (ticks >> 1) - 1; + + /* Account for rounding error in odd tick counts. */ + if (ticks & 1) { + ticks_hi++; + } + + /* Will results fit into 9 bit registers? (ticks_hi will always be >= ticks_lo. No need to check ticks_lo.) */ + if (ticks_hi > 0x1FF) { + return E_BAD_PARAM; + } + + /* 0 is an invalid value for the destination registers. (ticks_hi will always be >= ticks_lo. No need to check ticks_hi.) */ + if (ticks_lo == 0) { + return E_BAD_PARAM; + } + + /* Write results to destination registers. */ + i2c->clk_lo = ticks_lo; + i2c->clk_hi = ticks_hi; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int I2C_Init(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed, const sys_cfg_i2c_t* sys_cfg) +{ + int err; + int idx = MXC_I2C_GET_IDX(i2c); + // Check the base pointer + MXC_ASSERT(idx >= 0); + + // Set system level configurations + if ((err = SYS_I2C_Init(i2c, sys_cfg)) != E_NO_ERROR) { + return err; + } + + // Always disable the HW autoflush on data NACK and let the SW handle the flushing. + i2c->tx_ctrl0 |= 0x20; + + states[idx].num_wr = 0; + + i2c->ctrl = 0; // clear configuration bits + i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; // Enable I2C + i2c->master_ctrl = 0; // clear master configuration bits + i2c->status = 0; // clear status bits + + /* If either SDA or SCL is already low, there is a problem. + * Try reclaiming the bus by sending clocks until we have control of the SDA line. + * Follow procedure defined in i2c spec. + */ + if ((i2c->ctrl & (MXC_F_I2C_CTRL_SCL | MXC_F_I2C_CTRL_SDA)) != + (MXC_F_I2C_CTRL_SCL | MXC_F_I2C_CTRL_SDA)) { + + int i, have_control; + + // Set SCL/SDA as software controlled. + i2c->ctrl |= MXC_F_I2C_CTRL_SW_OUT_EN; + + // Try to get control of SDA. + for (i = 0; i < 16; i++) { + have_control = 1; + + // Drive SCL low and check its state. + i2c->ctrl &= ~(MXC_F_I2C_CTRL_SCL_OUT); + mxc_delay(MXC_DELAY_USEC(5)); + if ((i2c->ctrl & MXC_F_I2C_CTRL_SCL) == MXC_F_I2C_CTRL_SCL) { + have_control = 0; + } + + // Drive SDA low and check its state. + i2c->ctrl &= ~(MXC_F_I2C_CTRL_SDA_OUT); + mxc_delay(MXC_DELAY_USEC(5)); + if ((i2c->ctrl & MXC_F_I2C_CTRL_SDA) == MXC_F_I2C_CTRL_SDA) { + have_control = 0; + } + + // Release SDA and check its state. + i2c->ctrl |= (MXC_F_I2C_CTRL_SDA_OUT); + mxc_delay(MXC_DELAY_USEC(5)); + if ((i2c->ctrl & MXC_F_I2C_CTRL_SDA) != MXC_F_I2C_CTRL_SDA) { + have_control = 0; + } + + // Release SCL and check its state. + i2c->ctrl |= (MXC_F_I2C_CTRL_SCL_OUT); + mxc_delay(MXC_DELAY_USEC(5)); + if ((i2c->ctrl & MXC_F_I2C_CTRL_SCL) != MXC_F_I2C_CTRL_SCL) { + have_control = 0; + } + + if (have_control) { + // Issue stop + // Drive SDA low. + i2c->ctrl &= ~(MXC_F_I2C_CTRL_SDA_OUT); + mxc_delay(MXC_DELAY_USEC(5)); + // Release SDA. + i2c->ctrl |= (MXC_F_I2C_CTRL_SDA_OUT); + mxc_delay(MXC_DELAY_USEC(5)); + break; + } + } + + if (!have_control) { + return E_COMM_ERR; + } + } + + i2c->ctrl = 0; // clear configuration bits + i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; // Enable I2C + i2c->master_ctrl = 0; // clear master configuration bits + i2c->status= 0; // clear status bits + + // Check for HS mode + if (i2cspeed == I2C_HS_MODE) { + i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE; // Enable HS mode + } + + // Disable and clear interrupts + i2c->int_en0 = 0; + i2c->int_en1 = 0; + i2c->int_fl0 = i2c->int_fl0; + i2c->int_fl1 = i2c->int_fl1; + + i2c->timeout = 0x0; // set timeout + i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; // clear the RX FIFO + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; // clear the TX FIFO + + return I2C_Setspeed(i2c, i2cspeed); +} +/* ************************************************************************** */ +int I2C_Shutdown(mxc_i2c_regs_t *i2c) +{ + int i2c_num, err; + + // Check the base pointer + i2c_num = MXC_I2C_GET_IDX(i2c); + MXC_ASSERT(i2c_num >= 0); + + // Disable and clear interrupts + i2c->int_en0 = 0; + i2c->int_en1 = 0; + i2c->int_fl0 = i2c->int_fl0; + i2c->int_fl1 = i2c->int_fl1; + + i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; // clear the RX FIFO + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; // clear the TX FIFO + + // Call all of the pending callbacks for this I2C + if (states[i2c_num].req != NULL) { + I2C_Recover(i2c); + I2C_FreeCallback(i2c_num, E_SHUTDOWN); + } + + i2c->ctrl = 0; + + // Clears system level configurations + if ((err = SYS_I2C_Shutdown(i2c)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int I2C_MasterWrite(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* data, int len, int restart) +{ + int save_len = len; + + if (len == 0) { + return E_NO_ERROR; + } + + // Clear the lock out bit (W1C) in case it is set. + i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT; + i2c->int_fl0 = i2c->int_fl0; + + // Enable master mode + i2c->ctrl |= MXC_F_I2C_CTRL_MST; + + // Load FIFO with slave address for WRITE and as much data as we can + while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {} + i2c->fifo = addr & ~(0x1); + + while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { + i2c->fifo = *data++; + len--; + } + + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START; + + // Write remaining data to FIFO + while (len > 0) { + + // Check for errors + if (i2c->int_fl0 & I2C_ERROR) { + // Set the stop bit + i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART); + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; + while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP))) {} + + return E_COMM_ERR; + } + + if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { + i2c->fifo = *data++; + len--; + } + } + + if (restart) { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART; + } else { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; + } + + // Wait for Done or time out if enabled + uint32_t wait_timeoutcount = 0; + while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_DONE | I2C_ERROR ))) + { + wait_timeoutcount++; + if(wait_timeoutcount >= 0xFFFF) + { + return E_COMM_ERR; + } + } + + i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE; + + // Wait for Stop + if (!restart) { + while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP ))) {} + + i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP; + } + + // Check for errors + if (i2c->int_fl0 & I2C_ERROR) { + return E_COMM_ERR; + } + + return save_len; +} + +/* ************************************************************************** */ +int I2C_MasterRead(mxc_i2c_regs_t *i2c, uint8_t addr, uint8_t* data, int len, int restart) +{ + int save_len = len; + + if (len == 0) { + return E_NO_ERROR; + } + + if (len > 256) { + return E_BAD_PARAM; + } + + i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT; + i2c->int_fl0 = i2c->int_fl0; + + // Make sure the I2C has been initialized + if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) { + return E_UNINITIALIZED; + } + + // Enable master mode + i2c->ctrl |= MXC_F_I2C_CTRL_MST; + + // Set receive count + i2c->rx_ctrl1= len; + + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START; + + // Load FIFO with slave address + while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {} + i2c->fifo = (addr | 1); + + + // Wait for all data to be received or error + while (len > 0) { + + // Check for errors + if (i2c->int_fl0 & I2C_ERROR) { + // Set the stop bit + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; + return E_COMM_ERR; + } + + if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { + *data++ = i2c->fifo; + len--; + } + } + + if (i2c->int_fl0 & I2C_ERROR) { + // Set the stop bit + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; + return E_COMM_ERR; + } + + if (restart) { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART; + } else { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; + } + + // Wait for Done or time out if enabled + while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_DONE | I2C_ERROR ))) {} + + i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE; + + // Wait for Stop + if (!restart) { + while (!(i2c->int_fl0 & (MXC_F_I2C_INT_FL0_STOP | I2C_ERROR))) { + + } + + i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP; + } + + // Check for errors + if (i2c->int_fl0 & I2C_ERROR) { + return E_COMM_ERR; + } + + return save_len; +} + +/* ************************************************************************** */ +int I2C_Slave(mxc_i2c_regs_t *i2c, uint8_t addr, const uint8_t* read_data, int read_len, + uint8_t* write_data, int write_len, int* tx_num, int* rx_num, + i2c_autoflush_disable_t sw_autoflush_disable) +{ + int i2c_num; + + i2c_num = MXC_I2C_GET_IDX(i2c); + if ((read_data == NULL) && (write_data == NULL)) { + return E_NULL_PTR; + } + + // Make sure the I2C has been initialized + if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) { + return E_UNINITIALIZED; + } + + if ((read_len == 0) && (write_len == 0)) { + return E_NO_ERROR; + } + + if (mxc_get_lock((uint32_t*)&states[i2c_num].req, 1) != E_NO_ERROR) { + return E_BUSY; + } + // Disable master mode + i2c->ctrl &= ~MXC_F_I2C_CTRL_MST; + + // Clear any previous errors + i2c->int_fl0 = i2c->int_fl0; + i2c->int_fl1 = i2c->int_fl1; + + // Set the slave address + i2c->slave_addr = (addr >> 1); + + // Wait for address match + while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH) && !(i2c->int_fl0 & I2C_ERROR)) { + + } + + i2c->int_fl0 = MXC_F_I2C_INT_FL0_ADDR_MATCH; + i2c->int_fl0 = MXC_F_I2C_INT_FL0_TX_LOCK_OUT; + + if (i2c->int_fl0 & I2C_ERROR) { + if (!sw_autoflush_disable) { + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; + i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; + } + mxc_free_lock((uint32_t*)&states[i2c_num]); + return E_COMM_ERR; + } + + // See if we're reading or writing + if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { + // This is the master read/slave write case + if (read_data == NULL || read_len == 0) { + mxc_free_lock((uint32_t*)&states[i2c_num]); + return E_NULL_PTR; + } + + // Wait for all data to be received or error + while (read_len > 0) { + + // Check for errors + if (i2c->int_fl0 & I2C_ERROR) { + *tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS); + states[i2c_num].num_wr = 0; + if (!sw_autoflush_disable) { + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; + } + mxc_free_lock((uint32_t*)&states[i2c_num]); + return E_COMM_ERR; + } + + // Check for nack from master + if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_TX_LOCK_OUT) { + break; + } + + // Check for done bit + if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE) { + break; + } + + if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { + i2c->fifo = *read_data++; + states[i2c_num].num_wr++; + read_len--; + } + } + + // Wait for Done + while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {} + + // Calculate number of bytes sent by the slave + *tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS); + states[i2c_num].num_wr = 0; + if (!sw_autoflush_disable) { + // Flush the TX FIFO + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; + } + + } else { + // This is the master write/slave read case + if (write_data == NULL || write_len == 0) { + mxc_free_lock((uint32_t*)&states[i2c_num]); + return E_NULL_PTR; + } + + // Wait for all data to be written or error + while (write_len > 0) { + + // Check for errors + if (i2c->int_fl0 & I2C_ERROR) { + if (!sw_autoflush_disable) { + i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; + } + mxc_free_lock((uint32_t*)&states[i2c_num]); + return E_COMM_ERR; + } + + // Check for done bit + if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE) { + break; + } + + if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { + *write_data++ = i2c->fifo; + (*rx_num)++; + write_len--; + } + } + + // Wait for Done + while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) { + + } + // Flush the FIFO + if (!sw_autoflush_disable) { + i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; + } + } + + // Check for errors + if (i2c->int_fl0 & I2C_ERROR) { + // Flush the FIFO + if (!sw_autoflush_disable) { + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; + i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; + } + mxc_free_lock((uint32_t*)&states[i2c_num]); + return E_COMM_ERR; + } + mxc_free_lock((uint32_t*)&states[i2c_num]); + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int I2C_MasterAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req) +{ + int i2c_num; + + i2c_num = MXC_I2C_GET_IDX(i2c); + if (req->state == I2C_STATE_READING) { + // Check the parameters + if (req->rx_len == 0) { + return E_NO_ERROR; + } + if (req->rx_data == NULL) { + return E_NULL_PTR; + } + + } else { + // Check the parameters + if (req->tx_len == 0) { + return E_NO_ERROR; + } + if (req->tx_data == NULL) { + return E_NULL_PTR; + } + } + + // Make sure the I2C has been initialized + if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) { + return E_UNINITIALIZED; + } + + // Attempt to register this request + if (mxc_get_lock((uint32_t*)&states[i2c_num].req, (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + states[i2c_num].state = req->state; + states[i2c_num].req = req; + + // Enable master mode + i2c->ctrl |= MXC_F_I2C_CTRL_MST; + + // Clear the byte counters + req->tx_num = 0; + req->rx_num = 0; + + // Disable and clear the interrupts + i2c->int_en0 = 0; + i2c->int_en1 = 0; + i2c->int_fl0 = i2c->int_fl0; + i2c->int_fl1 = i2c->int_fl1; + + // Start the transaction + I2C_MasterHandler(i2c); + return E_NO_ERROR; +} + + +/* ************************************************************************** */ +static void I2C_MasterHandler(mxc_i2c_regs_t *i2c) +{ + + uint32_t int0, inten0 = 0; + int rx_remain, tx_remain, i2c_num; + i2c_req_t *req; + + i2c_num = MXC_I2C_GET_IDX(i2c); + req = states[i2c_num].req; + + // Check for errors + int0 = i2c->int_fl0; + if (int0 & I2C_ERROR) { + + // Set the done bit + i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART); + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; + + i2c->int_en0 = 0; + if (req->callback != NULL) { + I2C_Recover(i2c); + I2C_FreeCallback(i2c_num, E_COMM_ERR); + } + return; + } + + rx_remain = req->rx_len - req->rx_num; + tx_remain = req->tx_len - req->tx_num; + if (req->restart) { + // Check for DONE interrupt + if ((int0 & MXC_F_I2C_INT_FL0_DONE)) { + // Read out any data in the RX FIFO + while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { + *(req->rx_data)++ = i2c->fifo; + req->rx_num++; + rx_remain--; + } + i2c->int_en0 = 0; + if (req->callback != NULL) { + I2C_Recover(i2c); + I2C_FreeCallback(i2c_num, E_NO_ERROR); + } + return; + } + } else { + // Check for STOP interrupt + if ((int0 & MXC_F_I2C_INT_FL0_STOP)) { + i2c->int_en0 = 0; + if (req->callback != NULL) { + I2C_Recover(i2c); + I2C_FreeCallback(i2c_num, E_NO_ERROR); + } + + return; + } + + // Check for DONE interrupt + if ((int0 & MXC_F_I2C_INT_FL0_DONE)) { + // Read out any data in the RX FIFO + while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { + *(req->rx_data)++ = i2c->fifo; + req->rx_num++; + rx_remain--; + } + + return; + } + } + + // Clear the interrupts + i2c->int_fl0 = int0; + + if (states[i2c_num].state == I2C_STATE_READING) { + + + // Read out any data in the RX FIFO + while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { + *(req->rx_data)++ = i2c->fifo; + req->rx_num++; + rx_remain--; + } + + // Load the slave address if we haven't already started reading the data + if (rx_remain == req->rx_len) { + i2c->fifo = (req->addr | 1); + + // Set the RX Count + i2c->rx_ctrl1 = req->rx_len; + + // Start transmission if idle + if (!(i2c->status & MXC_F_I2C_STATUS_BUS)) { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START; + } + + // Set restart or stop + if (req->restart) { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART; + } else { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; + inten0 |= MXC_F_I2C_INT_EN0_STOP; + } + } + + // Set the RX threshold interrupt level + if (rx_remain >= (MXC_I2C_FIFO_DEPTH - 1)) { + i2c->rx_ctrl1 = ((i2c->rx_ctrl1 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | + (MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); + + inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH; + }else{ + i2c->rx_ctrl1 = ((i2c->rx_ctrl1 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | + (rx_remain) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); + + inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH; + } + + } else { + + // Load the slave address if we haven't already started writing the data + if (tx_remain == req->tx_len) { + i2c->fifo = req->addr; + // Start transmission if idle + if (!(i2c->status & MXC_F_I2C_STATUS_BUS)) { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START; + } + } + + // Fill the FIFO + while ((tx_remain > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { + i2c->fifo = *(req->tx_data)++; + req->tx_num++; + tx_remain--; + } + + // Set the TX threshold interrupt level, or restart/stop + if (tx_remain) { + i2c->tx_ctrl1 = ((i2c->tx_ctrl1 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | (1 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)); + inten0 |= MXC_F_I2C_INT_EN0_TX_THRESH; + } + // Set restart or stop if at the end of the transaction since these actions happen at the moment the bit is set. + else if (req->restart) { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART; + } else { + i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP; + inten0 |= MXC_F_I2C_INT_EN0_STOP; + } + } + + inten0 |= (MXC_F_I2C_INT_EN0_DONE | I2C_ERROR); + i2c->int_en0 = inten0; +} + +/* ************************************************************************** */ +int I2C_SlaveAsync(mxc_i2c_regs_t *i2c, i2c_req_t *req) +{ + int i2c_num; + + i2c_num = MXC_I2C_GET_IDX(i2c); + + // Make sure the I2C has been initialized + if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) { + return E_UNINITIALIZED; + } + + // Attempt to register this request + if (mxc_get_lock((uint32_t*)&states[i2c_num].req, (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + states[i2c_num].req = req; + + // Set Slave Address + i2c->slave_addr = (req->addr >> 1); + + // Clear the byte counters + req->tx_num = 0; + req->rx_num = 0; + + // Disable and clear the interrupts + i2c->int_en0 = 0; + i2c->int_en1 = 0; + i2c->int_fl0 = i2c->int_fl0; + i2c->int_fl1 = i2c->int_fl1; + i2c->int_en0 |= MXC_F_I2C_INT_EN0_ADDR_MATCH; + + return E_NO_ERROR; +} +/* ************************************************************************** */ +static void I2C_SlaveHandler(mxc_i2c_regs_t *i2c) +{ + uint32_t int0, inten0 = 0; + int rx_remain, tx_remain, i2c_num; + i2c_req_t *req; + + i2c_num = MXC_I2C_GET_IDX(i2c); + req = states[i2c_num].req; + + if ( i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH ) { + i2c->int_fl0 |=MXC_F_I2C_INT_EN0_STOP; + } + + // Check for errors + int0 = i2c->int_fl0; + if (int0 & I2C_ERROR) { + i2c->int_en0 = 0; + // Calculate the number of bytes sent by the slave + req->tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS); + + if (!req->sw_autoflush_disable) { + // Manually clear the TXFIFO + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; + } + states[i2c_num].num_wr = 0; + if (req->callback != NULL) { + I2C_Recover(i2c); + I2C_FreeCallback(i2c_num, E_COMM_ERR); + } + return; + } + + rx_remain = req->rx_len - req->rx_num; + tx_remain = req->tx_len - states[i2c_num].num_wr; + + //Check if Master Write has been called and if there is a rx_data buffer + if ((i2c->int_fl0 & MXC_F_I2C_INT_FL0_TX_LOCK_OUT) && !(i2c->ctrl & MXC_F_I2C_CTRL_READ)) { + + i2c->int_en0 = 0; + if (req->rx_data == NULL) { + I2C_Recover(i2c); + I2C_FreeCallback(i2c_num, E_NULL_PTR); + return; + } + } + + // Check for DONE interrupt + if (int0 & MXC_F_I2C_INT_EN0_DONE) { + // Read out any data in the RX FIFO + while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { + *(req->rx_data)++ = i2c->fifo; + req->rx_num++; + rx_remain--; + } + + // Calculate the number of bytes sent by the slave + req->tx_num = states[i2c_num].num_wr - ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >> MXC_F_I2C_TX_CTRL1_TX_FIFO_POS); + + if (!req->sw_autoflush_disable) { + // Manually clear the TXFIFO + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; + } + states[i2c_num].num_wr = 0; + i2c->int_en0 = 0; + if (req->callback != NULL) { + if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP) { + I2C_Recover(i2c); + } else { + i2c->int_fl0 = i2c->int_fl0; + i2c->int_fl1 = i2c->int_fl1; + } + I2C_FreeCallback(i2c_num, E_NO_ERROR); + } + return; + } + + // Clear the interrupts + i2c->int_fl0 = int0; + if (i2c->ctrl & MXC_F_I2C_CTRL_READ) { + + i2c->int_en0 = 0; + if (req->tx_data == NULL) { + I2C_Recover(i2c); + I2C_FreeCallback(i2c_num, E_NULL_PTR); + return; + } + // Fill the FIFO + while ((tx_remain > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) { + i2c->fifo = *(req->tx_data)++; + states[i2c_num].num_wr++; + tx_remain--; + } + + // Set the TX threshold interrupt level + if (tx_remain) { + i2c->tx_ctrl0 = ((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) | (1 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)); + inten0 |= MXC_F_I2C_INT_EN0_TX_THRESH; + } + + } else { + // Read out any data in the RX FIFO + while (rx_remain && !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) { + *(req->rx_data)++ = i2c->fifo; + req->rx_num++; + rx_remain--; + } + + // Set the RX threshold interrupt level + if (rx_remain >= (MXC_I2C_FIFO_DEPTH - 1)) { + i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | + (MXC_I2C_FIFO_DEPTH - 1) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); + + inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH; + }else{ + i2c->rx_ctrl0 = ((i2c->rx_ctrl0 & ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) | + (rx_remain) << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS); + + inten0 |= MXC_F_I2C_INT_EN0_RX_THRESH; + } + + } + inten0 |= (MXC_F_I2C_INT_EN0_DONE | I2C_ERROR | MXC_F_I2C_INT_EN0_TX_LOCK_OUT); + i2c->int_en0 = inten0; +} + +/* ************************************************************************** */ +void I2C_Handler(mxc_i2c_regs_t *i2c) +{ + if (i2c->ctrl & MXC_F_I2C_CTRL_MST && i2c->int_fl0) { + // Service master interrupts if we're in master mode + I2C_MasterHandler(i2c); + } else if (i2c->int_fl0 || i2c->int_fl1) { + // Service the slave interrupts + I2C_SlaveHandler(i2c); + } +} + +/* ************************************************************************** */ +void I2C_DrainRX(mxc_i2c_regs_t *i2c) +{ + i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; +} + +/* ************************************************************************** */ +void I2C_DrainTX(mxc_i2c_regs_t *i2c) +{ + i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; +} +/* ************************************************************************* */ +static void I2C_FreeCallback(int i2c_num, int error) +{ + // Save the request + i2c_req_t *temp_req = states[i2c_num].req; + + mxc_free_lock((uint32_t*)&states[i2c_num].req); + + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback(temp_req, error); + } +} + +/* ************************************************************************* */ +static void I2C_Recover(mxc_i2c_regs_t *i2c) +{ + // Disable and clear interrupts + i2c->int_en0 = 0; + i2c->int_en1 = 0; + i2c->int_fl0 = i2c->int_fl0; + i2c->int_fl1 = i2c->int_fl1; + i2c->ctrl = 0; + i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; +} + +/* ************************************************************************* */ +int I2C_AbortAsync(i2c_req_t *req) +{ + int i2c_num; + mxc_i2c_regs_t *i2c; + + // Find the request, set to NULL + for (i2c_num = 0; i2c_num < MXC_I2C_INSTANCES; i2c_num++) { + if (req == states[i2c_num].req) { + + i2c = MXC_I2C_GET_I2C(i2c_num); + I2C_Recover(i2c); + I2C_FreeCallback(i2c_num, E_ABORT); + + return E_NO_ERROR; + } + } + + return E_BAD_PARAM; +} + +/* ************************************************************************* */ +int I2C_SetTimeout(mxc_i2c_regs_t *i2c, int us){ + uint32_t timeout; + timeout = (PeripheralClock/1000000) * us; + if(timeout > 0xFFFF){ + return E_BAD_PARAM; + } + i2c->timeout = timeout; + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void I2C_ClearTimeout (mxc_i2c_regs_t *i2c) +{ + i2c->timeout = 0; +} diff --git a/Project/SDK/Driver/Source/i2s.c b/Project/SDK/Driver/Source/i2s.c new file mode 100644 index 0000000..adb770b --- /dev/null +++ b/Project/SDK/Driver/Source/i2s.c @@ -0,0 +1,216 @@ +/** + * @file i2s.c + * @brief Inter-Integrated Sound (I2S) driver implementation. + */ + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + *************************************************************************** */ + +#include +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "dma.h" +#include "i2s.h" + +#define I2S_CHANNELS 2 +#define I2S_WIDTH 16 + +int dma_channel = -1; + +int I2S_Init(const i2s_cfg_t *cfg, void (*dma_ctz_cb)(int, int), const sys_cfg_i2s_t* sys_cfg_i2s) +{ + unsigned int i2s_clk, baud; + uint16_t clocks; + uint8_t ctz_en; + int err; + + SYS_I2S_Init(sys_cfg_i2s); + + /* Setup SPI_MSS as master, mode 0, 16 bit transfers as I2S Requires */ + MXC_SPIMSS->ctrl = MXC_F_SPIMSS_CTRL_MMEN; + MXC_SPIMSS->mod = MXC_V_SPIMSS_MOD_NUMBITS_BITS16 | MXC_F_SPIMSS_MOD_SSIO; + MXC_SPIMSS->dma = MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8; + + /* Setup I2S register from i2s_cfg_t */ + MXC_SPIMSS->i2s_ctrl = cfg->left_justify << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS | + cfg->mono_audio << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS; + + /* Determine divisor for baud rate generator */ + baud = cfg->sample_rate*I2S_CHANNELS*I2S_WIDTH; + + i2s_clk = SYS_I2S_GetFreq(MXC_SPIMSS); + + if (i2s_clk/4 < baud) { + return E_BAD_PARAM; + } + + clocks = i2s_clk / (2*baud); + MXC_SPIMSS->brg = clocks; + + /* Prepare SPIMSS DMA register for DMA setup */ + if (dma_ctz_cb == NULL) { + ctz_en = 0; + } else { + ctz_en = 1; + } + + /* Initialize DMA */ + if (cfg->audio_direction % 2) { + MXC_SPIMSS->dma |= MXC_F_SPIMSS_DMA_TX_DMA_EN | MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR; + if ((err = DMA_Init()) != E_NO_ERROR) { + if (err != E_BAD_STATE) { + return err; + } + } + + if ((err = DMA_AcquireChannel()) < 0) { + return err; + } + + dma_channel = err; + + DMA_ConfigChannel(dma_channel, DMA_PRIO_MEDHIGH, + sys_cfg_i2s->dma_reqsel_tx, 1, DMA_TIMEOUT_512_CLK, + DMA_PRESCALE_DIV64K, DMA_WIDTH_HALFWORD, 1, + DMA_WIDTH_HALFWORD, 0, 16, 0, ctz_en); + + if (ctz_en) { + DMA_SetCallback(dma_channel, dma_ctz_cb); + DMA_EnableInterrupt(dma_channel); + } + } + if (cfg->audio_direction / 2) { + MXC_SPIMSS->dma = MXC_F_SPIMSS_DMA_RX_DMA_EN | MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR; + if ((err = DMA_Init()) != E_NO_ERROR) { + if (err != E_BAD_STATE) { //DMA already initialized + return err; + } + } + + if ((err = DMA_AcquireChannel()) < 0) { + return err; + } + + dma_channel = err; + + DMA_ConfigChannel(dma_channel, DMA_PRIO_MEDHIGH, + sys_cfg_i2s->dma_reqsel_rx, 1, DMA_TIMEOUT_512_CLK, + DMA_PRESCALE_DIV64K, DMA_WIDTH_HALFWORD, 0, + DMA_WIDTH_HALFWORD, 1, 8, 0, ctz_en); + + if (ctz_en) { + DMA_SetCallback(dma_channel, dma_ctz_cb); + DMA_EnableInterrupt(dma_channel); + } + } + + I2S_DMA_SetAddrCnt(cfg->dma_src_addr, cfg->dma_dst_addr, cfg->dma_cnt); + if (cfg->dma_reload_en) { + I2S_DMA_SetReload(cfg->dma_src_addr, cfg->dma_dst_addr, cfg->dma_cnt); + } + + if (cfg->start_immediately) { + return I2S_Start(); + } + return E_NO_ERROR; +} + +int I2S_Shutdown(void) +{ + MXC_SPIMSS->ctrl = 0; + MXC_SPIMSS->i2s_ctrl = 0; + MXC_SPIMSS->brg = 0; + MXC_SPIMSS->mod = 0; + MXC_SPIMSS->dma = 0; + SYS_I2S_Shutdown(); + return DMA_ReleaseChannel(dma_channel); +} + +int I2S_Mute(void) +{ + MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE; + return E_NO_ERROR; +} + +int I2S_Unmute(void) +{ + MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE; + return E_NO_ERROR; +} + +int I2S_Pause(void) +{ + MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE; + return E_NO_ERROR; +} + +int I2S_Unpause(void) +{ + MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE; + return E_NO_ERROR; +} + +int I2S_Stop(void) +{ + MXC_SPIMSS->ctrl &= ~MXC_F_SPIMSS_CTRL_SPIEN; + MXC_SPIMSS->i2s_ctrl &= ~MXC_F_SPIMSS_I2S_CTRL_I2S_EN; + return DMA_Stop(dma_channel); +} + +int I2S_Start(void) +{ + MXC_SPIMSS->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; + MXC_SPIMSS->i2s_ctrl |= MXC_F_SPIMSS_I2S_CTRL_I2S_EN; + return DMA_Start(dma_channel); +} + +int I2S_DMA_ClearFlags(void) +{ + return DMA_ClearFlags(dma_channel); +} + +int I2S_DMA_SetAddrCnt(void *src_addr, void *dst_addr, unsigned int count) +{ + return DMA_SetSrcDstCnt(dma_channel, src_addr, dst_addr, count); +} + +int I2S_DMA_SetReload(void *src_addr, void *dst_addr, unsigned int count) +{ + return DMA_SetReload(dma_channel, src_addr, dst_addr, count); +} diff --git a/Project/SDK/Driver/Source/icc.c b/Project/SDK/Driver/Source/icc.c new file mode 100644 index 0000000..17b2ba7 --- /dev/null +++ b/Project/SDK/Driver/Source/icc.c @@ -0,0 +1,84 @@ +/* ***************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include +#include "mxc_config.h" +#include "mxc_errors.h" +#include "icc_regs.h" +#include "icc.h" + +static int ICC_Ready(void) +{ + return (MXC_ICC->cache_ctrl & MXC_F_ICC_CACHE_CTRL_CACHE_RDY); +} + +int ICC_ID(icc_cache_id_t cid) +{ + switch (cid) { + case ICC_CACHE_ID_RELNUM: + return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_RELNUM) >> MXC_F_ICC_CACHE_ID_RELNUM_POS); + case ICC_CACHE_ID_PARTNUM: + return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_PARTNUM) >> MXC_F_ICC_CACHE_ID_PARTNUM_POS); + case ICC_CACHE_ID_CCHID: + return ((MXC_ICC->cache_id & MXC_F_ICC_CACHE_ID_CCHID) >> MXC_F_ICC_CACHE_ID_CCHID_POS); + default: + return E_BAD_PARAM; + } +} + +void ICC_Enable(void) +{ + // Invalidate cache and wait until ready + MXC_ICC->invalidate = 1; + while (!(ICC_Ready())); + + // Enable Cache + MXC_ICC->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_CACHE_EN; +} + +void ICC_Disable(void) +{ + // Disable Cache + MXC_ICC->cache_ctrl &= ~MXC_F_ICC_CACHE_CTRL_CACHE_EN; +} + +void ICC_Flush(void) +{ + ICC_Disable(); + ICC_Enable(); +} diff --git a/Project/SDK/Driver/Source/lp.c b/Project/SDK/Driver/Source/lp.c new file mode 100644 index 0000000..eca5310 --- /dev/null +++ b/Project/SDK/Driver/Source/lp.c @@ -0,0 +1,371 @@ +/** + * @file lp.c + * @brief Low power functions + */ + +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-10-07 11:05:30 -0500 (Mon, 07 Oct 2019) $ + * $Revision: 47429 $ + * + *************************************************************************** */ + + +/***** Includes *****/ +#include "lp.h" +#include "pwrseq_regs.h" +#include "mxc_errors.h" +#include "gcr_regs.h" +#include "mxc_config.h" +#include "mxc_sys.h" +#include "flc.h" +#include "tmr_utils.h" + +/***** Functions *****/ +void LP_ClearWakeStatus(void) +{ + MXC_PWRSEQ->lp_wakefl = 0xFFFFFFFF; + + /* These flags are slow to clear, so block until they do */ + while(MXC_PWRSEQ->lp_wakefl & (MXC_PWRSEQ->lpwk_en)); +} + +void LP_EnableSRAM3(void) +{ + MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF; +} + +void LP_DisableSRAM3(void) +{ + MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF; +} + +void LP_EnableSRAM2(void) +{ + MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF; +} + +void LP_DisableSRAM2(void) +{ + MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF; +} + +void LP_EnableSRAM1(void) +{ + MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF; +} + +void LP_DisableSRAM1(void) +{ + MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF; +} + +void LP_EnableSRAM0(void) +{ + MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF; +} + +void LP_DisableSRAM0(void) +{ + MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF; +} + +void LP_EnableICacheLightSleep(void) +{ + MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_ICACHELS); +} + +void LP_DisableICacheLightSleep(void) +{ + MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_ICACHELS); +} + +void LP_EnableSysRAM3LightSleep(void) +{ + MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM3LS); +} + +void LP_DisableSysRAM3LightSleep(void) +{ + MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM3LS); +} + +void LP_EnableSysRAM2LightSleep(void) +{ + MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM2LS); +} + +void LP_DisableSysRAM2LightSleep(void) +{ + MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM2LS); +} + +void LP_EnableSysRAM1LightSleep(void) +{ + MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM1LS); +} + +void LP_DisableSysRAM1LightSleep(void) +{ + MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM1LS); +} + +void LP_EnableSysRAM0LightSleep(void) +{ + MXC_GCR->memckcn |= (MXC_F_GCR_MEMCKCN_SYSRAM0LS); +} + +void LP_DisableSysRAM0LightSleep(void) +{ + MXC_GCR->memckcn &= ~(MXC_F_GCR_MEMCKCN_SYSRAM0LS); +} + +void LP_EnableRTCAlarmWakeup(void) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_RTCWKEN; +} + +void LP_DisableRTCAlarmWakeup(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_RTCWKEN; +} + +void LP_EnableGPIOWakeup(const gpio_cfg_t *wu_pins) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_GPIOWKEN; + switch(wu_pins->port) + { + case 0: MXC_PWRSEQ->lpwk_en |= wu_pins->mask; break; + } +} + +void LP_DisableGPIOWakeup(const gpio_cfg_t *wu_pins) +{ + switch(wu_pins->port) + { + case 0: MXC_PWRSEQ->lpwk_en &= ~wu_pins->mask; break; + } + + if(MXC_PWRSEQ->lpwk_en == 0) + { + MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIOWKEN; + } +} + +void LP_EnterSleepMode(void) +{ + // Clear SLEEPDEEP bit + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + // Go into Sleep mode and wait for an interrupt to wake the processor + __WFI(); +} + +void LP_EnterDeepSleepMode(void) +{ + // Set SLEEPDEEP bit + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + // Auto-powerdown 96 MHz oscillator when in deep sleep + MXC_GCR->pm |= MXC_F_GCR_PM_HIRCPD; + // Go into Deepsleep mode and wait for an interrupt to wake the processor + __WFI(); +} + +void LP_EnterBackupMode(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP; + while(1); +} + +void LP_EnterShutdownMode(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN; + while(1); +} +void LP_SetOperatingVoltage(lp_ovr_t ovr) +{ + uint32_t div; + + //Set flash wait state for any clock so its not to low after clock changes. + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + //set the OVR bits + MXC_PWRSEQ->lp_ctrl &= ~(MXC_F_PWRSEQ_LP_CTRL_OVR); + MXC_PWRSEQ->lp_ctrl |= ovr; + + //Set LVE bit + if(ovr == LP_OVR_0_9){ + MXC_FLC->cn |= MXC_F_FLC_CN_LVE; + } + else{ + MXC_FLC->cn &= ~(MXC_F_FLC_CN_LVE); + } + + // Update SystemCoreClock variable + SystemCoreClockUpdate(); + + // Get the clock divider + div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS; + + //Set Flash Wait States + if(ovr == LP_OVR_0_9){ + + if(div == 0){ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } else{ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } + + } else if( ovr == LP_OVR_1_0){ + if(div == 0){ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } else{ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } + + } else { + + if(div == 0){ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS); + } else if(div == 1){ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } else{ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } + } + +} + +void LP_EnableSRamRet0(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0; +} + +void LP_DisableSRamRet0(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0; +} + +void LP_EnableSRamRet1(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1; +} + +void LP_DisableSRamRet1(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1; +} + +void LP_EnableSRamRet2(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2; +} + +void LP_DisableSRamRet2(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2; +} + +void LP_EnableSRamRet3(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3; +} + +void LP_DisableSRamRet3(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3; +} + +void LP_EnableBlockDetect(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; +} + +void LP_DisableBlockDetect(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS; +} + +void LP_EnableRamRetReg(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_RETREG_EN; +} + +void LP_DisableRamRetReg(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_RETREG_EN; +} + +void LP_EnableFastWk(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN; +} + +void LP_DisableFastWk(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN; +} + +void LP_EnableBandGap(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_BG_OFF; +} + +void LP_DisableBandGap(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_BG_OFF; +} + +void LP_EnableVCorePORSignal(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS; +} + +void LP_DisableVCorePORSignal(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS; +} + +void LP_EnableLDO(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_LDO_DIS; +} + +void LP_DisableLDO(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_LDO_DIS; +} + +void LP_EnableVCoreSVM(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS; +} + +void LP_DisableVCoreSVM(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS; +} + +void LP_EnableVDDIOPorMonitoF(void){ + MXC_PWRSEQ->lp_ctrl &= ~MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS; +} + +void LP_DisableVDDIOPorMonitor(void){ + MXC_PWRSEQ->lp_ctrl |= MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS; +} diff --git a/Project/SDK/Driver/Source/mxc_assert.c b/Project/SDK/Driver/Source/mxc_assert.c new file mode 100644 index 0000000..b259715 --- /dev/null +++ b/Project/SDK/Driver/Source/mxc_assert.c @@ -0,0 +1,50 @@ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $ + * $Revision: 36818 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" + +/* **** Definitions **** */ + +/* **** Globals *****/ + +/* **** Functions **** */ + +/* ************************************************************************** */ +__weak void mxc_assert(const char *expr, const char *file, int line) +{ + while (1) {} +} diff --git a/Project/SDK/Driver/Source/mxc_delay.c b/Project/SDK/Driver/Source/mxc_delay.c new file mode 100644 index 0000000..5b7f626 --- /dev/null +++ b/Project/SDK/Driver/Source/mxc_delay.c @@ -0,0 +1,179 @@ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Id: mxc_delay.c 36202 2018-07-16 21:06:02Z michael.bayern $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_config.h" +#include "mxc_delay.h" + +/* **** File Scope Variables **** */ +static uint32_t ctrl_save; +static volatile uint64_t compare_value = 0; +static volatile uint64_t curr_value; +static volatile uint32_t reload; + +static void mxc_delay_init(unsigned long us); +extern void SysTick_Handler(void); + +/* ************************************************************************** */ +__weak void SysTick_Handler(void) +{ + mxc_delay_handler(); +} + +/* ************************************************************************** */ +void mxc_delay_handler(void) +{ + // Check and clear overflow flag + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) { + // Is a delay in progress? + if(compare_value != 0) { + curr_value += reload; + if(curr_value >= compare_value) { + mxc_delay_stop(); + } + } + } +} + +/* ************************************************************************** */ +static void mxc_delay_init(unsigned long us) +{ + uint32_t starttick, ticks; + + // Record the current tick value and clear the overflow flag + starttick = SysTick->VAL; + + // Save the state of control register (and clear the overflow flag) + ctrl_save = SysTick->CTRL & ~SysTick_CTRL_COUNTFLAG_Msk; + + // If the SysTick is not running, configure and start it + if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { + SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; + SysTick->VAL = SysTick_VAL_CURRENT_Msk; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk; + starttick = SysTick_VAL_CURRENT_Msk; + reload = SysTick_LOAD_RELOAD_Msk + 1; + } else { + reload = SysTick->LOAD + 1; // get the current reload value + } + + // Calculate the total number of ticks to delay + ticks = (uint32_t)(((uint64_t)us * (uint64_t)SystemCoreClock) / 1000000); + + compare_value = ticks + (reload - starttick); + curr_value = 0; + + if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + } +} + +/* ************************************************************************** */ +int mxc_delay_start(unsigned long us) +{ + // Check if timeout currently ongoing + if (compare_value != 0) { + return E_BUSY; + } + + // Check if there is nothing to do + if (us == 0) { + return E_NO_ERROR; + } + + // Calculate the necessary delay and start the timer + mxc_delay_init(us); + + // Enable SysTick interrupt if necessary + if (compare_value != 0) { + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int mxc_delay_check(void) +{ + // Check if timeout currently ongoing + if (compare_value == 0) { + return E_NO_ERROR; + } + + if((curr_value + (reload - SysTick->VAL)) >= compare_value) { + mxc_delay_stop(); + return E_NO_ERROR; + } + + return E_BUSY; +} + +/* ************************************************************************** */ +void mxc_delay_stop(void) +{ + SysTick->CTRL = ctrl_save; + compare_value = 0; +} + +/* ************************************************************************** */ +int mxc_delay(unsigned long us) +{ + // Check if timeout currently ongoing + if (compare_value != 0) { + return E_BUSY; + } + + // Check if there is nothing to do + if (us == 0) { + return E_NO_ERROR; + } + + // Calculate the necessary delay and start the timer + mxc_delay_init(us); + + // Wait until the total number of ticks exceeds the compare value. + while ((curr_value + (reload - SysTick->VAL)) < compare_value) { + // If SysTick interrupts are enabled, COUNTFLAG will never be set here and + // curr_value will be incremented in the ISR. If SysTick interrupts are + // disabled, curr_value is incremented here. + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) { + curr_value += reload; + } + } + + mxc_delay_stop(); + return E_NO_ERROR; +} diff --git a/Project/SDK/Driver/Source/mxc_lock.c b/Project/SDK/Driver/Source/mxc_lock.c new file mode 100644 index 0000000..56ea439 --- /dev/null +++ b/Project/SDK/Driver/Source/mxc_lock.c @@ -0,0 +1,85 @@ +/* **************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + *************************************************************************** */ + +/* Define to prevent redundant inclusion */ +#ifndef _MXC_LOCK_H_ +#define _MXC_LOCK_H_ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_lock.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined ( __ICCARM__ ) + #define MXC_LOCK_CAST unsigned int volatile * +#else + #define MXC_LOCK_CAST volatile unsigned long * +#endif + +/* ************************************************************************** */ +int mxc_get_lock(uint32_t *lock, uint32_t value) +{ + do { + + // Return if the lock is taken by a different thread + if(__LDREXW((MXC_LOCK_CAST)lock) != 0) { + return E_BUSY; + } + + // Attempt to take the lock + } while(__STREXW(value, (MXC_LOCK_CAST)lock) != 0); + + // Do not start any other memory access until memory barrier is complete + __DMB(); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void mxc_free_lock(uint32_t *lock) +{ + // Ensure memory operations complete before releasing lock + __DMB(); + *lock = 0; +} + +#ifdef __cplusplus +} +#endif +#endif /* _MXC_LOCK_H_ */ diff --git a/Project/SDK/Driver/Source/mxc_pins.c b/Project/SDK/Driver/Source/mxc_pins.c new file mode 100644 index 0000000..edc44d5 --- /dev/null +++ b/Project/SDK/Driver/Source/mxc_pins.c @@ -0,0 +1,79 @@ + /** + * @file mxc_pins.c + * @brief This file contains constant pin configurations for the peripherals. + */ + +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "gpio.h" +#include "mxc_config.h" + +/** + * @ingroup MXC_pins + * @{ + */ + +/* **** TIMER pins **** */ +const gpio_cfg_t gpio_cfg_tmr0 = { PORT_0, PIN_3, GPIO_FUNC_ALT3, GPIO_PAD_NONE }; + +/* **** UART pins **** */ +const gpio_cfg_t gpio_cfg_uart0rtscts = { PORT_0, (PIN_6 | PIN_7), GPIO_FUNC_ALT2, GPIO_PAD_NONE }; +const gpio_cfg_t gpio_cfg_uart0a = { PORT_0, (PIN_4 | PIN_5), GPIO_FUNC_ALT2, GPIO_PAD_NONE }; +const gpio_cfg_t gpio_cfg_uart1rtscts = { PORT_0, (PIN_12 | PIN_13), GPIO_FUNC_ALT2, GPIO_PAD_NONE }; +const gpio_cfg_t gpio_cfg_uart1a = { PORT_0, (PIN_10 | PIN_11), GPIO_FUNC_ALT2, GPIO_PAD_NONE }; +const gpio_cfg_t gpio_cfg_uart1b = { PORT_0, (PIN_0 | PIN_1), GPIO_FUNC_ALT3, GPIO_PAD_NONE }; +const gpio_cfg_t gpio_cfg_uart1c = { PORT_0, (PIN_6 | PIN_7), GPIO_FUNC_ALT3, GPIO_PAD_NONE }; + +/* **** I2C pins **** */ +const gpio_cfg_t gpio_cfg_i2c0 = { PORT_0, (PIN_8 | PIN_9), GPIO_FUNC_ALT1, GPIO_PAD_PULL_UP }; +const gpio_cfg_t gpio_cfg_i2c1 = { PORT_0, (PIN_2 | PIN_3), GPIO_FUNC_ALT1, GPIO_PAD_PULL_UP }; + +/* **** SPI/I2S pins **** */ +const gpio_cfg_t gpio_cfg_spi17y = { PORT_0, (PIN_4 | PIN_5 | PIN_6 | PIN_7), GPIO_FUNC_ALT1, GPIO_PAD_NONE }; // SPI0A +const gpio_cfg_t gpio_cfg_spimss1a = { PORT_0, (PIN_10 | PIN_11 | PIN_12 | PIN_13) , GPIO_FUNC_ALT1, GPIO_PAD_NONE }; // SPI1A +const gpio_cfg_t gpio_cfg_spimss1b = { PORT_0, (PIN_0 | PIN_1 | PIN_2 | PIN_3 ) , GPIO_FUNC_ALT2, GPIO_PAD_NONE }; // SPI1B +const gpio_cfg_t gpio_cfg_i2s1a = { PORT_0, (PIN_10 | PIN_11 | PIN_12 | PIN_13) , GPIO_FUNC_ALT1, GPIO_PAD_NONE }; // same port as SPI1A +const gpio_cfg_t gpio_cfg_i2s1b = { PORT_0, (PIN_0 | PIN_1 | PIN_2 | PIN_3 ) , GPIO_FUNC_ALT2, GPIO_PAD_NONE }; // same port as SPI1B + +/* **** SWD pins **** */ +const gpio_cfg_t gpio_cfg_swd = { PORT_0, (PIN_0 | PIN_1 | PIN_2 | PIN_3 ) , GPIO_FUNC_ALT1, GPIO_PAD_NONE }; + +/* **** RTC pins **** */ +const gpio_cfg_t gpio_cfg_rtc = { PORT_0, PIN_2, GPIO_FUNC_ALT3, GPIO_PAD_NONE }; + +/**@} end of ingroup MXC_pins*/ diff --git a/Project/SDK/Driver/Source/mxc_sys.c b/Project/SDK/Driver/Source/mxc_sys.c new file mode 100644 index 0000000..7a0fb13 --- /dev/null +++ b/Project/SDK/Driver/Source/mxc_sys.c @@ -0,0 +1,721 @@ +/** + * @file mxc_sys.c + * @brief System level setup help + */ + +/******************************************************************************* + * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2020-01-17 08:38:51 -0600 (Fri, 17 Jan 2020) $ + * $Revision: 50772 $ + * + ******************************************************************************/ + +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "gpio.h" +#include "mxc_pins.h" +#include "gcr_regs.h" +#include "tmr_regs.h" +#include "pwrseq_regs.h" +#include "spi17y_regs.h" +#include "spimss_regs.h" +#include "mxc_delay.h" +#include "rtc.h" + +/** + * @ingroup MXC_sys + * @{ + */ + +/***** Definitions *****/ +#define SYS_CLOCK_TIMEOUT MXC_DELAY_MSEC(1) + +#define SYS_RTC_CLK 32768UL + +/***** Functions ******/ +static int SYS_Clock_Timeout(uint32_t ready) +{ + // Start timeout, wait for ready + mxc_delay_start(SYS_CLOCK_TIMEOUT); + do { + if (MXC_GCR->clkcn & ready) { + mxc_delay_stop(); + return E_NO_ERROR; + } + } while (mxc_delay_check() == E_BUSY); + + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_Clock_Select(sys_system_clock_t clock, mxc_tmr_regs_t* tmr) +{ + uint32_t current_clock,ovr, div; + + // Save the current system clock + current_clock = MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL; + // Set FWS higher than what the minimum for the fastest clock is + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x5UL << MXC_F_GCR_MEMCKCN_FWS_POS); + switch(clock) { + case SYS_CLOCK_NANORING: + // Set NANORING clock as System Clock + MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_NANORING); + + break; + case SYS_CLOCK_HFXIN: + // Enable 32k Oscillator + MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN; + + // Check if 32k clock is ready + if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_X32K_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + MXC_RTC->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers + + // Set 32k clock as System Clock + MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HFXIN); + + break; + + case SYS_CLOCK_HFXIN_DIGITAL: + // Enable 32k Oscillator + MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN; + + // Check if 32k clock is ready + if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_X32K_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + MXC_RTC->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers + MXC_RTC->oscctrl |= MXC_F_RTC_OSCCTRL_BYPASS; // To allow square wave driven on 32KIN + // Set 32k clock as System Clock + MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HFXIN); + + break; + case SYS_CLOCK_HIRC: + // Enable 96MHz Clock + MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_HIRC_EN; + + // Check if 96MHz clock is ready + if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_HIRC_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + + // Set 96MHz clock as System Clock + MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, MXC_S_GCR_CLKCN_CLKSEL_HIRC); + + break; + default: + return E_BAD_PARAM; + } + + // Wait for system clock to be ready + if (SYS_Clock_Timeout(MXC_F_GCR_CLKCN_CKRDY) != E_NO_ERROR) { + + // Restore the old system clock if timeout + MXC_SETFIELD(MXC_GCR->clkcn, MXC_F_GCR_CLKCN_CLKSEL, current_clock); + + return E_TIME_OUT; + } + + // Disable other clocks + switch(clock) { + case SYS_CLOCK_NANORING: + MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN); + break; + + case SYS_CLOCK_HFXIN: + MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN); + break; + + case SYS_CLOCK_HFXIN_DIGITAL: + MXC_GCR->clkcn &= ~(MXC_F_GCR_CLKCN_HIRC_EN); + break; + + case SYS_CLOCK_HIRC: + //Don't disable 32KHz clock + break; + } + + // Update the system core clock + SystemCoreClockUpdate(); + + // Get the clock divider + div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS; + + //get ovr setting + ovr = (MXC_PWRSEQ->lp_ctrl & MXC_F_PWRSEQ_LP_CTRL_OVR); + + //Set flash wait settings + if(ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V){ + + if(div == 0){ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } else{ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } + + } else if( ovr == MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V){ + if(div == 0){ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } else{ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } + + } else { + + if(div == 0){ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x4UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } else if(div == 1){ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x2UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } else{ + MXC_GCR->memckcn = (MXC_GCR->memckcn & ~(MXC_F_GCR_MEMCKCN_FWS)) | (0x1UL << MXC_F_GCR_MEMCKCN_FWS_POS); + + } + } + + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_ClockEnable_X32K(sys_cfg_rtc_t *sys_cfg) +{ + // Enable 32k Oscillator + MXC_GCR->clkcn |=MXC_F_GCR_CLKCN_X32K_EN; + + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_ClockDisable_X32K() +{ + // Disable 32k Oscillator + MXC_GCR->clkcn &= (~MXC_F_GCR_CLKCN_X32K_EN); + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_UART_Init(mxc_uart_regs_t *uart, const sys_cfg_uart_t* sys_cfg) +{ + // Configure GPIO for UART + if (uart == MXC_UART0) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_UART0); + if(sys_cfg->map == MAP_A){ + GPIO_Config(&gpio_cfg_uart0a); + } + else{ + return E_BAD_PARAM; + } + if(sys_cfg->flow_flag == UART_FLOW_ENABLE){ + GPIO_Config(&gpio_cfg_uart0rtscts); + } + } + if (uart == MXC_UART1) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_UART1); + if(sys_cfg->map == MAP_A){ + GPIO_Config(&gpio_cfg_uart1a); + } + else if(sys_cfg->map == MAP_B){ + GPIO_Config(&gpio_cfg_uart1b); + } + else if(sys_cfg->map == MAP_C){ + GPIO_Config(&gpio_cfg_uart1c); + } + else{ + return E_BAD_PARAM; + } + if(sys_cfg->flow_flag == UART_FLOW_ENABLE){ + GPIO_Config(&gpio_cfg_uart1rtscts); + } + } + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_UART_Shutdown(mxc_uart_regs_t *uart) +{ + if (uart == MXC_UART0) { + SYS_ClockDisable(SYS_PERIPH_CLOCK_UART0); + } + else if (uart == MXC_UART1) { + SYS_ClockDisable(SYS_PERIPH_CLOCK_UART1); + } + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_I2C_Init(mxc_i2c_regs_t *i2c, const sys_cfg_i2c_t* sys_cfg) +{ + + // Configure GPIO for I2C + if (i2c == MXC_I2C0) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_I2C0); + GPIO_Config(&gpio_cfg_i2c0); + + } else if (i2c == MXC_I2C1) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_I2C1); + GPIO_Config(&gpio_cfg_i2c1); + } else { + return E_NO_DEVICE; + } + + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_I2C_Shutdown(mxc_i2c_regs_t *i2c) +{ + if (i2c == MXC_I2C0) { + gpio_cfg_t cfg = { gpio_cfg_i2c0.port, gpio_cfg_i2c0.mask, GPIO_FUNC_IN, GPIO_PAD_NONE }; + SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C0); + GPIO_Config(&cfg); + } else if (i2c == MXC_I2C1) { + gpio_cfg_t cfg = { gpio_cfg_i2c1.port, gpio_cfg_i2c1.mask, GPIO_FUNC_IN, GPIO_PAD_NONE }; + SYS_ClockDisable(SYS_PERIPH_CLOCK_I2C1); + GPIO_Config(&cfg); + } else { + return E_NO_DEVICE; + } + // Clear registers + i2c->ctrl = 0; + + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_DMA_Init(void) +{ + SYS_ClockEnable(SYS_PERIPH_CLOCK_DMA); + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_DMA_Shutdown(void) +{ + SYS_ClockDisable(SYS_PERIPH_CLOCK_DMA); + return E_NO_ERROR; +} + +/* ************************************************************************ */ +unsigned SYS_I2C_GetFreq(mxc_i2c_regs_t *i2c) +{ + return PeripheralClock; +} + +/* ************************************************************************ */ +unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr) +{ + return PeripheralClock; +} + +/* ************************************************************************ */ +void SYS_Reset0(sys_reset0_t reset) +{ + MXC_GCR->rstr0 = reset; + while(MXC_GCR->rstr0 != 0x0) {} +} + +/* ************************************************************************ */ +void SYS_Reset1(sys_reset1_t reset) +{ + MXC_GCR->rstr1 = reset; + while(MXC_GCR->rstr0 != 0x0) {} +} + +/* ************************************************************************ */ +void SYS_ClockDisable(sys_periph_clock_t clock) +{ + /* The sys_periph_clock_t enum uses bit 27 (an unused bit in both perkcn registers) + to determine which of the two perckcn registers to write to. */ + if (clock & (1<<27)) { + clock &= ~(1<<27); + MXC_GCR->perckcn1 |= clock; + } else { + MXC_GCR->perckcn0 |= clock; + } +} + +/* ************************************************************************ */ +void SYS_ClockEnable(sys_periph_clock_t clock) +{ + /* The sys_periph_clock_t enum uses bit 27 (an unused bit in both perkcn registers) + to determine which of the two perckcn registers to write to. */ + if (clock & (1<<27)) { + clock &= ~(1<<27); + MXC_GCR->perckcn1 &= ~(clock); + } else { + MXC_GCR->perckcn0 &= ~(clock); + } +} + +/* ************************************************************************ */ +#if defined (__ICCARM__) +#pragma optimize=none /* Turn off optimizations for next function */ +#elif defined ( __CC_ARM ) +/* Keil MDK - Turn off optimizations after saving current state */ +#pragma push /* Save current optimization level */ +#pragma O0 /* Optimization level 0 */ +#elif ( __GNUC__ ) +/* GCC - Turn off optimizations after saving current state */ +#pragma GCC push_options /* Save current optimization level */ +#pragma GCC optimize ("O0") /* Set optimization level to none for this function */ +#endif +void SYS_Flash_Operation(void) +{ + volatile uint32_t *line_addr; + volatile uint32_t __attribute__ ((unused)) line; + + // Clear the cache + MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN; + MXC_ICC->cache_ctrl ^= MXC_F_ICC_CACHE_CTRL_CACHE_EN; + + // Clear the line fill buffer + line_addr = (uint32_t*)(MXC_FLASH_MEM_BASE); + line = *line_addr; + + line_addr = (uint32_t*)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE); + line = *line_addr; +} +/* Set optimizations to the previous level. For IAR, the optimize none applies + only to the next function. Keil MDK and GNUC need state restored. */ +#if defined ( __CC_ARM ) +#pragma pop /* Restore Kiel MDK optimizations to saved level */ +#elif defined ( __GNUC__ ) +#pragma GCC pop_options /* Restore GCC optimization level */ +#endif + +/* ************************************************************************ */ +int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t* sys_cfg) +{ + if(sys_cfg) { + if(sys_cfg->out_en) { + + if (tmr == MXC_TMR0) { + GPIO_Config(&gpio_cfg_tmr0); + } + } + } + + if (tmr == MXC_TMR0) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_T0); + } + else if (tmr == MXC_TMR1) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_T1); + } + else if (tmr == MXC_TMR2) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_T2); + } + + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg) +{ + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_FLC_Shutdown(void) +{ + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_SPI17Y_Init(mxc_spi17y_regs_t *spi, const sys_cfg_spi17y_t* sys_cfg) +{ + // Configure GPIO for spi17y + if (spi == MXC_SPI17Y) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_SPI17Y); + if(sys_cfg->map == MAP_A){ + GPIO_Config(&gpio_cfg_spi17y); + MXC_GPIO0->ds |= 0x0003BF0; + }else{ + return E_BAD_PARAM; + } + } else { + return E_NO_DEVICE; + } + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi) +{ + if (spi == MXC_SPI17Y) { + SYS_ClockDisable(SYS_PERIPH_CLOCK_SPI17Y); + } + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_SPIMSS_Init(mxc_spimss_regs_t *spi, const sys_cfg_spimss_t* sys_cfg) +{ + // Configure GPIO for spimss + if (spi == MXC_SPIMSS) { + SYS_ClockEnable(SYS_PERIPH_CLOCK_SPIMSS); + if(sys_cfg->map == MAP_A){ + GPIO_Config(&gpio_cfg_spimss1a); // SPI1A chosen + }else if(sys_cfg->map == MAP_B){ + GPIO_Config(&gpio_cfg_spimss1b); // SPI1B chosen + }else{ + return E_BAD_PARAM; + } + } else { + return E_NO_DEVICE; + } + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_SPIMSS_Shutdown(mxc_spimss_regs_t *spi) +{ + if(spi == MXC_SPIMSS) { + SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS); + } + return E_NO_ERROR; +} + +int SYS_TMR_Shutdown(mxc_tmr_regs_t *tmr) +{ + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_I2S_Init(const sys_cfg_i2s_t* sys_cfg) +{ + if(sys_cfg->map == MAP_A) { + GPIO_Config(&gpio_cfg_i2s1a); + } + else if(sys_cfg->map == MAP_B) { + GPIO_Config(&gpio_cfg_i2s1b); + } + else { + return E_BAD_PARAM; + } + SYS_ClockEnable(SYS_PERIPH_CLOCK_SPIMSS); + + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_I2S_Shutdown(void) +{ + SYS_ClockDisable(SYS_PERIPH_CLOCK_SPIMSS); + + return E_NO_ERROR; +} + +/* ************************************************************************ */ +int SYS_I2S_GetFreq(mxc_spimss_regs_t *spimss) +{ + return PeripheralClock; +} + +/* ************************************************************************ */ +int SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg) +{ + GPIO_Config(&gpio_cfg_rtc); + return E_NO_ERROR; +} + +/* ************************************************************************ */ +uint32_t SYS_SysTick_GetFreq(void) +{ + // Determine is using internal (SystemCoreClock) or external (32768) clock + if ( (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) || !(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { + return SystemCoreClock; + } else { + return SYS_RTC_CLK; + } +} + +/* ************************************************************************ */ +int SYS_SysTick_Config(uint32_t ticks, int clk_src, mxc_tmr_regs_t* tmr) +{ + + if(ticks == 0) + return E_BAD_PARAM; + + // If SystemClock, call default CMSIS config and return + if (clk_src) { + return SysTick_Config(ticks); + } else { /* External clock source requested + enable RTC clock in run mode*/ + RTC_Init(MXC_RTC, 0, 0, NULL); + RTC_EnableRTCE(MXC_RTC); + + // Disable SysTick Timer + SysTick->CTRL = 0; + // Check reload value for valid + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) { + // Reload value impossible + return E_BAD_PARAM; + } + // set reload register + SysTick->LOAD = ticks - 1; + + // set Priority for Systick Interrupt + NVIC_SetPriority(SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); + + // Load the SysTick Counter Value + SysTick->VAL = 0; + + // Enable SysTick IRQ and SysTick Timer leaving clock source as external + SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; + + // Function successful + return E_NO_ERROR; + } +} + +/* ************************************************************************ */ +void SYS_SysTick_Disable(void) +{ + SysTick->CTRL = 0; +} + +/* ************************************************************************ */ +int SYS_SysTick_Delay(uint32_t ticks) +{ + uint32_t cur_ticks, num_full, num_remain, previous_ticks, num_subtract, i; + uint32_t reload, value, ctrl; // save/restore variables + + if(ticks == 0) + return E_BAD_PARAM; + + // If SysTick is not enabled we can take it for our delay + if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { + + // Save current state in case it's disabled but already configured, restore at return. + reload = SysTick->LOAD; + value = SysTick->VAL; + ctrl = SysTick->CTRL; + + // get the number of ticks less than max RELOAD. + num_remain = ticks % SysTick_LOAD_RELOAD_Msk; + + /* if ticks is < Max SysTick Reload num_full will be 0, otherwise it will + give us the number of max SysTicks cycles required */ + num_full = (ticks - 1) / SysTick_LOAD_RELOAD_Msk; + + // Do the required full systick countdowns + if (num_full) { + // load the max count value into systick + SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; + // load the starting value + SysTick->VAL = 0; + // enable SysTick counter with SystemClock source internal, immediately forces LOAD register into VAL register + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + // CountFlag will get set when VAL reaches zero + for (i = num_full; i > 0; i--) { + do { + cur_ticks = SysTick->CTRL; + } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk)); + } + // Disable systick + SysTick->CTRL = 0; + } + // Now handle the remainder of ticks + if (num_remain) { + SysTick->LOAD = num_remain; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + // wait for countflag to get set + do { + cur_ticks = SysTick->CTRL; + } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk)); + // Disable systick + SysTick->CTRL = 0; + } + + // restore original state of SysTick and return + SysTick->LOAD = reload; + SysTick->VAL = value; + SysTick->CTRL = ctrl; + + return E_NO_ERROR; + + } else { /* SysTick is enabled + When SysTick is enabled count flag can not be used + and the reload can not be changed. + Do not read the CTRL register -> clears count flag */ + + // Get the reload value for wrap/reload case + reload = SysTick->LOAD; + + // Read the starting systick value + previous_ticks = SysTick->VAL; + + do { + // get current SysTick value + cur_ticks = SysTick->VAL; + // Check for wrap/reload of timer countval + if (cur_ticks > previous_ticks) { + // subtract count to 0 (previous_ticks) and wrap (reload value - cur_ticks) + num_subtract = (previous_ticks + (reload - cur_ticks)); + } else { /* standard case (no wrap) + subtract off the number of ticks since last pass */ + num_subtract = (previous_ticks - cur_ticks); + } + // check to see if we are done. + if (num_subtract >= ticks) + return E_NO_ERROR; + else + ticks -= num_subtract; + // cur_ticks becomes previous_ticks for next timer read. + previous_ticks = cur_ticks; + } while (ticks > 0); + // Should not ever be reached + return E_NO_ERROR; + } +} + +/* ************************************************************************ */ +void SYS_SysTick_DelayUs(uint32_t us) +{ + SYS_SysTick_Delay((uint32_t)(((uint64_t)SYS_SysTick_GetFreq() * us) / 1000000)); +} + +/* ************************************************************************ */ +int SYS_WDT_Init(mxc_wdt_regs_t* wdt, const sys_cfg_wdt_t* sys_cfg) +{ + return E_NO_ERROR; +} +/**@} end of ingroup MXC_sys*/ diff --git a/Project/SDK/Driver/Source/nvic_table.c b/Project/SDK/Driver/Source/nvic_table.c new file mode 100644 index 0000000..e7860c0 --- /dev/null +++ b/Project/SDK/Driver/Source/nvic_table.c @@ -0,0 +1,84 @@ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-06-05 16:53:29 -0500 (Wed, 05 Jun 2019) $ + * $Revision: 43696 $ + * + **************************************************************************** */ + + +#include "mxc_config.h" +#include +#include "nvic_table.h" + +#if !defined (NVIC_USER_IRQ_OFFSET) + #define NVIC_USER_IRQ_OFFSET 16 /**! Offset for device specific IRQs */ +#endif + +/* RAM vector_table needs to be aligned with the size of the vector table */ +#if defined ( __ICCARM__ ) + #pragma data_alignment = 512 +#else + __attribute__((aligned(512))) +#endif +static void (*ramVectorTable[MXC_IRQ_COUNT])(void); + +void NVIC_SetRAM(void) +{ +#if defined (__ICCARM__) + extern void (* const __isr_vector[])(void); +#else + /* should be defined in starup_.S */ + extern uint32_t __isr_vector[97]; +#endif + + memcpy(&ramVectorTable, &__isr_vector, sizeof(ramVectorTable)); + SCB->VTOR = (uint32_t)&ramVectorTable; +} + +void NVIC_SetVector(IRQn_Type irqn, void(*irq_handler)(void)) +{ + int index = irqn + 16; /* offset for externals */ + + /* If not copied, do copy */ + if (SCB->VTOR != (uint32_t)&ramVectorTable) { + NVIC_SetRAM(); + } + + ramVectorTable[index] = irq_handler; + NVIC_EnableIRQ(irqn); +} + +uint32_t NVIC_GetVector(IRQn_Type irqn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)irqn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/Project/SDK/Driver/Source/rtc.c b/Project/SDK/Driver/Source/rtc.c new file mode 100644 index 0000000..6012f46 --- /dev/null +++ b/Project/SDK/Driver/Source/rtc.c @@ -0,0 +1,419 @@ +/* **************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * + **************************************************************************** */ + +#include "mxc_config.h" +#include "rtc_regs.h" +#include "rtc.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "gpio_regs.h" +#include "mxc_errors.h" + +#if TARGET == 32650 + #include "pwrseq_regs.h" +#endif + +#define RTC_CTRL_RESET_DEFAULT (0x0000UL) +#define RTC_IS_BUSY (MXC_RTC->ctrl & MXC_F_RTC_CTRL_BUSY) +#define RTC_IS_ENABLED (MXC_RTC->ctrl & MXC_F_RTC_CTRL_RTCE) + +#define BUSY_TIMEOUT 1000 // Timeout counts for the Busy bit + +// ***************************************************************************** +int RTC_EnableTimeofdayInterrupt(mxc_rtc_regs_t *rtc) +{ + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_CTRL_ADE; // Enable Time-of-day Interrupt + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_DisableTimeofdayInterrupt(mxc_rtc_regs_t *rtc) +{ + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_CTRL_ADE; // Disable Time-of-day Interrupt + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_EnableSubsecondInterrupt(mxc_rtc_regs_t *rtc) +{ + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_CTRL_ASE; // Enable Sub-Second Interrupt + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_DisableSubsecondInterrupt(mxc_rtc_regs_t *rtc) +{ + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_CTRL_ASE; // Alarm Sub-Second Interrupt disabled + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras) +{ + // ras can only be written if BUSY = 0 & (RTCE = 0 or ADE = 0); + + + if(RTC_DisableTimeofdayInterrupt(rtc) == E_BUSY) { + return E_BUSY; + } + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ras = (ras << MXC_F_RTC_RAS_RAS_POS) & MXC_F_RTC_RAS_RAS; + + if(RTC_EnableTimeofdayInterrupt(rtc) == E_BUSY) { + return E_BUSY; + } + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa) +{ + // ras can only be written if BUSY = 0 & (RTCE = 0 or ASE = 0); + + if(RTC_DisableSubsecondInterrupt(rtc) == E_BUSY) { + return E_BUSY; + } + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->rssa = (rssa << MXC_F_RTC_RSSA_RSSA_POS) & MXC_F_RTC_RSSA_RSSA; + + if(RTC_EnableSubsecondInterrupt(rtc) == E_BUSY) { + return E_BUSY; + } + + return E_SUCCESS; +} + + +// ***************************************************************************** +int RTC_EnableRTCE(mxc_rtc_regs_t *rtc) +{ + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers + if (RTC_CheckBusy()) { + return E_BUSY; + } + // Can only write if WE=1 and BUSY=0 + rtc->ctrl |= MXC_F_RTC_CTRL_RTCE; // setting RTCE = 1 + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Prevent Writing... + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_DisableRTCE(mxc_rtc_regs_t *rtc) +{ + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers + if (RTC_CheckBusy()) { + return E_BUSY; + } + + // Can only write if WE=1 and BUSY=0 + rtc->ctrl &= ~MXC_F_RTC_CTRL_RTCE; // setting RTCE = 0 + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Prevent Writing... + + return E_SUCCESS; +} + + +// ***************************************************************************** +int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint8_t ssec, sys_cfg_rtc_t *sys_cfg) +{ +#if((TARGET == 32650) || (TARGET == 32660)) + SYS_ClockEnable_X32K(sys_cfg); +#else + SYS_RTCClockEnable(sys_cfg); +#endif + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl = MXC_F_RTC_CTRL_WE; // Allow Writes + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl = RTC_CTRL_RESET_DEFAULT; // Start with a Clean Register + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_CTRL_WE; // Set Write Enable, allow writing to reg. + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ssec = ssec; + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->sec = sec; + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Prevent Writing... + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft, + rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg) +{ + + SYS_RTC_SqwavInit(sys_cfg); // Set the Output pins for the squarewave. + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_CTRL_WE; // Allow writing to registers + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + if (sqe == SQUARE_WAVE_ENABLED) { + if (ft == F_32KHZ){ // if 32KHz output is selected... + rtc->oscctrl |= MXC_F_RTC_OSCCTRL_OUT32K; // Enable 32KHz wave + if (RTC_CheckBusy()) { + return E_BUSY; + } + rtc->ctrl |= MXC_F_RTC_CTRL_SQE; // Enable output on the pin + } else { // if 1Hz, 512Hz, 4KHz output is selected + + rtc->oscctrl &= ~MXC_F_RTC_OSCCTRL_OUT32K; // Must make sure that the 32KHz is disabled + if (RTC_CheckBusy()) { + return E_BUSY; + } + rtc->ctrl &= ~(MXC_F_RTC_CTRL_FT | MXC_F_RTC_CTRL_X32KMD); + if (RTC_CheckBusy()) { + return E_BUSY; + } + rtc->ctrl |= (MXC_F_RTC_CTRL_SQE | ft | x32kmd); // Enable Sq. wave, + } + + if (RTC_CheckBusy()) { + return E_BUSY; + } + rtc->ctrl |= MXC_F_RTC_CTRL_RTCE; // Enable Real Time Clock + } else { // Turn off the square wave output on the pin + + rtc->oscctrl &= ~MXC_F_RTC_OSCCTRL_OUT32K; // Must make sure that the 32KHz is disabled + if (RTC_CheckBusy()) { + return E_BUSY; + } + rtc->ctrl &= ~MXC_F_RTC_CTRL_SQE; // No sq. wave output + } + + if (RTC_CheckBusy()) { + return E_BUSY; + } + rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Disable Writing to register + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_Trim(mxc_rtc_regs_t *rtc, int8_t trim) +{ + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + rtc->ctrl |= MXC_F_RTC_CTRL_WE; + + if (RTC_CheckBusy()) { + return E_BUSY; + } + + MXC_SETFIELD(rtc->trim, MXC_F_RTC_TRIM_TRIM, trim << MXC_F_RTC_TRIM_TRIM_POS); + + if (RTC_CheckBusy()) { + return E_BUSY; + } + rtc->ctrl &= ~MXC_F_RTC_CTRL_WE; // Disable Writing to register + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_CheckBusy(void) +{ + // Time-out transfer if it takes > BUSY_TIMEOUT microseconds + mxc_delay_start(MXC_DELAY_USEC(BUSY_TIMEOUT)); + while (RTC_IS_BUSY) { + if (mxc_delay_check() != E_BUSY){ + return E_BUSY; + } + } + mxc_delay_stop(); + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_GetFlags(void) +{ + return MXC_RTC->ctrl & (MXC_F_RTC_CTRL_ALDF | MXC_F_RTC_CTRL_ALSF | MXC_F_RTC_CTRL_RDY); +} + +// ***************************************************************************** +int RTC_ClearFlags(int flags) +{ + if (RTC_CheckBusy()) { + return E_BUSY; + } + MXC_RTC->ctrl &= ~(flags & (MXC_F_RTC_CTRL_ALDF | MXC_F_RTC_CTRL_ALSF | MXC_F_RTC_CTRL_RDY)); + + return E_SUCCESS; +} + +// ***************************************************************************** +int RTC_GetSubSecond(void) +{ +#if TARGET == 32650 + int ssec; + if(ChipRevision > 0xA1){ + ssec = ((MXC_PWRSEQ->lpcn >> 12)& 0xF00) | (MXC_RTC->ssec & 0xFF); + }else{ + ssec = MXC_RTC->ssec; + } + return ssec; +#else + return MXC_RTC->ssec; +#endif +} + +// ***************************************************************************** +int RTC_GetSecond(void) +{ + return MXC_RTC->sec; +} + +// ***************************************************************************** +int RTC_GetTime(uint32_t* sec, uint32_t* subsec) +{ + uint32_t temp_sec; + do { + // Check if an update is about to happen. + if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) { + return E_BUSY; + } + + // Read the seconds count. + temp_sec = RTC_GetSecond(); + + // Check if an update is about to happen. + if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) { + return E_BUSY; + } + + // Read the sub-seconds count. + *subsec = RTC_GetSubSecond(); + + // Check if an update is about to happen. + if(!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) { + return E_BUSY; + } + + // Read the seconds count. + *sec = RTC_GetSecond(); + + // Repeat until a steady state is reached. + } while (temp_sec != *sec); + + return E_NO_ERROR; +} + +// ***************************************************************************** +int RTC_IsEnabled(void) +{ + return RTC_IS_ENABLED; +} diff --git a/Project/SDK/Driver/Source/spi.c b/Project/SDK/Driver/Source/spi.c new file mode 100644 index 0000000..ab193d5 --- /dev/null +++ b/Project/SDK/Driver/Source/spi.c @@ -0,0 +1,254 @@ +/** + * @file spi.c + * @brief This file contains the function implementations for the + * Serial Peripheral Interface (SPIMSS) peripheral module. + */ + +/* ***************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $ + * $Revision: 38560 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "spi.h" +#include "mxc_sys.h" +#include "spimss.h" +#include "spi17y.h" + +/** + * @ingroup spi + * @{ + */ + +/***** Definitions *****/ + + +/***** Functions *****/ + + +/* ************************************************************************ */ +int SPI_Init(spi_type spi_name, unsigned mode, unsigned freq) +{ + sys_cfg_spimss_t spimss_cfg; + sys_cfg_spi17y_t spi17y_cfg; + int error = E_NO_ERROR; + + if (spi_name == SPI0A) { + spi17y_cfg.map = MAP_A; + error = SPI17Y_Init(MXC_SPI17Y, mode, freq, &spi17y_cfg); + + } else if(spi_name == SPI1A) { + spimss_cfg.map = MAP_A; + error = SPIMSS_Init(MXC_SPIMSS, mode, freq, &spimss_cfg); + + } else if(spi_name == SPI1B) { + spimss_cfg.map = MAP_B; + error = SPIMSS_Init(MXC_SPIMSS, mode, freq, &spimss_cfg); + + } else { + return E_BAD_PARAM; + } + + return error; +} + +/* ************************************************************************ */ +int SPI_MasterTransAsync(spi_type spi_name, spi_req_t *req) +{ + int error = E_NO_ERROR; + + if (spi_name == SPI0A) { + error = SPI17Y_MasterTransAsync(MXC_SPI17Y, (spi17y_req_t *) req); + + } else if((spi_name == SPI1A) || (spi_name == SPI1B)) { + error = SPIMSS_MasterTransAsync(MXC_SPIMSS, (spimss_req_t *) req); + + } else { + return E_BAD_PARAM; + } + + return error; +} + + +/* ************************************************************************ */ +int SPI_MasterTrans(spi_type spi_name, spi_req_t *req) +{ + int error = E_NO_ERROR; + + if (spi_name == SPI0A) { + error = SPI17Y_MasterTrans(MXC_SPI17Y, (spi17y_req_t *) req); + + } else if((spi_name == SPI1A) || (spi_name == SPI1B)) { + error = SPIMSS_MasterTrans(MXC_SPIMSS, (spimss_req_t *) req); + + } else { + return E_BAD_PARAM; + } + + return error; +} + +/* ************************************************************************ */ +int SPI_SlaveTrans(spi_type spi_name, spi_req_t *req) +{ + int error = E_NO_ERROR; + + if (spi_name == SPI0A) { + error = SPI17Y_SlaveTrans(MXC_SPI17Y, (spi17y_req_t *) req); + + } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) { + error = SPIMSS_SlaveTrans(MXC_SPIMSS, (spimss_req_t *) req); + + } else { + return E_BAD_PARAM; + } + + return error; +} + +/* ************************************************************************ */ +int SPI_SlaveTransAsync(spi_type spi_name, spi_req_t *req) +{ + int error = E_NO_ERROR; + + if (spi_name == SPI0A) { + error = SPI17Y_SlaveTransAsync(MXC_SPI17Y, (spi17y_req_t *) req); + + } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) { + error = SPIMSS_SlaveTransAsync(MXC_SPIMSS, (spimss_req_t *) req); + + } else { + return E_BAD_PARAM; + } + + return error; +} + +/* ************************************************************************ */ +int SPI_Shutdown(spi_type spi_name) +{ + int error = E_NO_ERROR; + + if (spi_name == SPI0A) { + error = SPI17Y_Shutdown(MXC_SPI17Y); + + } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) { + error = SPIMSS_Shutdown(MXC_SPIMSS); + + } else { + return E_BAD_PARAM; + } + + return error; +} + + +/* ************************************************************************ */ +int SPI_AbortAsync(spi_type spi_name, spi_req_t *req) +{ + int error = E_NO_ERROR; + + if (spi_name == SPI0A) { + error = SPI17Y_AbortAsync((spi17y_req_t *) req); + + } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) { + error = SPIMSS_AbortAsync((spimss_req_t *) req); + + } else { + return E_BAD_PARAM; + } + + return error; +} + +/* ************************************************************************ */ +int SPI_Handler(spi_type spi_name) +{ + if (spi_name == SPI0A) { + SPI17Y_Handler(MXC_SPI17Y); + + } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) { + SPIMSS_Handler(MXC_SPIMSS); + + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +// ***************************************************************************** +int SPI_Enable(spi_type spi_name) +{ + if (spi_name == SPI0A) { + SPI17Y_Enable(MXC_SPI17Y); + + } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) { + return E_NOT_SUPPORTED; + } else { + return E_BAD_PARAM; + } + return E_NO_ERROR; +} + +// ***************************************************************************** +int SPI_Disable(spi_type spi_name) +{ + if (spi_name == SPI0A) { + SPI17Y_Disable(MXC_SPI17Y); + + } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) { + return E_NOT_SUPPORTED; + } else { + return E_BAD_PARAM; + } + return E_NO_ERROR; +} + +// ***************************************************************************** +int SPI_Clear_fifo(spi_type spi_name) +{ + if (spi_name == SPI0A) { + SPI17Y_Clear_fifo(MXC_SPI17Y); + + } else if ((spi_name == SPI1A) || (spi_name == SPI1B)) { + return E_NOT_SUPPORTED; + } else { + return E_BAD_PARAM; + } + return E_NO_ERROR; +} + +/**@} end of group spi */ diff --git a/Project/SDK/Driver/Source/spi17y.c b/Project/SDK/Driver/Source/spi17y.c new file mode 100644 index 0000000..b5cd967 --- /dev/null +++ b/Project/SDK/Driver/Source/spi17y.c @@ -0,0 +1,641 @@ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-06-25 10:15:10 -0500 (Tue, 25 Jun 2019) $ + * $Revision: 44277 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "tmr_utils.h" +#include "mxc_lock.h" +#include "spi17y.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + + +typedef struct { + spi17y_req_t *req; + int started; + unsigned last_size; + unsigned deass; +} spi17y_req_state_t; + +static spi17y_req_state_t states[MXC_SPI17Y_INSTANCES]; + +/* **** Functions **** */ +static int SPI17Y_TransSetup(mxc_spi17y_regs_t *spi, spi17y_req_t *req, int master); +static int SPI17Y_MasterTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async); +static int SPI17Y_TransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async); +static int SPI17Y_SlaveTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async); + +/* ************************************************************************** */ +int SPI17Y_Init(mxc_spi17y_regs_t *spi, unsigned int mode, unsigned int freq, + const sys_cfg_spi17y_t* sys_cfg) +{ + uint32_t freq_div; + int spi_num, error, hi_clk, lo_clk, scale; + + spi_num = MXC_SPI17Y_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + + if (mode > 3) { + return E_BAD_PARAM; + } + + if ((error = SYS_SPI17Y_Init(spi, sys_cfg)) != E_NO_ERROR) { + return error; + } + + states[spi_num].req = NULL; + states[spi_num].last_size = 0; + states[spi_num].deass = 1; + + // Enable SPI17Y + spi->ctrl0 = (MXC_F_SPI17Y_CTRL0_EN); + spi->ss_time = ((0x1 << MXC_F_SPI17Y_SS_TIME_PRE_POS) | + (0x1 << MXC_F_SPI17Y_SS_TIME_POST_POS) | + (0x1 << MXC_F_SPI17Y_SS_TIME_INACT_POS)); + + // Check if frequency is too high + if (freq > PeripheralClock) { + return E_BAD_PARAM; + } + + // Set the clock high and low + freq_div = PeripheralClock/ (freq); + hi_clk = freq_div/2; + lo_clk = freq_div/2; + scale = 0; + + if (freq_div %2) { + hi_clk +=1; + } + + while (hi_clk > 16 && scale < 9) { + hi_clk /= 2; + lo_clk /=2; + scale ++; + } + + spi->clk_cfg = ((lo_clk << MXC_F_SPI17Y_CLK_CFG_LO_POS) | + (hi_clk << MXC_F_SPI17Y_CLK_CFG_HI_POS)); + + MXC_SETFIELD(spi->clk_cfg, MXC_F_SPI17Y_CLK_CFG_SCALE, (scale << MXC_F_SPI17Y_CLK_CFG_SCALE_POS)); + + // Set the mode + spi->ctrl2 = (mode << MXC_F_SPI17Y_CTRL2_CPHA_POS); + + // Clear the interrupts + spi->int_fl = spi->int_fl; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int SPI17Y_Shutdown(mxc_spi17y_regs_t *spi) +{ + int spi_num, err; + spi17y_req_t *temp_req; + + // Disable and clear interrupts + spi->int_en = 0; + spi->int_fl = spi->int_fl; + + // Disable SPI17Y and FIFOS + spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN); + spi->dma &= ~(MXC_F_SPI17Y_DMA_TX_FIFO_EN | MXC_F_SPI17Y_DMA_RX_FIFO_EN); + + // Call all of the pending callbacks for this SPI17Y + spi_num = MXC_SPI17Y_GET_IDX(spi); + if (states[spi_num].req != NULL) { + + // Save the request + temp_req = states[spi_num].req; + + // Unlock this SPI17Y + mxc_free_lock((uint32_t*)&states[spi_num].req); + + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback(temp_req, E_SHUTDOWN); + } + } + + // Clear registers + spi->ctrl0 = 0; + spi->ctrl1 = 0; + spi->ctrl2 = 0; + spi->ss_time = 0; + + // Clear system level configurations + if ((err = SYS_SPI17Y_Shutdown(spi)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int SPI17Y_TransSetup(mxc_spi17y_regs_t *spi, spi17y_req_t *req, int master) +{ + int spi_num; + if ((req->tx_data == NULL) && (req->rx_data == NULL)) { + return E_BAD_PARAM; + } + + if ((req->width > SPI17Y_WIDTH_1) && (req->tx_data != NULL) && (req->rx_data != NULL)) { + return E_BAD_PARAM; + } + + // HW has problem with these two character sizes + if (req->bits == 1 || req->bits == 9) { + return E_BAD_PARAM; + } + spi_num = MXC_SPI17Y_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + MXC_ASSERT(req->ssel < MXC_SPI17Y_SS_INSTANCES); + + req->tx_num = 0; + req->rx_num = 0; + + if (req->len == 0) { + return E_NO_ERROR; + } + + states[spi_num].req = req; + states[spi_num].started = 0; + + // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive). + if (states[spi_num].deass == 1) { + spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN); + } + + if (master) { + // Enable master mode + + spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_MASTER; + + // Setup the slave select + MXC_SETFIELD(spi->ctrl0, MXC_F_SPI17Y_CTRL0_SS, ((0x1 << req->ssel) << MXC_F_SPI17Y_CTRL0_SS_POS)); + spi->ctrl2 |= ((req->ssel_pol << req->ssel)<ctrl0 &= ~MXC_F_SPI17Y_CTRL0_MASTER; + // Setup the slave select + spi->ctrl2 |= ((req->ssel_pol << 0)<bits != states[spi_num].last_size)) { + // Setup the character size + // Master should only change character size at the end of a transaction. No restrictions on when slave can change. + if (!master || (!(spi->stat & MXC_F_SPI17Y_STAT_BUSY) && (states[spi_num].deass == 1)) || !(spi->ctrl0 & MXC_F_SPI17Y_CTRL0_EN)) { + //disable spi to change transfer size + spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN); + // set bit size + states[spi_num].last_size = req->bits; + if (req->bits <16) { + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_NUMBITS, req->bits << MXC_F_SPI17Y_CTRL2_NUMBITS_POS); + } else { + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_NUMBITS, 0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS); + } + } else { + // cant change transfer size while spi is busy + return E_BAD_STATE; + } + } + + // Setup the data width + if (req->width == SPI17Y_WIDTH_4) { + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD); + } else if (req->width == SPI17Y_WIDTH_2) { + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL); + } else { + MXC_SETFIELD(spi->ctrl2, MXC_F_SPI17Y_CTRL2_DATA_WIDTH, MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO); + } + + // Setup the number of characters to transact + if (req->len > (MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR >> MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) { + return E_BAD_PARAM; + } + + if (req->rx_data != NULL) { + // The TX_NUM field is used for both RX and TX length when in 4-wire mode. + if(req->width == SPI17Y_WIDTH_1) { + MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR, + req->len << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS); + } else { + MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR, + req->len << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS); + } + spi->dma |= MXC_F_SPI17Y_DMA_RX_FIFO_EN; + } else { + spi->ctrl1 &= ~(MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR); + spi->dma &= ~(MXC_F_SPI17Y_DMA_RX_FIFO_EN); + } + + // Must use TXFIFO and NUM in full duplex + if (req->width == SPI17Y_WIDTH_1 + && !((spi->ctrl2 & MXC_F_SPI17Y_CTRL2_THREE_WIRE)>> MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) { + + if (req->tx_data == NULL) { + // Must have something to send, so we'll use the rx_data buffer initialized to 0. + memset(req->rx_data, 0, (req->bits > 8 ? req->len << 1 : req->len)); + req->tx_data = req->rx_data; + req->tx_num = 0; + } + } + + if(req->tx_data != NULL) { + MXC_SETFIELD(spi->ctrl1, MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR, + req->len << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS); + spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_EN; + } else { + spi->dma &= ~(MXC_F_SPI17Y_DMA_TX_FIFO_EN); + } + + spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR | MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR; + spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN); + + states[spi_num].deass = req->deass; + // Clear master done flag + spi->int_fl = MXC_F_SPI17Y_INT_FL_M_DONE; + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void SPI17Y_Handler(mxc_spi17y_regs_t *spi) +{ + int spi_num, rx_avail; + uint32_t flags; + + // Clear the interrupt flags + spi->int_en = 0; + flags = spi->int_fl; + spi->int_fl = flags; + + spi_num = MXC_SPI17Y_GET_IDX(spi); + // Figure out if this SPI17Y has an active request + if ((states[spi_num].req != NULL) && (flags)) { + if ((spi->ctrl0 & MXC_F_SPI17Y_CTRL0_MASTER)>> MXC_F_SPI17Y_CTRL0_MASTER_POS) { + do { + SPI17Y_MasterTransHandler(spi, states[spi_num].req, 1); + rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS; + } while ((states[spi_num].req->rx_data != NULL) && (rx_avail > (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) + >>MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)); + + } else { + do { + SPI17Y_SlaveTransHandler(spi, states[spi_num].req, 1); + rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS; + } while ((states[spi_num].req->rx_data != NULL) && (rx_avail > (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) + >>MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)); + + } + } + +} + +/* ************************************************************************** */ +int SPI17Y_MasterTrans(mxc_spi17y_regs_t *spi,spi17y_req_t *req) +{ + int error; + if ((error =SPI17Y_TransSetup(spi, req, 1)) != E_NO_ERROR) { + return error; + } + req->callback = NULL; + + while (SPI17Y_MasterTransHandler(spi,req,0)==0) { + } + + while (!(spi->int_fl & MXC_F_SPI17Y_INT_FL_M_DONE)) { + + } + + return E_NO_ERROR; +} + + +/* ************************************************************************** */ +int SPI17Y_SlaveTrans(mxc_spi17y_regs_t *spi, spi17y_req_t *req) +{ + int error; + if ((error =SPI17Y_TransSetup(spi, req,0)) != E_NO_ERROR) { + return error; + } + req->callback = NULL; + + while (SPI17Y_SlaveTransHandler(spi,req,0)==0) { + + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int SPI17Y_MasterTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req) +{ + int error; + if ((error =SPI17Y_TransSetup(spi, req, 1))!= E_NO_ERROR) { + return error; + } + + SPI17Y_MasterTransHandler(spi,req, 1); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int SPI17Y_SlaveTransAsync(mxc_spi17y_regs_t *spi, spi17y_req_t *req) +{ + int error; + if ((error =SPI17Y_TransSetup(spi, req, 0)) != E_NO_ERROR) { + return error; + } + + SPI17Y_SlaveTransHandler(spi,req, 1); + + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int SPI17Y_MasterTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req,uint8_t async) +{ + int retval; + int spi_num; + + spi_num = MXC_SPI17Y_GET_IDX(spi); + + // Leave slave select asserted at the end of the transaction + if (!req->deass) { + spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_SS_CTRL; + } + + retval = SPI17Y_TransHandler(spi,req, async); + + if (!states[spi_num].started) { + spi->ctrl0 |= MXC_F_SPI17Y_CTRL0_START; + states[spi_num].started = 1; + } + + // Deassert slave select at the end of the transaction + if (req->deass) { + spi->ctrl0 &= ~MXC_F_SPI17Y_CTRL0_SS_CTRL; + } + + return retval; +} + +/* ************************************************************************** */ +int SPI17Y_SlaveTransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async) +{ + return SPI17Y_TransHandler(spi,req, async); +} + +/* ************************************************************************** */ +// Returns non-zero if transactions is complete, or 0 if not. +int SPI17Y_TransHandler(mxc_spi17y_regs_t *spi, spi17y_req_t *req, uint8_t async) +{ + + unsigned tx_avail, rx_avail; + int remain, spi_num; + uint32_t int_en =0; + uint32_t length =0; + spi_num = MXC_SPI17Y_GET_IDX(spi); + + // Read/write 2x number of bytes if larger character size + if (req->bits > 8) { + length = req->len*2; + } else { + length = req->len; + } + + if (req->tx_data != NULL) { + // Need to know when all bytes are transmitted, so the callback can be triggered. + int_en |= MXC_F_SPI17Y_INT_EN_TX_EMPTY; + + // Calculate how many bytes we can write to the FIFO + tx_avail = MXC_SPI17Y_FIFO_DEPTH - ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) >> + MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS); + if ((length - req->tx_num) < tx_avail) { + tx_avail = (length - req->tx_num); + } + if (req->bits > 8) { + tx_avail &= ~(unsigned)0x1; + } + // Write the FIFO + while (tx_avail) { + if (tx_avail > 3) { + memcpy((void*)&spi->data32,&((uint8_t*)req->tx_data)[req->tx_num], 4); + + tx_avail -= 4; + req->tx_num += 4; + + } else if (tx_avail > 1) { + memcpy((void*)&spi->data16[0],&((uint8_t*)req->tx_data)[req->tx_num], 2); + + tx_avail -= 2; + req->tx_num += 2; + + } else if (req->bits<=8) { + spi->data8[0] = ((uint8_t*)req->tx_data)[req->tx_num++]; + + tx_avail -= 1; + } + } + } + + remain = length - req->tx_num; + + // Set the TX interrupts + if (remain) { + if (remain > MXC_SPI17Y_FIFO_DEPTH) { + // Set the TX FIFO almost empty interrupt if we have to refill + spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL) | + ((MXC_SPI17Y_FIFO_DEPTH) << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS)); + } else { + + spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL) | + ((remain) << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS)); + } + int_en |= MXC_F_SPI17Y_INT_EN_TX_THRESH; + + } + // Break out if we've transmitted all the bytes and not receiving + if ((req->rx_data == NULL) && (req->tx_num == length) && ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) == 0)) { + spi->int_en = 0; + int_en = 0; + mxc_free_lock((uint32_t*)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + return 1; + } + + + // Read the RX FIFO + if (req->rx_data != NULL) { + + // Wait for there to be data in the RX FIFO + rx_avail = (spi->dma & MXC_F_SPI17Y_DMA_RX_FIFO_CNT) >> MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS; + if ((length - req->rx_num) < rx_avail) { + rx_avail = (length - req->rx_num); + } + if (req->bits <= 8 || rx_avail >= 2) { + // Read from the FIFO + while (rx_avail) { + if (rx_avail > 3) { + memcpy(&((uint8_t*)req->rx_data)[req->rx_num], (void*)&spi->data32, 4); + rx_avail -= 4; + req->rx_num += 4; + + } else if (rx_avail > 1) { + memcpy(&((uint8_t*)req->rx_data)[req->rx_num], (void*)&spi->data16[0], 2); + rx_avail -= 2; + req->rx_num += 2; + + } else { + ((uint8_t*)req->rx_data)[req->rx_num++] = spi->data8[0]; + rx_avail -= 1; + } + // Don't read less than 2 bytes if we are using greater than 8 bit characters + if (rx_avail == 1 && req->bits > 8) { + break; + } + } + } + remain = length - req->rx_num; + if (remain) { + if (remain > MXC_SPI17Y_FIFO_DEPTH) { + spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) | + ((2) << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)); + } else { + spi->dma = ((spi->dma & ~MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL) | + ((remain-1) << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)); + } + int_en |= MXC_F_SPI17Y_INT_EN_RX_THRESH; + } + + // Break out if we've received all the bytes and we're not transmitting + if ((req->tx_data == NULL) && (req->rx_num == length)) { + spi->int_en = 0; + int_en = 0; + mxc_free_lock((uint32_t*)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + return 1; + } + } + + // Break out once we've transmitted and received all of the data + if ((req->rx_num == length) && (req->tx_num == length) && ((spi->dma & MXC_F_SPI17Y_DMA_TX_FIFO_CNT) == 0)) { + spi->int_en = 0; + int_en = 0; + mxc_free_lock((uint32_t*)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + return 1; + } + if(async){ + spi->int_en = int_en; + } + return 0; +} + +/* ************************************************************************* */ +int SPI17Y_AbortAsync(spi17y_req_t *req) +{ + int spi_num; + mxc_spi17y_regs_t *spi; + + // Check the input parameters + if (req == NULL) { + return E_BAD_PARAM; + } + + // Find the request, set to NULL + for (spi_num = 0; spi_num < MXC_SPI17Y_INSTANCES; spi_num++) { + if (req == states[spi_num].req) { + + spi = MXC_SPI17Y_GET_SPI17Y(spi_num); + + // Disable interrupts, clear the flags + spi->int_en = 0; + spi->int_fl = spi->int_fl; + + // Reset the SPI17Y to cancel the on ongoing transaction + spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN); + spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN); + + // Unlock this SPI17Y + mxc_free_lock((uint32_t*)&states[spi_num].req); + + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_ABORT); + } + + return E_NO_ERROR; + } + } + + return E_BAD_PARAM; +} + +// ***************************************************************************** +void SPI17Y_Enable(mxc_spi17y_regs_t* spi) +{ + spi->ctrl0 |= (MXC_F_SPI17Y_CTRL0_EN); +} + +// ***************************************************************************** +void SPI17Y_Disable(mxc_spi17y_regs_t* spi) +{ + spi->ctrl0 &= ~(MXC_F_SPI17Y_CTRL0_EN); +} + +// ***************************************************************************** +void SPI17Y_Clear_fifo(mxc_spi17y_regs_t* spi) +{ + spi->dma |= MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR | MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR; +} diff --git a/Project/SDK/Driver/Source/spimss.c b/Project/SDK/Driver/Source/spimss.c new file mode 100644 index 0000000..6dfa2be --- /dev/null +++ b/Project/SDK/Driver/Source/spimss.c @@ -0,0 +1,514 @@ + /** + * @file spimss.c + * @brief This file contains the function implementations for the + * Serial Peripheral Interface (SPIMSS) peripheral module. + */ + +/* ***************************************************************************** + * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-05-06 14:44:04 -0500 (Mon, 06 May 2019) $ + * $Revision: 43157 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "spimss.h" +#include "mxc_lock.h" + +/** + * @ingroup spimss + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ +typedef struct { + spimss_req_t *req; +} spimss_req_state_t; + +static spimss_req_state_t states[MXC_SPIMSS_INSTANCES]; + + +/* **** Functions **** */ +static int SPIMSS_TransSetup(mxc_spimss_regs_t *spi, spimss_req_t *req, int master); +static uint32_t SPIMSS_MasterTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req); +static uint32_t SPIMSS_TransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req); +static uint32_t SPIMSS_SlaveTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req); + +/* ************************************************************************** */ +int SPIMSS_Init(mxc_spimss_regs_t *spi, unsigned mode, unsigned freq, const sys_cfg_spimss_t* sys_cfg) +{ + int spi_num, error; + unsigned int spimss_clk; + unsigned int pol, pha; // Polarity and phase of the clock (SPI mode) + + spi_num = MXC_SPIMSS_GET_IDX(spi); + + MXC_ASSERT(spi_num >= 0); + + if (mode > 3) { + return E_BAD_PARAM; + } + + if ((error = SYS_SPIMSS_Init(spi, sys_cfg)) != E_NO_ERROR) { + return error; + } + + states[spi_num].req = NULL; + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Keep the SPI Disabled (This is the SPI Start) + + // Check if frequency is too high + if (freq > PeripheralClock) { + return E_BAD_PARAM; + } + + // Set the bit rate + spimss_clk = PeripheralClock; + spi->brg = (spimss_clk / freq) >> 1; + + // Set the mode + pol = mode >> 1; // Get the polarity out of the mode input value + pha = mode & 1; // Get the phase out of the mode input value + + spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_CLKPOL)) | (pol << MXC_F_SPIMSS_CTRL_CLKPOL_POS); // polarity + + spi->ctrl = (spi->ctrl & ~(MXC_F_SPIMSS_CTRL_PHASE)) | (pha << MXC_F_SPIMSS_CTRL_PHASE_POS); // phase + + spi->status &= ~(MXC_F_SPIMSS_STATUS_IRQ); + + return E_NO_ERROR; +} +/* ************************************************************************* */ +int SPIMSS_Shutdown(mxc_spimss_regs_t *spi) +{ + int spi_num, err; + spimss_req_t *temp_req; + + // Disable and turn off the SPI transaction. + spi->ctrl = 0; // Interrupts, SPI transaction all turned off + spi->status = 0; + spi->mod = 0; + + // Reset FIFO counters + spi->dma &= ~(MXC_F_SPIMSS_DMA_RX_FIFO_CNT|MXC_F_SPIMSS_DMA_TX_FIFO_CNT); + + // Call all of the pending callbacks for this SPI + spi_num = MXC_SPIMSS_GET_IDX(spi); + if (states[spi_num].req != NULL) { + + // Save the request + temp_req = states[spi_num].req; + + // Unlock this SPI + mxc_free_lock((uint32_t*)&states[spi_num].req); + + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback(temp_req, E_SHUTDOWN); + } + } + + spi->status = 0; + + // Clear system level configurations + if ((err = SYS_SPIMSS_Shutdown(spi)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int SPIMSS_TransSetup(mxc_spimss_regs_t *spi, spimss_req_t *req, int master) +{ + int spi_num; + + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Make sure the Initiation + // of SPI Start is disabled. + + spi->mod |= MXC_F_SPIMSS_MOD_TX_LJ; // Making sure data is left + // justified. + + if ((req->tx_data == NULL) && (req->rx_data == NULL)) { + return -1; + } + + spi_num = MXC_SPIMSS_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + + if (req->len == 0) { + return 0; + } + + req->tx_num = 0; + req->rx_num = 0; + + if (mxc_get_lock((uint32_t*)&states[spi_num].req, (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + if (master) { // Enable master mode + spi->ctrl |= MXC_F_SPIMSS_CTRL_MMEN; // SPI configured as master. + spi->mod |= MXC_F_SPIMSS_CTRL_MMEN; // SSEL pin is an output. + } else { // Enable slave mode + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_MMEN); // SPI configured as slave. + spi->mod &= ~(MXC_F_SPIMSS_CTRL_MMEN); // SSEL pin is an input. + } + + // Setup the character size + + if (req->bits <16) { + MXC_SETFIELD(spi->mod, MXC_F_SPIMSS_MOD_NUMBITS , req->bits << MXC_F_SPIMSS_MOD_NUMBITS_POS); + + } else { + MXC_SETFIELD(spi->mod, MXC_F_SPIMSS_MOD_NUMBITS , 0 << MXC_F_SPIMSS_MOD_NUMBITS_POS); + + } + + // Setup the slave select + spi->mod |= MXC_F_SPIMSS_MOD_SSV; // Assert a high on Slave Select, + // to get the line ready for active low later + + // Clear the TX and RX FIFO + spi->dma |= (MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR | MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void SPIMSS_Handler(mxc_spimss_regs_t *spi) // From the IRQ +{ + int spi_num; + uint32_t flags; + unsigned int int_enable; + + flags = spi->status; + spi->status = flags; + spi->status|= 0x80; // clear interrupt + + spi_num = MXC_SPIMSS_GET_IDX(spi); + + int_enable = 0; + if (states[spi_num].req != NULL) { + if ((spi->ctrl & MXC_F_SPIMSS_CTRL_MMEN) >> MXC_F_SPIMSS_CTRL_MMEN_POS) { + int_enable = SPIMSS_MasterTransHandler(spi, states[spi_num].req); + + } else { + int_enable = SPIMSS_SlaveTransHandler(spi, states[spi_num].req); + } + } + + if (int_enable==1) { + spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE ); + + } +} + +/* ************************************************************************** */ +int SPIMSS_MasterTrans(mxc_spimss_regs_t *spi, spimss_req_t *req) +{ + int error; + + if ((error = SPIMSS_TransSetup(spi, req, 1)) != E_NO_ERROR) { + return error; + } + + req->callback = NULL; + + spi->mod &= ~(MXC_F_SPIMSS_MOD_SSV); // This will assert the Slave Select. + spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI + + while (SPIMSS_MasterTransHandler(spi,req)!=0) { + } + + spi->mod |= MXC_F_SPIMSS_MOD_SSV; + + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Last of the SPIMSS value has been transmitted... + // stop the transmission... + return E_NO_ERROR; +} + + +/* ************************************************************************** */ +int SPIMSS_SlaveTrans(mxc_spimss_regs_t *spi, spimss_req_t *req) +{ + int error; + + if ((error = SPIMSS_TransSetup(spi, req,0)) != E_NO_ERROR) { + return error; + } + + while (SPIMSS_SlaveTransHandler(spi,req)!=0) { + spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI + while ((spi->status & MXC_F_SPIMSS_STATUS_TXST) == MXC_F_SPIMSS_STATUS_TXST) {} + } + + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); // Last of the SPIMSS value has been transmitted... + // stop the transmission... + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int SPIMSS_MasterTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req) +{ + int error; + uint8_t int_enable; + if ((error = SPIMSS_TransSetup(spi, req, 1) )!= E_NO_ERROR) { + return error; + } + + int_enable = SPIMSS_MasterTransHandler(spi,req); + + spi->mod ^= MXC_F_SPIMSS_MOD_SSV; // This will assert the Slave Select. + + spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI + + if (int_enable==1) { + spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR); + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int SPIMSS_SlaveTransAsync(mxc_spimss_regs_t *spi, spimss_req_t *req) +{ + int error; + uint8_t int_enable; + if ((error = SPIMSS_TransSetup(spi, req, 0)) != E_NO_ERROR) { + return error; + } + + int_enable = SPIMSS_SlaveTransHandler(spi,req); + + spi->ctrl |= MXC_F_SPIMSS_CTRL_SPIEN; // Enable/Start SPI + + if (int_enable==1) { // Trigger a SPI Interrupt + spi->ctrl |= (MXC_F_SPIMSS_CTRL_IRQE ); + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +uint32_t SPIMSS_MasterTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req) +{ + unsigned start_set = 0; + uint32_t retval; + + if (!start_set) { + start_set = 1; + retval = SPIMSS_TransHandler(spi,req); + } + + return retval; +} + +/* ************************************************************************** */ +uint32_t SPIMSS_SlaveTransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req) +{ + return SPIMSS_TransHandler(spi,req); +} + +/* ************************************************************************** */ +uint32_t SPIMSS_TransHandler(mxc_spimss_regs_t *spi, spimss_req_t *req) +{ + unsigned tx_avail, rx_avail; + int remain, spi_num; + uint32_t int_en =0; + uint32_t length =req->len; + + + spi_num = MXC_SPIMSS_GET_IDX(spi); + + // Read the RX FIFO + if (req->rx_data != NULL) { + // Wait for there to be data in the RX FIFO + rx_avail = ((spi->dma & MXC_F_SPIMSS_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS); + if ((length - req->rx_num) < rx_avail) { + rx_avail = (length - req->rx_num); + } + + // Read from the FIFO + while (rx_avail) { + + // Don't read less than 2 bytes if we are using greater than 8 bit characters + if (req->bits>8) { + ((uint16_t*)req->rx_data)[req->rx_num++] = spi->data16; + rx_avail -= 1; + + } else { + ((uint8_t*)req->rx_data)[req->rx_num++] = spi->data8[0]; + rx_avail -= 1; + } + rx_avail = ((spi->dma & MXC_F_SPIMSS_DMA_RX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS); + if ((length - req->rx_num) < rx_avail) { + rx_avail = (length - req->rx_num); + } + } + + remain = length - req->rx_num; + + if (remain) { + if (remain > MXC_SPIMSS_FIFO_DEPTH) { + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_RX_FIFO_CNT) | ((2) << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)); + } else { + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_RX_FIFO_CNT) | ((remain-1) << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)); + } + + int_en = 1; + } + + // Break out if we've received all the bytes and we're not transmitting + if ((req->tx_data == NULL) && (req->rx_num == length)) { + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR); + int_en = 0; + mxc_free_lock((uint32_t*)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + } + } + // Note:- spi->dma shows the FIFO TX count and FIFO RX count in + // Words, while the calculation below is in bytes. + if (req->tx_data != NULL) { + + if (req->tx_num < length) { + + // Calculate how many bytes we can write to the FIFO (tx_avail holds that value) + tx_avail = MXC_SPIMSS_FIFO_DEPTH - (((spi->dma & MXC_F_SPIMSS_DMA_TX_FIFO_CNT) >> MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)); // in bytes + + if ((length - req->tx_num) < tx_avail) { + tx_avail = (length - req->tx_num); // This is for the last spin + } + if (req->bits > 8) { + tx_avail &= ~(unsigned)0x1; + } + // Write the FIFO + while (tx_avail) { + if (req->bits >8) { + spi->data16 = ((uint16_t*)req->tx_data)[req->tx_num++]; + + tx_avail -= 1; + } else { + spi->data8[0] = ((uint8_t*)req->tx_data)[req->tx_num++]; + tx_avail -=1; + } + + } + } + + remain = length - req->tx_num; + + // If there are values remaining to be transmitted, this portion will get + // executed and int_en set, to indicate that this must spin and come back again... + if (remain) { + if (remain > MXC_SPIMSS_FIFO_DEPTH) { // more tx rounds will happen... Transfer the maximum, + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_TX_FIFO_CNT) | ((MXC_SPIMSS_FIFO_DEPTH) << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)); + } else { // only one more tx round will be done... Transfer whatever remains, + spi->dma = ((spi->dma & ~MXC_F_SPIMSS_DMA_TX_FIFO_CNT) | ((remain) << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)); + } + int_en = 1; // This will act as a trigger for the next round... + } + + // Break out if we've transmitted all the bytes and not receiving + if ((req->rx_data == NULL) && (req->tx_num == length)) { + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR); + int_en = 0; + mxc_free_lock((uint32_t*)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + } + } + + + // Break out once we've transmitted and received all of the data + if ((req->rx_num == length) && (req->tx_num == length)) { + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR); + int_en = 0; + mxc_free_lock((uint32_t*)&states[spi_num].req); + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + } + + return int_en; +} + +/* ************************************************************************* */ +int SPIMSS_AbortAsync(spimss_req_t *req) +{ + int spi_num; + mxc_spimss_regs_t *spi; + + // Check the input parameters + if (req == NULL) { + return E_BAD_PARAM; + } + + // Find the request, set to NULL + for (spi_num = 0; spi_num < MXC_SPIMSS_INSTANCES; spi_num++) { + if (req == states[spi_num].req) { + + spi = MXC_SPIMSS_GET_SPI(spi_num); + + // Disable interrupts, clear the flags + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_IRQE | MXC_F_SPIMSS_CTRL_STR); + + // Disable and turn off the SPI transaction. + spi->ctrl &= ~(MXC_F_SPIMSS_CTRL_SPIEN); + + // Unlock this SPI + mxc_free_lock((uint32_t*)&states[spi_num].req); + + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_ABORT); + } + return E_NO_ERROR; + } + } + + return E_BAD_PARAM; +} +/**@} end of group spimss */ diff --git a/Project/SDK/Driver/Source/tmr.c b/Project/SDK/Driver/Source/tmr.c new file mode 100644 index 0000000..0d222b8 --- /dev/null +++ b/Project/SDK/Driver/Source/tmr.c @@ -0,0 +1,307 @@ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2019-09-11 14:32:22 -0500 (Wed, 11 Sep 2019) $ + * $Revision: 46047 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "tmr.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************** */ +int TMR_Init(mxc_tmr_regs_t *tmr, tmr_pres_t pres, const sys_cfg_tmr_t* sys_cfg) +{ + MXC_ASSERT(tmr); + + int err; + // System settigns + if((err=SYS_TMR_Init(tmr, sys_cfg)) !=E_NO_ERROR) + { + return err; + } + + // Disable timer and clear settings + tmr->cn = 0; + + // Clear interrupt flag + tmr->intr = MXC_F_TMR_INTR_IRQ_CLR; + + // Set the prescaler + tmr->cn = pres; + + return err; +} + +int TMR_Shutdown(mxc_tmr_regs_t *tmr) +{ + MXC_ASSERT(tmr); + + int err; + // System settigns + if((err=SYS_TMR_Shutdown(tmr)) !=E_NO_ERROR) + { + return err; + } + + // Disable timer and clear settings + tmr->cn = 0; + + return err; +} + +/* ************************************************************************** */ +void TMR_Enable(mxc_tmr_regs_t* tmr) +{ + MXC_ASSERT(tmr); + + tmr->cn |= MXC_F_TMR_CN_TEN; +} + +/* ************************************************************************** */ +void TMR_Disable(mxc_tmr_regs_t* tmr) +{ + MXC_ASSERT(tmr); + + tmr->cn &= ~(MXC_F_TMR_CN_TEN); +} + +/* ************************************************************************** */ +int TMR_Config(mxc_tmr_regs_t *tmr, const tmr_cfg_t *cfg) +{ + MXC_ASSERT(tmr); + + // Configure the timer + tmr->cn = (tmr->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) | + ((cfg->mode << MXC_F_TMR_CN_TMODE_POS) & MXC_F_TMR_CN_TMODE) | + ((cfg->pol << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL); + + tmr->cnt = 0x1; + tmr->cmp = cfg->cmp_cnt; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int TMR_PWMConfig(mxc_tmr_regs_t *tmr, const tmr_pwm_cfg_t *cfg) +{ + if (cfg->duty_cnt > cfg->per_cnt) { + return E_BAD_PARAM; + } + + // Configure the timer + tmr->cn = (tmr->cn & ~(MXC_F_TMR_CN_TMODE | MXC_F_TMR_CN_TPOL)) | + MXC_S_TMR_CN_TMODE_PWM | ((cfg->pol << MXC_F_TMR_CN_TPOL_POS) & MXC_F_TMR_CN_TPOL); + + tmr->cnt = 0x1; + tmr->cmp = cfg->per_cnt; + tmr->pwm = cfg->duty_cnt; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int TMR_PWMSetDuty(mxc_tmr_regs_t *tmr, uint32_t duty) +{ + uint32_t cnt; + + // Make sure the new Duty count is less than the period count + if (duty > tmr->cmp) { + return E_BAD_PARAM; + } + + cnt = tmr->cnt; // make sure order of volatile access is known. + // Avoid glitching the output + if (duty >= tmr->pwm) { + // Wait for the count to be in the range of 1 to tmr->pwm + while (cnt > tmr->pwm) { + cnt = tmr->cnt; // update the volatile access variable + } + } else { + // Wait for the count to pass tmr->pwm + while (cnt < tmr->pwm) { + cnt = tmr->cnt; // update the volatile access variable + } + } + tmr->pwm = duty; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int TMR_PWMSetPeriod(mxc_tmr_regs_t *tmr, uint32_t per) +{ + // Make sure the new Duty count is less than the period count + if (tmr->pwm > per) { + return E_BAD_PARAM; + } + + // Wait for the count to be less than the new dut_cnt + while (tmr->cnt >= per) {} + tmr->cmp = per; + + return E_NO_ERROR; +} + + +/* ************************************************************************** */ +uint32_t TMR_GetCompare(mxc_tmr_regs_t* tmr) +{ + return tmr->cmp; +} + +/* ************************************************************************** */ +uint32_t TMR_GetCapture(mxc_tmr_regs_t* tmr) +{ + return tmr->pwm; +} + +/* ************************************************************************* */ +uint32_t TMR_GetCount(mxc_tmr_regs_t* tmr) +{ + return tmr->cnt; +} + +/* ************************************************************************* */ +void TMR_IntClear(mxc_tmr_regs_t* tmr) +{ + tmr->intr = MXC_F_TMR_INTR_IRQ_CLR; +} + +/* ************************************************************************* */ +uint32_t TMR_IntStatus(mxc_tmr_regs_t* tmr) +{ + return tmr->intr; +} + +/* ************************************************************************* */ +void TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt) +{ + tmr->cmp = cmp_cnt; +} + +/* ************************************************************************* */ +void TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt) +{ + tmr->cnt = cnt; +} + +/* ************************************************************************* */ +int TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, tmr_unit_t units, uint32_t *ticks) +{ + uint32_t unit_div0, unit_div1; + uint32_t timerClock; + uint32_t prescale; + uint64_t temp_ticks; + + timerClock = SYS_TMR_GetFreq(tmr); + prescale = ((tmr->cn & MXC_F_TMR_CN_PRES) >> MXC_F_TMR_CN_PRES_POS) + | (((tmr->cn & MXC_F_TMR_CN_PRES3) >> (MXC_F_TMR_CN_PRES3_POS))<<3); + + switch (units) { + case TMR_UNIT_NANOSEC: + unit_div0 = 1000000; + unit_div1 = 1000; + break; + case TMR_UNIT_MICROSEC: + unit_div0 = 1000; + unit_div1 = 1000; + break; + case TMR_UNIT_MILLISEC: + unit_div0 = 1; + unit_div1 = 1000; + break; + case TMR_UNIT_SEC: + unit_div0 = 1; + unit_div1 = 1; + break; + default: + return E_BAD_PARAM; + } + + temp_ticks = (uint64_t)time * (timerClock / unit_div0) / (unit_div1 * (1 << (prescale & 0xF))); + + //make sure ticks is within a 32 bit value + if (!(temp_ticks & 0xffffffff00000000) && (temp_ticks & 0xffffffff)) { + *ticks = temp_ticks; + return E_NO_ERROR; + } + + return E_INVALID; +} + +/* ************************************************************************* */ +int TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, tmr_unit_t *units) +{ + uint64_t temp_time = 0; + uint32_t timerClock = SYS_TMR_GetFreq(tmr); + uint32_t prescale = ((tmr->cn & MXC_F_TMR_CN_PRES) >> MXC_F_TMR_CN_PRES_POS) + | (((tmr->cn & MXC_F_TMR_CN_PRES3) >> (MXC_F_TMR_CN_PRES3_POS))<<3); + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000000); + if (!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = TMR_UNIT_NANOSEC; + return E_NO_ERROR; + } + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / (timerClock / 1000); + if (!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = TMR_UNIT_MICROSEC; + return E_NO_ERROR; + } + + temp_time = (uint64_t)ticks * 1000 * (1 << (prescale & 0xF)) / timerClock; + if (!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = TMR_UNIT_MILLISEC; + return E_NO_ERROR; + } + + temp_time = (uint64_t)ticks * (1 << (prescale & 0xF)) / timerClock; + if (!(temp_time & 0xffffffff00000000)) { + *time = temp_time; + *units = TMR_UNIT_SEC; + return E_NO_ERROR; + } + + return E_INVALID; +} diff --git a/Project/SDK/Driver/Source/tmr_utils.c b/Project/SDK/Driver/Source/tmr_utils.c new file mode 100644 index 0000000..b2043ec --- /dev/null +++ b/Project/SDK/Driver/Source/tmr_utils.c @@ -0,0 +1,168 @@ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-10-17 14:16:30 -0500 (Wed, 17 Oct 2018) $ + * $Revision: 38560 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include +#include "mxc_assert.h" +#include "tmr.h" +#include "tmr_utils.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************** */ +void TMR_Delay(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg) +{ + // Return immediately if delay is 0 + if (!us) { + return; + } + + TMR_TO_Start(tmr, us, sys_cfg); + + while (TMR_TO_Check(tmr) != E_TIME_OUT) {} +} + +/* ************************************************************************** */ +void TMR_TO_Start(mxc_tmr_regs_t *tmr, unsigned long us, const sys_cfg_tmr_t *sys_cfg) +{ + uint64_t ticks; + int clk_shift = 0; + + ticks = (uint64_t)us * (uint64_t)PeripheralClock / (uint64_t)1000000; + while (ticks > 0xFFFFFFFFUL) { + ticks >>= 1; + ++clk_shift; + } + tmr_pres_t prescale = (tmr_pres_t)(clk_shift << MXC_F_TMR_CN_PRES_POS); + + TMR_Init(tmr, prescale, sys_cfg); + + // Initialize the timer in one-shot mode + tmr_cfg_t cfg; + cfg.mode = TMR_MODE_ONESHOT; + cfg.cmp_cnt = ticks; + cfg.pol = 0; + + TMR_Disable(tmr); + TMR_Config(tmr, &cfg); + + TMR_IntClear(tmr); + TMR_Enable(tmr); +} + +/* ************************************************************************** */ +int TMR_TO_Check(mxc_tmr_regs_t *tmr) +{ + if (TMR_IntStatus(tmr)) { + return E_TIME_OUT; + } + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void TMR_TO_Stop(mxc_tmr_regs_t *tmr) +{ + TMR_Disable(tmr); + TMR_SetCount(tmr, 0x0); +} + +/* ************************************************************************** */ +void TMR_TO_Clear(mxc_tmr_regs_t *tmr) +{ + TMR_IntClear(tmr); + TMR_SetCount(tmr, 0x0); +} + +/* ************************************************************************** */ +unsigned int TMR_TO_Elapsed(mxc_tmr_regs_t *tmr) +{ + uint32_t elapsed; + tmr_unit_t units; + + TMR_GetTime(tmr, TMR_GetCount(tmr), &elapsed, &units); + + switch (units) { + case TMR_UNIT_NANOSEC: + default: + return (elapsed / 1000); + case TMR_UNIT_MICROSEC: + return (elapsed); + case TMR_UNIT_MILLISEC: + return (elapsed * 1000); + case TMR_UNIT_SEC: + return (elapsed * 1000000); + } +} + +/* ************************************************************************** */ +unsigned int TMR_TO_Remaining(mxc_tmr_regs_t *tmr) +{ + uint32_t remaining_ticks, remaining_time; + tmr_unit_t units; + + remaining_ticks = TMR_GetCompare(tmr) - TMR_GetCount(tmr); + TMR_GetTime(tmr, remaining_ticks, &remaining_time, &units); + + switch (units) { + case TMR_UNIT_NANOSEC: + default: + return (remaining_time / 1000); + case TMR_UNIT_MICROSEC: + return (remaining_time); + case TMR_UNIT_MILLISEC: + return (remaining_time * 1000); + case TMR_UNIT_SEC: + return (remaining_time * 1000000); + } +} + +/* ************************************************************************** */ +void TMR_SW_Start(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *sys_cfg) +{ + TMR_TO_Start(tmr, 0xFFFFFFFF, sys_cfg); +} + +/* ************************************************************************** */ +unsigned int TMR_SW_Stop(mxc_tmr_regs_t *tmr) +{ + unsigned int elapsed = TMR_TO_Elapsed(tmr); + TMR_TO_Stop(tmr); + return elapsed; +} diff --git a/Project/SDK/Driver/Source/uart.c b/Project/SDK/Driver/Source/uart.c new file mode 100644 index 0000000..34b43bf --- /dev/null +++ b/Project/SDK/Driver/Source/uart.c @@ -0,0 +1,718 @@ +/* **************************************************************************** + * Copyright (C) 2014-2018 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2020-09-08 13:28:39 -0500 (Tue, 08 Sep 2020) $ + * $Revision: 55611 $ + * + *************************************************************************** */ + +/* **** Includes **** */ +#include +#include +#include "mxc_config.h" +#include "mxc_assert.h" +#include "uart_regs.h" +#include "uart.h" +#include "mxc_lock.h" +#include "mxc_sys.h" + +/* **** Definitions **** */ + +#define UART_ER_IF (MXC_F_UART_INT_FL_RX_FRAME_ERROR | \ + MXC_F_UART_INT_FL_RX_PARITY_ERROR | \ + MXC_F_UART_INT_FL_RX_OVERRUN) + +#define UART_ER_IE (MXC_F_UART_INT_EN_RX_FRAME_ERROR | \ + MXC_F_UART_INT_EN_RX_PARITY_ERROR | \ + MXC_F_UART_INT_EN_RX_OVERRUN ) + +#define UART_RX_IF (MXC_F_UART_INT_FL_RX_FIFO_THRESH) + +#define UART_RX_IE (MXC_F_UART_INT_EN_RX_FIFO_THRESH) + +#define UART_TX_IF (MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY | \ + MXC_F_UART_INT_FL_TX_FIFO_THRESH) + +#define UART_TX_IE (MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY | \ + MXC_F_UART_INT_EN_TX_FIFO_THRESH) + +#if (TARGET == 32660) || (TARGET == 32665) +#define MAX_FACTOR 3 +#else +#define MAX_FACTOR 7 +#endif + +/* **** File Scope Data **** */ + +// Saves the state of the non-blocking read requests. +static uart_req_t *rx_states[MXC_UART_INSTANCES]; + +// Saves the state of the non-blocking write requests. +static uart_req_t *tx_states[MXC_UART_INSTANCES]; + + +/* **** Functions **** */ +static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num); +static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num, + uint32_t flags); +static uint32_t uart_error_check(mxc_uart_regs_t *uart); +static void uart_error_clear(mxc_uart_regs_t *uart); + +/* ************************************************************************* */ +uint32_t uart_error_check(mxc_uart_regs_t *uart) +{ + return (uart->int_fl & UART_ER_IF); +} + +/* ************************************************************************* */ +void uart_error_clear(mxc_uart_regs_t *uart) +{ + UART_ClearFlags(uart,UART_ER_IF); +} + +/* ************************************************************************* */ +int UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *cfg, const sys_cfg_uart_t* sys_cfg) +{ + int err; + int uart_num; + + uint32_t baud0 = 0, baud1 = 0,div; + int32_t factor = -1; + + // Get the state array index + uart_num = MXC_UART_GET_IDX(uart); + if (uart_num == -1) { + return E_BAD_PARAM; + } + + if ((err = SYS_UART_Init(uart, sys_cfg)) != E_NO_ERROR) { + return err; + } + + // Initialize state pointers + rx_states[uart_num] = NULL; + tx_states[uart_num] = NULL; + + // Drain FIFOs, enable UART, and set configuration + uart->ctrl = (MXC_F_UART_CTRL_ENABLE | cfg->parity | cfg->size | cfg->stop | cfg->flow | cfg->pol); + + // Set the baud rate + // Calculate divisor +#if (TARGET != 32660) + uart->ctrl |= cfg->clksel; + if (cfg->clksel == UART_CLKSEL_ALTERNATE) { + div = UART_ALTERNATE_CLOCK_HZ / ((cfg->baud)); + } else { + div = PeripheralClock / ((cfg->baud)); + } +#else + div = PeripheralClock / ((cfg->baud)); +#endif + // Search for integer and fractional baud rate registers based on divisor + do { + factor += 1; + baud0 = div >> (7-factor); // divide by 128,64,32,16 to extract integer part + baud1 = ((div << factor) - (baud0 << 7)); //subtract factor corrected div - integer parts + } while ((baud0 == 0) && (factor < MAX_FACTOR)); + + uart->baud0 = ((factor << MXC_F_UART_BAUD0_FACTOR_POS) | baud0); +#if (TARGET == 32660) || (TARGET == 32665) || (TARGET == 32650) + /* Erratum: + * Hardware bug causes exact baud rates to generate framing error. Slightly mis-adjust timing + * to help avoid this bug. + */ + if (baud1 > 3) { + uart->baud1 = baud1 - 3; + } else { + uart->baud1 = baud1 + 3; + } +#else + uart->baud1 = baud1; +#endif + + // Clear pending requests + rx_states[uart_num] = NULL; + tx_states[uart_num] = NULL; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int UART_Shutdown(mxc_uart_regs_t *uart) +{ + int uart_num; + uart_req_t *temp_req; + + // Get the state array index + uart_num = MXC_UART_GET_IDX(uart); + if (uart_num < 0) { + return E_BAD_PARAM; + } + + // Disable interrupts + uart->int_en = 0; + + // Flush RX and TX FIFOS + uart->ctrl |= (MXC_F_UART_CTRL_TX_FLUSH | MXC_F_UART_CTRL_RX_FLUSH); + + // Call all of the pending callbacks for this UART + if(rx_states[uart_num] != NULL) { + + // Save the request + temp_req = rx_states[uart_num]; + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback(temp_req, E_SHUTDOWN); + } + } + + if (tx_states[uart_num] != NULL) { + + // Save the request + temp_req = tx_states[uart_num]; + + // Unlock this UART to write + mxc_free_lock((uint32_t*)&tx_states[uart_num]); + + // Callback if not NULL + if (temp_req->callback != NULL) { + temp_req->callback(temp_req, E_SHUTDOWN); + } + } + // Wait for not busy + while (uart->status & (MXC_F_UART_STATUS_TX_BUSY | MXC_F_UART_STATUS_RX_BUSY)) { + + } + + // Shutdown the UART + uart->ctrl = 0; + + // Shutdown any system level setup + SYS_UART_Shutdown(uart); + + // Clear pending requests + rx_states[uart_num] = NULL; + tx_states[uart_num] = NULL; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +void UART_Handler(mxc_uart_regs_t *uart) +{ + int uart_num; // Holds the current index of rx_states or tx_states + uint32_t intst; + + // Get the state array index + uart_num = MXC_UART_GET_IDX(uart); + if (uart_num == -1) { + return; + } + + // Read and clear interrupts + intst = uart->int_fl; + uart->int_fl = intst; + + // Read interrupt + if (intst & (UART_RX_IF | UART_ER_IF)) { + UART_ReadHandler(uart, rx_states[uart_num], uart_num, intst); + } + + // Write Interrupt + if (intst & (UART_TX_IF | UART_ER_IF)) { + UART_WriteHandler(uart, tx_states[uart_num], uart_num); + } +} + +/* ************************************************************************* */ +static void UART_WriteHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num) +{ + int remain, avail; + req = tx_states[uart_num]; + + if (req == NULL) { + // Nothing to do + uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; // disable interrupt + return; + } + + // Refill the TX FIFO + avail = UART_NumWriteAvail(uart); + remain = req->len - req->num; + + while (avail && remain) { + uart->fifo = req->data[req->num++]; + remain--; + avail--; + } + + // See if we've sent all of the characters + if (req->len == req->num) { + // Disable interrupts + uart->int_en &= ~MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY; + + // Deinit state before callback in case another is requested + tx_states[uart_num] = NULL; + mxc_free_lock((uint32_t*)&tx_states[uart_num]); + + // Callback when we've written all the characters + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + } + // Enable the interrupts + uart->int_en |= UART_TX_IE | UART_ER_IE; + +} + +/* ************************************************************************* */ +static void UART_ReadHandler(mxc_uart_regs_t *uart, uart_req_t *req, int uart_num, + uint32_t flags) +{ + int remain, avail; + + if (req == NULL) { + // Nothing to do + uart->int_en &= ~(UART_RX_IE | UART_ER_IE); // disable interrupts + return; + } + // Save the data in the FIFO while we still need data + avail = UART_NumReadAvail(uart); + remain = req->len - req->num; + while (avail && remain) { + req->data[req->num++] = uart->fifo; + remain--; + avail--; + } + // Check for errors + if (flags & MXC_F_UART_INT_FL_RX_OVERRUN) { + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + if (req->callback != NULL) { + req->callback(req, E_OVERFLOW); + } + + return; + } + if (flags & (MXC_F_UART_INT_FL_RX_FRAME_ERROR | + MXC_F_UART_INT_FL_RX_PARITY_ERROR)) { + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + if (req->callback != NULL) { + req->callback(req, E_COMM_ERR); + } + + return; + } + // Check to see if we've received all of the characters. + if (req->num == req->len) { + // Disable interrupts + uart->int_en &= ~(UART_RX_IE | UART_ER_IE); + + // Deinit state before callback in case another is requested + rx_states[uart_num] = NULL; + + // Call the callback function + if (req->callback != NULL) { + req->callback(req, E_NO_ERROR); + } + + return; + } else if (req->num > (req->len - MXC_UART_FIFO_DEPTH)) { + // Set RX threshold less than FIFO_DEPTH characters if needed + uart->thresh_ctrl = ((req->len - req->num)<< + MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS); + } else { + uart->thresh_ctrl = MXC_UART_FIFO_DEPTH<< + MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS; + } +} + +/* ************************************************************************* */ +int UART_Read(mxc_uart_regs_t *uart, uint8_t *data, int len, int *num) +{ + int uart_num; // Holds the current index of rx_states + int char_read = 0; // Holds the number of characters successfully read + int error_code =0; // Holds the error to return while reading + + // Get the state array index + uart_num = MXC_UART_GET_IDX(uart); + if (uart_num < 0) { + return E_BAD_PARAM; + } + + // Check to make sure baud rate has been set + if (uart->baud0 == 0) { + return E_UNINITIALIZED; + } + + // Check data pointer + if (data == NULL) { + return E_BAD_PARAM; + } + + // Check if there is already a request in progress + if (rx_states[uart_num] != NULL) { + return E_BUSY; + } + + // Lock this UART from reading + while (mxc_get_lock((uint32_t*)&rx_states[uart_num], 1) != E_NO_ERROR) { + + } + + // Get bytes FIFO + while (char_read < len) { + // Wait for RXFIFO to not be empty + while (uart->status & MXC_F_UART_STATUS_RX_EMPTY) { + // Check for error + if (uart_error_check(uart) != E_NO_ERROR) { + if (uart->int_fl & MXC_F_UART_INT_FL_RX_OVERRUN) { + error_code = E_OVERFLOW; + } else { + error_code = E_COMM_ERR; + } + + uart_error_clear(uart); + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + return error_code; + } + } + data[char_read] = uart->fifo; + char_read++; + } + if (num != NULL) { + *num = char_read; + } + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + return char_read; +} + +/* ************************************************************************* */ +uint8_t UART_ReadByte(mxc_uart_regs_t *uart) +{ + + while (uart->status & MXC_F_UART_STATUS_RX_EMPTY) {} + + return uart->fifo; +} + +/* ************************************************************************* */ +int UART_Write(mxc_uart_regs_t *uart, const uint8_t *data, int len) +{ + int uart_num; // Holds the current index of tx_states + int char_written = 0; // Holds the number of characters successfully written + + // Get the state array index + uart_num = MXC_UART_GET_IDX(uart); + if (uart_num < 0) { + return E_BAD_PARAM; + } + + // Check to make sure baud rate has been set + if (uart->baud0 == 0) { + return E_UNINITIALIZED; + } + + // Check data pointer + if (data == NULL) { + return E_BAD_PARAM; + } + + // Check if there is already a request in progress + if (tx_states[uart_num] != NULL) { + return E_BUSY; + } + + // Lock this UART from writing + while (mxc_get_lock((uint32_t*)&tx_states[uart_num], 1) != E_NO_ERROR) { + + } + + // Clear errors + uart_error_clear(uart); + + // Put bytes into FIFO + while (char_written < len) { + UART_WriteByte(uart,data[char_written]); + char_written++; + } + + // Unlock this UART to write + mxc_free_lock((uint32_t*)&tx_states[uart_num]); + + return char_written; +} + +/* ************************************************************************* */ +void UART_WriteByte(mxc_uart_regs_t *uart, uint8_t data) +{ + + // Wait for TXFIFO if full + while (uart->status & MXC_F_UART_STATUS_TX_FULL) { + + } + + // Put data into fifo + uart->fifo = data; +} + +/* ************************************************************************* */ +int UART_ReadAsync(mxc_uart_regs_t *uart, uart_req_t *req) +{ + int uart_num; // Holds the current index of tx_states + uint32_t flags; // Holds the Interrupt flags + + // Check data pointer + if (req == NULL) { + return E_BAD_PARAM; + } + + // Get the state array index + uart_num = MXC_UART_GET_IDX(uart); + if (uart_num < 0) { + return E_BAD_PARAM; + } + + if (req->data == NULL) { + return E_NULL_PTR; + } + // Check to make sure baud rate has been set + if (uart->baud0 == 0) { + return E_UNINITIALIZED; + } + + // Check if there is already a request in progress + if (rx_states[uart_num] != NULL) { + return E_BUSY; + } + + if (!(req->len > 0)) { + return E_NO_ERROR; + } + + // Attempt to register this write request + if (mxc_get_lock((uint32_t*)&rx_states[uart_num], (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + // Clear the data counter + req->num = 0; + + // Clear Interrupt Flags + flags = uart->int_fl; + uart->int_fl = flags; + UART_ReadHandler(uart,req,uart_num,flags); + + // Enable the interrupts + uart->int_en |= UART_RX_IE | UART_ER_IE; + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int UART_WriteAsync(mxc_uart_regs_t *uart, uart_req_t *req) +{ + int uart_num; // Holds the current index of tx_states + + // Check data pointer + if (req == NULL) { + return E_BAD_PARAM; + } + + // Get the state array index + uart_num = MXC_UART_GET_IDX(uart); + if (uart_num < 0) { + return E_BAD_PARAM; + } + + if (req->data == NULL) { + return E_NULL_PTR; + } + // Check to make sure baud rate has been set + if (uart->baud0 == 0) { + return E_UNINITIALIZED; + } + + // Check if there is already a request in progress + if (tx_states[uart_num] != NULL) { + return E_BUSY; + } + if (!(req->len > 0)) { + return E_NO_ERROR; + } + // Attempt to register this write request + if (mxc_get_lock((uint32_t*)&tx_states[uart_num], (uint32_t)req) != E_NO_ERROR) { + return E_BUSY; + } + + // Clear the data counter + req->num = 0; + UART_WriteHandler(uart, req, uart_num); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int UART_Busy(mxc_uart_regs_t *uart) +{ + int uart_num = MXC_UART_GET_IDX(uart); // Holds the current index of tx_states + MXC_ASSERT(uart_num >= 0); + if ((uart->status & MXC_F_UART_STATUS_TX_BUSY) || (uart->status & MXC_F_UART_STATUS_RX_BUSY)) { + return E_BUSY; + } + // Check to see if there are any ongoing transactions and the UART has room in its FIFO + if ((tx_states[uart_num] == NULL) && + !(uart->status & MXC_F_UART_STATUS_TX_FULL)) { + + return E_NO_ERROR; + } + + return E_BUSY; +} + +/* ************************************************************************* */ +int UART_PrepForSleep(mxc_uart_regs_t *uart) +{ + if (UART_Busy(uart) != E_NO_ERROR) { + return E_BUSY; + } + + // Leave read interrupts enabled, if already enabled + uart->int_en &= (UART_RX_IE | UART_ER_IE); + + return E_NO_ERROR; +} + +/* ************************************************************************* */ +int UART_AbortAsync(uart_req_t *req) +{ + int uart_num; + + // Figure out if this was a read or write request, find the request, set to NULL + for (uart_num = 0; uart_num < MXC_UART_INSTANCES; uart_num++) { + if (req == rx_states[uart_num]) { + + // Disable read interrupts, clear flags. + MXC_UART_GET_UART(uart_num)->int_en &= ~(UART_RX_IE | UART_ER_IE); + MXC_UART_GET_UART(uart_num)->int_fl = (UART_RX_IF | UART_ER_IF); + + // Unlock this UART to read + mxc_free_lock((uint32_t*)&rx_states[uart_num]); + + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_ABORT); + } + + return E_NO_ERROR; + } + + if (req == tx_states[uart_num]) { + + // Disable write interrupts, clear flags. + MXC_UART_GET_UART(uart_num)->int_en &= ~(UART_TX_IE | UART_ER_IE); + MXC_UART_GET_UART(uart_num)->int_fl = (UART_TX_IF | UART_ER_IF); + + // Unlock this UART to write + mxc_free_lock((uint32_t*)&tx_states[uart_num]); + + // Callback if not NULL + if (req->callback != NULL) { + req->callback(req, E_ABORT); + } + + return E_NO_ERROR; + } + } + + return E_BAD_PARAM; +} + +/* ************************************************************************* */ +unsigned UART_NumWriteAvail(mxc_uart_regs_t *uart) +{ + return MXC_UART_FIFO_DEPTH - ((uart->status & MXC_F_UART_STATUS_TX_FIFO_CNT) >> + MXC_F_UART_STATUS_TX_FIFO_CNT_POS); +} + +/* ************************************************************************* */ +unsigned UART_NumReadAvail(mxc_uart_regs_t *uart) +{ + return ((uart->status & MXC_F_UART_STATUS_RX_FIFO_CNT) >> + MXC_F_UART_STATUS_RX_FIFO_CNT_POS); +} + +/* ************************************************************************* */ +unsigned UART_GetFlags(mxc_uart_regs_t *uart) +{ + return (uart->int_fl); +} + +/* ************************************************************************* */ +void UART_ClearFlags(mxc_uart_regs_t *uart, uint32_t mask) +{ + uart->int_fl = mask; +} + +/* ************************************************************************* */ +void UART_Enable(mxc_uart_regs_t *uart) +{ + uart->ctrl |= MXC_F_UART_CTRL_ENABLE; +} + +/* ************************************************************************* */ +void UART_Disable(mxc_uart_regs_t *uart) +{ + uart->ctrl &= ~MXC_F_UART_CTRL_ENABLE; +} + +/* ************************************************************************* */ +void UART_DrainRX(mxc_uart_regs_t *uart) +{ + uart->ctrl |= MXC_F_UART_CTRL_RX_FLUSH; +} + +/* ************************************************************************* */ +void UART_DrainTX(mxc_uart_regs_t *uart) +{ + uart->ctrl |= MXC_F_UART_CTRL_TX_FLUSH; +} diff --git a/Project/SDK/Driver/Source/wdt.c b/Project/SDK/Driver/Source/wdt.c new file mode 100644 index 0000000..934f467 --- /dev/null +++ b/Project/SDK/Driver/Source/wdt.c @@ -0,0 +1,129 @@ +/* ***************************************************************************** + * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of Maxim Integrated + * Products, Inc. shall not be used except as stated in the Maxim Integrated + * Products, Inc. Branding Policy. + * + * The mere transfer of this software does not imply any licenses + * of trade secrets, proprietary technology, copyrights, patents, + * trademarks, maskwork rights, or any other form of intellectual + * property whatsoever. Maxim Integrated Products, Inc. retains all + * ownership rights. + * + * $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $ + * $Revision: 40072 $ + * + **************************************************************************** */ + +/* **** Includes **** */ +#include "mxc_config.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "wdt.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ************************************************************************** */ +int WDT_Init(mxc_wdt_regs_t* wdt, sys_cfg_wdt_t sys_cfg) +{ + SYS_WDT_Init(wdt, sys_cfg); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void WDT_SetIntPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period) +{ + MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_CTRL_INT_PERIOD, period); +} + +/* ************************************************************************** */ +void WDT_SetResetPeriod(mxc_wdt_regs_t* wdt, wdt_period_t period) +{ + MXC_SETFIELD(wdt->ctrl, MXC_F_WDT_CTRL_RST_PERIOD, (period << (MXC_F_WDT_CTRL_RST_PERIOD_POS - MXC_F_WDT_CTRL_INT_PERIOD_POS))); +} + +/* ************************************************************************** */ +void WDT_Enable(mxc_wdt_regs_t* wdt, int enable) +{ + if (enable) { + wdt->ctrl |= MXC_F_WDT_CTRL_WDT_EN; + } else { + wdt->ctrl &= ~(MXC_F_WDT_CTRL_WDT_EN); + } +} + +/* ************************************************************************** */ +void WDT_EnableInt(mxc_wdt_regs_t* wdt, int enable) +{ + if (enable) { + wdt->ctrl |= MXC_F_WDT_CTRL_INT_EN; + } else { + wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_EN); + } +} + +/* ************************************************************************** */ +void WDT_EnableReset(mxc_wdt_regs_t* wdt, int enable) +{ + if (enable) { + wdt->ctrl |= MXC_F_WDT_CTRL_RST_EN; + } else { + wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_EN); + } +} + +/* ************************************************************************** */ +void WDT_ResetTimer(mxc_wdt_regs_t* wdt) +{ + wdt->rst = 0x00A5; + wdt->rst = 0x005A; +} + +/* ************************************************************************** */ +int WDT_GetResetFlag(mxc_wdt_regs_t* wdt) +{ + return !!(wdt->ctrl & MXC_F_WDT_CTRL_RST_FLAG); +} + +/* ************************************************************************** */ +void WDT_ClearResetFlag(mxc_wdt_regs_t* wdt) +{ + wdt->ctrl &= ~(MXC_F_WDT_CTRL_RST_FLAG); +} + +/* ************************************************************************** */ +int WDT_GetIntFlag(mxc_wdt_regs_t* wdt) +{ + return !!(wdt->ctrl & MXC_F_WDT_CTRL_INT_FLAG); +} + +/* ************************************************************************** */ +void WDT_ClearIntFlag(mxc_wdt_regs_t* wdt) +{ + wdt->ctrl &= ~(MXC_F_WDT_CTRL_INT_FLAG); +} diff --git a/Project/SDK/FlashLoader/MAX32660.FLM b/Project/SDK/FlashLoader/MAX32660.FLM new file mode 100644 index 0000000000000000000000000000000000000000..37d6bcdb0d4a9c946fdde14244a9783094cfe85c GIT binary patch literal 13696 zcmeHNeQaCTbw7`fq-ayNWJ;FpMp2(^#*u7E7O9WOjvb34DT~$@O;WOxI3+2H5}8OO zM^gS;>W?5xJtGKGbS>hg=sX~Q1S>WS+l*n@0;C;KYy&nlZSu!}VeL?0$bg`5R&UPM z4BGG9`>yyTIp|hk88+xTm-n3C`MBqvci+ADUFBMMVpP*KQpH9cq_}teK>JW_D1N8t=v`U zS>?A<*K=cYrBh^>_3r9}4_2$=w{ul!22z1s`~7PHZUgrZiS{I?T@c|iQbE^;DT4ism5ALjD*zbIDw`sI~)G@mH;HA~mV>fcAPoEB*Nu9~H z-=j3QfqRV_w>MHdf9y!@%V`zap+vHYS)e)@yvKiv1* z+j8{PS8~)oo0`oXyhjV%j^1l@a{EfEFxvEq_Nx~Yk=FUPe|yi7qT3G}+b}Yxf3W&s z8?yEZvgSb6K6wZ8=5^b!9nC5V8l*lYL)2FFK?(WP`HSCjwGQ<~WY zBIF=ZILHrmqMJ=13{(`3or~nQez!8Pm4U4cY-M0816vu`%D`3zwlc7lfvpT|Wne1< zTN(KOlmV@sjx^xrs~v;VaY42_(t>*eFS*@MxpfzjW0$789&pG4$@t%5bhSl4x$z}L>vOq9ydv1FJnaeU_f6`a$h6SBT|FOR>qll)J@#9 z?SSV<%g{EWFG>>kEDGzdCu&!W+r7hG57+w}M3@Jj5RKP?hO_?|6GR8OvBBHpg21pk z8ik;<2_0itc!GzRWa6;Ih`O3Ej_xLeLe#@oJx5s5UoZ80CBqgzg%kOkG>)&YiCB-Q zp9!LY9#|f0c(UPWgYG(6A8C=f8C(xb@QE6D%G4XGLDJknuSeH|3>~XMr&<_zvIa;) zqT}l!q7yaX6ms=cjje?`jFg>RFW_Jq9d}4No_m#VAinNU>w=OxZ9J;D>ui#U@^BqT;Ovq#LP*}a%eXZMP^ey(45 zvTf^v;?s&Ddd4IX^s|y=h4YdmdQNF_pI=f;R|B(2lXWtal8lt3CByh!Kf0H_W(0|j z=9%DbvP=*yI7G9^4Zr9)hZ!qT-Xvl5yd;TUP-6DKq!`)rveIW+fgSSuSQG?&l+*|~ z*}o#0ll8~JlqJ*J!f{m;LsT6QZ}7^KBBK{h&|U<5ahJwxEzzapCV@m#FDl>7>gn=w zCUclTE9EWp_DTPFJ1F<=W=j?sB{8T{}P9#-+Lb+cw-!-DmWJ5w4Xk zP>N@|)xwW~=Idvc_oGgjd^6e{Y83S}YM|-bYj|Bq;lBxb)`GK7*1v~32*p6tm6sjA zW`9NhicQ$P3k+A=DE93=J?F)3`*gf#jDp4GQn8RNRF4^f*rdU1ekofv26}o2jg``T zx|%fxjE=dL{L;KJ;2-KV62;;Yl*`M(pz&<~eBYqo_Z(>yJa&FOn_o&^81Vbg!$+b!w|*Gu0voTG8|acQoq!t{g|)#9ioC((DXlX$#EHm#qlTkylaG zGgN8l$$WlK5Z#NitMPlHJ&z~4E}m$4@$-y_-+{ z)!55`Rijn*F&UD57?O=lB_!`{i-qIi*lak|D}jzRz$bw&X%Pw}0;WoD4Ka24YY0-n zqaCUteG)lN(b0(jQo`?GD7!!&kEV6&`;q6Pe{a{GbuOnb<(HES{P(|Pv6L(oD^(JI zk^Uy0tvSD3{~PnYq&nrbrf~wZ-L(Uo5nZPJycE-mwfXN5s-N@x=NJwmhTlhPm-Bh^ z;<|AO-S2sePX1WaCN|~0oW&}R(uMjhCL;H>uVdX|p0}x6j6L-|oAwpW5h>*HkUXyn z!36LNsQEOns$ZjjfSY_~=>?|$hUtYuhUq^A{iS5GoUN=ZRSCvg)TYr>FX`IXG{;O~ z%_sZgeQ%C^nznC0-1e@neM@tQWjC11mqbWx%G=`z>W1#d(B02;?K`H4xxn%`*x(-O zepD}F<)I|4vED)eu>RDpeWW>f*)OM;#ZJN2Y{^f8i^@WpM_#$Y1Lx_IpIgDyze_)X z$~wn?06=T`x&5!8U%{`OnqcxC6xh_aHuf>&f3(YSW-R>iM~6lV$wcdf&D^)(IZO#vD@j;fOnzetC32NnYL zKc{GKR+>Qhdzjh#kKah<5 zva6juI!C>J(RtWWr|*Ctj1=ZPX4W-_V|5|T;2&m)0A}@U<}lck8^dwzcDVJc>}K~m zA5HodfOYyd9`)mps$gnk(w%K=C-bx+M_BVTjaQ6+MzzzI=^Ni*iq{VteVIQYMd1~R zcR*mGWed>!c8L2(Zf0^(xW8sc=nYV1QMgR4Qj6;LHI~JuEZDs zyXQ#O>0qoUl#c0tlTJTrCza0GNGLIu#M4pP@*#*3DHY!YNo2z4I68>D2L&7t2NTn= zWc(SUL#79kQ6U+L#S_VR?yW2L}2E zF+ofXIXy<`6elOjM2hUd{?W;!|gHoP7-`Xf+xKwU>wJ3Jq_xg12b ziJOBI7KZ@p!#);Rb5UyIis(AD{si1cO&o7|84{<=Q7i-Ifs@yw+WGOW;>@Gr&%j#` zdvHL}A6nye z;yY|r?DX*}=T#M~Gvoy`1pRunIzm6BglJiR04@8w)5vn2hAr|&+sCUv0?#q>PT|4s z#k*BEYOBdRA&h|LxLNK7KWX9lo|o4}UJhB_3jR&de1FA!2l$Uc^Su@G{b)H}_P5Js zqagU>7JeN3u!T>6SMl$%;SB1nl6M~e^^~*eCEQ@8<;0Rlv7T!7Qk8mYFm8WvqU^~O z3ze!sNBFKQP_346X0K)|UTl9 z`(`HmKJU3>6F#3e4kQjF4kQu|hw*#X8#^0~c(2A2Jaw&aCO;RRODMy*=#vzF@fd#T%P3soF69d^hzrGmtp7Q}{o(`z z-Q5*Dh)fm4QZYTBOygoKxtuN~^M!>XK#;6+d3mn5Q~@=gPcJ4bE2R=XGb<;K9_{mW zO$_$+4nUMCt(*wreldHgd$J$=0{D1wp*lMn1-F#1R8RD*-B0q|1xhY7e3Z%t4)~tSm35%a{3^sL~~WtHo-1snWGlSgB;^yDnr4S=?K0 z$1{R+zH?p11#ATi%L3nmlyHq!{N+=*;bvB{NKAHaWzp!)7~RF5^R<2u^nA9IEzDym zYv?@CjoC_n3a8opG-YAdam(;2H)X=Sbe2NmkU`&>=Wp{_c_Q6mj71^`{9beX^Fyp*7jt%SFr$p{1STD zg@inZe$m}pQGMt3F?G06GQMxLghSQCL@5Y)U)qk!`Qvn6MYVK8@8b}|da5Y$6##tBQl-B~ ko^KSdp2w>Ilnu+G(EGln110-9WEPlk_NF^*U>2qKpS403`Tzg` literal 0 HcmV?d00001 diff --git a/Project/SDK/Startup/startup_max32660.s b/Project/SDK/Startup/startup_max32660.s new file mode 100644 index 0000000..6bddd01 --- /dev/null +++ b/Project/SDK/Startup/startup_max32660.s @@ -0,0 +1,373 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. + ; + ; Permission is hereby granted, free of charge, to any person obtaining a + ; copy of this software and associated documentation files (the "Software"), + ; to deal in the Software without restriction, including without limitation + ; the rights to use, copy, modify, merge, publish, distribute, sublicense, + ; and/or sell copies of the Software, and to permit persons to whom the + ; Software is furnished to do so, subject to the following conditions: + ; + ; The above copyright notice and this permission notice shall be included + ; in all copies or substantial portions of the Software. + ; + ; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + ; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + ; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + ; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES + ; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + ; OTHER DEALINGS IN THE SOFTWARE. + ; + ; Except as contained in this notice, the name of Maxim Integrated + ; Products, Inc. shall not be used except as stated in the Maxim Integrated + ; Products, Inc. Branding Policy. + ; + ; The mere transfer of this software does not imply any licenses + ; of trade secrets, proprietary technology, copyrights, patents, + ; trademarks, maskwork rights, or any other form of intellectual + ; property whatsoever. Maxim Integrated Products, Inc. retains all + ; ownership rights. + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; To map FreeRTOS function names to their CMSIS equivalents add following lines to FreeRTOSConfig.h +; #define vPortSVCHandler SVC_Handler +; #define xPortPendSVHandler PendSV_Handler +; #define xPortSysTickHandler SysTick_Handler +; *------- <<< Use Configuration Wizard in Context Menu to Modify Stack Size and Heap Size. >>> ---- + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp ; Name used with Keil Configuration Wizard and Keil MicroLib + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + EXPORT __isr_vector + IMPORT SysTick_Handler + +__isr_vector DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Device-specific Interrupts + DCD PF_IRQHandler ; 0x10 0x0040 16: Power Fail + DCD WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0 + DCD RSV00_IRQHandler ; 0x12 0x0048 18: RSV00 + DCD RTC_IRQHandler ; 0x13 0x004C 19: RTC + DCD RSV01_IRQHandler ; 0x14 0x0050 20: RSV1 + DCD TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0 + DCD TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1 + DCD TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2 + DCD RSV02_IRQHandler ; 0x18 0x0060 24: RSV02 + DCD RSV03_IRQHandler ; 0x19 0x0064 25: RSV03 + DCD RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04 + DCD RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05 + DCD RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06 + DCD I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0 + DCD UART0_IRQHandler ; 0x1E 0x0078 30: UART 0 + DCD UART1_IRQHandler ; 0x1F 0x007C 31: UART 1 + DCD SPI0_IRQHandler ; 0x20 0x0080 32: SPIY17 + DCD SPI1_IRQHandler ; 0x21 0x0084 33: SPIMSS + DCD RSV07_IRQHandler ; 0x22 0x0088 34: RSV07 + DCD RSV08_IRQHandler ; 0x23 0x008C 35: RSV08 + DCD RSV09_IRQHandler ; 0x24 0x0090 36: RSV09 + DCD RSV10_IRQHandler ; 0x25 0x0094 37: RSV10 + DCD RSV11_IRQHandler ; 0x26 0x0098 38: RSV11 + DCD FLC_IRQHandler ; 0x27 0x009C 39: FLC + DCD GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0 + DCD RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12 + DCD RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13 + DCD RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14 + DCD DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0 + DCD DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1 + DCD DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2 + DCD DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3 + DCD RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15 + DCD RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16 + DCD RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17 + DCD RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18 + DCD I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1 + DCD RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19 + DCD RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20 + DCD RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21 + DCD RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22 + DCD RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23 + DCD RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24 + DCD RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25 + DCD RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26 + DCD RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27 + DCD RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28 + DCD RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29 + DCD RSV30_IRQHandler ; 0x40 0x0100 64: RSV30 + DCD RSV31_IRQHandler ; 0x41 0x0104 65: RSV31 + DCD RSV32_IRQHandler ; 0x42 0x0108 66: RSV32 + DCD RSV33_IRQHandler ; 0x43 0x010C 67: RSV33 + DCD RSV34_IRQHandler ; 0x44 0x0110 68: RSV34 + DCD RSV35_IRQHandler ; 0x45 0x0114 69: RSV35 + DCD GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup +__isr_vector_end + +__isr_vector_size EQU __isr_vector_end - __isr_vector +__Vectors EQU __isr_vector +__Vectors_End EQU __isr_vector_end +__Vectors_Size EQU __isr_vector_size + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT PreInit + ;IMPORT SystemInit + IMPORT __main + LDR R0, =PreInit ; Call to PreInit (prior to RAM initialization) + BLX R0 + LDR R0, =__main ; SystemInit() is called from post scatter memory initialization in function $Sub$$__main_after_scatterload - system_max32660.c + BX R0 +__SPIN + WFI + BL __SPIN + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +Default_Handler\ + PROC + ; MAX32660 Device-specific Interrupts + EXPORT PF_IRQHandler [WEAK] ; 0x10 0x0040 16: Power Fail + EXPORT WDT0_IRQHandler [WEAK] ; 0x11 0x0044 17: Watchdog 0 + EXPORT RSV00_IRQHandler [WEAK] ; 0x12 0x0048 18: RSV00 + EXPORT RTC_IRQHandler [WEAK] ; 0x13 0x004C 19: RTC + EXPORT RSV01_IRQHandler [WEAK] ; 0x14 0x0050 20: RSV01 + EXPORT TMR0_IRQHandler [WEAK] ; 0x15 0x0054 21: Timer 0 + EXPORT TMR1_IRQHandler [WEAK] ; 0x16 0x0058 22: Timer 1 + EXPORT TMR2_IRQHandler [WEAK] ; 0x17 0x005C 23: Timer 2 + EXPORT RSV02_IRQHandler [WEAK] ; 0x18 0x0060 24: RSV02 + EXPORT RSV03_IRQHandler [WEAK] ; 0x19 0x0064 25: RSV03 + EXPORT RSV04_IRQHandler [WEAK] ; 0x1A 0x0068 26: RSV04 + EXPORT RSV05_IRQHandler [WEAK] ; 0x1B 0x006C 27: RSV05 + EXPORT RSV06_IRQHandler [WEAK] ; 0x1C 0x0070 28: RSV06 + EXPORT I2C0_IRQHandler [WEAK] ; 0x1D 0x0074 29: I2C0 + EXPORT UART0_IRQHandler [WEAK] ; 0x1E 0x0078 30: UART 0 + EXPORT UART1_IRQHandler [WEAK] ; 0x1F 0x007C 31: UART 1 + EXPORT SPI0_IRQHandler [WEAK] ; 0x20 0x0080 32: SPIY17 + EXPORT SPI1_IRQHandler [WEAK] ; 0x21 0x0084 33: SPIMSS + EXPORT RSV07_IRQHandler [WEAK] ; 0x22 0x0088 34: RSV07 + EXPORT RSV08_IRQHandler [WEAK] ; 0x23 0x008C 35: RSV08 + EXPORT RSV09_IRQHandler [WEAK] ; 0x24 0x0090 36: RSV09 + EXPORT RSV10_IRQHandler [WEAK] ; 0x25 0x0094 37: RSV10 + EXPORT RSV11_IRQHandler [WEAK] ; 0x26 0x0098 38: RSV11 + EXPORT FLC_IRQHandler [WEAK] ; 0x27 0x009C 39: FLC + EXPORT GPIO0_IRQHandler [WEAK] ; 0x28 0x00A0 40: GPIO0 + EXPORT RSV12_IRQHandler [WEAK] ; 0x29 0x00A4 41: RSV12 + EXPORT RSV13_IRQHandler [WEAK] ; 0x2A 0x00A8 42: RSV13 + EXPORT RSV14_IRQHandler [WEAK] ; 0x2B 0x00AC 43: RSV14 + EXPORT DMA0_IRQHandler [WEAK] ; 0x2C 0x00B0 44: DMA0 + EXPORT DMA1_IRQHandler [WEAK] ; 0x2D 0x00B4 45: DMA1 + EXPORT DMA2_IRQHandler [WEAK] ; 0x2E 0x00B8 46: DMA2 + EXPORT DMA3_IRQHandler [WEAK] ; 0x2F 0x00BC 47: DMA3 + EXPORT RSV15_IRQHandler [WEAK] ; 0x30 0x00C0 48: RSV15 + EXPORT RSV16_IRQHandler [WEAK] ; 0x31 0x00C4 49: RSV16 + EXPORT RSV17_IRQHandler [WEAK] ; 0x32 0x00C8 50: RSV17 + EXPORT RSV18_IRQHandler [WEAK] ; 0x33 0x00CC 51: RSV18 + EXPORT I2C1_IRQHandler [WEAK] ; 0x34 0x00D0 52: I2C1 + EXPORT RSV19_IRQHandler [WEAK] ; 0x35 0x00D4 53: RSV19 + EXPORT RSV20_IRQHandler [WEAK] ; 0x36 0x00D8 54: RSV20 + EXPORT RSV21_IRQHandler [WEAK] ; 0x37 0x00DC 55: RSV21 + EXPORT RSV22_IRQHandler [WEAK] ; 0x38 0x00E0 56: RSV22 + EXPORT RSV23_IRQHandler [WEAK] ; 0x39 0x00E4 57: RSV23 + EXPORT RSV24_IRQHandler [WEAK] ; 0x3A 0x00E8 58: RSV24 + EXPORT RSV25_IRQHandler [WEAK] ; 0x3B 0x00EC 59: RSV25 + EXPORT RSV26_IRQHandler [WEAK] ; 0x3C 0x00F0 60: RSV26 + EXPORT RSV27_IRQHandler [WEAK] ; 0x3D 0x00F4 61: RSV27 + EXPORT RSV28_IRQHandler [WEAK] ; 0x3E 0x00F8 62: RSV28 + EXPORT RSV29_IRQHandler [WEAK] ; 0x3F 0x00FC 63: RSV29 + EXPORT RSV30_IRQHandler [WEAK] ; 0x40 0x0100 64: RSV30 + EXPORT RSV31_IRQHandler [WEAK] ; 0x41 0x0104 65: RSV31 + EXPORT RSV32_IRQHandler [WEAK] ; 0x42 0x0108 66: RSV32 + EXPORT RSV33_IRQHandler [WEAK] ; 0x43 0x010C 67: RSV33 + EXPORT RSV34_IRQHandler [WEAK] ; 0x44 0x0110 68: RSV34 + EXPORT RSV35_IRQHandler [WEAK] ; 0x45 0x0114 69: RSV35 + EXPORT GPIOWAKE_IRQHandler [WEAK] ; 0x46 0x0118 70: GPIO Wakeup + +;******************************************************************************* +; Default handler implementations +;******************************************************************************* +PF_IRQHandler ; 0x10 0x0040 16: Power Fail +WDT0_IRQHandler ; 0x11 0x0044 17: Watchdog 0 +RSV00_IRQHandler ; 0x12 0x0048 18: RSV00 +RTC_IRQHandler ; 0x13 0x004C 19: RTC +RSV01_IRQHandler ; 0x14 0x0050 20: RSV01 +TMR0_IRQHandler ; 0x15 0x0054 21: Timer 0 +TMR1_IRQHandler ; 0x16 0x0058 22: Timer 1 +TMR2_IRQHandler ; 0x17 0x005C 23: Timer 2 +RSV02_IRQHandler ; 0x18 0x0060 24: RSV02 +RSV03_IRQHandler ; 0x19 0x0064 25: RSV03 +RSV04_IRQHandler ; 0x1A 0x0068 26: RSV04 +RSV05_IRQHandler ; 0x1B 0x006C 27: RSV05 +RSV06_IRQHandler ; 0x1C 0x0070 28: RSV06 +I2C0_IRQHandler ; 0x1D 0x0074 29: I2C0 +UART0_IRQHandler ; 0x1E 0x0078 30: UART 0 +UART1_IRQHandler ; 0x1F 0x007C 31: UART 1 +SPI0_IRQHandler ; 0x20 0x0080 32: SPI0 +SPI1_IRQHandler ; 0x21 0x0084 33: SPI1 +RSV07_IRQHandler ; 0x22 0x0088 34: RSV07 +RSV08_IRQHandler ; 0x23 0x008C 35: RSV08 +RSV09_IRQHandler ; 0x24 0x0090 36: RSV09 +RSV10_IRQHandler ; 0x25 0x0094 37: RSV10 +RSV11_IRQHandler ; 0x26 0x0098 38: RSV11 +FLC_IRQHandler ; 0x27 0x009C 39: FLC +GPIO0_IRQHandler ; 0x28 0x00A0 40: GPIO0 +RSV12_IRQHandler ; 0x29 0x00A4 41: RSV12 +RSV13_IRQHandler ; 0x2A 0x00A8 42: RSV13 +RSV14_IRQHandler ; 0x2B 0x00AC 43: RSV14 +DMA0_IRQHandler ; 0x2C 0x00B0 44: DMA0 +DMA1_IRQHandler ; 0x2D 0x00B4 45: DMA1 +DMA2_IRQHandler ; 0x2E 0x00B8 46: DMA2 +DMA3_IRQHandler ; 0x2F 0x00BC 47: DMA3 +RSV15_IRQHandler ; 0x30 0x00C0 48: RSV15 +RSV16_IRQHandler ; 0x31 0x00C4 49: RSV16 +RSV17_IRQHandler ; 0x32 0x00C8 50: RSV17 +RSV18_IRQHandler ; 0x33 0x00CC 51: RSV18 +I2C1_IRQHandler ; 0x34 0x00D0 52: I2C1 +RSV19_IRQHandler ; 0x35 0x00D4 53: RSV19 +RSV20_IRQHandler ; 0x36 0x00D8 54: RSV20 +RSV21_IRQHandler ; 0x37 0x00DC 55: RSV21 +RSV22_IRQHandler ; 0x38 0x00E0 56: RSV22 +RSV23_IRQHandler ; 0x39 0x00E4 57: RSV23 +RSV24_IRQHandler ; 0x3A 0x00E8 58: RSV24 +RSV25_IRQHandler ; 0x3B 0x00EC 59: RSV25 +RSV26_IRQHandler ; 0x3C 0x00F0 60: RSV26 +RSV27_IRQHandler ; 0x3D 0x00F4 61: RSV27 +RSV28_IRQHandler ; 0x3E 0x00F8 62: RSV28 +RSV29_IRQHandler ; 0x3F 0x00FC 63: RSV29 +RSV30_IRQHandler ; 0x40 0x0100 64: RSV30 +RSV31_IRQHandler ; 0x41 0x0104 65: RSV31 +RSV32_IRQHandler ; 0x42 0x0108 66: RSV32 +RSV33_IRQHandler ; 0x43 0x010C 67: RSV33 +RSV34_IRQHandler ; 0x44 0x0110 68: RSV34 +RSV35_IRQHandler ; 0x45 0x0114 69: RSV35 +GPIOWAKE_IRQHandler ; 0x46 0x0118 70: GPIO Wakeup + + B . + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap\ + PROC + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END + +;;;;;;;;;;;;;;;;;;;;;;;;; +;; End of file. +;;;;;;;;;;;;;;;;;;;;;;;;;