Maxim-Integrated
Maxim
max32660
ARMCM4
1.0
MAX32660.
CM4
r2p1
little
true
true
3
false
8
32
0x20
read-write
0x00000000
0xFFFFFFFF
GCR
Global Control Registers.
0x40000000
0
0x400
registers
SCON
System Control.
0x00
0xFFFFFFFE
FLASH_PAGE_FLIP
Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.
4
1
normal
Physical layout matches logical layout.
0
swapped
Bottom half mapped to logical top half and vice versa.
1
FPU_DIS
Floating Point Unit Disable
5
1
enable
enable Floating point unit
0
disable
disable floating point unit
1
ICC0_FLUSH
Instruction Cache Controller Flush. Write 1 to flush the internal flash cache. This bit is cleared by hardware when the flush is complete.
6
1
normal
Normal Code Cache Operation
0
flush
Code Caches and CPU instruction buffer are flushed
1
SWD_DIS
Serial Wire Debug Disable
14
1
enable
Enable JTAG SWD
0
disable
Disable JTAG SWD
1
RST0
Reset.
0x04
DMA
DMA Reset.
0
dma_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
1
dma_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
WDT0
Watchdog Timer Reset.
1
1
wdt_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
wdt_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
GPIO0
GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.
2
1
gpio0_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
gpio0_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
TIMER0
Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.
5
1
timer0_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
timer0_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
TIMER1
Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.
6
1
timer1_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
timer1_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
TIMER2
Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.
7
1
timer2_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
timer2_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
UART0
UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.
11
1
uart0_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
uart0_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
UART1
UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.
12
1
uart1_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
uart1_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
SPI0
SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.
13
1
spi0_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
spi0_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
SPI1
SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.
14
1
spi1_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
xpi1_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
I2C0
I2C0 Reset.
16
1
i2c0_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
i2c0_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
RTC
Real Time Clock Reset.
17
1
rtc_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
rtc_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
SOFT
Soft Reset.Write 1 to perform a Soft Reset. A soft reset performs a Peripheral Reset and also resets the GPIO peripheral but does not reset the CPU or Watchdog Timer.
29
1
srst_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
srst_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
PERIPH
Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.
30
1
prst_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
prst_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
SYSTEM
System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.
31
1
system_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
system_read
read
Reset_Done
Reset Complete
0
Busy
Reset Busy
1
CLK_CTRL
Clock Control.
0x08
0x00000008
PSC
Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.
6
3
div1
Divide by 1.
0
div2
Divide by 2.
1
div4
Divide by 4.
2
div8
Divide by 8.
3
div16
Divide by 16.
4
div32
Divide by 32.
5
div64
Divide by 64.
6
div128
Divide by 128.
7
CLKSEL
Clock Source Select. This 3 bit field selects the source for the system clock.
9
3
HIRC
The internal 96 MHz oscillator is used for the system clock.
0
nanoRing
The nano-ring output is used for the system clock.
3
hfxIn
HFXIN is used for the system clock.
6
CLKRDY
Clock Ready. This read only bit reflects whether the currently selected system clock source is running.
13
1
read-only
busy
Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.
0
ready
System clock running from CLKSEL clock source.
1
X32K_EN
32kHz Crystal Oscillator Enable.
17
1
dis
Is Disabled.
0
en
Is Enabled.
1
HIRC_EN
60MHz High Frequency Internal Reference Clock Enable.
18
1
dis
Is Disabled.
0
en
Is Enabled.
1
X32K_RDY
32kHz Crystal Oscillator Ready
25
1
read-only
not
Not Ready
0
Ready
X32K Ready
1
HIRC_RDY
60MHz HIRC Ready.
26
1
not
Not Ready
0
ready
HIRC Ready
1
LIRC8K_RDY
8kHz Low Frequency Reference Clock Ready.
29
1
not
Not Ready
0
ready
Clock Ready
1
PM
Power Management.
0x0C
MODE
Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.
0
3
active
Active Mode.
0
shutdown
Shutdown Mode.
3
backup
Backup Mode.
4
GPIOWK_EN
GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.
4
1
dis
Wake Up Disable.
0
en
Wake Up Enable.
1
RTCWK_EN
RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.
5
1
dis
Wake Up Disable.
0
en
Wake Up Enable.
1
HFIOPD
HFIO DEEPSLEEP Auto Off. When set, the High-Frequency Internal Oscillator is automatically powered off when in DEEPSLEEP mode.
15
1
active
Mode is Active.
0
deepsleep
Powered down in DEEPSLEEP.
1
PCLK_DIS0
Peripheral Clock Disable.
0x24
GPIO0D
GPIO0 Disable.
0
1
GPIODisable
en
enable it.
0
dis
disable it.
1
DMAD
DMA Disable.
5
1
GPIODisable
en
enable it.
0
dis
disable it.
1
SPI0D
SPI 0 Disable.
6
1
GPIODisable
en
enable it.
0
dis
disable it.
1
SPI1D
SPI 1 Disable.
7
1
GPIODisable
en
enable it.
0
dis
disable it.
1
UART0D
UART 0 Disable.
9
1
GPIODisable
en
enable it.
0
dis
disable it.
1
UART1D
UART 1 Disable.
10
1
GPIODisable
en
enable it.
0
dis
disable it.
1
I2C0D
I2C 0 Disable.
13
1
GPIODisable
en
enable it.
0
dis
disable it.
1
TIMER0D
Timer 0 Disable.
15
1
GPIODisable
en
enable it.
0
dis
disable it.
1
TIMER1D
Timer 1 Disable.
16
1
GPIODisable
en
enable it.
0
dis
disable it.
1
TIMER2D
Timer 2 Disable.
17
1
GPIODisable
en
enable it.
0
dis
disable it.
1
I2C1D
I2C 1 Disable.
28
1
GPIODisable
en
enable it.
0
dis
disable it.
1
MEM_CTRL
Memory Clock Control Register.
0x28
FWS
Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
0
3
RAM0_LS
System RAM 0 Light Sleep Mode.
8
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
RAM1_LS
System RAM 1 Light Sleep Mode.
9
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
RAM2_LS
System RAM 2 Light Sleep Mode.
10
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
RAM3_LS
System RAM 3 Light Sleep Mode.
11
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
ICACHE_RET
ICache RAM Light Sleep Mode.
12
1
active
Memory is active.
0
light_sleep
Memory is in Light Sleep mode.
1
MEM_ZCTRL
Memory Zeroize Control.
0x2C
SRAM_ZERO
System RAM Block 0.
0
1
nop
No operation/complete.
0
start
Start operation.
1
ICACHE_ZERO
Instruction Cache.
1
1
nop
No operation/complete.
0
start
Start operation.
1
SYS_STAT
System Status Register.
0x40
ICECLOCK
ARM ICE Lock Status.
0
1
unlocked
ICE is unlocked.
0
locked
ICE is locked.
1
RST1
Reset 1.
0x44
I2C1
I2C1 Reset.
0
1
reset_write
write
RFU
Reserved. Do not use.
0
reset
Starts reset operation.
1
reset_read
read
reset_done
Reset complete.
0
busy
Reset in progress.
1
PCLK_DIS1
Peripheral Clock Disable.
0x48
FLCD
Secure Flash Controller Disable.
3
1
en
Enable.
0
dis
Disable.
1
ICCD
ICache Clock Disable.
11
1
en
Enable.
0
dis
Disable.
1
EVTEN
Event Enable Register.
0x4C
DMAEVENT
Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.
0
1
RX_EVT
Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode.
1
1
REV
Revision Register.
0x50
read-only
REVISION
Manufacturer Chip Revision.
0
16
SYS_IE
System Status Interrupt Enable
0x54
ICEULIE
Arm ICE Unlocked Interrupt Enable. Set this bit to enable a PWRSEQ IRQ if the Arm ICE is unlocked.
0
1
SIR
System Initialization Registers.
0x40000400
read-only
0x00
0x400
registers
STATUS
System Initialization Status Register.
0x00
read-only
CFG_VALID
Configuration Valid Flag. This field is set to 1 by hardware during reset if the device configuration is valid.
0
1
read-only
read
invalid
config invalid
0
valid
config valid
1
CFG_ERR
Configuration Error Flag. This field is set by hardware during reset if an error in the device configuration is detected
1
1
read-only
read
valid
config valid
0
invalid
config invalid
1
ADDR
Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).
0x04
read-only
ADDR
0
32
FCR
Function Control.
0x40000800
0x00
0x400
registers
REG0
Register 0.
0x00
read-write
I2C0_SDA_FILTER_EN
I2C0 SDA Filter Enable
20
1
dis
Filter disabled.
0
en
Filter enabled.
1
I2C0_SCL_FILTER_EN
I2C0 SCL Filter Enable
21
1
dis
Filter disabled.
0
en
Filter enabled.
1
I2C1_SDA_FILTER_EN
I2C1 SDA Filter Enable
22
1
dis
Filter disabled.
0
en
Filter enabled.
1
I2C1_SCL_FILTER_EN
I2C1 SCL Filter Enable
23
1
dis
Filter disabled.
0
en
Filter enabled.
1
WDT0
Watchdog Timer 0
0x40003000
0x00
0x0400
registers
WDT0
1
CTRL
Watchdog Timer Control Register.
0x00
0x7FFFF000
INT_PERIOD
Watchdog Interrupt Period. The watchdog timer will assert an interrupt, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
0
4
wdt2pow31
2**31 clock cycles.
0
wdt2pow30
2**30 clock cycles.
1
wdt2pow29
2**29 clock cycles.
2
wdt2pow28
2**28 clock cycles.
3
wdt2pow27
2^27 clock cycles.
4
wdt2pow26
2**26 clock cycles.
5
wdt2pow25
2**25 clock cycles.
6
wdt2pow24
2**24 clock cycles.
7
wdt2pow23
2**23 clock cycles.
8
wdt2pow22
2**22 clock cycles.
9
wdt2pow21
2**21 clock cycles.
10
wdt2pow20
2**20 clock cycles.
11
wdt2pow19
2**19 clock cycles.
12
wdt2pow18
2**18 clock cycles.
13
wdt2pow17
2**17 clock cycles.
14
wdt2pow16
2**16 clock cycles.
15
RST_PERIOD
Watchdog Reset Period. The watchdog timer will assert a reset, if enabled, if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.
4
4
wdt2pow31
2**31 clock cycles.
0
wdt2pow30
2**30 clock cycles.
1
wdt2pow29
2**29 clock cycles.
2
wdt2pow28
2**28 clock cycles.
3
wdt2pow27
2^27 clock cycles.
4
wdt2pow26
2**26 clock cycles.
5
wdt2pow25
2**25 clock cycles.
6
wdt2pow24
2**24 clock cycles.
7
wdt2pow23
2**23 clock cycles.
8
wdt2pow22
2**22 clock cycles.
9
wdt2pow21
2**21 clock cycles.
10
wdt2pow20
2**20 clock cycles.
11
wdt2pow19
2**19 clock cycles.
12
wdt2pow18
2**18 clock cycles.
13
wdt2pow17
2**17 clock cycles.
14
wdt2pow16
2**16 clock cycles.
15
WDT_EN
Watchdog Timer Enable.
8
1
dis
Disable.
0
en
Enable.
1
INT_FLAG
Watchdog Timer Interrupt Flag.
9
1
oneToClear
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
INT_EN
Watchdog Timer Interrupt Enable.
10
1
dis
Disable.
0
en
Enable.
1
RST_EN
Watchdog Timer Reset Enable.
11
1
dis
Disable.
0
en
Enable.
1
RST_FLAG
Watchdog Timer Reset Flag.
31
1
read-write
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
RST
Watchdog Timer Reset Register.
0x04
write-only
WDT_RST
Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD then a watchdog reset will occur, if enabled.
0
8
seq0
The first value to be written to reset the WDT.
0x000000A5
seq1
The second value to be written to reset the WDT.
0x0000005A
RTC
Real Time Clock and Alarm.
0x40006000
0x00
0x400
registers
RTC
RTC interrupt.
3
SEC
RTC Second Counter. This register contains the 32-bit second counter.
0x00
0x00000000
SSEC
RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.
0x04
0x00000000
RTSS
RTC Sub-second Counter.
0
8
RAS
Time-of-day Alarm.
0x08
0x00000000
RAS
Time-of-day Alarm.
0
20
RSSA
RTC sub-second alarm. This register contains the reload value for the sub-second alarm.
0x0C
0x00000000
RSSA
This register contains the reload value for the sub-second alarm.
0
32
CTRL
RTC Control Register.
0x10
0x00000008
0xFFFFFF38
RTCE
Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
ADE
Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
1
1
dis
Disable.
0
en
Enable.
1
ASE
Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
2
1
dis
Disable.
0
en
Enable.
1
BUSY
RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.
3
1
read-only
idle
Idle.
0
busy
Busy.
1
RDY
RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.
4
1
busy
Register has not updated.
0
ready
Ready.
1
RDYE
RTC Ready Interrupt Enable.
5
1
dis
Disable.
0
en
Enable.
1
ALDF
Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
6
1
read-only
inactive
Not active
0
Pending
Active
1
ALSF
Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
7
1
read-only
inactive
Not active
0
Pending
Active
1
SQE
Square Wave Output Enable.
8
1
inactive
Not active
0
Pending
Active
1
FT
Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.
9
2
freq1Hz
1 Hz (Compensated).
0
freq512Hz
512 Hz (Compensated).
1
freq4KHz
4 KHz.
2
clkDiv8
RTC Input Clock / 8.
3
X32KMD
32KHz Oscillator Mode.
11
2
noiseImmuneMode
Always operate in Noise Immune Mode. Oscillator warm-up required.
0
quietMode
Always operate in Quiet Mode. No oscillator warm-up required.
1
quietInStopWithWarmup
Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.
2
quietInStopNoWarmup
Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit.
3
WE
Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.
15
1
inactive
Not active
0
Pending
Active
1
TRIM
RTC Trim Register.
0x14
0x00000000
TRIM
RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.
0
8
VBATTMR
VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.
8
24
OSCCTRL
RTC Oscillator Control Register.
0x18
0x00000000
FLITER_EN
RTC Oscillator Filter Enable
0
1
IBIAS_SEL
RTC Oscillator 4X Bias Current Select
1
1
2X
Selects 2X bias current for RTC oscillator
0
4X
Selects 4X bias current for RTC oscillator
1
HYST_EN
RTC Oscillator Hysteresis Buffer Enable
2
1
IBIAS_EN
RTC Oscillator Bias Current Enable
3
1
BYPASS
RTC Crystal Bypass
4
1
OUT32K
RTC 32kHz Square Wave Output
5
1
PWRSEQ
Power Sequencer / Low Power Control Register.
0x40006800
0x00
0x800
registers
LP_CTRL
Low Power Control Register.
0x00
RAMRET_SEL0
System RAM 0 Data retention in BACKUP mode.
0
1
dis
Disabled.
0
en
Enabled.
1
RAMRET_SEL1
System RAM 1 Data retention in BACKUP mode.
1
1
dis
Disabled.
0
en
Enabled.
1
RAMRET_SEL2
System RAM 2 Data retention in BACKUP mode.
2
1
dis
Disabled.
0
en
Enabled.
1
RAMRET_SEL3
System RAM 3 Data retention in BACKUP mode.
3
1
dis
Disabled.
0
en
Enabled.
1
OVR
Operating Voltage Range
4
2
0_9V
0.9V 24MHz
0
1_0V
1.0V 48MHz
1
1_1V
1.1V 96MHz
2
VCORE_DET_BYPASS
Bypass V CORE External Supply Detection
6
1
enabled
enable
0
Disable
disable
1
RETREG_EN
Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode.
8
1
dis
Disabled.
0
en
Enabled.
1
FAST_WK_EN
Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode.
10
1
dis
Disabled.
0
en
Enabled.
1
BG_OFF
Band Gap Disable for DEEPSLEEP and BACKUP Mode
11
1
on
Bandgap is always ON.
0
off
Bandgap is OFF in DeepSleep mode(default).
1
VCORE_POR_DIS
V CORE POR Disable for DEEPSLEEP and BACKUP Mode
12
1
dis
Disabled.
0
en
Enabled.
1
LDO_DIS
LDO Disable
16
1
en
Enable if Bandgap is ON(default)
0
dis
Disabled.
1
VCORE_SVM_DIS
V CORE Supply Voltage Monitor Disable
20
1
en
Enable if Bandgap is ON(default)
0
dis
Disabled.
1
VDDIO_POR_DIS
VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.
25
1
en
Enabled.
0
dis
Disabled.
1
LP_WAKEFL
Low Power Mode Wakeup Flags for GPIO0
0x04
WAKEST
Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.
0
14
LPWK_EN
Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.
0x08
WAKEEN
Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.
0
14
LPMEMSD
Low Power Memory Shutdown Control.
0x40
SRAM0_OFF
System RAM block 0 Shut Down.
0
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM1_OFF
System RAM block 1 Shut Down.
1
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM2_OFF
System RAM block 2 Shut Down.
2
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
SRAM3_OFF
System RAM block 3 Shut Down.
3
1
normal
Normal Operating Mode.
0
shutdown
Shutdown Mode.
1
GPIO0
Individual I/O for each GPIO
GPIO
0x40008000
0x00
0x1000
registers
GPIO0
GPIO0 interrupt.
24
EN
GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.
0x00
GPIO_EN
Mask of all of the pins on the port.
0
32
alternate
Alternate function enabled.
0
GPIO
GPIO function is enabled.
1
EN_SET
GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.
0x04
ALL
Mask of all of the pins on the port.
0
32
EN_CLR
GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.
0x08
ALL
Mask of all of the pins on the port.
0
32
OUT_EN
GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.
0x0C
GPIO_OUT_EN
Mask of all of the pins on the port.
0
32
dis
GPIO Output Disable
0
en
GPIO Output Enable
1
OUT_EN_SET
GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.
0x10
ALL
Mask of all of the pins on the port.
0
32
OUT_EN_CLR
GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.
0x14
ALL
Mask of all of the pins on the port.
0
32
OUT
GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.
0x18
GPIO_OUT
Mask of all of the pins on the port.
0
32
low
Drive Logic 0 (low) on GPIO output.
0
high
Drive logic 1 (high) on GPIO output.
1
OUT_SET
GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.
0x1C
write-only
GPIO_OUT_SET
Mask of all of the pins on the port.
0
32
no
No Effect.
0
set
Set GPIO_OUT bit in this position to '1'
1
OUT_CLR
GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.
0x20
write-only
GPIO_OUT_CLR
Mask of all of the pins on the port.
0
32
IN
GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.
0x24
read-only
GPIO_IN
Mask of all of the pins on the port.
0
32
INT_MOD
GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.
0x28
GPIO_INT_MOD
Mask of all of the pins on the port.
0
32
level
Interrupts for this pin are level triggered.
0
edge
Interrupts for this pin are edge triggered.
1
INT_POL
GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.
0x2C
GPIO_INT_POL
Mask of all of the pins on the port.
0
32
falling
Interrupts are latched on a falling edge or low level condition for this pin.
0
rising
Interrupts are latched on a rising edge or high condition for this pin.
1
IN_EN
GPIO Port Input Enable.
0x30
GPIO_IN_EN
Mask of all of the pins on the port.
0
32
dis
GPIO Input Disable
0
en
GPIO Input Enable
1
INT_EN
GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.
0x34
GPIO_INT_EN
Mask of all of the pins on the port.
0
32
dis
Interrupts are disabled for this GPIO pin.
0
en
Interrupts are enabled for this GPIO pin.
1
INT_EN_SET
GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.
0x38
GPIO_INT_EN_SET
Mask of all of the pins on the port.
0
32
no
No effect.
0
set
Set GPIO_INT_EN bit in this position to '1'
1
INT_EN_CLR
GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.
0x3C
GPIO_INT_EN_CLR
Mask of all of the pins on the port.
0
32
no
No Effect.
0
clear
Clear GPIO_INT_EN bit in this position to '0'
1
INT_STAT
GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.
0x40
read-only
GPIO_INT_STAT
Mask of all of the pins on the port.
0
32
no
No Interrupt is pending on this GPIO pin.
0
pending
An Interrupt is pending on this GPIO pin.
1
INT_CLR
GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.
0x48
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN
GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.
0x4C
GPIO_WAKE_EN
Mask of all of the pins on the port.
0
32
dis
PMU wakeup for this GPIO is disabled.
0
en
PMU wakeup for this GPIO is enabled.
1
WAKE_EN_SET
GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.
0x50
ALL
Mask of all of the pins on the port.
0
32
WAKE_EN_CLR
GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.
0x54
ALL
Mask of all of the pins on the port.
0
32
INT_DUAL_EDGE
GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.
0x5C
GPIO_INT_DUAL_EDGE
Mask of all of the pins on the port.
0
32
no
No Effect.
0
en
Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.
1
PAD_CFG1
GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x60
GPIO_PAD_CFG1
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
PAD_CFG2
GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.
0x64
GPIO_PAD_CFG2
The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.
0
32
impedance
High Impedance.
0
pu
Weak pull-up mode.
1
pd
weak pull-down mode.
2
EN1
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x68
GPIO_EN1
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN1_SET
GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.
0x6C
ALL
Mask of all of the pins on the port.
0
32
EN1_CLR
GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.
0x70
ALL
Mask of all of the pins on the port.
0
32
EN2
GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.
0x74
GPIO_EN2
Mask of all of the pins on the port.
0
32
primary
Primary function selected.
0
secondary
Secondary function selected.
1
EN2_SET
GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.
0x78
ALL
Mask of all of the pins on the port.
0
32
EN2_CLR
GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.
0x7C
ALL
Mask of all of the pins on the port.
0
32
DS0
GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB0
ALL
Mask of all of the pins on the port.
0
32
ld
GPIO port pin is in low-drive mode.
0
hd
GPIO port pin is in high-drive mode.
1
DS1
GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.
0xB4
ALL
Mask of all of the pins on the port.
0
32
PS
GPIO Pull Select Mode.
0xB8
ALL
Mask of all of the pins on the port.
0
32
VSSEL
GPIO Voltage Select.
0xC0
ALL
Mask of all of the pins on the port.
0
32
TMR0
Low-Power Configurable Timer
0x40010000
0x00
0x1000
registers
TMR
5
CNT
Timer Counter Register.
0x00
read-write
COUNT
The current count value for the timer. This field increments as the timer counts.
0
32
CMP
Timer Compare Register.
0x04
read-write
COMPARE
The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.
0
32
PWM
Timer PWM Register.
0x08
read-write
PWM
Timer PWM Match:
In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value:
In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.
0
32
INTR
Timer Interrupt Status Register.
0x0C
read-write
IRQ
Interrupt Flag for Timer A.
0
1
CN
Timer Control Register.
0x10
read-write
TMODE
Mode Select
0
3
ONE_SHOT
One-Shot Mode
0
CONTINUOUS
Continuous Mode
1
COUNTER
Counter Mode
2
PWM
PWM Mode
3
CAPTURE
Capture Mode
4
COMPARE
Compare Mode
5
GATED
Gated Mode
6
CAPCOMP
Capture/Compare Mode
7
PRES
Timer Prescaler Select
3
3
DIV_BY_1
Prescaler Divide-By-1
0
DIV_BY_2
Prescaler Divide-By-2
1
DIV_BY_4
Prescaler Divide-By-4
2
DIV_BY_8
Prescaler Divide-By-8
3
DIV_BY_16
Prescaler Divide-By-16
4
DIV_BY_32
Prescaler Divide-By-32
5
DIV_BY_64
Prescaler Divide-By-64
6
DIV_BY_128
Prescaler Divide-By-128
7
TPOL
Timer Polarity
6
1
TEN
Timer Enable
7
1
PRES3
Timer Prescale Select MSB
8
1
PWMSYNC
PWM Synchronization Mode
9
1
NOLHPOL
PWM Phase A (Non-Overlapping High) Polarity
10
1
NOLLPOL
PWM Phase A-prime (Non-Overlapping Low) Polarity
11
1
PWMCKBD
PWM Phase A-Prime Output Disable
12
1
TMR1
Low-Power Configurable Timer 1
0x40011000
TMR1
TMR1 IRQ
6
TMR2
Low-Power Configurable Timer 2
0x40012000
TMR2
TMR2 IRQ
7
SPIMSS
Serial Peripheral Interface.
SPIMSS
0x40019000
0x00
0x1000
registers
DATA
SPI 16-bit Data Access
0x00
16
read-write
DATA
SPI data.
0
16
CTRL
SPI Control Register.
0x04
ENABLE
SPI Enable.
0
1
dis_en_enum
disable
0
enable
1
MMEN
SPI Master Mode Enable.
1
1
slv_mst_enum
slave
0
master
1
WOR
Wired OR (open drain) Enable.
2
1
dis_en_enum
disable
0
enable
1
CLKPOL
Clock Polarity.
3
1
spi_pol_enum
idleLo
SCLK idles Low (0) after character transmission/reception.
0
idleHi
SCLK idles High (1) after character transmission/reception.
1
PHASE
Phase Select.
4
1
spi_phase_enum
activeEdge
Transmit on active edge of SCLK.
0
inactiveEdge
Transmit on inactive edge of SCLK.
1
BIRQ
Baud Rate Generator Timer Interrupt Request.
5
1
dis_en_enum
disable
0
enable
1
STR
Start SPI Interrupt.
6
1
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
IRQE
Interrupt Request Enable.
7
1
dis_en_enum
disable
0
enable
1
INT_FL
SPI Interrupt Flag Register.
0x08
0x00000001
SLAS
Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.
0
1
read-only
sel_enum
selected
0
notSelected
1
TXST
Transmit Status.
1
1
read-only
busy_enum
idle
0
busy
1
TUND
Transmit Underrun.
2
1
oneToClear
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
ROVR
Receive Overrun.
3
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
ABT
Slave Mode Transaction Abort.
4
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
COL
Collision.
5
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
TOVR
Transmit Overrun.
6
1
event_flag_enum
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
IRQ
SPI Interrupt Request.
7
1
oneToClear
flag_enum
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
MODE
SPI Mode Register.
0x0C
SSV
Slave Select Value.
0
1
lo_hi_enum
lo
The SSEL pin will be driven low.
0
hi
The SSEL pin will be driven high.
1
SS_IO
Slave Select I/O.
1
1
input_output_enum
input
0
output
1
NUMBITS
2
4
spi_bits_enum
bits16
0
bits1
1
bits2
2
bits3
3
bits4
4
bits5
5
bits6
6
bits7
7
bits8
8
bits9
9
bits10
10
bits11
11
bits12
12
bits13
13
bits14
14
bits15
15
TX_LJ
Transmit Left Justify.
7
1
dis_en_enum
disable
0
enable
1
BRG
Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4).
0x14
0x0000FFFF
DIV
Baud Rate Reload Value.
0
16
DMA
SPI DMA Register.
0x18
0x00070007
TX_FIFO_LVL
Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.
0
3
fifo_level_enum
entry1
0
entries2
1
entries3
2
entries4
3
entries5
4
entries6
5
entries7
6
entries8
7
TX_FIFO_CLR
Transmit FIFO Clear.
4
1
write-only
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
TX_FIFO_CNT
Transmit FIFO Count.
8
4
read-only
TX_DMA_EN
Transmit DMA Enable.
15
1
dis_en_enum
disable
0
enable
1
RX_FIFO_LVL
Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.
16
3
fifo_level_enum
entry1
0
entries2
1
entries3
2
entries4
3
entries5
4
entries6
5
entries7
6
entries8
7
RX_FIFO_CLR
Receive FIFO Clear.
20
1
start_op_enum
complete
No operation/complete.
0
start
Start operation.
1
RX_FIFO_CNT
Receive FIFO Count.
24
4
read-only
RX_DMA_EN
Receive DMA Enable.
31
1
dis_en_enum
disable
0
enable
1
I2S_CTRL
I2S Control Register.
0x1C
I2S_EN
I2S Mode Enable.
0
1
dis_en_enum
disable
0
enable
1
I2S_MUTE
I2S Mute transmit.
1
1
normal
Normal Transmit.
0
replaced
Transmit data is replaced with 0.
1
I2S_PAUSE
I2S Pause transmit/receive.
2
1
normal
Normal Transmit.
0
halt
Halt transmit and receive FIFO and DMA access, transmit 0's.
1
I2S_MONO
I2S Monophonic Audio Mode.
3
1
stereophonic
Stereophonic audio.
0
monophonic
Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
1
I2S_LJ
I2S Left Justify.
4
1
normal
Normal I2S audio protocol.
0
replaced
Audio data is synchronized with SSEL.
1
I2C0
Inter-Integrated Circuit.
I2C
0x4001D000
32
0x00
0x1000
registers
I2C0
I2C0 IRQ
13
CTRL0
Control Register0.
0x00
I2CEN
I2C Enable.
[0:0]
read-write
dis
Disable I2C.
0
en
enable I2C.
1
MST
Master Mode Enable.
[1:1]
read-write
slave_mode
Slave Mode.
0
master_mode
Master Mode.
1
GCEN
General Call Address Enable.
[2:2]
read-write
dis
Ignore Gneral Call Address.
0
en
Acknowledge general call address.
1
IRXM
Interactive Receive Mode.
[3:3]
read-write
dis
Disable Interactive Receive Mode.
0
en
Enable Interactive Receive Mode.
1
ACK
Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.
[4:4]
read-write
ack
return ACK (pulling SDA LOW).
0
nack
return NACK (leaving SDA HIGH).
1
SCLO
SCL Output. This bits control SCL output when SWOE =1.
[6:6]
read-write
drive_scl_low
Drive SCL low.
0
release_scl
Release SCL.
1
SDAO
SDA Output. This bits control SDA output when SWOE = 1.
[7:7]
read-write
drive_sda_low
Drive SDA low.
0
release_sda
Release SDA.
1
SCL
SCL status. This bit reflects the logic gate of SCL signal.
[8:8]
read-only
SDA
SDA status. THis bit reflects the logic gate of SDA signal.
[9:9]
read-only
SWOE
Software Output Enable.
[10:10]
read-write
outputs_disable
I2C Outputs SCLO and SDAO disabled.
0
outputs_enable
I2C Outputs SCLO and SDAO enabled.
1
READ
Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match(GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.
[11:11]
read-only
write
Write.
0
read
Read.
1
SCL_STRD
This bit will disable slave clock stretching when set.
[12:12]
read-write
en
Slave clock stretching enabled.
0
dis
Slave clock stretching disabled.
1
SCL_PPM
SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.
[13:13]
read-write
dis
Standard open-drain operation: drive low for 0, Hi-Z for 1
0
en
Non-standard push-pull operation: drive low for 0, drive high for 1
1
HSMODE
Hs-mode Enable.
15
1
dis
Hs-mode disabled.
0
en
Hs-mode enabled.
1
STATUS
Status Register.
0x04
BUSY
Bus Status.
[0:0]
read-only
idle
I2C Bus Idle.
0
busy
I2C Bus Busy.
1
RXE
RX empty.
[1:1]
read-only
not_empty
Not Empty.
0
empty
Empty.
1
RXF
RX Full.
[2:2]
read-only
not_full
Not Full.
0
full
Full.
1
TXE
TX Empty.
[3:3]
not_empty
Not Empty.
0
empty
Empty.
1
TXF
TX Full.
[4:4]
not_empty
Not Empty.
0
empty
Empty.
1
CKMD
Clock Mode.
[5:5]
read-only
not_actively_driving_scl_clock
Device not actively driving SCL clock cycles.
0
actively_driving_scl_clock
Device operating as master and actively driving SCL clock cycles.
1
STAT
Controller Status.
[11:8]
idle
Controller Idle.
0
mtx_addr
master Transmit address.
1
mrx_addr_ack
Master Receive address ACK.
2
mtx_ex_addr
Master Transmit extended address.
3
mrx_ex_addr
Master Receive extended address ACK.
4
srx_addr
Slave Receive address.
5
stx_addr_ack
Slave Transmit address ACK.
6
srx_ex_addr
Slave Receive extended address.
7
stx_ex_addr_ack
Slave Transmit extended address ACK.
8
tx
Transmit data (master or slave).
9
rx_ack
Receive data ACK (master or slave).
10
rx
Receive data (master or slave).
11
tx_ack
Transmit data ACK (master or slave).
12
nack
NACK stage (master or slave).
13
by_st
Bystander state (ongoing transaction but not participant- another master addressing another slave).
15
INTFL0
Interrupt Status Register.
0x08
DONEI
Transfer Done Interrupt.
[0:0]
INT_FL0_Done
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
IRXMI
Interactive Receive Interrupt.
[1:1]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
GCI
Slave General Call Address Match Interrupt.
[2:2]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
AMI
Slave Address Match Interrupt.
[3:3]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
RXTHI
Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.
[4:4]
inactive
No interrupt is pending.
0
pending
An interrupt is pending. RX_FIFO equal or more bytes than the threshold.
1
TXTHI
Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.
[5:5]
inactive
No interrupt is pending.
0
pending
An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
1
STOPI
STOP Interrupt.
[6:6]
inactive
No interrupt is pending.
0
pending
An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.
1
ADRACKI
Address Acknowledge Interrupt.
[7:7]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
ARBERI
Arbritation error Interrupt.
[8:8]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TOERI
timeout Error Interrupt.
[9:9]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
ADRERI
Address NACK Error Interrupt.
[10:10]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
DATERI
Data NACK Error Interrupt.
[11:11]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
DNRERI
Do Not Respond Error Interrupt.
[12:12]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
STRTERI
Start Error Interrupt.
[13:13]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
STOPERI
Stop Error Interrupt.
[14:14]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TXLOI
Transmit Lock Out Interrupt.
[15:15]
INTEN0
Interrupt Enable Register.
0x0C
read-write
DONEIE
Transfer Done Interrupt Enable.
[0:0]
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when DONE = 1.
1
IRXMIE
Description not available.
[1:1]
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when RX_MODE = 1.
1
GCIE
Slave mode general call address match received input enable.
[2:2]
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when GEN_CTRL_ADDR = 1.
1
AMIE
Slave mode incoming address match interrupt.
[3:3]
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when ADDR_MATCH = 1.
1
RXTHIE
RX FIFO Above Treshold Level Interrupt Enable.
[4:4]
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
TXTHIE
TX FIFO Below Treshold Level Interrupt Enable.
[5:5]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
STOPIE
Stop Interrupt Enable
[6:6]
read-write
dis
Interrupt disabled.
0
en
Interrupt enabled when STOP = 1.
1
ADRACKIE
Received Address ACK from Slave Interrupt.
[7:7]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
ARBERIE
Master Mode Arbitration Lost Interrupt.
[8:8]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
TOERIE
Timeout Error Interrupt Enable.
[9:9]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
ADRERIE
Master Mode Address NACK Received Interrupt.
[10:10]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
DATERIE
Master Mode Data NACK Received Interrupt.
[11:11]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
DNRERIE
Slave Mode Do Not Respond Interrupt.
[12:12]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
STRTERIE
Out of Sequence START condition detected interrupt.
[13:13]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
STOPERIE
Out of Sequence STOP condition detected interrupt.
[14:14]
dis
Interrupt disabled.
0
en
Interrupt enabled.
1
TXLOIE
TX FIFO Locked Out Interrupt.
[15:15]
dis
Interrupt disabled.
0
en
Interrupt enabled when TXLOIE = 1.
1
INTFL1
Interrupt Status Register 1.
0x10
RXOFI
Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.
[0:0]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
TXUFI
Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).
[1:1]
inactive
No Interrupt is Pending.
0
pending
An interrupt is pending.
1
INTEN1
Interrupt Staus Register 1.
0x14
read-write
RXOFIE
Receiver Overflow Interrupt Enable.
[0:0]
dis
No Interrupt is Pending.
0
en
An interrupt is pending.
1
TXUFIE
Transmit Underflow Interrupt Enable.
[1:1]
dis
No Interrupt is Pending.
0
en
An interrupt is pending.
1
FIFOLEN
FIFO Configuration Register.
0x18
RXLEN
Receive FIFO Length.
[7:0]
read-only
TXLEN
Transmit FIFO Length.
[15:8]
read-only
RXCTRL0
Receive Control Register 0.
0x1C
DNR
Do Not Respond.
[0:0]
respond
Always respond to address match.
0
not_respond_rx_fifo_empty
Do not respond to address match when RX_FIFO is not empty.
1
RXFSH
Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.
[7:7]
not_flushed
FIFO not flushed.
0
flush
Flush RX_FIFO.
1
RXTH
Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.
[11:8]
RXCTRL1
Receive Control Register 1.
0x20
RXCNT
Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.
[7:0]
RXFIFO
Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.
[11:8]
read-only
TXCTRL0
Transmit Control Register 0.
0x24
TXPRELD
Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.
[0:0]
TX_READY_MODE
Transmit FIFO Ready Manual Mode.
[1:1]
en
HW control of I2CTXRDY enabled.
0
dis
HW control of I2CTXRDY disabled.
1
TXFSH
Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.
[7:7]
not_flushed
FIFO not flushed.
0
flush
Flush TX_FIFO.
1
TXTH
Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.
[11:8]
TXCTRL1
Transmit Control Register 1.
0x28
TXRDY
Transmit FIFO Preload Ready.
[0:0]
TXLAST
Transmit Last. This bit is used in slave mod only. Do not use when preloading (cleared by hardware).
[1:1]
hold_scl_low
Hold SCL low on TX_FIFO empty.
0
end_transaction
End transaction on TX_FIFO empty.
1
FLSH_GCADDR_DIS
TX FIFO Auto Flush Disable on General Call Address Match.Setting this field to 1 disables the TX FIFO Automatic Flush when a General Call Address Match occurs.
[2:2]
autoflush_en
The TX FIFO is automatically flushed on a General Call Address Match.
0
autoflush_dis
The TX FIFO is not flushed on a General Call Address Match.
1
FLSH_SLADDR_DIS
TX FIFO Auto Flush Disable for Slave Address Match.
Setting this field to 1 disables the TX FIFO Automatic Flush when a Slave Address
Match occurs.
[4:4]
autoflush_en
The TX FIFO is automatically flushed on a Slave Address Match.
0
autoflush_dis
The TX FIFO is not flushed on a Slave Address Match.
1
FLSH_NACK_DIS
TX FIFO Auto Flush Disable for NACK.
Setting this field to 1 disables the TX FIFO Automatic Flush when a NACK is received at the end of a slave transaction.
[5:5]
autoflush_en
The TX FIFO is automatically flushed if a NACK is received at the end of a slave
transaction.
0
autoflush_dis
The TX FIFO is not flushed when a NACK is received at the end of a slave
transaction.
1
TXFIFO
Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.
[11:8]
read-only
FIFO
Data Register.
0x2C
DATA
Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.
0
8
MSTR_MODE
Master Control Register.
0x30
START
Setting this bit to 1 will start a master transfer.
[0:0]
RESTART
Setting this bit to 1 will generate a repeated START.
[1:1]
STOP
Setting this bit to 1 will generate a STOP condition.
[2:2]
SEA
Slave Extend Address Select.
[7:7]
7_bits_address
7-bit address.
0
10_bits_address
10-bit address.
1
CLKLO
Clock Low Register.
0x34
SCL_LO
Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.
[8:0]
CLKHI
Clock high Register.
0x38
SCL_HI
Clock High. In master mode, these bits define the SCL high period.
[8:0]
HS_CLK
HS-Mode Clock Control Register
0x3C
HS_CLK_LO
Slave Address.
[7:0]
HS_CLK_HI
Slave Address.
[15:8]
TIMEOUT
Timeout Register
0x40
TO
Timeout
[15:0]
SLADDR
Slave Address Register.
0x44
SLA
Slave Address.
[9:0]
EA
Extended Address Select.
[15:15]
7_bits_address
7-bit address.
0
10_bits_address
10-bit address.
1
DMA
DMA Register.
0x48
TXEN
TX channel enable.
[0:0]
dis
Disable.
0
en
Enable.
1
RXEN
RX channel enable.
[1:1]
dis
Disable.
0
en
Enable.
1
I2C1
Inter-Integrated Circuit. 1
0x4001E000
I2C1
I2C1 IRQ
36
DMA
DMA Controller Fully programmable, chaining capable DMA channels.
0x40028000
32
0x00
0x1000
registers
DMA0
28
DMA1
29
DMA2
30
DMA3
31
INT_EN
DMA Control Register.
0x000
CHIEN
Channel Interrupt Enable.
0
4
dis
Disable.
0
en
Enable.
1
INT_FL
DMA Interrupt Register.
0x004
read-only
IPEND
Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.
0
4
ch_ipend_enum
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
4
4
CH[%s]
DMA Channel registers.
dma_ch
0x100
read-write
CFG
DMA Channel Configuration Register.
0x100
CHEN
Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
0
1
dis
Disable.
0
en
Enable.
1
RLDEN
Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
1
1
dis
Disable.
0
en
Enable.
1
PRI
DMA Priority.
2
2
high
Highest Priority.
0
medHigh
Medium High Priority.
1
medLow
Medium Low Priority.
2
low
Lowest Priority.
3
REQSEL
Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
4
6
MEMTOMEM
Memory To Memory
0x00
SPI0RX
SPI0 RX
0x01
SPI1RX
SPI1 RX
0x02
UART0RX
UART0 RX
0x04
UART1RX
UART1 RX
0x05
I2C0RX
I2C0 RX
0x07
I2C1RX
I2C1 RX
0x08
SPI0TX
SPI0 TX
0x21
SPI1TX
SPI1 TX
0x22
UART0TX
UART0 TX
0x24
UART1TX
UART1 TX
0x25
I2C0TX
I2C0 TX
0x27
I2C1TX
I2C1 TX
0x28
REQWAIT
Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
10
1
dis
Disable.
0
en
Enable.
1
TOSEL
Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
11
3
to4
Timeout of 3 to 4 prescale clocks.
0
to8
Timeout of 7 to 8 prescale clocks.
1
to16
Timeout of 15 to 16 prescale clocks.
2
to32
Timeout of 31 to 32 prescale clocks.
3
to64
Timeout of 63 to 64 prescale clocks.
4
to128
Timeout of 127 to 128 prescale clocks.
5
to256
Timeout of 255 to 256 prescale clocks.
6
to512
Timeout of 511 to 512 prescale clocks.
7
PSSEL
Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
14
2
dis
Disable timer.
0
div256
hclk / 256.
1
div64k
hclk / 64k.
2
div16M
hclk / 16M.
3
SRCWD
Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
16
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
SRCINC
Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
18
1
dis
Disable.
0
en
Enable.
1
DSTWD
Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
20
2
byte
Byte.
0
halfWord
Halfword.
1
word
Word.
2
DSTINC
Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
22
1
dis
Disable.
0
en
Enable.
1
BRST
Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
24
5
CHDIEN
Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
30
1
dis
Disable.
0
en
Enable.
1
CTZIEN
Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
31
1
dis
Disable.
0
en
Enable.
1
STAT
DMA Channel Status Register.
0x104
CH_ST
Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
0
1
read-only
dis
Disable.
0
en
Enable.
1
IPEND
Channel Interrupt.
1
1
read-only
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
CTZ_ST
Count-to-Zero (CTZ) Status
2
1
oneToClear
ctz_st_enum_rd
read
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
ctz_st_enum_wr
write
Clear
Clears the interrupt flag
1
RLD_ST
Reload Status.
3
1
oneToClear
read
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
write
Clear
Clears the interrupt flag
1
BUS_ERR
Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
4
1
oneToClear
read
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
write
Clear
Clears the interrupt flag
1
TO_ST
Time-Out Status.
6
1
oneToClear
read
noEvent
The event has not occurred.
0
occurred
The event has occurred.
1
write
Clear
Clears the interrupt flag
1
SRC
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
0x108
SRC
0
32
DST
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
0x10C
DST
0
32
CNT
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
0x110
CNT
DMA Counter.
0
24
SRC_RLD
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
0x114
SRC_RLD
Source Address Reload Value.
0
31
DST_RLD
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
0x118
DST_RLD
Destination Address Reload Value.
0
31
CNT_RLD
DMA Channel Count Reload Register.
0x11C
CNT_RLD
Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
0
24
RLDEN
Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
31
1
dis
Disable.
0
en
Enable.
1
FLC
Flash Memory Control.
FLC_
0x40029000
0x00
0x1000
registers
Flash_Controller
Flash Controller interrupt.
23
ADDR
Flash Write Address.
0x00
ADDR
Address for next operation.
0
32
CLKDIV
Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.
0x04
0x00000064
CLKDIV
Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.
0
8
CTRL
Flash Control Register.
0x08
WRITE
Write. This bit is automatically cleared after the operation.
0
1
complete
No operation/complete.
0
start
Start operation.
1
MASS_ERASE
Mass Erase. This bit is automatically cleared after the operation.
1
1
PAGE_ERASE
Page Erase. This bit is automatically cleared after the operation.
2
1
WIDTH
Data Width. This bits selects write data width.
4
1
size128
128-bit.
0
size32
32-bit.
1
ERASE_CODE
Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.
8
8
nop
No operation.
0
erasePage
Enable Page Erase.
0x55
eraseAll
Enable Mass Erase. The debug port must be enabled.
0xAA
BUSY
Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.
24
1
read-only
idle
Idle.
0
busy
Busy.
1
LVE
Low Voltage enable.
25
1
UNLOCK_CODE
Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.
28
4
unlocked
Flash Unlocked.
2
locked
Flash Locked.
3
INTR
Flash Interrupt Register.
0x024
DONE
Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.
0
1
inactive
No interrupt is pending.
0
pending
An interrupt is pending.
1
ACCESS_FAIL
Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.
1
1
noError
No Failure.
0
error
Failure occurs.
1
DONE_IE
Flash Done Interrupt Enable.
8
1
disable
Disable.
0
enable
Enable.
1
ACCESS_FAIL_IE
9
1
4
4
DATA
Flash Write Data.
0x30
DATA
Data next operation.
0
32
ACTRL
Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block:
pflc-actrl = 0x3a7f5ca3;
pflc-actrl = 0xa1e34f20;
pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.
0x40
write-only
ACTRL
Access control.
0
32
ICC0
Instruction Cache Controller Registers
0x4002A000
0x00
0x1000
registers
CACHE_ID
Cache ID Register.
0x0000
read-only
RELNUM
Release Number. Identifies the RTL release version.
0
6
PARTNUM
Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.
6
4
CCHID
Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.
10
6
MEM_SIZE
Memory Configuration Register.
0x0004
read-only
0x00080008
CCHSZ
Cache Size. Indicates total size in Kbytes of cache.
0
16
MEMSZ
Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.
16
16
CACHE_CTRL
Cache Control and Status Register.
0x0100
ENABLE
Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.
0
1
dis
Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.
0
en
Cache Enabled.
1
READY
Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.
16
1
read-only
notReady
Not Ready.
0
ready
Ready.
1
INVALIDATE
Invalidate All Registers.
0x0700
read-write
UART0
UART
0x40042000
0
0x1000
registers
UART0
UART0 IRQ
14
CTRL0
Control Register.
0x00
32
ENABLE
UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.
0
1
dis
UART disabled. FIFOs are flushed. Clock is gated off for power savings.
0
en
UART enabled.
1
PARITY_EN
Enable/disable Parity bit (9th character).
1
1
dis
No Parity
0
en
Parity enabled as 9th bit
1
PARITY_MODE
When PARITY_EN=1, selects odd, even, Mark or Space parity.
Mark parity = always 1; Space parity = always 0.
2
2
Even
Even parity selected.
0
ODD
Odd parity selected.
1
MARK
Mark parity selected.
2
SPACE
Space parity selected.
3
PARITY_LVL
Selects parity based on 1s or 0s count (when PARITY_EN=1).
4
1
1
Parity calculation is based on number of 1s in frame.
0
0
Parity calculation is based on number of 0s in frame.
1
TXFLUSH
Flushes the TX FIFO buffer.
5
1
RXFLUSH
Flushes the RX FIFO buffer.
6
1
BITACC
If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.
7
1
FRAME
Frame accuracy.
0
BIT
Bit accuracy.
1
SIZE
Selects UART character size.
8
2
5
5 bits.
0
6
6 bits.
1
7
7 bits.
2
8
8 bits.
3
STOP
Selects the number of stop bits that will be generated.
10
1
1
1 stop bit.
0
1_5
1.5 stop bits.
1
FLOW
Enables/disables hardware flow control.
11
1
en
HW Flow Control with RTS/CTS enabled
1
dis
HW Flow Control disabled
0
FLOWPOL
RTS/CTS polarity.
12
1
0
RTS/CTS asserted is logic 0.
0
1
RTS/CTS asserted is logic 1.
1
NULLMOD
NULL Modem Support (RTS/CTS and TXD/RXD swap).
13
1
DIS
Direct convention.
0
EN
Null Modem Mode.
1
BREAK
Break control bit. It causes a break condition to be transmitted to receiving UART.
14
1
DIS
Break characters are not generated.
0
EN
Break characters are sent(all the bits are at '0' including start/parity/stop).
1
CLK_SEL
Baud Rate Clock Source Select. Selects the baud rate clock.
15
1
SYSTEM
System clock.
0
ALTERNATE
Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.
1
TO_CNT
RX Time Out. RX time out interrupt will occur after RXTO Uart
characters if RX-FIFO is not empty and RX FIFO has not been read.
16
8
CTRL1
Threshold Control register.
0x04
32
RX_FIFO_LVL
RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.
0
6
TX_FIFO_LVL
TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.
8
6
RTS_FIFO_LVL
RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.
16
6
STAT
Status Register.
0x08
32
read-only
TX_BUSY
Read-only flag indicating the UART transmit status.
0
1
read-only
RX_BUSY
Read-only flag indicating the UARTreceiver status.
1
1
read-only
PARITY
9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.
2
1
read-only
BREAK
Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
3
1
read-only
RX_EMPTY
Read-only flag indicating the RX FIFO state.
4
1
read-only
RX_FULL
Read-only flag indicating the RX FIFO state.
5
1
read-only
TX_EMPTY
Read-only flag indicating the TX FIFO state.
6
1
read-only
TX_FULL
Read-only flag indicating the TX FIFO state.
7
1
read-only
RX_NUM
Indicates the number of bytes currently in the RX FIFO.
8
6
read-only
TX_NUM
Indicates the number of bytes currently in the TX FIFO.
16
6
read-only
RX_TO
RX Timeout status.
24
1
read-only
INT_EN
Interrupt Enable Register.
0x0C
32
RX_FRAME_ERROR
Enable for RX Frame Error Interrupt.
0
1
RX_PARITY_ERROR
Enable for RX Parity Error interrupt.
1
1
CTS
Enable for CTS signal change interrupt.
2
1
RX_OVERRUN
Enable for RX FIFO OVerrun interrupt.
3
1
RX_FIFO_LVL
Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
4
1
TX_FIFO_AE
Enable for interrupt when TX FIFO has only one byte remaining.
5
1
TX_FIFO_LVL
Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
6
1
BREAK
Enable for received BREAK character interrupt.
7
1
RX_TO
Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
8
1
LAST_BREAK
Enable for Last break character interrupt.
9
1
INT_FL
Interrupt Status Flags.
0x10
32
oneToClear
FRAME
FLAG for RX Frame Error Interrupt.
0
1
PARITY
FLAG for RX Parity Error interrupt.
1
1
CTS
FLAG for CTS signal change interrupt.
2
1
RX_OVR
FLAG for RX FIFO Overrun interrupt.
3
1
RX_FIFO_LVL
FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
4
1
TX_FIFO_AE
FLAG for interrupt when TX FIFO has only one byte remaining.
5
1
TX_FIFO_LVL
FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
6
1
BREAK
FLAG for received BREAK character interrupt.
7
1
RX_TO
FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
8
1
LAST_BREAK
FLAG for Last break character interrupt.
9
1
BAUD0
Baud rate register. Integer portion.
0x14
32
IBAUD
Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).
0
12
CLKDIV
FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.
16
3
128
Baud Factor 128
0
64
Baud Factor 64
1
32
Baud Factor 32
2
16
Baud Factor 16
3
8
Baud Factor 8
4
BAUD1
Baud rate register. Decimal Setting.
0x18
32
DBAUD
Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.
0
12
FIFO
FIFO Data buffer.
0x1C
32
FIFO
Load/unload location for TX and RX FIFO buffers.
0
8
DMA
DMA Configuration.
0x20
32
TXDMA_EN
TX DMA channel enable.
0
1
dis
DMA is disabled
0
en
DMA is enabled
1
RXDMA_EN
RX DMA channel enable.
1
1
dis
DMA is disabled
0
en
DMA is enabled
1
TXDMA_LVL
TX threshold for DMA transmission.
8
6
RXDMA_LVL
RX threshold for DMA transmission.
16
6
TXFIFO
Transmit FIFO Status register.
0x24
32
DATA
Reading from this field returns the next character available at the
output of the TX FIFO (if one is available, otherwise 00h is returned).
0
7
UART1
UART 1
0x40043000
UART1
UART1 IRQ
15
SPI0
SPI peripheral.
0x400BE000
0x00
0x1000
registers
SPI0
56
DATA
Register for reading and writing the FIFO.
0x00
32
read-write
CTRL0
Register for controlling SPI peripheral.
0x04
read-write
SPI_EN
SPI Enable.
0
1
dis
SPI is disabled.
0
en
SPI is enabled.
1
MM_EN
Master Mode Enable.
1
1
dis
SPI is Slave mode.
0
en
SPI is Master mode.
1
SS_IO
Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.
4
1
output
Slave select 0 is output.
0
input
Slave Select 0 is input, only valid if MMEN=1.
1
START
Start Transmit.
5
1
start
Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.
1
SS_CTRL
Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.
8
1
DEASSERT
SPI De-asserts Slave Select at the end of a transaction.
0
ASSERT
SPI leaves Slave Select asserted at the end of a transaction.
1
SS_SEL
Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.
16
4
SS0
SS0 is selected.
0x1
SS1
SS1 is selected.
0x2
SS2
SS2 is selected.
0x4
SS3
SS3 is selected.
0x8
CTRL1
Register for controlling SPI peripheral.
0x08
read-write
TX_NUM_CHAR
Nubmer of Characters to transmit.
0
16
RX_NUM_CHAR
Nubmer of Characters to receive.
16
16
CTRL2
Register for controlling SPI peripheral.
0x0C
read-write
CLK_PHA
Clock Phase.
0
1
Rising_Edge
Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2
0
Falling_Edge
Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3
1
CLK_POL
Clock Polarity.
1
1
Normal
Normal Clock. Use when in SPI Mode 0 and Mode 1
0
Inverted
Inverted Clock. Use when in SPI Mode 2 and Mode 3
1
NUM_BITS
Number of Bits per character.
8
4
0
16 bits per character.
0
DATA_WIDTH
SPI Data width.
12
2
Mono
1 data pin.
0
Dual
2 data pins.
1
Quad
4 data pins.
2
THREE_WIRE
Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.
15
1
dis
Use four wire mode (Mono only).
0
en
Use three wire mode.
1
SS_POL
Slave Select Polarity, each Slave Select can have unique polarity.
16
1
SS0_low
SS1 active low.
0x0
SS0_high
SS0 active high.
0x1
SS_TIME
Register for controlling SPI peripheral/Slave Select Timing.
0x10
read-write
SSACT1
Slave Select Pre delay 1.
0
8
256
256 system clocks between SS active and first serial clock edge.
0
SSACT2
Slave Select Post delay 2.
8
8
256
256 system clocks between last serial clock edge and SS inactive.
0
SSINACT
Slave Select Inactive delay.
16
8
256
256 system clocks between transactions.
0
CLK_CFG
Register for controlling SPI clock rate.
0x14
read-write
LO
Low duty cycle control. In timer mode, reload[7:0].
0
8
Dis
Duty cycle control of serial clock generation is disabled.
0
HI
High duty cycle control. In timer mode, reload[15:8].
8
8
Dis
Duty cycle control of serial clock generation is disabled.
0
SCALE
System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.
16
4
DMA
Register for controlling DMA.
0x1C
read-write
TX_FIFO_LEVEL
Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.
0
5
TX_FIFO_EN
Transmit FIFO enabled for SPI transactions.
6
1
dis
Transmit FIFO is not enabled.
0
en
Transmit FIFO is enabled.
1
TX_FIFO_CLEAR
Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
7
1
CLEAR
Clear the Transmit FIFO, clears any pending TX FIFO status.
1
TX_FIFO_CNT
Count of entries in TX FIFO.
8
6
read-only
TX_DMA_EN
TX DMA Enable.
15
1
DIS
TX DMA requests are disabled, andy pending DMA requests are cleared.
0
en
TX DMA requests are enabled.
1
RX_FIFO_LEVEL
Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.
16
5
RX_FIFO_EN
Receive FIFO enabled for SPI transactions.
22
1
DIS
Receive FIFO is not enabled.
0
en
Receive FIFO is enabled.
1
RX_FIFO_CLEAR
Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
23
1
CLEAR
Clear the Receive FIFO, clears any pending RX FIFO status.
1
RX_FIFO_CNT
Count of entries in RX FIFO.
24
6
read-only
RX_DMA_EN
RX DMA Enable.
31
1
dis
RX DMA requests are disabled, any pending DMA requests are cleared.
0
en
RX DMA requests are enabled.
1
INT_FL
Register for reading and clearing interrupt flags. All bits are write 1 to clear.
0x20
read-write
TX_LEVEL
TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_LEVEL
RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_FULL
RX FIFO FULL.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSA
Slave Select Asserted.
4
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
SSD
Slave Select Deasserted.
5
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
ABORT
Slave Abort Detected.
9
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
M_DONE
Master Done, set when SPI Master has completed any transactions.
11
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_OVR
Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.
12
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_UND
Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.
13
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_OVR
Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.
14
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_UND
Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.
15
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
INT_EN
Register for enabling interrupts.
0x24
read-write
TX_LEVEL
TX FIFO Threshold interrupt enable.
0
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_EMPTY
TX FIFO Empty interrupt enable.
1
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_LEVEL
RX FIFO Threshold Crossed interrupt enable.
2
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_FULL
RX FIFO FULL interrupt enable.
3
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSA
Slave Select Asserted interrupt enable.
4
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
SSD
Slave Select Deasserted interrupt enable.
5
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
FAULT
Multi-Master Mode Fault interrupt enable.
8
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
ABORT
Slave Abort Detected interrupt enable.
9
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
M_DONE
Master Done interrupt enable.
11
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_OVR
Transmit FIFO Overrun interrupt enable.
12
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
TX_UND
Transmit FIFO Underrun interrupt enable.
13
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_OVR
Receive FIFO Overrun interrupt enable.
14
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
RX_UND
Receive FIFO Underrun interrupt enable.
15
1
dis
Interrupt is disabled.
0
en
Interrupt is enabled.
1
WAKE_FL
Register for wake up flags. All bits in this register are write 1 to clear.
0x28
read-write
TX_LEVEL
Wake on TX FIFO Threshold Crossed.
0
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
TX_EMPTY
Wake on TX FIFO Empty.
1
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_LEVEL
Wake on RX FIFO Threshold Crossed.
2
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
RX_FULL
Wake on RX FIFO Full.
3
1
clear
Flag is set when value read is 1. Write 1 to clear this flag.
1
WAKE_EN
Register for wake up enable.
0x2C
read-write
TX_LEVEL
Wake on TX FIFO Threshold Crossed Enable.
0
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
TX_EMPTY
Wake on TX FIFO Empty Enable.
1
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
RX_LEVEL
Wake on RX FIFO Threshold Crossed Enable.
2
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
RX_FULL
Wake on RX FIFO Full Enable.
3
1
dis
Wakeup source disabled.
0
en
Wakeup source enabled.
1
STAT
SPI Status register.
0x30
read-only
BUSY
SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.
0
1
not
SPI not active.
0
active
SPI active.
1